Display device, electronic device including the same, and electronic device driving method

Abstract

A display device, an electronic device including the display device, and a method for driving the electronic device are provided. The electronic device includes: a host processor for generating a first clock signal and outputting frame data and a synchronization signal; a driving controller for receiving the synchronization signal and the frame data from the host processor, and generating a control signal based on a second clock signal; and a display panel, in which the drive controller synchronizes the second clock signal with the first clock signal based on the synchronization signal, in which the drive controller includes an error detector for detecting an error of the synchronization signal, and in which the error detector outputs the first signal when the error is an initial synchronization failure error; and when the error is a synchronization loss error, the error detector outputs a second signal different from the first signal.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0081316 filed in the Korean Intellectual Property Office on June 23, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] Embodiments of the present disclosure described herein relate to a display device having improved reliability, an electronic device including the display device, and a method for driving the electronic device. Background Art

[0003] The electronic device may include a host processor, a drive controller, and a display panel. The host processor may provide input image data to the drive controller. In turn, the drive controller may process the input image data to generate a data signal. The host processor and the drive controller may be connected to each other via a specified interface. The host processor may include a data transmitter circuit that facilitates transmission of frame data from the host processor to the drive controller. Summary of the invention

[0004] Embodiments of the present disclosure provide a display device having improved reliability, an electronic device including the display device, and a method for driving the electronic device.

[0005] According to an embodiment of the present disclosure, an electronic device is provided, which includes: a host processor configured to generate a first clock signal and output frame data and a synchronization signal, wherein the synchronization signal is flipped based on the first clock signal; a drive controller connected to the host processor and configured to receive the synchronization signal and frame data from the host processor and generate a control signal based on a second clock signal; and a display panel configured to be driven based on the control signal, wherein the drive controller synchronizes the second clock signal with the first clock signal based on the synchronization signal, wherein the drive controller includes an error detector, which is configured to detect an error in the synchronization signal, wherein the error is one of an initial synchronization failure error indicating that the drive controller has not received the synchronization signal and a synchronization loss error indicating that a portion of the synchronization signal is omitted, and wherein when the error is an initial synchronization failure error, the error detector outputs a first signal; and when the error is a synchronization loss error, the error detector outputs a second signal different from the first signal.

[0006] The error detector includes: a first counter configured to check whether a synchronization signal is received at a first time point and to count a failure time during which the synchronization signal is not received; and a first comparator configured to compare the failure time with an initial time after the first time point and to output a first signal when the failure time is greater than the initial time.

[0007] The first time point is a time point when the driving controller switches from the sleep mode to the sleep exit mode.

[0008] The error detector includes: a second counter configured to count the number of consecutive lost flips of the synchronization signal, wherein the number of consecutive lost flips corresponds to the number of times the flip of the synchronization signal is not recognized; and a second comparator configured to compare the number of lost flips with a predetermined value and output a second signal when the number of lost flips is greater than the predetermined value.

[0009] When the number of lost flips is smaller than a predetermined value, the second comparator does not output the second signal.

[0010] The driving controller further includes: a signal output circuit configured to generate an error flag signal when receiving the first signal or the second signal, and output the error flag signal to the host processor.

[0011] When the host processor receives the error flag signal, the host processor initializes the drive controller by outputting a reset signal to the drive controller.

[0012] When the drive controller is initialized, no error flag signal is output.

[0013] When the first signal is output from the error detector, the driving controller is initialized and operates in a sleep mode.

[0014] When the driving controller operates in the sleep mode, the error detector does not output the first signal.

[0015] The drive controller and host processor communicate with each other via the Mobile Industry Processor Interface (MIPI).

[0016] The drive controller outputs a tearing signal to the host processor to control the transmission period of the frame data.

[0017] The driving controller controls the period of the tearing signal.

[0018] The frame data includes a vertical active area and a vertical blank area, and the host processor controls the size of the vertical blank area.

[0019] According to an embodiment of the present disclosure, a display device is provided, comprising: a drive controller configured to receive a clock signal, frame data, and a flipped synchronization signal, and output a scan control signal, a data control signal, and image data; and a display panel controlled by the drive controller, wherein the drive controller comprises an error detector configured to detect an error in the synchronization signal, wherein the error is an initial synchronization failure error indicating that the drive controller has failed to receive the synchronization signal or a synchronization loss error indicating that a portion of the synchronization signal is omitted, and wherein, when the error is an initial synchronization failure error, the error detector outputs a first signal; and when the error is a synchronization loss error, the error detector outputs a second signal different from the first signal.

[0020] The error detector includes: a first counter configured to check whether a synchronization signal is received at a first time point and to count a failure time during which the synchronization signal is not received; and a first comparator configured to compare the failure time with an initial time after the first time point and to output a first signal when the failure time is greater than the initial time.

[0021] The error detector includes: a second counter configured to count the number of consecutive lost flips of the synchronization signal, wherein the number of consecutive lost flips corresponds to the number of times the flip of the synchronization signal is not recognized; and a second comparator configured to compare the number of lost flips with a predetermined value and output a second signal when the number of lost flips is greater than the predetermined value.

[0022] The driving controller further includes: a signal output circuit configured to generate an error flag signal when receiving the first signal or the second signal, and output the error flag signal.

[0023] When the first signal is output from the error detector, the driving controller is initialized and operates in a sleep mode.

[0024] When the driving controller operates in the sleep mode, the error detector does not output the first signal.

[0025] According to an embodiment of the present disclosure, a method for driving an electronic device is provided, wherein the electronic device includes a host processor and a drive controller that communicate with each other through MIPI, the method including: at the drive controller, receiving a synchronization signal from the host processor to synchronize a second clock signal of the drive controller with a first clock signal of the host processor; and at an error detector of the drive controller, detecting an error in the synchronization signal, wherein the error includes an initial synchronization failure error indicating that the drive controller has not received the synchronization signal or a synchronization loss error indicating that a portion of the synchronization signal is omitted, and wherein the step of detecting the error in the synchronization signal includes: when the error is an initial synchronization failure error, outputting a first signal; and when the error is a synchronization loss error, outputting a second signal different from the first signal.

[0026] The step of outputting the first signal includes: checking whether a synchronization signal is received with respect to a first time point; and generating the first signal when the synchronization signal is not received within an initial time from the first time point.

[0027] The first time point is a time point when the driving controller switches from the sleep mode to the sleep exit mode.

[0028] The step of outputting the second signal includes: counting the number of consecutive missing flips of the synchronization signal; and generating the second signal when the number of missing flips is greater than a predetermined value.

[0029] The method may further include generating, at the drive controller, an error flag signal to be output to the host processor when the first signal or the second signal is received.

[0030] The method may further include initializing the driving controller based on a reset signal at the host processor when the host processor receives the error flag signal.

[0031] The method may further include operating the driving controller in a sleep mode when the first signal is output. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other features of the present disclosure will become apparent by describing embodiments of the present disclosure in detail with reference to the attached drawings.

[0033] Figure 1 is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0034] Figure 2 is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0035] Figure 3 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0036] Figure 4 is a timing diagram illustrating the operation of the electronic device according to an embodiment of the present disclosure.

[0037] Figure 5 is a flowchart illustrating a method for driving an electronic device according to an embodiment of the present disclosure.

[0038] Figure 6 is a diagram illustrating an error detector according to an embodiment of the present disclosure.

[0039] Figure 7 is a timing diagram illustrating the operation of the electronic device according to an embodiment of the present disclosure.

[0040] Figure 8 is a diagram illustrating an initial time code according to an embodiment of the present disclosure.

[0041] Fig. 9 is a timing diagram illustrating the operation of the electronic device according to an embodiment of the present disclosure.

[0042] Fig.10 is a diagram illustrating a lost rollover count code according to an embodiment of the present disclosure.

[0043] Fig.11 is a timing diagram illustrating the operation of the electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] In this specification, the expression that a first component (or region, layer, part, portion, etc.) is "on" a second component, "connected to" a second component, or "coupled to" a second component may mean that the first component is directly on the second component, directly connected to the second component, or directly coupled to the second component, or may mean that a third component is disposed between the first component and the second component.

[0045] The same reference numerals may refer to the same components. In addition, in the drawings, the thickness, proportion and size of the components may be exaggerated in order to effectively describe the technical content. The term "and / or" includes one or more combinations of related elements defined in each of them.

[0046] Although the terms "first", "second", etc. can be used to describe various components, these components should not be interpreted as being limited by these terms. The terms are used to distinguish one component from another component. For example, a first component can be referred to as a "second component", and similarly, a second component can be referred to as a "first component". The articles "a", "one", and "the" are singular because they have a single referent, but the singular form used in the specification should not exclude the presence of more than one referent.

[0047] Furthermore, the terms “under,” “beneath,” “on,” “over,” etc. are used to describe the relationship of components shown in the drawings. Conceptually relative terms are described based on the directions shown in the drawings.

[0048] It will also be understood that the terms “includes,” “comprising,” “having,” etc. specify the presence of stated features, numbers, steps, operations, elements, components, or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used in the specification have the same meaning as those generally understood by those skilled in the art to which the present disclosure belongs. In addition, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0050] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0051] Figure 1 is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0052] Reference Figure 1 In the operating system, the electronic device 1000 outputs various information through the display device DD. When the host processor AP executes the application stored in the memory 1300, the display device DD provides the application information to the user through the display panel DP.

[0053] The host processor AP obtains external input through the input module 1400 or the sensor module 1610, and executes an application corresponding to the external input. For example, when a user selects a camera icon displayed in the display panel DP, the host processor AP obtains the user input through the input sensor 1612 and activates the camera module 1710. The host processor AP transmits image data corresponding to the captured image obtained through the camera module 1710 to the display device DD. The display device DD can display an image corresponding to the captured image through the display panel DP.

[0054] As another example, when authentication of personal information is performed in the display device DD, the fingerprint sensor 1611 acquires input fingerprint information as input data. The host processor AP compares the input data obtained by the fingerprint sensor 1611 with the authentication data stored in the memory 1300, and executes the application according to the result of the comparison. The display device DD can display information executed according to the logic of the application through the display panel DP.

[0055] As another example, when the user selects a music streaming icon displayed in the display device DD, the host processor AP obtains the user input through the input sensor 1612 and activates the music streaming application stored in the memory 1300. When a music playback command is input to the music streaming application, the host processor AP activates the sound output module 1630 and provides the user with sound information corresponding to the music playback command.

[0056] The operation of the electronic device 1000 is briefly described above. Next, the configuration of the electronic device 1000 will be described in detail. Some of the components of the electronic device 1000 to be described later may be implemented integrally with one component, and the one component may be divided into two or more components.

[0057] Reference Figure 1 , the electronic device 1000 can communicate with the external electronic device 2000 through a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to an embodiment, the electronic device 1000 may include a host processor AP, a memory 1300, an input module 1400, a display device DD, a power module 1500, an embedded module (or internal module) 1600, and an external module 1700. According to an embodiment, the electronic device 1000 may not include at least one of the above components, or may also include one or more other components. According to an embodiment, some of the above components (e.g., a sensor module 1610, an antenna module 1620, or a sound output module 1630) may be integrated into any other component (e.g., a display device DD).

[0058] The host processor AP may execute software to control at least one component (e.g., hardware or software component) connected to the host processor AP of the electronic device 1000, and may perform various data processing or operations. According to an embodiment, as at least part of the data processing or operation, the host processor AP may store a command or data received from any other component (e.g., the input module 1400, the sensor module 1610, or the communication module 1730) in the volatile memory 1310, may process the command or data stored in the volatile memory 1310, and may store the processed data in the non-volatile memory 1320.

[0059] The host processor AP may include a main processor 1100 and an auxiliary processor 1200. The main processor 1100 may include one or more of a central processing unit (CPU) 220 and an application processor (AP). The main processor 1100 may also include one or more of a graphics processing unit (GPU) 1110, a communication processor (CP), and an image signal processor (ISP). The main processor 1100 may also include a neural processing unit (NPU) 1120. The neural processing unit 1120 may be a processor dedicated to processing an artificial intelligence model. The artificial intelligence model may be created by machine learning. The artificial intelligence model may include multiple artificial neural network layers. The artificial neural network may include a deep neural network (DNN), a convolutional neural network (CNN), a recursive neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recursive deep neural network (BRDNN), a deep Q network, or a combination of two or more of them, but the present disclosure is not limited thereto. Additionally or optionally, in addition to the hardware structure, the artificial intelligence model may include a software structure. At least two of the above-mentioned processing units and processors may be integrally implemented with one component (eg, a single chip), or each of the above-mentioned processing units and processors may be implemented with an independent component (eg, a plurality of chips).

[0060] The auxiliary processor 1200 may include an image processor 210, a data conversion circuit 1210, a gamma correction circuit 1220, and a rendering circuit 1230. The image processor 210 may convert and output a data format of image data.

[0061] The data conversion circuit 1210 may receive image data from the drive controller TED. The data conversion circuit 1210 may compensate the image data to ensure that the image is displayed at a desired brightness. The adjustment is based on the characteristics of the electronic device 1000 or user settings. In addition, the data conversion circuit 1210 may convert the image data to reduce power consumption or compensate for afterimages. The gamma correction circuit 1220 may convert image data or a gamma reference voltage so that an image displayed on the electronic device 1000 has a desired gamma characteristic. The rendering circuit 1230 may receive image data from the drive controller TED and may render the image data in consideration of the pixel arrangement of the display panel DP. At least one of the data conversion circuit 1210, the gamma correction circuit 1220, and the rendering circuit 1230 may be integrated into any other component (e.g., the main processor 1100 or the drive controller TED). At least one of the data conversion circuit 1210, the gamma correction circuit 1220, and the rendering circuit 1230 may be integrated into a data driver DIC to be described later.

[0062] The memory 1300 may store various data used by at least one component of the electronic device 1000 (eg, the host processor AP or the sensor module 1610) and input data or output data for commands related thereto. The memory 1300 may include at least one of a volatile memory 1310 and a nonvolatile memory 1320.

[0063] The input module 1400 may receive commands or data from outside the electronic device 1000 (eg, a user or an external electronic device 2000 ) to be used by components of the electronic device 1000 (eg, the host processor AP, the sensor module 1610 , or the sound output module 1630 ).

[0064] The input module 1400 may include a first input module 1410 to which a command or data from a user is input and a second input module 1420 to which a command or data from an external electronic device 2000 is input. The first input module 1410 may include a microphone, a mouse, a keyboard, a key (e.g., a button) or a pen (e.g., a passive pen or an active pen). The second input module 1420 may support a specified protocol so that it can be connected to the external electronic device 2000 by wire or wirelessly. According to one embodiment, the second input module 1420 may include a high-definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface. The second input module 1420 may include a connector (e.g., an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector)) that can be physically connected to the external electronic device 2000.

[0065] The display device DD may visually provide information to a user. The display device DD may include a display panel DP, a drive controller TED, and a data driver DIC. The display device DD may further include a window, a base, and a bracket for protecting the display panel DP. The display device DD may further include an emission drive circuit, a voltage generator, and the like. The display device DD will be described later.

[0066] The power module 1500 supplies power to the components of the electronic device 1000. The power module 1500 may include a battery that charges the power supply voltage. The battery may include a primary battery that cannot be recharged, a rechargeable secondary battery, or a fuel cell. The power module 1500 may include a power management integrated circuit (PMIC). The PMIC supplies optimized power to each of the above-mentioned modules and the modules to be described later. The PMIC may supply optimized power to each of the above-mentioned components and the components to be described later. The power module 1500 may include a wireless power transmission / reception component electrically connected to the battery. The wireless power transmission / reception component may include a plurality of antenna radiators in the form of a coil.

[0067] The electronic device 1000 may further include an embedded module 1600 and an external module 1700. The embedded module 1600 may include a sensor module 1610, an antenna module 1620, and a sound output module 1630. The external module 1700 may include a camera module 1710, an optical module 1720, and a communication module 1730.

[0068] The sensor module 1610 may sense the input of the user's body or the input of the pen in the first input module 1410 and may generate an electric signal or a data value corresponding to the input. The sensor module 1610 may include at least one of a fingerprint sensor 1611, an input sensor 1612, and a digitizer 1613.

[0069] The fingerprint sensor 1611 may generate a data value corresponding to the user's fingerprint. The fingerprint sensor 1611 may include one of an optical fingerprint sensor and a capacitive fingerprint sensor.

[0070] The input sensor 1612 may generate a data value corresponding to the coordinate information of the input of the user's body or the input of the pen. The input sensor 1612 generates a capacitance change as a data value due to the input. The input sensor 1612 may sense the input of the passive pen, or may exchange data with the active pen.

[0071] The input sensor 1612 may measure biometric signals such as blood pressure, moisture, or body fat. For example, when a user contacts his / her body part to the sensor layer or sensing panel and does not move during a given period of time, the input sensor 1612 may detect the biometric signal based on the change in the electric field caused by the body part, and may output the information to the display device DD.

[0072] The digitizer 1613 may generate a data value corresponding to the coordinate information of the input of the pen. The digitizer 1613 generates an amount of electromagnetic change caused by the input as a data value. The digitizer 1613 may sense the input of the passive pen, or may exchange data with the active pen.

[0073] At least one of the fingerprint sensor 1611, the input sensor 1612, and the digitizer 1613 may be implemented using a sensor layer formed on the display panel DP through a continuous process. The fingerprint sensor 1611, the input sensor 1612, and the digitizer 1613 may be disposed above / on the display panel DP, and at least one of the fingerprint sensor 1611, the input sensor 1612, and the digitizer 1613 (e.g., the digitizer 1613) may be disposed below / under the display panel DP.

[0074] At least two of the fingerprint sensor 1611, the input sensor 1612, and the digitizer 1613 may be formed integrally with one sensing panel by the same process. When they are formed integrally with one sensing panel, the sensing panel may be disposed between the display panel DP and a window disposed above / on the display panel DP. According to one embodiment, the sensing panel may be disposed on the window, and the position of the sensing panel is not particularly limited.

[0075] At least one of the fingerprint sensor 1611, the input sensor 1612, and the digitizer 1613 may be embedded in the display panel DP. For example, at least one of the fingerprint sensor 1611, the input sensor 1612, and the digitizer 1613 may be simultaneously formed by a process of forming elements (e.g., light emitting devices and transistors) included in the display panel DP.

[0076] In addition, the sensor module 1610 may generate an electrical signal or a data value corresponding to an internal state or an external state of the electronic device 1000. The sensor module 1610 may also include, for example, a gesture sensor, a gyro sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illumination sensor.

[0077] The antenna module 1620 may include one or more antennas to transmit or receive signals or power to or from an external source. According to an embodiment, the communication module 1730 may transmit or receive signals to or from an external electronic device 2000 using an antenna suitable for a communication method. The antenna pattern of the antenna module 1620 may be integrated with a component of the display device DD (e.g., the display panel DP) or the input sensor 1612.

[0078] The sound output module 1630, which is a device for outputting a sound signal to the outside of the electronic device 1000, may include, for example, a speaker for general purposes such as multimedia playback or recording playback and a receiver specifically for receiving calls. According to an embodiment, the receiver and the speaker may be implemented integrally or separately. The sound output mode of the sound output module 1630 may be integrated with the display device DD.

[0079] The camera module 1710 can capture still images and moving images. According to one embodiment, the camera module 1710 may include one or more lenses, image sensors, or image signal processors. The camera module 1710 may also include an infrared camera capable of measuring the presence or absence of a user, the position of the user, and the line of sight of the user.

[0080] The light module 1720 may provide light. The light module 1720 may include a light emitting diode or a xenon lamp. The light module 1720 may operate together with the camera module 1710, or may operate independently.

[0081] The communication module 1730 can establish a wired or wireless communication channel between the electronic device 1000 and the external electronic device 2000. The communication module 1730 can also promote and manage communication activities throughout the established communication channel. The communication module 1730 may include one of a wireless communication module (such as a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) and a wired communication module (such as a local area network (LAN) communication module or a power line communication module), or may include all of these modules. The communication module 1730 can communicate with the external electronic device 2000 through a short-range communication network (such as Bluetooth, Wi-Fi Direct or Infrared Data Protocol (IrDA)) or a long-range communication network (such as a cellular network, the Internet, or a computer network (e.g., LAN or WAN)). The above-mentioned various communication modules can be implemented with a single chip, or respectively implemented with a plurality of separate chips.

[0082] The input module 1400 , the sensor module 1610 , the camera module 1710 , etc. may be used together with the host processor AP to control the operation of the display device DD.

[0083] The host processor AP outputs a command or data to the display device DD, the sound output module 1630, the camera module 1710, or the optical module 1720 based on the input data received from the input module 1400. For example, the host processor AP may generate image data corresponding to the input data applied by a mouse or an active pen, and may output the image data to the display device DD. In another example, the host processor AP may generate command data corresponding to the input data, and may output the command data to the camera module 1710 or the optical module 1720. When no input data is received from the input module 1400 during a given period of time, the host processor AP may switch the operation mode of the electronic device 1000 to a low power mode or a sleep mode, so that the power consumption of the electronic device 1000 is reduced.

[0084] The host processor AP outputs a command or data to the display device DD, the sound output module 1630, the camera module 1710, or the optical module 1720 based on the sensing data received from the sensor module 1610. For example, the host processor AP may compare the authentication data obtained by the fingerprint sensor 1611 with the authentication data stored in the memory 1300, and then may execute an application program according to the result of the comparison. The host processor AP may execute a command based on the sensing data sensed by the input sensor 1612 or the digital converter 1613, or may output image data corresponding to the sensing data to the display device DD. When the sensor module 1610 includes a temperature sensor, the host processor AP may receive temperature data related to the measured temperature from the sensor module 1610, and may also perform brightness correction on the image data based on the temperature data.

[0085] The host processor AP may receive measurement data regarding the presence or absence of a user, the position of the user, and the line of sight of the user from the camera module 1710. The host processor AP may also perform brightness correction on the image data based on the measurement data. For example, the host processor AP, which determines the presence or absence of a user through an input from the camera module 1710, may provide image data whose brightness is corrected through the data conversion circuit 1210 or the gamma correction circuit 1220 to the display device DD.

[0086] Some of the above components may be connected to each other through a communication scheme between peripheral devices (e.g., a bus, a general purpose input / output (GPIO), a serial peripheral interface (SPI), a mobile industry processor interface (MIPI), or an ultra-path interconnect (UPI) link), and may exchange signals (e.g., commands or data). The host processor AP may communicate with the display device DD through a given interface. For example, one of the above communication methods may be used, and the present disclosure is not limited thereto.

[0087] The electronic device 1000 according to various embodiments of the present disclosure may be implemented as various types of devices. The electronic device 1000 may include, for example, at least one of a portable communication device (e.g., a smart phone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, and a home appliance. The electronic device 1000 according to an embodiment of the present disclosure is not limited to the above-mentioned devices.

[0088] Figure 2 is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0089] Reference Figure 2 The electronic device 1000 may be a device activated by an electrical signal. The electronic device 1000 may process image data and may display the processed image data through the display panel DP.

[0090] The electronic device 1000 may include a host processor AP and a display device DD. The display device DD may include a driving controller TED and a display panel DP.

[0091] The host processor AP may be implemented with an integrated circuit, a system on chip, an application processor, or a mobile application processor, but the present disclosure is not limited thereto. The host processor AP may control various components (eg, a drive controller TED) included in the electronic device 1000 .

[0092] The host processor AP and the drive controller TED may be connected to each other through a given interface. The given interface may include a Mobile Industry Processor Interface (MIPI).

[0093] MIPI can be driven in command mode and video mode.

[0094] In command mode, the drive controller TED may output a first tearing signal to the host processor AP. The first tearing signal may be generated based on the vertical synchronization signal. The first tearing signal may be referred to as a "tearing effect (TE) signal". The first tearing signal is an example of a signal that can prevent the tearing effect. The tearing effect may refer to a visual artifact on the display panel DP. The host processor AP may output a first frame of data to the drive controller TED. The transmission of the first frame of data may be controlled by the first tearing signal. The first frame of data may include only image data. When the display panel DP is set to display a still image, the drive controller TED may periodically read the image data stored in the frame memory. Then, the drive controller TED may output the read image data to the display panel DP according to the timing determined by the drive controller TED.

[0095] The video mode may include a first video mode and a second video mode.

[0096] In the first video mode, the host processor AP may output the second frame data to the drive controller TED. The second frame data may be transmitted in the form of a packet. The second frame data may include a vertical valid area and a vertical blank area. The vertical valid area may include image data. In the first video mode, the drive controller TED may not receive a tearing signal. When the display panel DP is set to display video, the drive controller TED may output the image data to the display panel DP according to the timing included in the second frame data. The drive controller TED may cause the display panel DP to operate at a first driving frequency. The first video mode may be referred to as a "normal mode".

[0097] In the second video mode, the drive controller TED may output a second tearing signal TE to the host processor AP. The second tearing signal TE may be generated based on the vertical synchronization signal. The second tearing signal TE may be referred to as an "adaptive refresh panel tearing effect (ARP-TE) signal". The host processor AP may output the second frame data to the drive controller TED. The transmission of the second frame data may be controlled by the second tearing signal TE. The drive controller TED may analyze the second frame data and may determine the second driving frequency of the display panel DP. The size of the vertical blank area of ​​the second frame data may be controlled by the drive controller TED based on the second driving frequency. In the vertical blank area, the host processor AP and the drive controller TED may operate in a low power mode. In this way, the power consumption of the electronic device 1000 may be reduced. The display panel DP may operate at a second driving frequency lower than the first driving frequency. The power consumption of the electronic device 1000 may be reduced. The second video mode may be referred to as an "adaptive refresh panel (ARP) mode". In this specification, a configuration in which the host processor AP and the drive controller TED operate in the second video mode is shown as an example. Below, the second tearing signal TE is referred to as a "tear signal TE".

[0098] The host processor AP may include an image processor 210 , a data transmitter circuit TX, a central processing unit 220 , a bus 230 , and a first clock source (clock source 1 ) 240 .

[0099] The image processor 210 may convert the image data into a format suitable for being processed by the data transmitter circuit TX.

[0100] The data transmitter circuit TX may include one clock lane and one or more data lanes.

[0101] The clock channel may transmit a clock signal CLK. The clock signal CLK may be a continuously toggled signal. The clock signal CLK may be generated based on a first clock signal CLK1 to be described later.

[0102] The data channel can transmit frame data DATA. The frame data DATA can be transmitted through a bidirectional data channel or a unidirectional data channel.

[0103] The central processing unit 220 may cause the host processor AP to compress the image data and provide the compressed image data to the driving controller TED through the data transmitter circuit TX.

[0104] The central processing unit 220 may control components of the host processor AP via the bus 230 .

[0105] The first clock source 240 may generate a first clock signal CLK1 that continuously flips. The first clock signal CLK1 may be used to drive various components in the host processor AP and generate various signals. The first clock source 240 may include a ring oscillator, an RC oscillator, a crystal oscillator, or a temperature compensated crystal oscillator. For example, the first clock source 240 may be a crystal oscillator.

[0106] The host processor AP may output a reset signal RST to the drive controller TED. The reset signal RST may be used to initialize the drive controller TED.

[0107] The host processor AP may output a synchronization signal ESYNC to the drive controller TED. The synchronization signal ESYNC may be generated based on the first clock signal CLK1 and may be flipped at a given period PD1. In other words, the synchronization signal ESYNC may be flipped at a given period PD1. For example, the pulse width of the synchronization signal ESYNC may correspond to one horizontal period, and the given period PD1 may correspond to 2 horizontal periods.

[0108] The synchronization signal ESYNC may be a signal transmitted to synchronize the host processor AP and the drive controller TED. The host processor AP and the drive controller TED may synchronize internal timing based on the synchronization signal ESYNC. For example, the synchronization signal ESYNC may be a signal corresponding to a horizontal synchronization signal used in the electronic device 1000. The synchronization signal ESYNC may be used in common in the host processor AP and the drive controller TED. For example, the synchronization signal ESYNC may be shared by the host processor AP and the drive controller TED.

[0109] The driving controller TED may control the display panel DP. The driving controller TED may be connected to the host processor AP in a specified interface mode. The driving controller TED may receive data (e.g., frame data DATA) from the host processor AP, and may generate image data DS by converting the format of the frame data DATA into an interface specification suitable for the display panel DP (refer to Figure 3 The driving controller TED may provide a scanning control signal SCS to the display panel DP (refer to Figure 3 )、Data control signal DCS (refer to Figure 3 ), image data DS (refer to Figure 3 ) etc. This will be described later.

[0110] The driving controller TED may include a data receiver circuit RX, an error detector 110 , a signal output circuit 120 , and a second clock source (clock source 2 ) 130 .

[0111] The data receiver circuit RX may include a clock channel and one or more data channels. The data receiver circuit RX may be connected to the data transmitter circuit TX via MIPI. The data receiver circuit RX may receive a clock signal CLK from the data transmitter circuit TX.

[0112] The clock channel may receive a clock signal CLK. The clock channel of the data receiver circuit RX may correspond to the clock channel of the data transmitter circuit TX. The clock signal CLK may be provided to the second clock source 130. The second clock source 130 may synchronize the second clock signal CLK2 with the first clock signal CLK1 based on the clock signal CLK.

[0113] The data channel may receive frame data DATA. The data channel of the data receiver circuit RX may correspond to the data channel of the data transmitter circuit TX. Thus, for example, the data receiver circuit RX may receive frame data DATA from the data transmitter circuit TX via the data channel, and vice versa.

[0114] The error detector 110 may receive the synchronization signal ESYNC. The error detector 110 may detect an error of the synchronization signal ESYNC. This will be described later.

[0115] When the error detector 110 detects an error of the synchronization signal ESYNC, the signal output circuit 120 may generate an error flag signal ERF and may output the error flag signal ERF to the host processor AP. This will be described later.

[0116] The second clock source 130 can generate a second clock signal CLK2 that continuously flips. The second clock signal CLK2 can be used to drive various components in the drive controller TED and generate various signals. For example, the drive controller TED can generate a control signal CTRL (refer to Figure 3 ). The second clock source 130 may include a ring oscillator, an RC oscillator, a crystal oscillator, or a temperature compensated crystal oscillator. For example, the second clock source 130 may be a ring oscillator.

[0117] The second clock source 130 may synchronize the second clock signal CLK2 with the first clock signal CLK1 based on the clock signal CLK or the synchronization signal ESYNC. For example, the second clock source 130 may align the second clock signal CLK2 with the first clock signal CLK1.

[0118] The driving controller TED may output a tearing signal TE controlling a transmission period of the frame data DATA to the host processor AP.

[0119] The drive controller TED may control the period of the tearing signal TE. For example, the drive controller TED may receive and analyze a command output from the host processor AP, and may adjust the period of the tearing signal TE based on the command output from the host processor AP. The command output from the host processor AP may include information about the size of the vertical blank area of ​​the frame data DATA.

[0120] Unlike the present disclosure, although the host processor and the drive controller operate in the low power mode, the drive controller may not receive the clock signal through the clock channel. When the low power mode ends, there is a possibility of experiencing the phenomenon of tearing of the brightness of the image displayed on the display panel. This tearing effect can be attributed to the divergence of the horizontal synchronization signal due to the clock difference between the host processor and the drive controller. However, according to an embodiment of the present disclosure, the synchronization signal ESYNC can be continuously generated and supplied to the drive controller TED, regardless of the transmission of the frame data DATA. For example, even when the frame data DATA is not transmitted, the synchronization signal ESYNC can be provided from the host processor AP to the drive controller TED. The drive controller TED can synchronize the second clock signal CLK2 with the first clock signal CLK1 based on the synchronization signal ESYNC. Therefore, flickering caused by a fine skew difference of the horizontal synchronization signal can be prevented. In addition, the divergence of the horizontal synchronization signal caused by the clock difference between the host processor AP and the drive controller TED can be prevented. Therefore, an electronic device 1000 with improved display quality and improved reliability can be provided.

[0121] The display panel DP may be a component that basically generates an image. The display panel DP may include a plurality of pixels PX (refer to Figure 3 ), and can display images under the control of the drive controller TED.

[0122] The display panel DP according to the embodiment of the present disclosure may be a light-emitting display panel, but the present disclosure is not limited thereto. For example, the display panel DP may be an organic light-emitting display panel, a quantum dot light-emitting display panel, a micro-LED display panel, or a nano-LED display panel. The emission layer of the organic light-emitting display panel may include an organic light-emitting material. The emission layer of the quantum dot light-emitting display panel may include quantum dots or quantum rods, etc. The emission layer of the micro-LED display panel may include micro-LEDs. The emission layer of the nano-LED display panel may include nano-LEDs.

[0123] Figure 3 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0124] Reference Figure 3, the display device DD includes a display panel DP, a driving controller TED, a data driver DIC and a voltage generator VG.

[0125] The drive controller TED may receive the frame data DATA and the control signal CTRL. The drive controller TED may generate the image data DS by converting the data format of the frame data DATA into a specification suitable for the interface with the data driver DIC. The drive controller TED may output a scan control signal SCS, a data control signal DCS, an emission drive control signal ECS, and a voltage control signal VCS. The scan control signal SCS, the data control signal DCS, the emission drive control signal ECS, and the voltage control signal VCS may be collectively referred to as “control signals”.

[0126] The driver controller TED can receive the information from the host processor AP (refer to Figure 1 )Frame data of a frequency determined by

[0127] The data driver DIC receives a data control signal DCS and image data DS from the driving controller TED. The data driver DIC may convert the image data DS into data signals and may output the data signals to a plurality of data lines DL1 to DLm, respectively. The data signals may refer to analog voltages corresponding to grayscale values ​​of the image data DS.

[0128] The driving controller TED and the data driver DIC may be implemented integrally, which may be referred to as a “timing controller embedded data driver”.

[0129] In an embodiment of the present disclosure, the data driver DIC may output data signals corresponding to the image data DS to the data lines DL1 to DLm, respectively, during a driving period of one frame.

[0130] The voltage generator VG may receive a voltage control signal VCS from the driving controller TED. The voltage generator VG may generate voltages required for the operation of the display panel DP. In an embodiment of the present disclosure, the voltage generator VG generates a first power voltage ELVDD, a second power voltage ELVSS, and a reference voltage Vref.

[0131] The display panel DP may include scan lines GCL1 to GCLn, GWL1 to GWLn and GRL1 to GRLn, emission control lines EML11 to EML1n and EML21 to EML2n, data lines DL1 to DLm, and pixels PX. The display panel DP may further include a scan driving circuit SD and an emission driving circuit EDC.

[0132] The scan driving circuit SD may be disposed at a first side of the display panel DP. The scan lines GCL1 to GCLn, GWL1 to GWLn, and GRL1 to GRLn may extend from the scan driving circuit SD in a first direction DR1.

[0133] The emission driving circuit EDC may be disposed at the second side of the display panel DP. The emission control lines EML11 to EML1n and EML21 to EML2n may extend from the emission driving circuit EDC in a direction away from the first direction DR1.

[0134] The scan lines GCL1 to GCLn, GWL1 to GWLn, and GRL1 to GRLn and the emission control lines EML11 to EML1n and EML21 to EML2n may be spaced apart from each other in the second direction DR2.

[0135] The scan lines GCL1 to GCLn, GWL1 to GWLn, and GRL1 to GRLn may include compensation scan lines GCL1 to GCLn, write scan lines GWL1 to GWLn, and initialization scan lines GRL1 to GRLn.

[0136] The emission control lines EML11 to EML1n and EML21 to EML2n may include first emission control lines EML11 to EML1n and second emission control lines EML21 to EML2n.

[0137] The data lines DL1 to DLm may extend from the data driver DIC in a direction away from the second direction DR2. In other words, the data lines DL1 to DLm may extend from the data driver DIC in a direction opposite to the second direction DR2. The data lines DL1 to DLm may be spaced apart from each other in the first direction DR1.

[0138] exist Figure 3 In the example shown in , the scan drive circuit SD and the emission drive circuit EDC are arranged to face each other, and the pixel PX is placed between the scan drive circuit SD and the emission drive circuit EDC. However, the present disclosure is not limited thereto. For example, the scan drive circuit SD and the emission drive circuit EDC may be arranged adjacent to each other on the first side or the second side of the display panel DP. In an embodiment, the scan drive circuit SD and the emission drive circuit EDC may be implemented with one circuit.

[0139] The plurality of pixels PX may be electrically connected to scan lines GCL1 to GCLn, GWL1 to GWLn, GRL1 to GRLn, emission control lines EML11 to EML1n and EML21 to EML2n, and data lines DL1 to DLm. Each of the plurality of pixels PX may be electrically connected to three scan lines and two emission control lines.

[0140] Each of the plurality of pixels PX may include a light emitting element and a pixel circuit for controlling emission of the light emitting element.

[0141] The light emitting element of each of the plurality of pixels PX may generate light having different colors. For example, the pixel PX may include a red pixel for generating red light, a green pixel for generating green light, and a blue pixel for generating blue light. The light emitting element of the red pixel, the light emitting element of the green pixel, and the light emitting element of the blue pixel may include emission layers of different materials, respectively.

[0142] The pixel circuit may include at least one transistor and at least one capacitor. This will be described later. The scan drive circuit SD and the emission drive circuit EDC may include transistors formed by the same process as the transistors of the pixel circuit.

[0143] Each of the plurality of pixels PX may receive a first power voltage ELVDD, a second power voltage ELVSS, and a reference voltage Vref from a voltage generator VG.

[0144] The scan driving circuit SD may receive a scan control signal SCS from the driving controller TED. The scan driving circuit SD may output a scan signal to the scan lines GCL1 to GCLn, GWL1 to GWLn, and GRL1 to GRLn in response to the scan control signal SCS.

[0145] The emission driving circuit EDC may output an emission control signal to the emission control lines EML11 to EML1n and EML21 to EML2n in response to an emission driving control signal ECS from the driving controller TED.

[0146] The driving controller TED according to an embodiment of the present disclosure may determine a driving frequency, and may control the data driver DIC, the scan driving circuit SD, and the emission driving circuit EDC according to the determined driving frequency.

[0147] Figure 4 is a timing diagram illustrating the operation of the electronic device according to an embodiment of the present disclosure.

[0148] Reference Figure 2 and Figure 4 , the drive controller TED can operate in the shutdown mode PWR DN where the power is turned off.

[0149] The driving controller TED may receive a power signal PWR from the host processor AP. The power signal PWR may control the driving controller TED to be turned on or off.

[0150] When the power signal PWR is set to an active state, the driving controller TED may be switched to a power-on on mode PWR UP, and thus the driving controller TED may operate.

[0151] The host processor AP may output a reset signal RST to the drive controller TED. The reset signal RST may be used to initialize the drive controller TED. The reset signal RST may be activated after the power signal PWR is activated.

[0152] When the reset signal RST is set to an active state (eg, a high level), the driving controller TED may be switched from the on mode PWR UP to the sleep mode Sleep in, and thus the driving controller TED may operate.

[0153] In the sleep mode Sleep in, the host processor AP may start to output the synchronization signal ESYNC to the drive controller TED. For example, the synchronization signal ESYNC may be output from the time point when the drive controller TED enters the sleep mode Sleep in.

[0154] Before providing the tearing signal TE (eg, before the first time point t1 ), the host processor AP may output a sleep out command to the drive controller TED.

[0155] In response to the sleep exit command, the drive controller TED may switch from the sleep mode Sleep in to the sleep exit mode Sleep out, so the drive controller TED may operate. For example, the first time point t1 may be a time point when the drive controller TED switches from the sleep mode Sleep in to the sleep exit mode Sleep out.

[0156] The drive controller TED may operate after the sleep exit mode Sleep out.

[0157] In the sleep exit mode Sleep out, the driving controller TED may output a tearing signal TE to the host processor AP. The tearing signal TE may be generated based on a vertical synchronization signal. For example, the tearing signal TE may be output when the sleep exit mode Sleep out starts.

[0158] At the second time point t2, the host processor AP may output a display on command instructing the driving controller TED to output the frame data DATA stored in the buffer.

[0159] In response to the display on command, the drive controller TED may switch from the sleep exit mode Sleep out to the display on mode Display on and may operate.

[0160] The frame data DATA may be transmitted in the form of a packet. The packet of the frame data DATA may include a vertical active area VAA1 / VAA2 and a vertical blank area VBA1 / VBA2. The vertical active area VAA1 / VAA2 may include image data.

[0161] The host processor AP may control the size of the vertical blank area VBA1 / VBA2 and adjust the transmission timing of the frame data DATA according to the size of the vertical blank area VBA1 / VBA2.

[0162] The driving controller TED may receive and analyze the previous frame data output from the host processor AP, and may output a timing control signal corresponding to the analysis result.

[0163] The driving controller TED may adjust the period of the tearing signal TE based on the timing control signal, and may provide the tearing signal TE having the adjusted period to the host processor AP.

[0164] The tearing signal TE may control the transmission period of the frame data DATA. The host processor AP may control the transmission timing of the next frame data to be provided to the driving controller TED according to the tearing signal TE having the adjusted period.

[0165] For example, when the transmission of the previous frame data ends, the drive controller TED may receive an end-of-frame (EOF) command from the host processor AP. When the scanning of the previous frame data ends and the entire previous frame data is displayed on the display panel DP, the drive controller TED may generate an end-of-scan (EOS) command. A tear signal TE may be generated to be activated when the EOF command for the previous frame data is received and the EOS command for the previous frame data is generated. The drive controller TED may provide the tear signal TE to the host processor AP. The host processor AP may output the next frame data in response to the tear signal TE.

[0166] The first frame data among the segments of the frame data DATA may include a first vertical active area VAA1 and a first vertical blank area VBA1. The first vertical blank area VBA1 may have a first size T1. The second frame data among the segments of the frame data DATA may include a second vertical active area VAA2 and a second vertical blank area VBA2. The size of the second vertical blank area VBA2 may be greater than the size of the first vertical blank area VBA1. The second vertical blank area VBA2 may have a second size T2.

[0167] The host processor AP may output the first frame data in response to the tearing signal TE. The first frame data may have a first driving frequency FT1. For example, the first driving frequency FT1 may be 120 Hz (Hertz).

[0168] The host processor AP may output the second frame data in response to the tear signal TE. The second frame data may have a second driving frequency FT2. The host processor AP may increase the size of the second vertical blank area VBA2 to control the transmission timing of the frame data to be provided to the drive controller TED. The second driving frequency FT2 may be lower than the first driving frequency FT1. For example, the second driving frequency FT2 may be 60 Hz.

[0169] According to an embodiment of the present disclosure, when the second frame data is output, the display panel DP may be operated at the second driving frequency FT2 lower than the first driving frequency FT1. The power consumption of the electronic device 1000 may be reduced.

[0170] In addition, according to an embodiment of the present disclosure, during the first vertical blank area VBA1 and the second vertical blank area VBA2, the host processor AP and the drive controller TED may operate in a low power mode. In the low power mode, the host processor AP may not provide the clock signal CLK and the frame data DATA to the drive controller TED. In this way, the power consumption of the electronic device 1000 may be reduced.

[0171] The synchronization signal ESYNC may be continuously generated and provided to the drive controller TED regardless of the low power mode. For example, even if the host processor AP operates in the low power mode and does not provide the first clock signal CLK1 to the drive controller TED, the synchronization signal ESYNC may be provided to the drive controller TED.

[0172] According to an embodiment of the present disclosure, the drive controller TED can synchronize the second clock signal CLK2 with the first clock signal CLK1 based on the synchronization signal ESYNC. In this way, flickering due to a fine skew difference of the horizontal synchronization signal can be prevented. In addition, divergence of the horizontal synchronization signal due to a clock difference between the host processor AP and the drive controller TED can be prevented. Therefore, an electronic device 1000 with improved display quality and improved reliability can be provided.

[0173] Figure 5 is a flowchart illustrating a method for driving an electronic device according to an embodiment of the present disclosure, Figure 6 is a diagram illustrating an error detector according to an embodiment of the present disclosure.

[0174] Reference Figure 2 , Figure 5 and Figure 6 , the host processor AP and the drive controller TED can communicate through MIPI.

[0175] The driving controller TED may receive a synchronization signal ESYNC from the host processor AP to synchronize the second clock signal CLK2 of the driving controller TED with the first clock signal CLK1 of the host processor AP ( S100 ).

[0176] The error detector 110 of the drive controller TED may detect an error of the synchronization signal ESYNC ( S200 ).

[0177] The error may include an initial synchronization failure error indicating that the drive controller TED does not receive the activated synchronization signal ESYNC and a synchronization loss error indicating that a part of the synchronization signal ESYNC is omitted, which will be described later.

[0178] When the detected error corresponds to an initial synchronization failure error, the error detector 110 may output a first signal SG1. When the detected error corresponds to a synchronization loss error, the error detector 110 may output a second signal SG2 different from the first signal SG1.

[0179] The error detector 110 may include a first counter 111 , a first comparator 112 , a second counter 113 , and a second comparator 114 .

[0180] The first counter 111 may receive the synchronization signal ESYNC. The first counter 111 may check whether the synchronization signal ESYNC is received at a given time point, and may count the failure time IT during which the synchronization signal ESYNC is not received. The first counter 111 may output the failure time IT. The given time point may be a first time point t1 (for example, time point t1 (refer to Figure 4 )).

[0181] The first comparator 112 may receive a failure time IT. After a given time point, the first comparator 112 may compare the failure time IT from the first counter 111 with a given initial time. When the failure time IT is greater than the initial time, the first comparator 112 may output a first signal SG1. The initial time is a predetermined time, and the present disclosure is not limited thereto. For example, the initial time may be 16 ms (milliseconds).

[0182] The first counter 111 and the first comparator 112 may detect an error of the synchronization signal ESYNC due to an initial synchronization failure error.

[0183] The second counter 113 may count the number of consecutive missing flips MT of the synchronization signal ESYNC. The second counter 113 may output the number of missing flips MT. The number of consecutive missing flips MT of the synchronization signal ESYNC may refer to the number of times the flip of the synchronization signal ESYNC is not recognized.

[0184] The second comparator 114 may receive the number of lost flip MTs. The second comparator 114 may compare the number of lost flip MTs with a predetermined value. When the number of lost flip MTs is greater than the predetermined value, the second comparator 114 may output a second signal SG2. The predetermined value may be a predetermined number of flips, and the present disclosure is not limited thereto. For example, the predetermined value may be 8.

[0185] The second counter 113 and the second comparator 114 may detect an error of the synchronization signal ESYNC due to a synchronization loss error.

[0186] When generating the first signal SG1 or the second signal SG2, the driving controller TED may generate an error flag signal ERF (refer to Figure 7 )(S300).

[0187] When the host processor AP receives the error flag signal ERF (refer to Figure 7 ), the host processor AP can initialize the drive controller TED (S400). Figure 7 ) no matter what, the drive controller TED can be automatically initialized according to whether the first signal SG1 and / or the second signal SG2 is output.

[0188] Figure 7 is a timing diagram showing the operation of the electronic device according to an embodiment of the present disclosure, Figure 8 is a diagram showing an initial time code according to an embodiment of the present disclosure. Figure 7 In the description of Figure 4 The described components are labeled by the same reference numerals / symbols, and thus, additional description will be omitted to avoid redundancy.

[0189] Figure 7 The operation of the electronic device when an initial synchronization failure error occurs is shown.

[0190] Reference Figure 2 , Figure 6 , Figure 7 and Figure 8 The drive controller TED can sequentially operate in a shutdown mode PWR DN, an open mode PWRUP, a sleep mode Sleep in, and a sleep exit mode Sleep out.

[0191] During operation of the electronic device 1000, an error may occur in which the activated synchronization signal ESYNC is not provided from the host processor AP to the drive controller TED. The case in which the drive controller TED fails to receive the activated synchronization signal ESYNC may be referred to as a case in which an initial synchronization failure error occurs.

[0192] The initial synchronization failure error may occur due to various reasons or in various situations. For example, in the case where the host processor AP does not provide the activated synchronization signal ESYNC, the initial synchronization failure error may occur. As another example, in the case where the activated synchronization signal ESYNC is provided after the sleep mode Sleep in or the sleep exit mode Sleep out due to the delay of the activated synchronization signal ESYNC, the initial synchronization failure error may occur.

[0193] The error detector 110 may detect an error of the synchronization signal ESYNC. The error detector 110 may operate after a sleep exit mode Sleep out in which the driving controller TED operates.

[0194] The first counter 111 may check whether the synchronization signal ESYNC is received at a first time point t1 (the first time point t1 is a time point when the sleep mode Sleepin is switched to the sleep exit mode Sleep out), and may count the failure time IT in which the synchronization signal ESYNC is not received. For example, the first counter 111 may not check whether the synchronization signal ESYNC provided before the first time point t1 is received. The first counter 111 may output the failure time IT to the first comparator 112.

[0195] When the activated synchronization signal ESYNC is normally output after the first time point t1 , the first counter 111 may determine that an initial synchronization failure error does not occur and may not count the failure time IT.

[0196] After the first time point t1, the first comparator 112 may compare the failure time IT with a given initial time. When the failure time IT is greater than the initial time, the first comparator 112 may output a first signal SG1.

[0197] The initial time code may include a value specified for each initial time. The initial time code may correspond to a value consisting of four bits. The initial time code may store a value of 4'b0000 specified relative to 1ms, a value of 4'b0001 specified relative to 2ms, and a value of 4'b1111 specified relative to 16ms. However, this is only an example, and the initial time code according to an embodiment of the present disclosure is not limited thereto.

[0198] When the initial time code is 4'b1111, the first comparator 112 may set the initial time to 16ms, and may determine whether the failure time IT exceeds 16ms. When the failure time IT exceeds 16ms, the first comparator 112 may output the first signal SG1. When the failure time IT does not exceed 16ms and the drive controller TED normally receives the activated synchronization signal ESYNC within the initial time, the first comparator 112 may not output the first signal SG1.

[0199] As another example, when the initial time code is 4'b0001, the first comparator 112 may set the initial time to 2ms, and may determine whether the failure time IT exceeds 2ms. When the failure time IT exceeds 2ms, the first comparator 112 may output the first signal SG1. When the failure time IT does not exceed 2ms and the drive controller TED normally receives the activated synchronization signal ESYNC within the initial time, the first comparator 112 may not output the first signal SG1.

[0200] The signal output circuit 120 may receive the first signal SG1. When the signal output circuit 120 receives the first signal SG1, the signal output circuit 120 may generate an error flag signal ERF and may output the error flag signal ERF to the host processor AP.

[0201] When the host processor AP receives the error flag signal ERF, the host processor AP may initialize the drive controller TED by outputting a reset signal RST to the drive controller TED. The host processor AP may deactivate the reset signal RST at the initialization time point tr and then may activate the reset signal RST.

[0202] At the initialization time point tr when the reset signal RST is deactivated (for example, the reset signal RST has a low level), the drive controller TED may operate in the power-on mode PWR UP again. When the drive controller TED enters the power-on mode PWRUP, the drive controller TED may be initialized. In this case, the output of the first signal SG1 and the error flag signal ERF may be stopped. For example, after the initialization time point tr, the first signal SG1 and the error flag signal ERF may not be output.

[0203] The reset signal RST may be activated again. When the reset signal RST is activated, the drive controller TED may operate in the sleep mode Sleep in.

[0204] In the sleep mode Sleep in, the host processor AP may output the activated synchronization signal ESYNC to the drive controller TED again.

[0205] At a first time point t1 , the host processor AP may output a sleep exit command to the drive controller TED.

[0206] In response to the sleep exit command, the drive controller TED may operate in the sleep exit mode Sleep out.

[0207] Starting from the first time point t1, the first counter 111 may check whether the synchronization signal ESYNC is received. When the synchronization signal ESYNC is normally output, the first counter 111 may not count the failure time IT.

[0208] According to an embodiment of the present disclosure, in the event that an error occurs in the synchronization signal ESYNC, the drive controller TED can detect the error and can perform a recovery operation to ensure the normal reception of the synchronization signal ESYNC. Even if an error occurs in the synchronization signal ESYNC, the drive controller TED can receive the normal synchronization signal ESYNC through the recovery operation. The drive controller TED can synchronize the second clock signal CLK2 with the first clock signal CLK1 based on the synchronization signal ESYNC. Therefore, flickering due to a fine skew difference of the horizontal synchronization signal can be prevented. In addition, divergence of the horizontal synchronization signal due to the clock difference between the host processor AP and the drive controller TED can be prevented. Therefore, an electronic device 1000 with improved display quality and improved reliability can be provided.

[0209] Fig. 9 is a timing diagram showing the operation of the electronic device according to an embodiment of the present disclosure, Fig.10 is a diagram showing a lost flip count code according to an embodiment of the present disclosure. Fig. 9 In the description of Figure 4 The described components are labeled by the same reference numerals / symbols, and thus, additional description will be omitted to avoid redundancy.

[0210] Fig. 9 The operation of the electronic device when a synchronization loss error occurs is shown.

[0211] Reference Figure 2 , Figure 6 , Fig. 9 and Fig.10 The drive controller TED can sequentially operate in the shutdown mode PWR DN, the startup mode PWRUP, the sleep mode Sleep in, the sleep exit mode Sleep out and the display on mode Display on.

[0212] During operation of the electronic device 1000, a portion of the synchronization signal ESYNC provided from the host processor AP may be missed. This may be a case where a synchronization loss error occurs.

[0213] The error detector 110 may detect an error of the synchronization signal ESYNC. The error detector 110 may operate after a sleep exit mode Sleep out in which the driving controller TED operates.

[0214] The second counter 113 may be activated after a given time point, and may count the number of consecutive lost flips MT of the synchronization signal ESYNC. The given time point may be a second time point t2. However, this is an example, and the given time point according to an embodiment of the present disclosure is not limited thereto. For example, the given time point may be a first time point t1. Below, a description will be given when the given time point is the second time point t2.

[0215] The second counter 113 may output the number of missing toggles MT to the second comparator 114. For example, after a second time point t2 when the driving controller TED operates in the display on mode Display on, the second counter 113 may detect an error of the synchronization signal ESYNC.

[0216] The second comparator 114 may compare the number of lost flips MT with a predetermined value, and when the number of lost flips MT is greater than the predetermined value, the second comparator 114 may output a second signal SG2 .

[0217] The lost flip count code may include a value specified for each predetermined value. The lost flip count code may correspond to a value consisting of three bits. The lost flip count code may store a value of 3'b000 specified relative to 0, a value of 3'b001 specified relative to 1, and a value of 3'b111 specified relative to 8. However, this is only an example, and the lost flip count code according to an embodiment of the present disclosure is not limited thereto. For example, the predetermined value may indicate the minimum number of lost flip MTs that can synchronize the second clock signal CLK2 with the first clock signal CLK1 based on the synchronization signal ESYNC even if a lost flip MT occurs.

[0218] When the lost flip count code is 3'b111, the second comparator 114 may set the predetermined value to 8, and may determine whether the number of lost flip MTs exceeds 8. When the number of lost flip MTs exceeds 8, the second comparator 114 may output the second signal SG2. When the number of lost flip MTs does not exceed 8 and the normal synchronization signal ESYNC is received, the second comparator 114 may not output the second signal SG2.

[0219] As another example, when the lost flip count code is 3'b001, the second comparator 114 may set the predetermined value to 1, and may determine whether the number of lost flip MTs exceeds 1. When the number of lost flip MTs exceeds 1, the second comparator 114 may output the second signal SG2. When the number of lost flip MTs does not exceed 1 and the normal synchronization signal ESYNC is received, the second comparator 114 may not output the second signal SG2.

[0220] The signal output circuit 120 may receive the second signal SG2. When the signal output circuit 120 receives the second signal SG2, the signal output circuit 120 may generate an error flag signal ERF and may output the error flag signal ERF to the host processor AP.

[0221] When the host processor AP receives the error flag signal ERF, the host processor AP may initialize the drive controller TED by outputting a reset signal RST to the drive controller TED. The host processor AP may deactivate the reset signal RST at the initialization time point tr and then may activate the reset signal RST.

[0222] At the initialization time point tr when the reset signal RST is deactivated, the drive controller TED may operate in the on mode PWR UP again. When the drive controller TED enters the on mode PWR UP, the drive controller TED may be initialized. In this case, the output of the second signal SG2 and the error flag signal ERF may be stopped. For example, after the initialization time point tr, the second signal SG2 and the error flag signal ERF may not be output.

[0223] The reset signal RST may be activated again. When the reset signal RST is activated, the drive controller TED may operate in the sleep mode Sleep in.

[0224] In the sleep mode Sleep in, the host processor AP may output the activated synchronization signal ESYNC to the drive controller TED again.

[0225] At a first time point t1 , the host processor AP may output a sleep exit command to the drive controller TED.

[0226] The drive controller TED that has received the sleep exit command may operate in the sleep exit mode Sleep out.

[0227] At the second time point t2, the host processor AP may output a display on command instructing the driving controller TED to output the frame data DATA stored in the buffer.

[0228] The drive controller TED receiving the display on command may operate in a display on mode Display on.

[0229] From the second time point t2, the second counter 113 may check whether the synchronization signal ESYNC is received. When the synchronization signal ESYNC is normally output, the second counter 113 may not count the number of lost flip MTs.

[0230] According to the present disclosure, in the event that an error occurs in the synchronization signal ESYNC, the drive controller TED can detect the error and can perform a recovery operation to ensure the normal reception of the synchronization signal ESYNC. Even if an error occurs in the synchronization signal ESYNC, the drive controller TED can receive the normal synchronization signal ESYNC through the recovery operation. The drive controller TED can synchronize the second clock signal CLK2 with the first clock signal CLK1 based on the synchronization signal ESYNC. Therefore, flickering due to a fine skew difference of the horizontal synchronization signal can be prevented. In addition, divergence of the horizontal synchronization signal due to the clock difference between the host processor AP and the drive controller TED can be prevented. Therefore, an electronic device 1000 with improved display quality and improved reliability can be provided.

[0231] Fig.11 is a timing diagram showing the operation of the electronic device according to an embodiment of the present disclosure. Fig.11 In the description of Figure 4 The described components are labeled by the same reference numerals / symbols, and thus, additional description will be omitted to avoid redundancy.

[0232] Fig.11 The operation of the electronic device when an initial synchronization failure error occurs is shown.

[0233] Reference Figure 2 , Figure 6 , Figure 7 and Fig.11 The drive controller TED can sequentially operate in a shutdown mode PWR DN, an open mode PWRUP, a sleep mode Sleep in, and a sleep exit mode Sleep out.

[0234] During operation of the electronic device 1000, the activated synchronization signal ESYNC may not be provided from the host processor AP to the drive controller TED. The case where the drive controller TED fails to receive the activated synchronization signal ESYNC may be referred to as a case where an initial synchronization failure error occurs.

[0235] The error detector 110 may detect an error of the synchronization signal ESYNC. The error detector 110 may operate after a sleep exit mode Sleep out in which the driving controller TED operates.

[0236] The first counter 111 may check whether the synchronization signal ESYNC is received at a first time point t1 (the first time point t1 is a time point when the sleep mode Sleepin is switched to the sleep exit mode Sleep out), and may count the failure time IT in which the synchronization signal ESYNC is not received. For example, the first counter 111 may not check whether the synchronization signal ESYNC provided before the first time point t1 is received. The first counter 111 may output the failure time IT to the first comparator 112.

[0237] When the activated synchronization signal ESYNC is normally output after the first time point t1 , the first counter 111 may determine that an initial synchronization failure error does not occur and may not count the failure time IT.

[0238] After the first time point t1, the first comparator 112 may compare the failure time IT with a given initial time. When the failure time IT is greater than the initial time, the first comparator 112 may output a first signal SG1.

[0239] When the first signal SG1 is output from the error detector 110, the drive controller TED may operate in the sleep mode Sleepin. The time point when the drive controller TED operates in the sleep mode Sleepin may be referred to as the sleep time point ts. After the first signal SG1 is output, the sleep time point ts may be provided. When the first signal SG1 is output, the drive controller TED may be automatically initialized. The drive controller TED may provide a signal indicating the initialization of the drive controller TED to the host processor AP. For example, the signal indicating the initialization of the drive controller TED may include a flag signal, etc.

[0240] When the driving controller TED operates in the sleep mode Sleep in, the output of the first signal SG1 may be stopped.

[0241] After the drive controller TED is initialized, a synchronization signal ESYNC may be provided. The host processor AP may output a sleep exit command to the drive controller TED. For example, the host processor AP may determine that the drive controller TED enters the sleep mode Sleep in based on a signal indicating that the drive controller TED is initialized, and may output a sleep exit command. The drive controller TED may operate in the sleep exit mode Sleep out in response to the sleep exit command.

[0242] Thereafter, the first counter 111 may check whether the synchronization signal ESYNC is received. When the synchronization signal ESYNC is normally output, the first counter 111 may not count the failure time IT.

[0243] According to an embodiment of the present disclosure, in the event that an error occurs in the synchronization signal ESYNC, the drive controller TED can detect the error and can perform a recovery operation to ensure the normal reception of the synchronization signal ESYNC. Even if an error occurs in the synchronization signal ESYNC, the drive controller TED can receive the normal synchronization signal ESYNC through the recovery operation. The drive controller TED can synchronize the second clock signal CLK2 with the first clock signal CLK1 based on the synchronization signal ESYNC. Therefore, flickering due to a fine skew difference of the horizontal synchronization signal can be prevented. In addition, divergence of the horizontal synchronization signal due to the clock difference between the host processor AP and the drive controller TED can be prevented. Therefore, an electronic device 1000 with improved display quality and improved reliability can be provided.

[0244] According to the above description, in the case of an error in the synchronization signal, the drive controller can detect the situation and can perform a recovery operation to ensure the reception of a normal synchronization signal. Even if an error occurs in the synchronization signal, the drive controller can receive a normal synchronization signal through a recovery operation. The drive controller can synchronize the clock signal with the clock signal of the host processor based on the synchronization signal. Therefore, flickering caused by a fine skew difference of the horizontal synchronization signal can be prevented. In addition, divergence of the horizontal synchronization signal caused by the clock difference between the host processor and the drive controller can be prevented. Therefore, an electronic device with improved display quality and improved reliability can be provided.

[0245] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the claims.

Claims

1. An electronic device, comprising: A host processor configured to generate a first clock signal and output frame data and a synchronization signal, wherein the synchronization signal is flipped based on the first clock signal; a drive controller connected to the host processor and configured to receive the synchronization signal and the frame data from the host processor and generate a control signal based on a second clock signal; and A display panel is configured to be driven based on the control signal, wherein the driving controller synchronizes the second clock signal with the first clock signal based on the synchronization signal, The drive controller includes an error detector configured to detect an error in the synchronization signal. wherein the error is one of an initial synchronization failure error indicating that the drive controller has not received the synchronization signal and a synchronization loss error indicating that a portion of the synchronization signal is omitted, and Wherein, when the error is the initial synchronization failure error, the error detector outputs a first signal; and when the error is the synchronization loss error, the error detector outputs a second signal different from the first signal.

2. The electronic device according to claim 1, wherein: The error detector comprises: a first counter configured to check whether the synchronization signal is received at a first time point, and to count a failure time during which the synchronization signal is not received; and A first comparator is configured to compare the failure time with an initial time after the first time point, and output the first signal when the failure time is greater than the initial time.

3. The electronic device according to claim 2, wherein: The first time point is a time point when the driving controller switches from the sleep mode to the sleep exit mode.

4. The electronic device according to claim 1, wherein: The error detector comprises: a second counter configured to count the number of consecutive missing flips of the synchronization signal, wherein the number of consecutive missing flips corresponds to the number of times the flip of the synchronization signal is not recognized; and The second comparator is configured to compare the number of lost flips with a predetermined value and output the second signal when the number of lost flips is greater than the predetermined value.

5. The electronic device according to claim 4, wherein: When the number of the lost flips is smaller than the predetermined value, the second comparator does not output the second signal.

6. The electronic device according to claim 1, wherein: The drive controller also includes: The signal output circuit is configured to generate an error flag signal when receiving the first signal or the second signal, and output the error flag signal to the host processor.

7. The electronic device according to claim 6, wherein: When the host processor receives the error flag signal, the host processor initializes the drive controller by outputting a reset signal to the drive controller.

8. The electronic device according to claim 7, wherein: When the drive controller is initialized, the error flag signal is not output.

9. The electronic device according to claim 1, wherein: When the first signal is output from the error detector, the driving controller is initialized and operates in a sleep mode.

10. The electronic device according to claim 9, wherein: When the driving controller operates in the sleep mode, the error detector does not output the first signal.

11. The electronic device according to claim 1, wherein: The drive controller and the host processor communicate with each other via a mobile industrial processor interface.

12. The electronic device according to claim 11, wherein: The driving controller outputs a tearing signal to the host processor to control a transmission period of the frame data.

13. The electronic device according to claim 12, wherein: The driving controller controls a period of the tearing signal.

14. The electronic device according to claim 11, wherein: The frame data includes a vertical valid area and a vertical blank area, and Wherein, the host processor controls the size of the vertical blank area.

15. A display device, comprising: A driving controller configured to receive a clock signal, frame data and a flipped synchronization signal, and output a scanning control signal, a data control signal and image data; as well as The display panel is controlled by the driving controller, The drive controller includes an error detector configured to detect an error in the synchronization signal. wherein the error is an initial synchronization failure error indicating that the drive controller fails to receive the synchronization signal or a synchronization loss error indicating that a portion of the synchronization signal is omitted, and Wherein, when the error is the initial synchronization failure error, the error detector outputs a first signal; and when the error is the synchronization loss error, the error detector outputs a second signal different from the first signal.

16. The display device according to claim 15, wherein: The error detector comprises: a first counter configured to check whether the synchronization signal is received at a first time point, and to count a failure time during which the synchronization signal is not received; and A first comparator is configured to compare the failure time with an initial time after the first time point, and output the first signal when the failure time is greater than the initial time.

17. The display device according to claim 15, wherein: The error detector comprises: a second counter configured to count the number of consecutive missing flips of the synchronization signal, wherein the number of consecutive missing flips corresponds to the number of times the flip of the synchronization signal is not recognized; and The second comparator is configured to compare the number of lost flips with a predetermined value and output the second signal when the number of lost flips is greater than the predetermined value.

18. The display device according to claim 15, wherein: The drive controller also includes: The signal output circuit is configured to generate an error flag signal when receiving the first signal or the second signal, and output the error flag signal.

19. The display device according to claim 15, wherein: When the first signal is output from the error detector, the driving controller is initialized and operates in a sleep mode.

20. The display device according to claim 19, wherein: When the driving controller operates in the sleep mode, the error detector does not output the first signal.

21. A method for driving an electronic device, the electronic device comprising a host processor and a drive controller communicating with each other via a mobile industrial processor interface, the method comprising: At the drive controller, receiving a synchronization signal from the host processor to synchronize a second clock signal of the drive controller with a first clock signal of the host processor; as well as detecting an error in the synchronization signal at an error detector of the drive controller, wherein the error comprises an initial synchronization failure error indicating that the drive controller has not received the synchronization signal or a synchronization loss error indicating that a portion of the synchronization signal is omitted, and The step of detecting the error of the synchronization signal comprises: When the error is the initial synchronization failure error, outputting a first signal; and When the error is the synchronization loss error, a second signal different from the first signal is output.

22. The method according to claim 21, wherein: The step of outputting the first signal comprises: checking whether the synchronization signal is received relative to a first time point; and When the synchronization signal is not received within an initial time from the first time point, the first signal is generated.

23. The method according to claim 22, wherein: The first time point is a time point when the driving controller switches from the sleep mode to the sleep exit mode.

24. The method according to claim 21, wherein: The step of outputting the second signal comprises: counting the number of consecutive missing toggles of the synchronization signal; and When the number of lost flips is greater than a predetermined value, the second signal is generated.

25. The method according to claim 21, further comprising: When the first signal or the second signal is received, an error flag signal is generated at the drive controller to be output to the host processor.

26. The method according to claim 25, further comprising: When the host processor receives the error flag signal, the drive controller is initialized based on a reset signal at the host processor.

27. The method according to claim 21, further comprising: When the first signal is output, the driving controller operates in a sleep mode.

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