Display device

Abstract

A display device includes a display panel, a gate driver, a data driver, and an emission driver. The display panel includes pixels. The gate driver is configured to provide the data write gate signal, the data initialization gate signal, and the compensation gate signal to the pixels. The data driver is configured to supply a data voltage to the pixels. The emission driver is configured to provide an emission signal to the pixel. The pixel is configured to emit light based on a data write gate signal, a data initialization gate signal, a compensation gate signal, an emission signal, and a data voltage. A frequency of at least one of the data initialization gate signal and the compensation gate signal is less than a frequency of the data write gate signal when the data write gate signal is driven at a maximum frequency in the variable frequency driving.

Description

Technical Field

[0001] Embodiments of the inventive concept relate to a display device and more particularly, to a display device that reduces power consumption by determining a frequency of at least one of a data initialization gate signal and a compensation gate signal to be lower than a frequency of a data write gate signal. Background Art

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driver includes a gate driver, a data driver, an emission driver, and a drive controller. The gate driver outputs a gate signal to a plurality of gate lines. The data driver outputs a data voltage to a plurality of data lines. The emission driver outputs an emission signal to a plurality of emission lines. The drive controller controls the gate driver, the data driver, and the emission driver.

[0003] In a display device supporting a variable frequency, data can be written to a pixel at a maximum frequency so that the frequency of a data write gate signal, the frequency of a data initialization gate signal, and the frequency of a compensation gate signal can be the same as each other. When the frequency of a data write gate signal, the frequency of a data initialization gate signal, and the frequency of a compensation gate signal can be the same as each other, the power consumption of the display device may be large. Summary of the invention

[0004] Embodiments of the inventive concept provide a display device capable of reducing power consumption of a display device supporting a variable frequency.

[0005] In an embodiment of a display device according to the present invention, the display device includes a display panel, a gate driver, a data driver and an emission driver. The display panel includes pixels. The gate driver is configured to provide a data write gate signal, a data initialization gate signal and a compensation gate signal to the pixel. The data driver is configured to provide a data voltage to the pixel. The emission driver is configured to provide an emission signal to the pixel. The pixel is configured to emit light based on the data write gate signal, the data initialization gate signal, the compensation gate signal, the emission signal and the data voltage. When the data write gate signal is driven at a maximum frequency in a variable frequency drive, the frequency of at least one of the data initialization gate signal and the compensation gate signal is less than the frequency of the data write gate signal.

[0006] In an embodiment, when the frequency of the data write gate signal is reduced in the variable frequency driving, the frequency of at least one of the data initialization gate signal and the compensation gate signal may be reduced.

[0007] In an embodiment, the frequency of the emission signal may be greater than the frequency of the data write gate signal.

[0008] In an embodiment, the frequency of the data initialization gate signal may be less than the frequency of the data write gate signal. The frequency of the compensation gate signal may be less than the frequency of the data write gate signal.

[0009] In an embodiment, the frequency of the compensation gate signal may be less than the frequency of the data write gate signal.

[0010] In an embodiment, the frequency of the data initialization gate signal may be the same as the frequency of the data write gate signal.

[0011] In an embodiment, the frequency of the emission signal may be greater than the frequency of the data writing gate signal. The frequency of the data initialization gate signal may be the same as the frequency of the emission signal.

[0012] In an embodiment, the frequency of the data initialization gate signal may be less than the frequency of the data write gate signal. The frequency of the compensation gate signal may be the same as the frequency of the data write gate signal.

[0013] In an embodiment, the pixel may include a light emitting element, a first transistor configured to apply a driving current to the light emitting element, and a second transistor configured to write a data voltage to the storage capacitor. A data write gate signal may be applied to a control electrode of the second transistor.

[0014] In an embodiment, the pixel may further include a third transistor connected between a control electrode of the first transistor and the second electrode of the first transistor. The compensation gate signal may be applied to the control electrode of the third transistor.

[0015] In an embodiment, the pixel may further include a fifth transistor configured to apply a reference voltage to the second electrode of the second transistor. The compensation gate signal may be applied to a control electrode of the fifth transistor.

[0016] In an embodiment, the pixel may further include a fourth transistor configured to apply an initialization voltage to a control electrode of the first transistor. A data initialization gate signal may be applied to the control electrode of the fourth transistor.

[0017] In an embodiment, a pixel may include: a first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a control electrode configured to receive a data write gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to a fourth node; a third transistor including a control electrode configured to receive a compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the third node; a fourth transistor including a control electrode configured to receive a data initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the first node; a fifth transistor including a control electrode configured to receive a compensation gate signal, a first electrode configured to receive a reference voltage, and a second electrode connected to the fourth node; a sixth transistor including a control electrode configured to receive a second emission signal, a first electrode connected to the a first electrode of a third node and a second electrode connected to the anode electrode of the light-emitting element; a seventh transistor, including a control electrode configured to receive an initialization gate signal of the light-emitting element, a first electrode configured to receive an initialization voltage, and a second electrode connected to the anode electrode of the light-emitting element; an eighth transistor, including a control electrode configured to receive an initialization gate signal of the light-emitting element, a first electrode configured to receive a bias voltage, and a second electrode connected to the second node; a ninth transistor, including a control electrode configured to receive a first emission signal, a first electrode configured to receive a high power voltage, and a second electrode connected to the second node; a holding capacitor, including a first electrode configured to receive a high power voltage and a second electrode connected to a fourth node; a storage capacitor, including a first electrode connected to the fourth node and a second electrode connected to the first node; and a light-emitting element, including an anode electrode and a cathode electrode configured to receive a low power voltage.

[0018] In an embodiment, the data initialization gate signal may have a valid pulse in the data initialization period. The compensation gate signal may have a non-valid pulse in the data initialization period. The data write gate signal may have a non-valid level in the data initialization period. The data initialization gate signal may have a non-valid level in the compensation period. The compensation gate signal may have a valid pulse in the compensation period. The data write gate signal may have a non-valid level in the compensation period. The data initialization gate signal may have a non-valid level in the data write period. The compensation gate signal may have a non-valid level in the data write period. The data write gate signal may have a valid pulse in the data write period.

[0019] In an embodiment, the data initialization cycle and the compensation cycle may be repeated multiple times before the data writing cycle.

[0020] In an embodiment, a pixel may include: a first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a control electrode configured to receive a data write gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to a fourth node; a third transistor including a control electrode configured to receive a compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the third node; a fourth transistor including a control electrode configured to receive a data initialization gate signal, a first electrode configured to receive a first initialization voltage, and a second electrode connected to the first node; a fifth transistor including a control electrode configured to receive a compensation gate signal, a first electrode configured to receive a reference voltage, and a second electrode connected to the fourth node; a sixth transistor including a control electrode configured to receive a second emission signal, a first electrode connected to the a first electrode of a third node and a second electrode connected to the anode electrode of the light-emitting element; a seventh transistor, including a control electrode configured to receive an initialization gate signal of the light-emitting element, a first electrode configured to receive a second initialization voltage, and a second electrode connected to the anode electrode of the light-emitting element; an eighth transistor, including a control electrode configured to receive an initialization gate signal of the light-emitting element, a first electrode configured to receive a bias voltage, and a second electrode connected to the second node; a ninth transistor, including a control electrode configured to receive a first emission signal, a first electrode configured to receive a high power voltage, and a second electrode connected to the second node; a holding capacitor, including a first electrode configured to receive a high power voltage and a second electrode connected to a fourth node; a storage capacitor, including a first electrode connected to the fourth node and a second electrode connected to the first node; and a light-emitting element, including an anode electrode and a cathode electrode configured to receive a low power voltage.

[0021] In an embodiment of a display device according to the present invention, the display device includes a display panel, a gate driver, a data driver and an emission driver. The display panel includes pixels. The gate driver is configured to provide a gate signal to the pixel. The data driver is configured to provide a data voltage to the pixel. The emission driver is configured to provide an emission signal to the pixel. The pixel is configured to emit light based on a data write gate signal, a data initialization gate signal, a compensation gate signal, an emission signal and a data voltage. The data initialization gate signal has a valid pulse in a first cycle. The compensation gate signal has a valid pulse in the first cycle. The data write gate signal has a valid pulse in the first cycle. The emission signal has a valid period in the first cycle. The data initialization gate signal does not have a valid pulse in a second cycle after the first cycle. The compensation gate signal does not have a valid pulse in the second cycle. The data write gate signal does not have a valid pulse in the second cycle. The emission signal has a valid period in the second cycle. At least one of the data initialization gate signal and the compensation gate signal does not have a valid pulse in a third cycle after the second cycle. The data write gate signal has a valid pulse in the third cycle. The emission signal has a valid period in the third cycle.

[0022] In an embodiment, the data initialization gate signal may not have a valid pulse in the third period. The compensation gate signal may not have a valid pulse in the third period.

[0023] In an embodiment, the data initialization gate signal may have a valid pulse in the third period. The compensation gate signal may not have a valid pulse in the third period.

[0024] In an embodiment, the data initialization gate signal may not have a valid pulse in the third period. The compensation gate signal may have a valid pulse in the third period.

[0025] According to the display device, in a display device supporting a variable frequency, the frequency of at least one of the data initialization gate signal and the compensation gate signal may be set to be different from the frequency of the data write gate signal, so that the power consumption of the display device can be reduced. For example, in a display device supporting a variable frequency, the frequency of at least one of the data initialization gate signal and the compensation gate signal may be set to be less than the frequency of the data write gate signal, so that the power consumption of the display device can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other features and advantages of the present invention will become more apparent by describing detailed embodiments of the present invention with reference to the accompanying drawings, in which:

[0027] Figure 1 is a block diagram illustrating a display device according to an embodiment of the inventive concept;

[0028] Figure 2 It is shown Figure 1 A schematic diagram of a driving frequency of a display panel;

[0029] Figure 3 It is shown Figure 1 A circuit diagram of an example of a pixel of a display panel;

[0030] Figure 4 It is shown Figure 3 A timing diagram of a driving signal of a pixel;

[0031] Figure 5 is shown in the variable frequency drive Figure 3 A timing diagram of a driving signal of a pixel;

[0032] Figure 6 is a graph showing that when the driving frequency of the display panel is the maximum frequency Figure 3 A timing diagram of an example of a driving signal of a pixel;

[0033] Figure 7 It shows that when the driving frequency of the display panel is less than the maximum frequency Figure 3 A timing diagram of an example of a driving signal of a pixel;

[0034] Figure 8 is a timing diagram illustrating an example of a driving signal of a pixel when a driving frequency of a display panel is a maximum frequency according to an embodiment of the inventive concept;

[0035] Fig. 9 is a timing diagram illustrating an example of a driving signal of a pixel when a driving frequency of a display panel is a maximum frequency according to an embodiment of the inventive concept;

[0036] Fig.10 is a timing diagram illustrating an example of a driving signal of a pixel when a driving frequency of a display panel is a maximum frequency according to an embodiment of the inventive concept;

[0037] Fig.11 It is shown Figure 1 A circuit diagram of an example of a pixel of a display panel;

[0038] Fig.12 is a block diagram illustrating an electronic device according to an embodiment of the inventive concept; and

[0039] Fig.13 It shows that Fig.12 The electronic device is implemented as an example of a smart phone. DETAILED DESCRIPTION

[0040] Hereinafter, the inventive concept will be explained in detail with reference to the accompanying drawings.

[0041] Figure 1 is a block diagram illustrating a display device according to an embodiment of the inventive concept.

[0042] Reference Figure 1 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0043] The display panel 100 has a display area on which an image is displayed and a peripheral area disposed adjacent to the display area.

[0044] The display panel 100 includes a plurality of gate lines GWL, GCL, GIL, and EBL, a plurality of data lines DL, a plurality of emission lines EM1L and EM2L, and a plurality of pixels electrically connected to the gate lines GWL, GCL, GIL, and EBL, the data lines DL, and the emission lines EM1L and EM2L. The gate lines GWL, GCL, GIL, and EBL may extend in a first direction D1, the data lines DL may extend in a second direction D2 crossing the first direction D1, and the emission lines EM1L and EM2L may extend in the first direction D1.

[0045] The driving controller 200 receives input image data IMG and input control signal CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0046] The driving controller 200 generates a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , a fourth control signal CONT4 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0047] The driving controller 200 generates a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0048] The driving controller 200 generates a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0049] The driving controller 200 generates a data signal DATA based on the input image data IMG. The driving controller 200 outputs the data signal DATA to the data driver 500.

[0050] The driving controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the third control signal CONT3 to the gamma reference voltage generator 400 .

[0051] The driving controller 200 generates a fourth control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT, and outputs the fourth control signal CONT4 to the emission driver 600 .

[0052] The gate driver 300 generates a gate signal driving the gate lines GWL, GCL, GIL, and EBL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may sequentially output the gate signal to the gate lines GWL, GCL, GIL, and EBL.

[0053] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to a level of the data signal DATA.

[0054] In an embodiment, the gamma reference voltage generator 400 may be embedded in the driving controller 200 or in the data driver 500 .

[0055] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200, and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into a data voltage of an analog type using the gamma reference voltage VGREF received from the gamma reference voltage generator 400. The data driver 500 outputs the data voltage to the data line DL.

[0056] The emission driver 600 generates an emission signal to drive the emission lines EM1L and EM2L in response to the fourth control signal CONT4 received from the driving controller 200. The emission driver 600 may output the emission signal to the emission lines EM1L and EM2L.

[0057] Although for ease of explanation, Figure 1 In the embodiment, the gate driver 300 is disposed at a first side of the display panel 100 and the emission driver 600 is disposed at a second side of the display panel 100 opposite to the first side, but the inventive concept is not limited thereto. For example, both the gate driver 300 and the emission driver 600 may be disposed at a first side of the display panel 100. For example, the gate driver 300 and the emission driver 600 may be integrally formed. For example, both the gate driver 300 and the emission driver 600 may be disposed at both sides of the display panel 100.

[0058] Figure 2 It is shown Figure 1 Schematic diagram of the driving frequency of the display panel 100.

[0059] Reference Figure 1 and Figure 2 , the display panel 100 may be driven at a variable frequency. A first frame FR1 having a first frequency may include a first effective period AC1 and a first blanking period BL1. A second frame FR2 having a second frequency different from the first frequency may include a second effective period AC2 and a second blanking period BL2. A third frame FR3 having a third frequency different from the first frequency and the second frequency may include a third effective period AC3 and a third blanking period BL3.

[0060] The first active period AC1 may have the same length as that of the second active period AC2. The first blank period BL1 may have a different length from that of the second blank period BL2.

[0061] The second active period AC2 may have the same length as that of the third active period AC3. The second blank period BL2 may have a different length from that of the third blank period BL3.

[0062] The display device supporting variable frequency may include a data write duration in which a data voltage is written to a pixel and a self scan duration in which only light emission is performed without writing a data voltage to the pixel. The data write duration may be set in the active periods AC1, AC2, and AC3. The self scan duration may be set in the blanking periods BL1, BL2, and BL3.

[0063] Figure 3 It is shown Figure 1 FIG. 1 is a circuit diagram of an example of a pixel of the display panel 100 .

[0064] Reference Figures 1 to 3 , the pixel may emit light based on the data write gate signal GW, the data initialization gate signal GI, the compensation gate signal GC, the emission signals EM1 and EM2, and the data voltage VDATA.

[0065] The frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC may be different from the frequency of the data write gate signal GW. The frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC may be lower than the frequency of the data write gate signal GW. When the data write gate signal GW is driven at the maximum frequency in the variable frequency driving, the frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC may be lower than the frequency of the data write gate signal GW.

[0066] The pixel includes a light emitting element EE, a first transistor T1 applying a driving current to the light emitting element EE, and a second transistor T2 writing a data voltage VDATA to a storage capacitor CST. A data write gate signal GW may be applied to a control electrode of the second transistor T2.

[0067] The pixel may further include a third transistor T3 connected to a control electrode of the first transistor T1 and a second electrode of the first transistor T1. A compensation gate signal GC may be applied to the control electrode of the third transistor T3.

[0068] The pixel may further include a fifth transistor T5 applying a reference voltage VREF to the second electrode of the second transistor T2. A compensation gate signal GC may be applied to a control electrode of the fifth transistor T5.

[0069] The pixel may further include a fourth transistor T4 applying the initialization voltage VINT to the control electrode of the first transistor T1. A data initialization gate signal GI may be applied to the control electrode of the fourth transistor T4.

[0070] Specifically, the pixel may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9, the first transistor T1 including a control electrode connected to the first node N1, a first electrode connected to the second node N2 and a second electrode connected to the third node N3, the second transistor T2 including a control electrode receiving a data write gate signal GW, a first electrode receiving a data voltage VDATA and a second electrode connected to the fourth node N4, the third transistor T3 including a control electrode receiving a compensation gate signal GC, a first electrode connected to the first node N1 and a second electrode connected to the third node N3, the fourth transistor T4 including a control electrode receiving a data initialization gate signal GI, a first electrode receiving an initialization voltage VINT and a second electrode connected to the first node N1 The fifth transistor T5 includes a control electrode receiving a compensation gate signal GC, a first electrode receiving a reference voltage VREF, and a second electrode connected to a fourth node N4. The sixth transistor T6 includes a control electrode receiving a second emission signal EM2, a first electrode connected to a third node N3, and a second electrode connected to an anode electrode of the light-emitting element EE. The seventh transistor T7 includes a control electrode receiving a light-emitting element initialization gate signal EB, a first electrode receiving an initialization voltage VINT, and a second electrode connected to the anode electrode of the light-emitting element EE. The eighth transistor T8 includes a control electrode receiving a light-emitting element initialization gate signal EB, a first electrode receiving a bias voltage VBIAS, and a second electrode connected to the second node N2. The ninth transistor T9 includes a control electrode receiving a first emission signal EM1, a first electrode receiving a high power voltage ELVDD, and a second electrode connected to the second node N2.

[0071] The pixel may further include a holding capacitor CHOLD including a first electrode receiving the high power voltage ELVDD and a second electrode connected to a fourth node N4 and a storage capacitor CST including a first electrode connected to the fourth node N4 and a second electrode connected to the first node N1.

[0072] An anode electrode of the light emitting element EE may be connected to the sixth transistor T6 and the seventh transistor T7. A cathode electrode of the light emitting element EE may receive the low power voltage ELVSS.

[0073] The pixel circuit of the present invention may not be limited to Figure 3 The present invention can be applied to a pixel circuit having Figure 3 The structure of the pixels is similar to that of Figure 3 The pixels of are operated similarly.

[0074] Figure 4It is shown Figure 3 Timing diagram of the pixel driving signal. Figure 4 Indicates the gate signal in the data write duration in which the data voltage VDATA is written to the pixel.

[0075] Reference Figures 1 to 4 In the data initialization periods DU1 and DU3, the data initialization gate signal GI may have an effective level, the compensation gate signal GC may have an ineffective level, and the data write gate signal GW may have an ineffective level. In the data initialization periods DU1 and DU3, the first emission signal EM1 may have an effective level, the second emission signal EM2 may have an ineffective level, and the light emitting element initialization gate signal EB may have an ineffective level.

[0076] In the data initialization periods DU1 and DU3 , the initialization voltage VINT may be applied to the first node N1 .

[0077] In the compensation periods DU2 and DU4, the data initialization gate signal GI may have an inactive level, the compensation gate signal GC may have an active pulse, and the data write gate signal GW may have an inactive level. In the compensation periods DU2 and DU4, the first emission signal EM1 may have an active level, the second emission signal EM2 may have an inactive level, and the light emitting element initialization gate signal EB may have an inactive level.

[0078] In the compensation periods DU2 and DU4 , the reference voltage VREF may be applied to the fourth node N4 , and the threshold voltage of the first transistor T1 may be compensated.

[0079] In the data write period DU5, the data initialization gate signal GI may have a non-active level, the compensation gate signal GC may have a non-active level, and the data write gate signal GW may have a valid pulse. In the data write period DU5, the first emission signal EM1 may have a non-active level, the second emission signal EM2 may have a non-active level, and the light emitting element initialization gate signal EB may have a non-active level.

[0080] In the data write period DU5 , the data voltage VDATA may be written into the storage capacitor CST.

[0081] In the light emitting element initialization and bias period DU6, the data initialization gate signal GI may have a non-active level, the compensation gate signal GC may have a non-active level, and the data write gate signal GW may have a non-active level. In the light emitting element initialization and bias period DU6, the first emission signal EM1 may have a non-active level, the second emission signal EM2 may have a non-active level, and the light emitting element initialization gate signal EB may have a valid pulse. For example, in the light emitting element initialization and bias period DU6, the light emitting element initialization gate signal EB may have a plurality of valid pulses.

[0082] In the light emitting element initialization and bias period DU6 , the initialization voltage VINT may be applied to the anode electrode of the light emitting element EE, and the bias voltage VBIAS may be applied to the second node N2 .

[0083] In the light emitting period DU7, the data initialization gate signal GI may have a non-active level, the compensation gate signal GC may have a non-active level, the data write gate signal GW may have a non-active level, and the light emitting element initialization gate signal EB may have a non-active level. In the light emitting period DU7, the first emission signal EM1 may have an active level, and the second emission signal EM2 may have an active level.

[0084] In the light emitting period DU7 , the light emitting element EE may emit light corresponding to the data voltage VDATA.

[0085] like Figure 4 As shown in FIG, the data initialization cycle and the compensation cycle may be repeated multiple times before the data writing cycle DU5. Figure 4 The data initialization cycle and the compensation cycle are repeated twice before the data write cycle DU5, but the inventive concept is not limited thereto. Alternatively, the data initialization cycle and the compensation cycle may be repeated three times before the data write cycle DU5. Alternatively, the data initialization cycle and the compensation cycle may be run only once before the data write cycle DU5. In addition, the number of operations of the data initialization cycle and the number of operations of the compensation cycle may be different from each other.

[0086] Figure 5 is shown in the variable frequency drive Figure 3 Timing diagram of the pixel driving signal.

[0087] Reference Figures 1 to 5 , the display panel 100 may be driven at a variable frequency. For example, the display panel 100 may be driven at a maximum frequency of 240 Hz.

[0088] When the display panel 100 is driven at a frequency of 240 Hz (maximum frequency), the data write gate signal GW may have valid pulses in the first period P1, the third period P3, the fifth period P5, and the seventh period P7, so that the data write operation may be performed in the first period P1, the third period P3, the fifth period P5, and the seventh period P7. When the display panel 100 is driven at a frequency of 240 Hz, the light emitting operation may be performed once every two periods.

[0089] When the display panel 100 is driven at a frequency of 160 Hz, the data write gate signal GW may have valid pulses in the first period P1, the fourth period P4, and the seventh period P7, so that the data write operation may be performed in the first period P1, the fourth period P4, and the seventh period P7. When the display panel 100 is driven at a frequency of 160 Hz, the light emitting operation may be performed once every three periods.

[0090] When the display panel 100 is driven at a frequency of 120 Hz, the data write gate signal GW may have a valid pulse in the first period P1 and the fifth period P5, so that the data write operation may be performed in the first period P1 and the fifth period P5. When the display panel 100 is driven at a frequency of 120 Hz, a light emitting operation may be performed every four periods.

[0091] When the display panel 100 is driven at a frequency of 96 Hz, the data write gate signal GW may have valid pulses in the first period P1 and the sixth period P6, so that the data write operation may be performed in the first period P1 and the sixth period P6. When the display panel 100 is driven at a frequency of 96 Hz, the light emitting operation may be performed once every five periods.

[0092] When the display panel 100 is driven at a frequency of 80 Hz, the data write gate signal GW may have valid pulses in the first period P1 and the seventh period P7, so that the data write operation may be performed in the first period P1 and the seventh period P7. When the display panel 100 is driven at a frequency of 80 Hz, the light emitting operation may be performed once every six periods.

[0093] When the display panel 100 is driven at a frequency of 68 Hz (about 68.57 Hz), the data write gate signal GW may have a valid pulse in the first period P1 and the eighth period P8, so that the data write operation may be performed in the first period P1 and the eighth period P8. When the display panel 100 is driven at a frequency of 68 Hz, the light emitting operation may be performed once every seven periods.

[0094] When the display panel 100 is driven at a frequency of 60 Hz, the data write gate signal GW may have a valid pulse in the first period P1 and the ninth period, so that the data write operation may be performed in the first period P1 and the ninth period. When the display panel 100 is driven at a frequency of 60 Hz, a light emitting operation may be performed every eight periods.

[0095] When the display panel 100 is driven at a frequency of 240 Hz, the light emitting operations EM1 and EM2 of the light emitting element EE may be performed at a frequency of 480 Hz, and the initialization operation EB of the light emitting element EE may be performed at a frequency of 480 Hz.

[0096] As explained above, when the display panel 100 is driven at a frequency of 240 Hz and the emission operation is performed at a frequency of 480 Hz, it can be said that the display panel 100 operates in two cycles.

[0097] Although the display panel 100 is driven at a frequency less than 240 Hz, the light emitting operations EM1 and EM2 of the light emitting element EE may be performed at a frequency of 480 Hz, and the initialization operation EB of the light emitting element EE may be performed at a frequency of 480 Hz.

[0098] Figure 6 is a graph showing that when the driving frequency of the display panel 100 is the maximum frequency (240 Hz) Figure 3 FIG. 1 is a timing diagram of an example of a driving signal for a pixel. Figure 7 is a graph showing that when the driving frequency of the display panel 100 is less than the maximum frequency Figure 3 FIG. 1 is a timing diagram of an example of a driving signal for a pixel.

[0099] Figure 6 represents a driving signal of a pixel when the driving frequency of the display panel 100 is 240 Hz. Figure 7 represents a driving signal of a pixel when the driving frequency of the display panel 100 is 120 Hz.

[0100] Reference Figures 1 to 7 , the frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC is lower than the frequency of the data write gate signal GW.

[0101] In this embodiment, if Figure 6 As shown in , the frequency of the data initialization gate signal GI may be lower than the frequency of the data write gate signal GW, and the frequency of the compensation gate signal GC may be lower than the frequency of the data write gate signal GW.

[0102] Herein, when determining the frequency of the data initialization gate signal GI, the frequency of the compensation gate signal GC, and the frequency of the data write gate signal GW, it is not considered that the signal has a plurality of pulses within one cycle (one frame).

[0103] For example, the data write gate signal GW is Figure 6 The first period P1, the third period P3, the fifth period P5 and the seventh period P7 in the data writing gate signal GW have valid pulses, so that the frequency of the data writing gate signal GW is Figure 6 Medium can be 240Hz.

[0104] The data initialization gate signal GI is Figure 6 The first period P1 and the fifth period P5 in the data initialization gate signal GI have valid pulses, so that the frequency of the data initialization gate signal GI is Figure 6 Medium can be 120Hz.

[0105] The compensation gate signal GC is Figure 6 The first period P1 and the fifth period P5 in the embodiment have effective pulses, so that the frequency of the compensation gate signal GC is Figure 6 Medium can be 120Hz.

[0106] Although for ease of explanation, Figure 6 , the frequency of the data initialization gate signal GI and the frequency of the compensation gate signal GC are half the frequency of the data write gate signal GW, but the inventive concept is not limited thereto.

[0107] The frequency of the emission signals EM1 and EM2 may be greater than the frequency of the data write gate signal GW.

[0108] exist Figure 6 In the first cycle P1, the data initialization gate signal GI has a valid pulse, the compensation gate signal GC has a valid pulse, the data writing gate signal GW has a valid pulse, and the emission signals EM1 and EM2 have a valid cycle. Figure 6 In the first period P1, the light emitting element initialization gate signal EB has a valid pulse. Figure 6 The first period P1 may be a normal data writing duration in which data initialization, threshold voltage compensation, data writing, and light emission operate.

[0109] exist Figure 6 After the first cycle P1 Figure 6 In the second period P2, the data initialization gate signal GI has no valid pulse, the compensation gate signal GC has no valid pulse, the data writing gate signal GW has no valid pulse, and the emission signals EM1 and EM2 have valid periods. Figure 6 In the second period P2, the light emitting element initialization gate signal EB has a valid pulse. Figure 6 The second period P2 may be a self-scan duration in which data initialization, threshold voltage compensation, and data writing are not executed but light emission is executed.

[0110] exist Figure 6 After the second cycle P2 Figure 6 In the third period P3 of , at least one of the data initialization gate signal GI and the compensation gate signal GC does not have a valid pulse, the data write gate signal GW has a valid pulse, and the emission signals EM1 and EM2 have a valid period. Figure 6 In the third period P3, the light emitting element initialization gate signal EB has a valid pulse.

[0111] In this embodiment, Figure 6 In the third period P3 of FIG. 1 , the data initialization gate signal GI has no valid pulse, and the compensation gate signal GC has no valid pulse.

[0112] Figure 6 The third period P3 of may be a power down duration in which the data initialization gate signal GI and the compensation gate signal GC do not have a valid pulse but the data write gate signal GW has a valid pulse.

[0113] Figure 6 After the third cycle P3 Figure 6 The fourth period P4 may be a self-scan duration in which data initialization, threshold voltage compensation, and data writing operations are not performed but light emission is performed.

[0114] Figure 6 The fifth period P5 after the fourth period P4 in the Figure 6 The first period P1 is similar to the conventional data writing duration. Figure 6 The sixth period P6 after the fifth period P5 in the Figure 6 The second period P2 is similar to the self-scanning duration. Figure 6 The seventh cycle P7 after the sixth cycle P6 in the Figure 6 The third period P3 has a similar power reduction duration. Figure 6 The eighth cycle P8 after the seventh cycle P7 in the Figure 6 The fourth cycle P4 is similar to the self-scanning duration.

[0115] Figure 7 represents a case where the driving frequency of the display panel 100 is reduced from the maximum frequency in the variable frequency driving. When the frequency of the data writing gate signal GW is reduced in the variable frequency driving, the frequencies of the data initializing gate signal GI and the compensation gate signal GC may also be reduced.

[0116] Figure 7 The first period P1 may be a normal data writing duration in which data initialization, threshold voltage compensation, data writing, and light emission operate.

[0117] Figure 7 The second to fourth periods P2 to P4 and the sixth to eighth periods P6 to P8 may be self-scan durations in which data initialization, threshold voltage compensation, and data writing are not operated but light emission is operated.

[0118] Figure 7 The fifth period P5 may be a power down duration in which the data initialization gate signal GI and the compensation gate signal GC do not have a valid pulse but the data write gate signal GW has a valid pulse.

[0119] According to the present embodiment, in a display device supporting a variable frequency, the frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC can be set to be different from the frequency of the data write gate signal GW, so that the power consumption of the display device can be reduced. For example, in a display device supporting a variable frequency, the frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC can be set to be lower than the frequency of the data write gate signal GW, so that the power consumption of the display device can be reduced.

[0120] Figure 8 1 is a timing diagram illustrating an example of a driving signal of a pixel when the driving frequency of the display panel 100 is a maximum frequency according to an embodiment of the inventive concept.

[0121] In addition to the fact that the frequency of the compensation gate signal GC is less than the frequency of the data writing gate signal GW and the frequency of the data initialization gate signal GI is the same as the frequency of the data writing gate signal GW, the pixel driving signal according to the present embodiment is Figure 6 Therefore, the same or similar reference numerals will be used to represent the same pixel driving signals as those of Figures 1 to 7 The present invention relates to components that are the same or like as those described in the previous embodiments of the present invention, and any repeated explanation regarding the above elements will be omitted.

[0122] Reference Figures 1 to 5 and Figure 8 , the pixel can emit light based on the data writing gate signal GW, the data initialization gate signal GI, the compensation gate signal GC, the emission signals EM1 and EM2, and the data voltage VDATA. The pixel in this embodiment can be connected with Figure 3 The pixels in are the same or different.

[0123] The frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC may be different from the frequency of the data write gate signal GW. The frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC may be lower than the frequency of the data write gate signal GW. When the data write gate signal GW is driven at the maximum frequency in the variable frequency driving, the frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC may be lower than the frequency of the data write gate signal GW.

[0124] In this embodiment, if Figure 8 As shown in , the frequency of the data initialization gate signal GI may be the same as the frequency of the data write gate signal GW, and the frequency of the compensation gate signal GC may be less than the frequency of the data write gate signal GW.

[0125] exist Figure 8 In the first cycle P1, the data initialization gate signal GI has a valid pulse, the compensation gate signal GC has a valid pulse, the data writing gate signal GW has a valid pulse, and the emission signals EM1 and EM2 have a valid cycle. Figure 8 In the first period P1, the light emitting element initialization gate signal EB has a valid pulse. Figure 8 The first period P1 may be a normal data writing duration in which data initialization, threshold voltage compensation, data writing, and light emission operate.

[0126] exist Figure 8 After the first cycle P1 Figure 8 In the second period P2, the data initialization gate signal GI has no valid pulse, the compensation gate signal GC has no valid pulse, the data writing gate signal GW has no valid pulse, and the emission signals EM1 and EM2 have valid periods. Figure 8 In the second period P2, the light emitting element initialization gate signal EB has a valid pulse. Figure 8 The second period P2 may be a self-scan duration in which data initialization, threshold voltage compensation, and data writing are not executed but light emission is executed.

[0127] exist Figure 8 After the second cycle P2 Figure 8 In the third period P3 of , at least one of the data initialization gate signal GI and the compensation gate signal GC does not have a valid pulse, the data write gate signal GW has a valid pulse, and the emission signals EM1 and EM2 have a valid period. Figure 8 In the third period P3, the light emitting element initialization gate signal EB has a valid pulse.

[0128] In this embodiment, Figure 8In the third period P3 of FIG. 1 , the data initialization gate signal GI has a valid pulse, and the compensation gate signal GC has no valid pulse.

[0129] Figure 8 The third period P3 of may be a power reduction duration in which the compensation gate signal GC has no valid pulse but the data initialization gate signal GI and the data write gate signal GW have valid pulses.

[0130] According to the present embodiment, in a display device supporting a variable frequency, the frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC can be set to be different from the frequency of the data write gate signal GW, so that the power consumption of the display device can be reduced. For example, in a display device supporting a variable frequency, the frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC can be set to be lower than the frequency of the data write gate signal GW, so that the power consumption of the display device can be reduced.

[0131] Fig. 9 1 is a timing diagram illustrating an example of a driving signal of a pixel when the driving frequency of the display panel 100 is a maximum frequency according to an embodiment of the inventive concept.

[0132] Except that the frequency of the data initialization gate signal GI is less than the frequency of the data writing gate signal GW and the frequency of the compensation gate signal GC is the same as the frequency of the data writing gate signal GW, the pixel driving signal according to the present embodiment is Figure 6 Therefore, the same or similar reference numerals will be used to represent the same pixel driving signals as those of Figures 1 to 7 The same or similar components to those described in the previous embodiments of the present invention will be described below, and any repeated explanation regarding the above elements will be omitted.

[0133] Reference Figures 1 to 5 and Fig. 9 , the pixel can emit light based on the data writing gate signal GW, the data initialization gate signal GI, the compensation gate signal GC, the emission signals EM1 and EM2, and the data voltage VDATA. The pixel in this embodiment can be connected with Figure 3 The pixels in are the same or different.

[0134] The frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC may be different from the frequency of the data write gate signal GW. The frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC may be lower than the frequency of the data write gate signal GW. When the data write gate signal GW is driven at the maximum frequency in the variable frequency driving, the frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC may be lower than the frequency of the data write gate signal GW.

[0135] In this embodiment, if Fig. 9 As shown in , the frequency of the compensation gate signal GC may be the same as the frequency of the data write gate signal GW, and the frequency of the data initialization gate signal GI may be less than the frequency of the data write gate signal GW.

[0136] exist Fig. 9 In the first cycle P1, the data initialization gate signal GI has a valid pulse, the compensation gate signal GC has a valid pulse, the data writing gate signal GW has a valid pulse, and the emission signals EM1 and EM2 have a valid cycle. Fig. 9 In the first period P1, the light emitting element initialization gate signal EB has a valid pulse. Fig. 9 The first period P1 may be a normal data writing duration in which data initialization, threshold voltage compensation, data writing, and light emission operate.

[0137] exist Fig. 9 After the first cycle P1 Fig. 9 In the second period P2, the data initialization gate signal GI has no valid pulse, the compensation gate signal GC has no valid pulse, the data writing gate signal GW has no valid pulse, and the emission signals EM1 and EM2 have valid periods. Fig. 9 In the second period P2, the light emitting element initialization gate signal EB has a valid pulse. Fig. 9 The second period P2 may be a self-scan duration in which data initialization, threshold voltage compensation, and data writing operations are not performed but light emission is performed.

[0138] exist Fig. 9 After the second cycle P2 Fig. 9 In the third period P3 of , at least one of the data initialization gate signal GI and the compensation gate signal GC does not have a valid pulse, the data write gate signal GW has a valid pulse, and the emission signals EM1 and EM2 have a valid period. Fig. 9 In the third period P3, the light emitting element initialization gate signal EB has a valid pulse.

[0139] In this embodiment, Fig. 9 In the third period P3 of FIG. 1 , the data initialization gate signal GI has no valid pulse, and the compensation gate signal GC has a valid pulse.

[0140] Fig. 9 The third period P3 of may be a power down duration in which the data initialization gate signal GI has no valid pulse but the compensation gate signal GC and the data write gate signal GW have valid pulses.

[0141] According to the present embodiment, in a display device supporting a variable frequency, the frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC can be set to be different from the frequency of the data write gate signal GW, so that the power consumption of the display device can be reduced. For example, in a display device supporting a variable frequency, the frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC can be set to be lower than the frequency of the data write gate signal GW, so that the power consumption of the display device can be reduced.

[0142] Fig.10 1 is a timing diagram illustrating an example of a driving signal of a pixel when the driving frequency of the display panel 100 is a maximum frequency according to an embodiment of the inventive concept.

[0143] The pixel driving signal according to the present embodiment is the same as the frequency of the compensation gate signal GC except that the frequency of the compensation gate signal GC is less than the frequency of the data writing gate signal GW and the frequency of the data initialization gate signal GI is the same as the frequency of the emission signals EM1 and EM2. Figure 6 Therefore, the same or similar reference numerals will be used to represent the same pixel driving signals as those of Figures 1 to 7 The present invention relates to components that are the same as or similar to those described in the previous embodiments, and any repeated explanation regarding the above elements will be omitted.

[0144] Reference Figures 1 to 5 and Fig.10 , the pixel can emit light based on the data writing gate signal GW, the data initialization gate signal GI, the compensation gate signal GC, the emission signals EM1 and EM2, and the data voltage VDATA. The pixel in this embodiment can be connected with Figure 3 The pixels in are the same or different.

[0145] The frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC may be different from the frequency of the data write gate signal GW. The frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC may be lower than the frequency of the data write gate signal GW. When the data write gate signal GW is driven at the maximum frequency in the variable frequency driving, the frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC may be lower than the frequency of the data write gate signal GW.

[0146] In this embodiment, if Fig.10 As shown in , the frequency of the data initialization gate signal GI may be the same as the frequencies of the emission signals EM1 and EM2, and the frequency of the compensation gate signal GC may be less than the frequency of the data write gate signal GW.

[0147] For example, in Fig.10In the embodiment, the waveform of the data initialization gate signal GI is the same as the waveform of the light emitting element initialization gate signal EB.

[0148] exist Fig.10 In the first cycle P1, the data initialization gate signal GI has a valid pulse, the compensation gate signal GC has a valid pulse, the data writing gate signal GW has a valid pulse, and the emission signals EM1 and EM2 have a valid cycle. Fig.10 In the first period P1, the light emitting element initialization gate signal EB has a valid pulse. Fig.10 The first period P1 may be a normal data writing duration in which data initialization, threshold voltage compensation, data writing, and light emission operate.

[0149] exist Fig.10 After the first cycle P1 Fig.10 In the second period P2, the data initialization gate signal GI has a valid pulse, the compensation gate signal GC has no valid pulse, the data writing gate signal GW has no valid pulse, and the emission signals EM1 and EM2 have a valid period. Fig.10 In the second period P2, the light emitting element initialization gate signal EB has a valid pulse. Fig.10 The second period P2 may be a self-scan duration in which threshold voltage compensation and data writing are not executed but data initialization and light emission are executed.

[0150] exist Fig.10 After the second cycle P2 Fig.10 In the third period P3 of , at least one of the data initialization gate signal GI and the compensation gate signal GC does not have a valid pulse, the data write gate signal GW has a valid pulse, and the emission signals EM1 and EM2 have a valid period. Fig.10 In the third period P3, the light emitting element initialization gate signal EB has a valid pulse.

[0151] In this embodiment, Fig.10 In the third period P3 of FIG. 1 , the data initialization gate signal GI has a valid pulse, and the compensation gate signal GC has no valid pulse.

[0152] Fig.10 The third period P3 of may be a power reduction duration in which the compensation gate signal GC has no valid pulse but the data initialization gate signal GI and the data write gate signal GW have valid pulses.

[0153] According to the present embodiment, in a display device supporting a variable frequency, the frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC can be set to be different from the frequency of the data write gate signal GW, so that the power consumption of the display device can be reduced. For example, in a display device supporting a variable frequency, the frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC can be set to be lower than the frequency of the data write gate signal GW, so that the power consumption of the display device can be reduced.

[0154] Fig.11 It is shown Figure 1 FIG. 1 is a circuit diagram of an example of a pixel of the display panel 100 .

[0155] In addition to the second initialization voltage VAINT applied to the seventh transistor T7 being different from the first initialization voltage VINT applied to the fourth transistor T4, the pixel and Figure 3 Therefore, the same or similar reference numerals will be used to represent the same Figures 1 to 7 The same or similar components to those described in the previous embodiments of the present invention will be described below, and any repeated explanation regarding the above elements will be omitted.

[0156] Reference Figure 1 , Figure 2 , Figures 4 to 7 and Fig.11 , the pixel may emit light based on the data write gate signal GW, the data initialization gate signal GI, the compensation gate signal GC, the emission signals EM1 and EM2, and the data voltage VDATA.

[0157] The frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC may be different from the frequency of the data write gate signal GW. The frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC may be lower than the frequency of the data write gate signal GW. When the data write gate signal GW is driven at the maximum frequency in the variable frequency driving, the frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC may be lower than the frequency of the data write gate signal GW.

[0158] The pixel includes a light emitting element EE, a first transistor T1 applying a driving current to the light emitting element EE, and a second transistor T2 writing a data voltage VDATA to a storage capacitor CST. A data write gate signal GW may be applied to a control electrode of the second transistor T2.

[0159] The pixel may further include a third transistor T3 connected to a control electrode of the first transistor T1 and a second electrode of the first transistor T1. A compensation gate signal GC may be applied to the control electrode of the third transistor T3.

[0160] The pixel may further include a fifth transistor T5 applying a reference voltage VREF to the second electrode of the second transistor T2. A compensation gate signal GC may be applied to a control electrode of the fifth transistor T5.

[0161] The pixel may further include a fourth transistor T4 applying the first initialization voltage VINT to the control electrode of the first transistor T1. A data initialization gate signal GI may be applied to the control electrode of the fourth transistor T4.

[0162] Specifically, the pixel may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9, the first transistor T1 includes a control electrode connected to the first node N1, a first electrode connected to the second node N2 and a second electrode connected to the third node N3, the second transistor T2 includes a control electrode receiving a data write gate signal GW, a first electrode receiving a data voltage VDATA and a second electrode connected to the fourth node N4, the third transistor T3 includes a control electrode receiving a compensation gate signal GC, a first electrode connected to the first node N1 and a second electrode connected to the third node N3, the fourth transistor T4 includes a control electrode receiving a data initialization gate signal GI, a first electrode receiving a first initialization voltage VINT and a second electrode connected to the first node N1 The fifth transistor T5 includes a control electrode receiving a compensation gate signal GC, a first electrode receiving a reference voltage VREF, and a second electrode connected to a fourth node N4. The sixth transistor T6 includes a control electrode receiving a second emission signal EM2, a first electrode connected to a third node N3, and a second electrode connected to an anode electrode of the light emitting element EE. The seventh transistor T7 includes a control electrode receiving a light emitting element initialization gate signal EB, a first electrode receiving a second initialization voltage VAINT, and a second electrode connected to the anode electrode of the light emitting element EE. The eighth transistor T8 includes a control electrode receiving a light emitting element initialization gate signal EB, a first electrode receiving a bias voltage VBIAS, and a second electrode connected to the second node N2. The ninth transistor T9 includes a control electrode receiving a first emission signal EM1, a first electrode receiving a high power voltage ELVDD, and a second electrode connected to the second node N2.

[0163] The pixel may further include a holding capacitor CHOLD including a first electrode receiving the high power voltage ELVDD and a second electrode connected to a fourth node N4 and a storage capacitor CST including a first electrode connected to the fourth node N4 and a second electrode connected to the first node N1.

[0164] An anode electrode of the light emitting element EE may be connected to the sixth transistor T6 and the seventh transistor T7. A cathode electrode of the light emitting element EE may receive the low power voltage ELVSS.

[0165] The pixel circuit of the present invention may not be limited to Fig.11 The present invention can be applied to a pixel circuit having Fig.11 The structure of the pixels is similar to that of Fig.11 The pixels of operate similarly.

[0166] According to the present embodiment, in a display device supporting a variable frequency, the frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC can be set to be different from the frequency of the data write gate signal GW, so that the power consumption of the display device can be reduced. For example, in a display device supporting a variable frequency, the frequency of at least one of the data initialization gate signal GI and the compensation gate signal GC can be set to be lower than the frequency of the data write gate signal GW, so that the power consumption of the display device can be reduced.

[0167] Fig.12 is a block diagram illustrating an electronic device according to an embodiment of the inventive concept. Fig.13 It shows that Fig.12 The electronic device is implemented as an example of a smart phone.

[0168] Reference Figures 1 to 13 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may be Figure 1 In addition, the electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0169] In an embodiment, Fig.13 As shown in , the electronic device 1000 can be implemented as a smart phone. However, the electronic device 1000 is not limited thereto. For example, the electronic device 1000 can be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet personal computer (PC), a car navigation system, a computer monitor, a laptop computer, and a head mounted display (HMD) device, etc.

[0170] The processor 1010 may perform various computing functions or various tasks. The processor 1010 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 1010 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 1010 may be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0171] The processor 1010 can output the input image data IMG and the input control signal CONT to Figure 1 A drive controller 200 is provided.

[0172] The memory device 1020 may store data used for the operation of the electronic device 1000. For example, the memory device 1020 may include at least one nonvolatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device, etc.).

[0173] The storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, and a compact disk read-only memory (CD-ROM) device, etc. The I / O device 1040 may include input devices such as a keyboard, a keypad, a mouse device, a touch pad, and a touch screen, etc., and output devices such as a printer and a speaker, etc. In some embodiments, a display device 1060 may be included in the I / O device 1040. The power supply 1050 may provide power for the operation of the electronic device 1000. The display device 1060 may be coupled to other components via a bus or other communication link.

[0174] According to the display device of the present embodiment as explained above, power consumption can be reduced in the display device supporting a variable frequency.

[0175] The foregoing is an illustration of the inventive concept and will not be construed as a limitation on the inventive concept. Although several example embodiments of the inventive concept have been described, it will be readily appreciated by those skilled in the art that many modifications in the example embodiments are possible without departing substantially from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the means-plus-function clause is intended to cover the structure described herein as performing the described function, and includes not only structural equivalents but also equivalent structures. Therefore, it will be understood that the foregoing is an illustration of the inventive concept and will not be construed as being limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims. The inventive concept is defined by the appended claims, and the equivalents of the claims are included herein.

Claims

1. A display device, wherein: The display device comprises: A display panel, including pixels; a gate driver configured to provide a data write gate signal, a data initialization gate signal, and a compensation gate signal to the pixel; a data driver configured to provide a data voltage to the pixel; and an emission driver configured to provide an emission signal to the pixel, wherein the pixel is configured to emit light based on the data writing gate signal, the data initialization gate signal, the compensation gate signal, the emission signal and the data voltage, When the data writing gate signal is driven at a maximum frequency in the variable frequency driving, a frequency of at least one of the data initialization gate signal and the compensation gate signal is smaller than a frequency of the data writing gate signal.

2. The display device according to claim 1, wherein: When the frequency of the data write gate signal decreases in the variable frequency driving, the frequency of at least one of the data initialization gate signal and the compensation gate signal decreases.

3. The display device according to claim 1, wherein: The frequency of the emission signal is greater than the frequency of the data write gate signal.

4. The display device according to claim 1, wherein: The frequency of the data initialization gate signal is less than the frequency of the data write gate signal, and Wherein, the frequency of the compensation gate signal is less than the frequency of the data writing gate signal.

5. The display device according to claim 1, wherein: A frequency of the compensation gate signal is less than the frequency of the data writing gate signal.

6. The display device according to claim 5, wherein: The frequency of the data initialization gate signal is the same as the frequency of the data write gate signal.

7. The display device according to claim 5, wherein: The frequency of the emission signal is greater than the frequency of the data write gate signal, and Wherein, the frequency of the data initialization gate signal is the same as the frequency of the emission signal.

8. The display device according to claim 1, wherein: The frequency of the data initialization gate signal is less than the frequency of the data write gate signal, and The frequency of the compensation gate signal is the same as the frequency of the data writing gate signal.

9. The display device according to claim 1, wherein: The pixels include: Light emitting element; a first transistor configured to apply a driving current to the light emitting element; and a second transistor configured to write the data voltage to the storage capacitor, and The data writing gate signal is applied to the control electrode of the second transistor.

10. The display device according to claim 9, wherein: The pixel further includes a third transistor connected between a control electrode of the first transistor and a second electrode of the first transistor, and The compensation gate signal is applied to the control electrode of the third transistor.

11. The display device according to claim 10, wherein: The pixel further includes a fifth transistor configured to apply a reference voltage to a second electrode of the second transistor, and The compensation gate signal is applied to the control electrode of the fifth transistor.

12. The display device according to claim 9, wherein: The pixel further includes a fourth transistor configured to apply an initialization voltage to a control electrode of the first transistor, and The data initialization gate signal is applied to the control electrode of the fourth transistor.

13. The display device according to claim 1, wherein: The pixels include: a first transistor including a control electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node; a second transistor including a control electrode configured to receive the data write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to a fourth node; a third transistor including a control electrode configured to receive the compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the third node; a fourth transistor including a control electrode configured to receive the data initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the first node; a fifth transistor including a control electrode configured to receive the compensation gate signal, a first electrode configured to receive a reference voltage, and a second electrode connected to the fourth node; a sixth transistor including a control electrode configured to receive a second emission signal, a first electrode connected to the third node, and a second electrode connected to an anode electrode of the light emitting element; a seventh transistor including a control electrode configured to receive a light emitting element initialization gate signal, a first electrode configured to receive the initialization voltage, and a second electrode connected to the anode electrode of the light emitting element; an eighth transistor including a control electrode configured to receive the light emitting element initialization gate signal, a first electrode configured to receive a bias voltage, and a second electrode connected to the second node; a ninth transistor including a control electrode configured to receive the first transmission signal, a first electrode configured to receive the high power voltage, and a second electrode connected to the second node; a holding capacitor including a first electrode configured to receive the high power voltage and a second electrode connected to the fourth node; a storage capacitor including a first electrode connected to the fourth node and a second electrode connected to the first node; and The light emitting element includes the anode electrode and a cathode electrode configured to receive a low power voltage.

14. The display device according to claim 13, wherein: The data initialization gate signal has a valid pulse in the data initialization period. Wherein, the compensation gate signal has a non-valid pulse in the data initialization period, wherein the data writing gate signal has a non-effective level during the data initialization period, wherein the data initialization gate signal has a non-effective level during the compensation period, wherein the compensation gate signal has a valid pulse in the compensation period, wherein the data writing gate signal has the non-valid level in the compensation period, wherein the data initialization gate signal has the non-valid level during the data writing cycle, wherein the compensation gate signal has the non-valid level during the data writing cycle, and The data writing gate signal has a valid pulse in the data writing cycle.

15. The display device according to claim 14, wherein: The data initialization period and the compensation period are repeated a plurality of times before the data writing period.

16. The display device according to claim 1, wherein: The pixels include: a first transistor including a control electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node; a second transistor including a control electrode configured to receive the data write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to a fourth node; a third transistor including a control electrode configured to receive the compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the third node; a fourth transistor including a control electrode configured to receive the data initialization gate signal, a first electrode configured to receive a first initialization voltage, and a second electrode connected to the first node; a fifth transistor including a control electrode configured to receive the compensation gate signal, a first electrode configured to receive a reference voltage, and a second electrode connected to the fourth node; a sixth transistor including a control electrode configured to receive a second emission signal, a first electrode connected to the third node, and a second electrode connected to an anode electrode of the light emitting element; a seventh transistor including a control electrode configured to receive a light emitting element initialization gate signal, a first electrode configured to receive a second initialization voltage, and a second electrode connected to the anode electrode of the light emitting element; an eighth transistor including a control electrode configured to receive the light emitting element initialization gate signal, a first electrode configured to receive a bias voltage, and a second electrode connected to the second node; a ninth transistor including a control electrode configured to receive the first transmission signal, a first electrode configured to receive the high power voltage, and a second electrode connected to the second node; a holding capacitor including a first electrode configured to receive the high power voltage and a second electrode connected to the fourth node; a storage capacitor including a first electrode connected to the fourth node and a second electrode connected to the first node; and The light emitting element includes the anode electrode and a cathode electrode configured to receive a low power voltage.

Images