Drive controller and display device

Abstract

The invention relates to a driving controller and a display device. The drive controller includes: an overcurrent load calculator that calculates a load of an input image signal, compares the load with a reference load, and outputs a first signal corresponding to a first comparison result; an overcurrent reference controller analyzing a gray level of the input image signal and outputting, as a reference current signal, one of a first reference current signal and a second reference current signal corresponding to the gray level, the current level of the second reference current signal being higher than the current level of the first reference current signal; a current sensor receiving the feedback current signal, comparing a current level of the feedback current signal with a current level of the reference current signal, and outputting a second signal corresponding to a second comparison result; and a voltage controller outputting a voltage control signal for adjusting a voltage level of the driving voltage based on the first signal and the second signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0080308 filed in the Korean Intellectual Property Office on June 22, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure described herein relate to a driving controller and a display device including the driving controller. Background Art

[0004] An electronic device that provides an image to a user, such as a smart phone, a digital camera, a notebook computer, a navigation system, a monitor, or a smart TV, includes a display device for displaying the image. The display device generates an image and provides the generated image to the user through a display screen.

[0005] The display device includes a display panel and a driving controller for controlling the display panel. When the driving controller provides a data signal to the display panel and a current corresponding to the data signal is provided to pixels of the display panel, a given image may be displayed.

[0006] In order to prevent the power consumption of the display device from increasing, the driving controller may adjust the brightness of the display panel according to the load of the input image signal. For example, when the load of the input image signal is relatively large, the driving controller may reduce the brightness of the display panel; when the load of the input image signal is relatively small, the driving controller may not reduce the brightness of the display panel. Summary of the invention

[0007] Embodiments of the present disclosure provide a driving controller capable of preventing excessive power consumption of a display panel and a display device including the driving controller.

[0008] According to an embodiment, a driving controller may include an overcurrent load calculator, an overcurrent reference controller, a current sensor, and a voltage controller. The overcurrent load calculator calculates a load of an input image signal, compares the load with a reference load, and outputs a first signal corresponding to a first comparison result. The overcurrent reference controller analyzes a grayscale of the input image signal, and outputs one of a first reference current signal and a second reference current signal corresponding to the grayscale as a reference current signal, wherein a current level of the second reference current signal is higher than a current level of the first reference current signal. The current sensor receives a feedback current signal, compares a current level of the feedback current signal with a current level of the reference current signal, and outputs a second signal corresponding to a second comparison result. The voltage controller outputs a voltage control signal for adjusting a voltage level of a driving voltage based on the first signal and the second signal.

[0009] In an embodiment, when the load corresponding to the input image signal belongs to a first load area, the overcurrent reference controller can output the first reference current signal as the reference current signal; and when the load corresponding to the input image signal belongs to a second load area different from the first load area, the overcurrent reference controller can output the second reference current signal as the reference current signal.

[0010] In an embodiment, when the voltage level of the predicted voltage signal corresponding to the gray level is lower than the voltage level of the target voltage signal, the overcurrent reference controller may output the first reference current signal as the reference current signal; and when the voltage level of the predicted voltage signal corresponding to the gray level is higher than or equal to the voltage level of the target voltage signal, the overcurrent reference controller may output the second reference current signal as the reference current signal.

[0011] In an embodiment, when the load is lower than the reference load, the overcurrent load calculator may output the first signal of a valid level.

[0012] In an embodiment, when the current level of the feedback current signal is higher than the current level of the reference current signal, the current sensor may output the second signal of the active level.

[0013] In an embodiment, when both the first signal and the second signal are at the active level, the voltage controller may output the voltage control signal such that the voltage level of the driving voltage decreases.

[0014] In an embodiment, when the load is higher than or equal to the reference load, the overcurrent load calculator may output the first signal of a non-active level.

[0015] In an embodiment, the overcurrent reference controller may include: a grayscale analyzer, which analyzes the grayscale of the input image signal, and the grayscale analyzer outputs a maximum grayscale in a frame; a power control block, which outputs a predicted voltage signal based on the maximum grayscale and the load; and an overcurrent reference setting block, which compares the predicted voltage signal and a target voltage signal, and the overcurrent reference setting block outputs one of the first reference current signal and the second reference current signal as the reference current signal according to a third comparison result.

[0016] In an embodiment, when the voltage level of the predicted voltage signal is lower than the voltage level of the target voltage signal, the overcurrent reference setting block may output the first reference current signal as the reference current signal; and when the voltage level of the predicted voltage signal is higher than or equal to the voltage level of the target voltage signal, the overcurrent reference setting block may output the second reference current signal as the reference current signal.

[0017] In an embodiment, the overcurrent load calculator may include: a power brightness controller that calculates the load of the input image signal; and an overcurrent control determiner that outputs the first signal corresponding to the first comparison result of the load and the reference load.

[0018] In an embodiment, when the load is lower than the reference load, the overcurrent control determiner may output the first signal of a valid level; and when the load is higher than or equal to the reference load, the overcurrent control determiner may output the first signal of a non-valid level.

[0019] According to an embodiment, a display device may include: a display panel; a driving controller receiving an input image signal and outputting an image data signal; a data driving circuit providing a data signal corresponding to the image data signal to the display panel; and a voltage generator providing a driving voltage to the display panel in response to a voltage control signal. The driving controller may include an overcurrent load calculator, an overcurrent reference controller, a current sensor, and a voltage controller. The overcurrent load calculator calculates a load of the input image signal, compares the load with a reference load, and outputs a first signal corresponding to a first comparison result. The overcurrent reference controller analyzes a grayscale of the input image signal and outputs one of a first reference current signal and a second reference current signal corresponding to the grayscale as a reference current signal, the current level of the second reference current signal being higher than the current level of the first reference current signal. The current sensor receives a feedback current signal from the display panel, compares the current level of the feedback current signal with the current level of the reference current signal, and outputs a second signal corresponding to a second comparison result. The voltage controller outputs the voltage control signal based on the first signal and the second signal.

[0020] In an embodiment, when the voltage level of the predicted voltage signal corresponding to the gray level is lower than the voltage level of the target voltage signal, the overcurrent reference controller may output the first reference current signal as the reference current signal; and when the voltage level of the predicted voltage signal corresponding to the gray level is higher than or equal to the voltage level of the target voltage signal, the overcurrent reference controller may output the second reference current signal as the reference current signal.

[0021] In an embodiment, when the load is lower than the reference load, the overcurrent load calculator may output the first signal of a valid level; and when the load is higher than or equal to the reference load, the overcurrent load calculator may output the first signal of a non-valid level.

[0022] In an embodiment, when the current level of the feedback current signal is higher than the current level of the reference current signal, the current sensor may output the second signal of the active level.

[0023] In an embodiment, when both the first signal and the second signal are at the active level, the voltage controller may output the voltage control signal such that the voltage level of the driving voltage decreases.

[0024] In an embodiment, the overcurrent reference controller may include: a grayscale analyzer, which analyzes the grayscale of the input image signal, and the grayscale analyzer outputs a maximum grayscale in a frame; a power control block, which outputs a predicted voltage signal based on the maximum grayscale and the load; and an overcurrent reference setting block, which compares the predicted voltage signal and a target voltage signal, and the overcurrent reference setting block outputs one of the first reference current signal and the second reference current signal as the reference current signal according to a third comparison result.

[0025] In an embodiment, when the voltage level of the predicted voltage signal is lower than the voltage level of the target voltage signal, the overcurrent reference setting block may output the first reference current signal as the reference current signal; and when the voltage level of the predicted voltage signal is higher than or equal to the voltage level of the target voltage signal, the overcurrent reference setting block may output the second reference current signal as the reference current signal.

[0026] In an embodiment, the overcurrent load calculator may include: a power brightness controller that calculates the load of the input image signal; and an overcurrent control determiner that outputs the first signal corresponding to the first comparison result of the load and the reference load.

[0027] In an embodiment, the power brightness controller may output the data signal obtained by adjusting the gray level of the input image signal based on the load. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other features of the present disclosure will become apparent by describing the embodiments of the present disclosure in detail with reference to the attached drawings.

[0029] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0030] Figure 2 is an exploded perspective view of a display device according to an embodiment of the present disclosure.

[0031] Figure 3 is a block diagram of a display device according to an embodiment of the present disclosure.

[0032] Figure 4 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0033] Figure 5 is a block diagram showing the configuration of a drive controller.

[0034] Figure 6 It is shown Figure 5A block diagram of the configuration of the power brightness controller is shown in FIG.

[0035] Figure 7 It is shown Figure 6 The data output unit scale factors are shown in the diagram.

[0036] Figure 8 is a graph showing a first reference current signal and a second reference current signal according to a load.

[0037] Fig. 9 is a diagram showing a change in the voltage level of a predicted voltage signal according to a load.

[0038] Fig.10 is a graph showing a relationship between a feedback current signal and first and second reference current signals in a state in which an overcurrent event does not occur.

[0039] Fig.11A is a graph showing a feedback current signal when the same reference current signal is applied regardless of the load.

[0040] Fig. 11B is a diagram showing a feedback current signal when one of a first reference current signal and a second reference current signal is selected as a reference current signal according to a load.

[0041] Fig. 12A It shows that according to Fig.11A . A graph of the first driving voltage of the feedback current signal is shown in FIG.

[0042] Fig. 12B It shows that according to Fig. 11B . A graph of the first driving voltage of the feedback current signal is shown in FIG.

[0043] Fig.13A It shows that according to Fig.11A The feedback current signal and Fig. 12A Graph of power consumption for the first driving voltage shown in FIG.

[0044] Fig. 13B It shows that according to Fig. 11B The feedback current signal and Fig. 12B Graph of power consumption for the first driving voltage shown in FIG.

[0045] Fig.14A is a graph showing a feedback current signal and power consumption according to the operation of a display device when a consistent reference current signal is applied regardless of a load.

[0046] Fig. 14Bis a graph showing a feedback current signal and power consumption according to operation of a display device when one of a first reference current signal and a second reference current signal is selected as a reference current signal according to a load. DETAILED DESCRIPTION

[0047] In this specification, the statement that a first component (or region, layer, part, etc.) is "on", "connected to" or "coupled to" a second component means that the first component is directly on, directly connected to or directly coupled to the second component, or that a third component is interposed therebetween.

[0048] The same reference numerals / symbols refer to the same components. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated for the effectiveness of the description of the technical content. The term "and / or" includes one or more combinations of the related listed items.

[0049] The terms "first", "second", etc. are used to describe various components, but the components are not limited by these terms. These terms are only used to distinguish one component from another component. For example, without departing from the scope and spirit of the present invention, the first component can be referred to as the "second component", and similarly, the second component can be referred to as the "first component". The articles "one", "a (kind / person)" and "the (the)" are singular because they have a single referent, but the use of the singular form in the specification should not exclude the presence of more than one referent.

[0050] In addition, the terms "below", "under", "on", "over", etc. are used to describe the relationship between components shown in the drawings. These terms are relative and are described with reference to the directions indicated in the drawings.

[0051] It will be understood that the terms “includes,” “comprising,” “having,” etc. specify the presence of features, quantities, steps, operations, elements or components, or a combination thereof, described in the specification, and do not exclude the presence or additional possibility of one or more other features, quantities, steps, operations, elements or components, or a combination thereof.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. In addition, unless explicitly defined herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0053] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0054] Figure 1is a perspective view of a display device DD according to an embodiment of the present disclosure. Figure 2 is an exploded perspective view of a display device DD according to an embodiment of the present disclosure.

[0055] Reference Figure 1 and Figure 2 , the display device DD may be a device activated according to an electrical signal. The display device DD according to the present disclosure may be a small or medium-sized electronic device such as a mobile phone, a tablet computer, a car navigation system or a game console, and a large electronic device such as a television or a monitor. The above examples are provided only as examples, and it is obvious that the display device DD may include (a plurality of) any other display devices without departing from the concept of the present invention. The display device DD is in the shape of a rectangle having a long side (or side) in a first direction DR1 and a short side (or side) in a second direction DR2 intersecting the first direction DR1. However, the shape of the display device DD is not limited thereto. For example, the display device DD may be implemented in various shapes. The display device DD may display an image IM on a display surface IS that is parallel to each of the first direction DR1 and the second direction DR2 to face the third direction DR3. The display surface IS on which the image IM is displayed may correspond to the front surface of the display device DD.

[0056] In an embodiment, the front surface (or upper / top surface) and the rear surface (or lower / bottom surface) of each member are defined relative to the direction in which the image IM is displayed. The front surface and the rear surface may be opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3.

[0057] The separation distance between the front and rear surfaces in the third direction DR3 may correspond to the thickness of the display device DD in the third direction DR3. Meanwhile, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 may be relative in concept and may be changed to different directions.

[0058] The display device DD can sense external input applied from the outside. The external input may include various types of inputs provided from the outside of the display device DD. The display device DD according to an embodiment of the present disclosure can sense the external input of the user applied from the outside. The external input of the user may be one of various types of external inputs (such as a part of his / her body, light, heat, his / her sight and pressure, or a combination thereof). In addition, the display device DD can sense the external input of the user applied to the side surface or rear surface of the display device DD according to the structure of the display device DD, and is not limited to any one embodiment. As an example of the present disclosure, the external input may include an input applied by using an input device (e.g., a stylus, an active pen, a touch pen, an electronic pen, or an electronic-like pen).

[0059] The display surface IS of the display device DD may be divided into a display area DA and a non-display area NDA. The display area DA may refer to an area in which an image IM is displayed. A user visually perceives the image IM through the display area DA. In an embodiment, the display area DA is shown in the shape of a quadrilateral whose vertices are rounded. However, this is shown as an example. The display area DA may have various shapes and is not limited to any one embodiment.

[0060] The non-display area NDA is adjacent to the display area DA. The non-display area NDA may have a given color. The non-display area NDA may surround the display area DA. In this way, the shape of the display area DA may be substantially defined by the non-display area NDA. However, this is shown as an example. The non-display area NDA may be provided only adjacent to one side of the display area DA or may be omitted. The display device DD according to an embodiment of the present disclosure may include various embodiments and is not limited to any one embodiment.

[0061] like Figure 2 As shown in , the display device DD may include a display module DM and a window WM disposed on or over the display module DM. The display module DM may include a display panel DP and an input sensing layer ISP.

[0062] The display panel DP according to the embodiment of the present disclosure may be a light-emitting display panel. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The emission layer of the organic light-emitting display panel may include an organic light-emitting material. The emission layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. The emission layer of the quantum dot light-emitting display panel may include quantum dots, quantum rods, etc. In the following embodiments, description will be made under the condition that the display panel DP is an organic light-emitting display panel.

[0063] The display panel DP may output an image IM, and the output image IM may be displayed through the display surface IS.

[0064] The input sensing layer ISP may be disposed on the display panel DP to sense external input. The input sensing layer ISP may be disposed directly on the display panel DP. According to an embodiment of the present disclosure, the input sensing layer ISP may be formed on the display panel DP by a continuous process. That is, in a case where the input sensing layer ISP is disposed directly on the display panel DP, an internal adhesive film (not shown) is not interposed between the input sensing layer ISP and the display panel DP. However, an internal adhesive film may be interposed between the input sensing layer ISP and the display panel DP. In this case, the input sensing layer ISP is not manufactured by a process subsequent to the process of the display panel DP. That is, the input sensing layer ISP may be manufactured by a process independent of the process of the display panel DP, and may then be fixed on the upper surface of the display panel DP by an internal adhesive film.

[0065] The window WM may be formed of a transparent material capable of outputting the image IM. For example, the window WM may be formed of glass, sapphire, plastic, etc. An example is shown in which the window WM is implemented in a single layer, but the present disclosure is not limited thereto. For example, the window WM may include multiple layers.

[0066] Meanwhile, although not shown, the non-display area NDA of the above-mentioned display device DD may correspond to an area defined by printing a material including a given color on an area of ​​the window WM. As an example of the present disclosure, the window WM may include a light blocking (or shielding) pattern for defining the non-display area NDA. The light blocking pattern as a colored organic film may be formed, for example, in a coating manner.

[0067] The window WM can be coupled to the display module DM through an adhesive film. As an example of the present disclosure, the adhesive film may include an optically clear adhesive (OCA) film. However, the adhesive film is not limited thereto. For example, the adhesive film may include a typical adhesive or adhesive. For example, the adhesive film may include an optically clear resin (OCR) film or a pressure sensitive adhesive (PSA) film.

[0068] The anti-reflection layer may also be interposed between the window WM and the display module DM. The anti-reflection layer reduces the reflectivity of external light incident from above the window WM. The anti-reflection layer according to an embodiment of the present disclosure may include a phase retarder and a polarizer. The polarizer may be a film type or a liquid crystal coating type. The film type may include a stretched synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a given direction. The phase retarder and the polarizer may be implemented with one polarizing film.

[0069] As an example of the present disclosure, the anti-reflection layer may further include a color filter. Figure 3 ) determines the arrangement of the color filter. In addition, the anti-reflection layer may further include a light blocking pattern.

[0070] The display module DM may display an image IM according to an electrical signal, and may transmit / receive information about an external input. The display module DM may be defined by an active area AA and a non-active area NAA. The active area AA may be defined as an area through which an image IM provided from the display area DA is output. In addition, the active area AA may be defined as an area in which the input sensing layer ISP senses an external input applied from the outside.

[0071] The non-active area NAA is adjacent to the active area AA. For example, the non-active area NAA may surround the active area AA. However, this is shown as an example. For example, the non-active area NAA may be defined in various shapes without being limited to any one embodiment. According to an embodiment, the active area AA of the display module DM may correspond to at least a portion of the display area DA.

[0072] The display device DD may further include a main circuit board MCB, a flexible circuit film D-FCB, a driver chip DIC, a driving controller 100, and a voltage generator 300. The main circuit board MCB may be connected to the flexible circuit film D-FCB to be electrically connected to the display panel DP. The flexible circuit film D-FCB is connected to the display panel DP to electrically connect the display panel DP to the main circuit board MCB. The main circuit board MCB may include a plurality of driving elements. The plurality of driving elements may include a circuit unit for driving the display panel DP. The driver chips DIC may be mounted on the flexible circuit films D-FCB, respectively.

[0073] As an example of the present disclosure, the flexible circuit film D-FCB may include a first flexible circuit film D-FCB1, a second flexible circuit film D-FCB2, and a third flexible circuit film D-FCB3. The driver chip DIC may include a first driver chip DIC1, a second driver chip DIC2, and a third driver chip DIC3. The first flexible circuit film D-FCB1, the second flexible circuit film D-FCB2, and the third flexible circuit film D-FCB3 may be positioned to be spaced apart from each other in the first direction DR1, and may be connected to the display panel DP to electrically connect the display panel DP and the main circuit board MCB. The first driver chip DIC1 may be mounted on the first flexible circuit film D-FCB1. The second driver chip DIC2 may be mounted on the second flexible circuit film D-FCB2. The third driver chip DIC3 may be mounted on the third flexible circuit film D-FCB3. However, the present disclosure is not limited thereto. For example, the display panel DP may be electrically connected to the main circuit board MCB through one flexible circuit film, and only one driver chip may be mounted on the one flexible circuit film. In addition, the display panel DP may be electrically connected to the main circuit board MCB through four or more flexible circuit films, and driver chips may be mounted on the flexible circuit films, respectively.

[0074] Figure 2 , a structure in which the first driver chip DIC1, the second driver chip DIC2, and the third driver chip DIC3 are mounted on the first flexible circuit film D-FCB1, the second flexible circuit film D-FCB2, and the third flexible circuit film D-FCB3, respectively, is shown, but the present disclosure is not limited thereto. For example, the first driver chip DIC1, the second driver chip DIC2, and the third driver chip DIC3 may be directly mounted on the display panel DP. In this case, a portion of the display panel DP on which the first driver chip DIC1, the second driver chip DIC2, and the third driver chip DIC3 are mounted may be bent so that the first driver chip DIC1, the second driver chip DIC2, and the third driver chip DIC3 are disposed on the rear surface of the display module DM. In addition, the first driver chip DIC1, the second driver chip DIC2, and the third driver chip DIC3 may be directly mounted on the main circuit board MCB.

[0075] The input sensing layer ISP may be electrically connected to the main circuit board MCB through the display panel DP and the flexible circuit film D-FCB. However, the present disclosure is not limited thereto. That is, the display module DM may further include a separate flexible circuit film for electrically connecting the input sensing layer ISP and the main circuit board MCB.

[0076] In an embodiment, the driving controller 100 and the voltage generator 300 may be mounted on the main circuit board MCB. The driving controller 100 and the voltage generator 300 may be electrically connected to the display panel DP through the main circuit board MCB and the flexible circuit film D-FCB.

[0077] The display device DD also includes a housing EDC that accommodates the display module DM. The housing EDC may be coupled to the window WM to define the appearance of the display device DD. The housing EDC may absorb external impacts and may prevent foreign matter or moisture, etc. from penetrating into the display module DM, thereby protecting the components accommodated in the housing EDC. Meanwhile, as an example of the present disclosure, the housing EDC may be provided in the form of a combination of a plurality of accommodating members.

[0078] Figure 3 is a block diagram of a display device DD according to an embodiment of the present disclosure.

[0079] Reference Figure 3 The display device DD includes a driving controller 100, a data driving circuit 200, a voltage generator 300, a scan driving circuit 400, and a display panel DP. The driving controller 100, the data driving circuit 200, and the scan driving circuit 400 may be referred to as a driving circuit that provides data signals to the pixels PX of the display panel DP.

[0080] The driving controller 100 receives an input image signal RGB and a control signal CTRL. The driving controller 100 converts the input image signal RGB and outputs it as an image data signal DS. The driving controller 100 outputs a scan control signal SCS and a data control signal DCS. In an embodiment, the driving controller 100 may output a voltage control signal VCTRL for controlling the voltage generator 300.

[0081] The data driving circuit 200 receives a data control signal DCS and an image data signal DS from the driving controller 100. The data driving circuit 200 converts the image data signal DS into a data signal, and then outputs the data signal to a plurality of data lines DL1, DL2, . . . and DLm to be described later. The data signal is an analog voltage corresponding to a grayscale value of the image data signal DS. The data driving circuit 200 may be set at Figure 2 The driver chip shown in DIC.

[0082] The display panel DP includes first scan lines SCL1, SCL2, SCL3, . . . and SCLn, second scan lines SSL1, SSL2, SSL3, . . . and SSLn, data lines DL1 to DLm, and pixels PX, wherein m and n are each a positive integer.

[0083] The display panel DP may be divided into an active area AA and a non-active area NAA. The pixels PX may be disposed in the active area AA, and the scan driving circuit 400 may be disposed in the non-active area NAA.

[0084] The first scan lines SCL1 to SCLn and the second scan lines SSL1 to SSLn are arranged to be spaced apart from each other in the second direction DR2. The data lines DL1 to DLm extend from the data driving circuit 200 in a direction away from the second direction DR2 and are arranged to be spaced apart from each other in the first direction DR1.

[0085] The pixels PX are electrically connected to the first scan lines SCL1 to SCLn, the second scan lines SSL1 to SSLn, and the data lines DL1 to DLm. For example, the pixels PX belonging to the first row may be connected to the scan lines SCL1 and SSL1. In addition, the pixels PX belonging to the second row may be connected to the scan lines SCL2 and SSL2.

[0086] Each of the plurality of pixels PX includes a light emitting element ED (see Figure 4 ) and a pixel circuit PXC for controlling emission of the light emitting element ED (refer to Figure 4). The pixel circuit PXC may include a plurality of transistors and capacitors. The scan driving circuit 400 may include transistors formed by the same process as the pixel circuit PXC. In an embodiment, the light emitting element ED may be an organic light emitting diode. However, the present disclosure is not limited thereto.

[0087] Each of the plurality of pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, and an initialization voltage VINT.

[0088] The scan driving circuit 400 receives a scan control signal SCS from the driving controller 100. In response to the scan control signal SCS, the scan driving circuit 400 may output a first scan signal to the first scan lines SCL1 to SCLn and may output a second scan signal to the second scan lines SSL1 to SSLn.

[0089] In an embodiment, the scan driving circuit 400 may be disposed in the non-active area NAA adjacent to the first side of the active area AA. The first and second scan lines SCL1 to SCLn and SSL1 to SSLn extend from the scan driving circuit 400 in the first direction DR1.

[0090] In an embodiment, the scan driving circuits may be disposed on the first side and the second side of the active area AA, respectively. For example, the scan driving circuit disposed on the first side of the active area AA may provide a first scan signal to the first scan lines SCL1 to SCLn, and the scan driving circuit disposed on the second side of the active area AA may provide a second scan signal to the second scan lines SSL1 to SSLn.

[0091] The voltage generator 300 generates voltages required for the operation of the display panel DP. In an embodiment, the voltage generator 300 generates a first driving voltage ELVDD, a second driving voltage ELVSS, and an initialization voltage VINT required for the operation of the display panel DP. The first driving voltage ELVDD, the second driving voltage ELVSS, and the initialization voltage VINT may be provided to the display panel DP through a first voltage line VL1, a second voltage line VL2, and a third voltage line VL3, respectively.

[0092] The voltage generator 300 may generate various voltages required for operations of the display panel DP, the driving controller 100 , the data driving circuit 200 , and the scan driving circuit 400 in addition to the first driving voltage ELVDD, the second driving voltage ELVSS, and the initialization voltage VINT.

[0093] In an embodiment, the driving controller 100 may output a voltage control signal VCTRL for controlling the voltage generator 300 .

[0094] In an embodiment, the driving controller 100 may output the voltage control signal VCTRL based on the feedback current signal FI received from the display panel DP through the feedback line FL. The configuration and operation of the driving controller 100 will be described in detail later.

[0095] Figure 4 is an equivalent circuit diagram of a pixel PXij according to an embodiment of the present disclosure.

[0096] Reference Figure 4 , connected to data lines DL1 to DLm (refer to Figure 3 ), the i-th data line DLi (hereinafter also referred to as the data line DLi, where i is a positive integer less than or equal to m), the first scan lines SCL1 to SCLn (refer to Figure 3 ) among the j-th first scan line SCLj (hereinafter also referred to as the first scan line SCLj, where j is a positive integer less than or equal to n), the second scan lines SSL1 to SSLn (refer to Figure 3 ) in the j-th second scan line SSLj (hereinafter also referred to as the second scan line SSLj) as an example. Figure 4 Shown in.

[0097] Figure 3 The circuit configuration of each of the plurality of pixels PX shown in FIG. Figure 4 The equivalent circuit configuration of the pixel PXij shown in FIG. 1 is the same as that of FIG. 1 . In an embodiment, the pixel PXij includes at least one light emitting element ED and a pixel circuit PXC.

[0098] The pixel circuit PXC may include at least one transistor electrically connected to the light emitting element ED and used to provide the light emitting element ED with a current corresponding to the data signal Di transmitted from the data line DLi. In an embodiment, the pixel circuit PXC of the pixel PXij includes a first transistor T1, a second transistor T2, a third transistor T3 and a capacitor Cst. Each of the first transistor T1 to the third transistor T3 is an N-type transistor using an oxide semiconductor as a semiconductor layer. However, the present disclosure is not limited thereto. For example, each of the first transistor T1 to the third transistor T3 may be a P-type transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer. In an embodiment, at least one of the first transistor T1 to the third transistor T3 may be an N-type transistor, and the other transistors of the first transistor TR1 to the third transistor TR3 may be P-type transistors. In addition, the circuit configuration of the pixel PXij according to the present disclosure is not limited to Figure 4 . Figure 4 The pixel circuit PXC shown in FIG. 1 is provided only as an example, and the configuration of the pixel circuit PXC may be modified and implemented.

[0099] Also refer to Figure 3 The first scan line SCLj may transmit a first scan signal SCj, and the second scan line SSLj may transmit a second scan signal SSj. The data line DLi transmits a data signal Di. The data signal Di may have a signal similar to that input to the display device DD (refer to FIG. 1 ). Figure 1 )’s input image signal RGB corresponding to the voltage level.

[0100] The first and third voltage lines VL1 and VL3 may transmit the first driving voltage ELVDD and the initialization voltage VINT to the pixel circuit PXC, respectively, and the second voltage line VL2 may transmit the second driving voltage ELVSS to the cathode (or second terminal) of the light emitting element ED.

[0101] The first transistor T1 includes a first electrode connected to the first voltage line VL1, a second electrode electrically connected to the anode (or first terminal) of the light emitting element ED, and a gate electrode connected to the first end of the capacitor Cst. The first transistor T1 can supply a driving current to the light emitting element ED in response to a data signal Di transmitted through the data line DLi according to a switching operation of the second transistor T2.

[0102] The second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the gate electrode of the first transistor T1, and a gate electrode connected to the first scan line SCLj. The second transistor T2 may be turned on according to the first scan signal SCj transmitted through the first scan line SCLj, and may transmit the data signal Di from the data line DLi to the gate electrode of the first transistor T1.

[0103] The third transistor T3 includes a first electrode connected to the third voltage line VL3, a second electrode connected to the anode of the light emitting element ED, and a gate electrode connected to the second scan line SSLj. The third transistor T3 can be turned on according to the second scan signal SSj transmitted through the second scan line SSLj, and can transmit the initialization voltage VINT to the anode of the light emitting element ED.

[0104] As described above, the first end of the capacitor Cst is connected to the gate electrode of the first transistor T1, and the second end of the capacitor Cst is connected to the second electrode of the first transistor T1. Figure 4 In the pixel PXij, the number of transistors, the number of capacitors, and the connection relationship between the transistors and the capacitors can be variously changed or modified.

[0105] The pixel PXij can operate in an emission mode and a current sensing mode. In the emission mode, when the third transistor T3 is turned on, the initialization voltage VINT from the third voltage line VL3 can be transmitted to the anode of the light emitting element ED.

[0106] In the current sensing mode, when the third transistor T3 is turned on, the voltage of the anode of the light emitting element ED corresponding to the data signal Di may be transmitted to the third voltage line VL3. In an embodiment, the third voltage line VL3 may be a feedback line FL.

[0107] In an embodiment, the third voltage line VL3 and the feedback line FL may be implemented with different wirings.

[0108] Figure 5 is a block diagram showing the configuration of the drive controller 100 .

[0109] Figure 5 Only components associated with the voltage control function for adjusting power consumption among the functions of the drive controller 100 are shown. Figure 5 In addition to the components shown in FIG. 1 , the drive controller 100 may also include components associated with various functions (e.g., Figure 3 As shown in FIG, components associated with a function of converting an input image signal RGB into an image data signal DS and components associated with a function of outputting a scan control signal SCS and a data control signal DCS in response to a control signal CTRL).

[0110] Reference Figure 5 , also refer to Figure 3 The driving controller 100 includes an overcurrent reference controller 101 , an overcurrent load calculator 102 , a current sensor 160 and a voltage controller 170 .

[0111] The overcurrent reference controller 101 analyzes the grayscale of the input image signal RGB and outputs one of a first reference current signal RI1 and a second reference current signal RI2 corresponding to the grayscale as the reference current signal RI, the current level of the second reference current signal RI2 being higher than that of the first reference current signal RI1.

[0112] The overcurrent load calculator 102 calculates a load LD of the input image signal RGB, compares the load LD with a reference load L_TH, and outputs a first signal ALT_EN corresponding to the comparison result.

[0113] The current sensor 160 is connected to the display panel DP (see Figure 3 ) receives a feedback current signal FI, compares a current level of the feedback current signal FI with a current level of a reference current signal RI, and outputs a second signal ALT corresponding to the comparison result.

[0114] The voltage controller 170 outputs a voltage control signal VCTRL based on the first signal ALT_EN and the second signal ALT. The voltage control signal VCTRL may be provided to Figure 3 The voltage generator 300 shown in FIG.

[0115] The configuration and operation of the driving controller 100 will be described in detail below. The overcurrent reference controller 101 includes a gray level analyzer 110 , a power control block 120 , and an overcurrent reference setting block 130 .

[0116] The gray level analyzer 110 analyzes the gray level of the input image signal RGB of one frame. The gray level analyzer 110 detects the maximum gray level MAX of the input image signal RGB of one frame.

[0117] The power control block 120 predicts the voltage level of the first driving voltage ELVDD based on the maximum gray level MAX from the gray level analyzer 110 and the load LD from the power brightness controller 140. The power control block 120 outputs a predicted voltage signal P_ELVDD corresponding to the predicted voltage level of the first driving voltage ELVDD.

[0118] The overcurrent reference setting block 130 compares the prediction voltage signal P_ELVDD and the target voltage signal T_ELVDD, and outputs a reference current signal RI corresponding to the comparison result.

[0119] In an embodiment, each of the predicted voltage signal P_ELVDD and the target voltage signal T_ELVDD may be a digital signal.

[0120] In an embodiment, when the voltage level of the prediction voltage signal P_ELVDD is lower than the voltage level of the target voltage signal T_ELVDD, the overcurrent reference setting block 130 outputs the first reference current signal RI1 as the reference current signal RI.

[0121] In an embodiment, when the voltage level of the prediction voltage signal P_ELVDD is higher than or equal to the voltage level of the target voltage signal T_ELVDD, the overcurrent reference setting block 130 outputs the second reference current signal RI2 as the reference current signal RI.

[0122] In an embodiment, the current level of the second reference current signal RI2 is higher than the current level of the first reference current signal RI1 .

[0123] The overcurrent load calculator 102 includes a power brightness controller 140 and an overcurrent control determiner 150. The power brightness controller 140 calculates the load LD of the input image signal RGB. In an embodiment, the power brightness controller 140 can adjust the load LD to be displayed on the display panel DP (refer to Figure 3 ) displays the brightness of the image.

[0124] The overcurrent control determiner 150 compares the load LD from the power brightness controller 140 with the reference load L_TH and outputs a first signal ALT_EN corresponding to the comparison result.

[0125] In an embodiment, when the load LD is less than the reference load L_TH, the overcurrent control determiner 150 outputs the first signal ALT_EN of an active level.

[0126] When the load LD is greater than or equal to the reference load L_TH, the overcurrent control determiner 150 outputs the first signal ALT_EN of a non-active level.

[0127] The voltage controller 170 outputs a voltage control signal VCTRL based on the first signal ALT_EN and the second signal ALT. When both the first signal ALT_EN and the second signal ALT are at active levels, the voltage controller 170 may output the voltage control signal VCTRL so that the voltage level of the first driving voltage ELVDD decreases.

[0128] Figure 6 It is shown Figure 5 A block diagram of the configuration of the power brightness controller 140 is shown in FIG.

[0129] Reference Figure 6 , also refer to Figure 3 The power brightness controller 140 includes a gray level adder 141 , a load calculator 142 , a power controller 143 and a data output unit 144 .

[0130] The grayscale adder 141 sums the input image signals RGB of one frame and outputs a sum signal RGB_T.

[0131] For example, the display panel DP may be divided into a plurality of blocks, and the gray level adder 141 may calculate the sum of the respective gray levels of the blocks.

[0132] The load calculator 142 may calculate the load LD for one frame based on the sum signal RGB_T.

[0133] The load LD may have a value between 0% and 100%. For example, when the input image signal RGB corresponds to a full black image (e.g., 0 gray level), the load LD may be 0%. In addition, when the input image signal RGB corresponds to a full white image (e.g., 255 gray levels), the load LD may be 100%.

[0134] In an embodiment, the load LD output from the load calculator 142 may be provided to Figure 5 The overcurrent control determiner 150 shown in FIG.

[0135] The power controller 143 adjusts the level of the load LD according to the power consumption reference value PREF and outputs the adjusted load signal C_LD.

[0136] The data output unit 144 may output the image data signal DS obtained by adjusting the grayscale of the input image signal RGB based on the adjusted load signal C_LD.

[0137] Figure 7 It is shown Figure 6 Graph of the scaling factor SF of the data output unit 144 shown in FIG.

[0138] Reference Figure 6 and Figure 7 In order to maintain or reduce the gray level of the input image signal RGB, the data output unit 144 may calculate the scale factor SF according to the adjusted load signal C_LD. The scale factor SF may have a value less than or equal to "1". For example, when the scale factor SF is 0.5, the gray level of the image data signal DS may be reduced to half the gray level of the input image signal RGB.

[0139] In an embodiment, the scale factor SF may be a value set differently according to the adjusted load signal C_LD. For example, as the adjusted load signal C_LD increases (ie, becomes close to 100%), the scale factor SF may decrease; as the adjusted load signal C_LD decreases (ie, becomes close to 0%), the scale factor SF may increase to 1.

[0140] In the following description, for convenience of description, it is assumed that the adjusted load signal C_LD and the load LD are identical to each other.

[0141] For example, when the sum signal RGB_T of the input image signal RGB corresponds to a full white image (i.e., 255 gray levels), the scale factor SF may be 0.3. When the sum signal RGB_T corresponds to 225 gray levels, the scale factor SF may be 0.4. When the sum signal RGB_T corresponds to a full black image (i.e., 0 gray levels), the scale factor SF may be 1.

[0142] When the sum signal RGB_T of the input image signal RGB indicates a high gray level, that is, when the power consumption of the display panel DP is expected to be high, the power brightness controller 140 reduces the gray level of the image data signal DS according to the scale factor SF to be lower than the gray level of the input image signal RGB. As a result, the display panel DP (refer to Figure 3 ) is damaged due to overcurrent.

[0143] return Figure 5 When the load LD output from the power brightness controller 140 is higher than the reference load L_TH, the gray level of the image data signal DS may be adjusted by the power brightness controller 140, and thus, the display panel DP (return) may be reduced. Figure 3 ) current consumption.

[0144] When the load LD is higher than the reference load L_TH, the overcurrent control determiner 150 outputs the first signal ALT_EN of the non-active level. When the overcurrent control determiner 150 outputs the first signal ALT_EN of the non-active level, the gray level of the image data signal DS is adjusted by the power brightness controller 140, and therefore, the voltage controller 170 does not need to reduce the voltage level of the first driving voltage ELVDD. Therefore, when the first signal ALT_EN is at the non-active level, the voltage controller 170 may not change the voltage control signal VCTRL for the purpose of reducing the voltage level of the first driving voltage ELVDD.

[0145] Figure 8 is shown according to the load LD (see Figure 5 ) is a diagram of the first reference current signal RI1 and the second reference current signal RI2.

[0146] Reference Figure 5 and Figure 8 , also refer to Figure 3 , the power control block 120 predicts the voltage level of the first driving voltage ELVDD based on the maximum gray level MAX and the load LD, and outputs a predicted voltage signal P_ELVDD.

[0147] According to the relationship between the prediction voltage signal P_ELVDD and the target voltage signal T_ELVDD, the overcurrent reference setting block 130 outputs one of the first reference current signal RI1 and the second reference current signal RI2 as the reference current signal RI.

[0148] For example, when the load LD is included in the first load region LD1 , the reference current signal RI may be the first reference current signal RI1 .

[0149] For example, when the load LD is included in the second load region LD2 , the reference current signal RI may be the second reference current signal RI2 .

[0150] In an embodiment, the first load region LD1 may be a region in which the load LD is within a range of 0% to 30%, and the second load region LD2 may be a region in which the load LD is within a range of 30% to 75%.

[0151] The power control block 120 may set the current level to the first reference current signal RI1 in consideration of the maximum gray level MAX so that a current margin is ensured as much as a given current level (eg, 0.5A) when the upper limit value of the first load region LD1 (ie, load LD) is 30%.

[0152] The power control block 120 may set the current level to the second reference current signal RI2 in consideration of the maximum gray level MAX so that when the upper limit value of the second load region LD2 (ie, load LD) is 75%, a current margin as much as a given current level (eg, 0.5A) is ensured.

[0153] As reference Figure 6 and Figure 7 As described, the third load region LD3 may be a region in which the voltage controller 170 does not need to adjust the voltage level of the first driving voltage ELVDD.

[0154] Figure 8 The first load region LD1 , the second load region LD2 , the third load region LD3 , and the current margin shown in FIG. 1 are provided only as examples for better understanding of the present disclosure, and the present disclosure is not limited thereto.

[0155] When the current level of the feedback current signal FI is higher than the current level of the reference current signal RI (ie, one of the first reference current signal RI1 and the second reference current signal RI2 ), the current sensor 160 outputs the second signal ALT of an active level.

[0156] Assuming that the current load LD belongs to the first load region LD1 , when the current level of the feedback current signal FI is higher than the current level of the first reference current signal RI1 , the current sensor 160 may output the second signal ALT of an active level.

[0157] Assuming that the current load LD belongs to the second load region LD2 , when the current level of the feedback current signal FI is higher than the current level of the second reference current signal RI2 , the current sensor 160 may output the second signal ALT of an active level.

[0158] Fig. 9 is shown according to the load LD (see Figure 5 ) is a diagram showing the voltage level change of the predicted voltage signal P_ELVDD.

[0159] Reference Figure 5 and Fig. 9 , the power control block 120 outputs a prediction voltage signal P_ELVDD based on the load LD and the maximum gray level MAX. When the load LD is low, the voltage level of the prediction voltage signal P_ELVDD is high; when the load LD is higher than a given level, the voltage level of the prediction voltage signal P_ELVDD is reduced to a minimum voltage (e.g., 18V).

[0160] The overcurrent reference setting block 130 compares the prediction voltage signal P_ELVDD and the target voltage signal T_ELVDD and may output a reference current signal RI corresponding to the comparison result.

[0161] Fig.10 is a graph showing a relationship between the feedback current signal FI and the first and second reference current signals RI1 and RI2 in a state in which an overcurrent event does not occur.

[0162] Reference Figure 5 and Fig.10 , when the current load LD is lower than 30%, the reference current signal RI may be the first reference current signal RI1. In a state where no over-current event occurs, the minimum current margin of the feedback current signal FI and the first reference current signal RI1 may be 0.5A.

[0163] When the current load LD is greater than or equal to 30%, the reference current signal RI may be the second reference current signal RI2. In a state where no over-current event occurs, the minimum current margin of the feedback current signal FI and the second reference current signal RI2 may be 0.5A.

[0164] Fig.11A is shown when no matter the load LD (see Figure 5 ) is a diagram of the feedback current signal FIa when the same reference current signal RI is applied.

[0165] Reference Figure 5 and Fig.11A In an embodiment, the current level of the reference current signal RI of the overcurrent reference setting block 130 may be a consistent current level (eg, 18 A) regardless of the load LD.

[0166] When the maximum gray level MAX is a 255 gray level 255G and the load LD is 3%, the current level of the feedback current signal FIa may be lower than the current level of the reference current signal RI.

[0167] When the maximum gray level MAX is the 255 gray level 255G and the load LD is 100%, the current level of the feedback current signal FIa may increase to the current level of the reference current signal RI (ie, 18 A).

[0168] Reference Figure 6 The power brightness controller 140 described can output the image data signal DS whose gray scale is adjusted according to the load LD of the input image signal RGB. The operation of the power brightness controller 140 may take one frame time. Therefore, even if the load LD is 100%, the current level of the feedback current signal FIa can also increase to the current level of the reference current signal RI (i.e., 18A).

[0169] When the current level of the feedback current signal FIa increases to the current level of the reference current signal RI (ie, 18 A), the current sensor 160 outputs the second signal ALT of an active level.

[0170] In the skip period SKP in which the first signal ALT_EN is at the inactive level, the voltage controller 170 may not perform the voltage control operation regardless of the current level of the feedback current signal FIa.

[0171] Fig. 11B is shown when the load LD (see Figure 5 ) selects one of the first reference current signal RI1 and the second reference current signal RI2 as the reference current signal RI (see Figure 5 ) when the feedback current signal FI is .

[0172] Reference Figure 5 and Fig. 11B In an embodiment, the reference current signal RI of the overcurrent reference setting block 130 may be one of a first reference current signal RI1 and a second reference current signal RI2 depending on the load LD. In an embodiment, the current level of the first reference current signal RI1 may be lower than the current level of the second reference current signal RI2. In an embodiment, the first reference current signal RI1 may correspond to 16A, and the current level of the second reference current signal RI2 may be the same as the current level of the reference current signal RI (i.e., Fig.11A 18A) shown in FIG.

[0173] When the maximum gray level MAX is a 255 gray level 255G and the load LD is 3%, the current level of the feedback current signal FI may be lower than the current level of the first reference current signal RI1.

[0174] When the maximum gray level MAX is the 255 gray level 255G and the load LD is 100%, the current level of the feedback current signal FI may increase to the current level of the first reference current signal RI1 (ie, 16 A).

[0175] Reference Figure 6The power brightness controller 140 described can output the image data signal DS whose gray level is adjusted according to the load LD of the input image signal RGB. The operation of the power brightness controller 140 may take one frame time. Therefore, even if the load LD is 100%, the current level of the feedback current signal FI can also increase to the current level of the first reference current signal RI1 (i.e., 16A).

[0176] When the current level of the feedback current signal FI increases to the current level of the first reference current signal RI1 (ie, 16A) as the reference current signal RI, the current sensor 160 outputs the second signal ALT of an active level.

[0177] In the skip period SKP in which the first signal ALT_EN is at the inactive level, the voltage controller 170 may not perform the voltage control operation regardless of the current level of the feedback current signal FI.

[0178] Fig. 12A It shows that according to Fig.11A . A graph of the first driving voltage ELVDDa of the feedback current signal FIa is shown in FIG.

[0179] Reference Figure 5 , Fig.11A and Fig. 12A When the current level of the feedback current signal FIa is lower than the current level of the reference current signal RI, the first driving voltage ELVDDa may have a preset first voltage level (eg, 24V).

[0180] When the current level of the feedback current signal FIa increases to the current level of the reference current signal RI (i.e., 18A), the current sensor 160 outputs the second signal ALT of the effective level. When both the first signal ALT_EN and the second signal ALT are at the effective level, the voltage controller 170 outputs the voltage control signal VCTRL so that the voltage level of the first driving voltage ELVDDa is reduced. Therefore, the voltage level of the first driving voltage ELVDDa can be changed to a voltage level lower than the first voltage level.

[0181] In the skip period SKP in which the first signal ALT_EN is at the inactive level, the voltage controller 170 may not perform the voltage control operation regardless of the current level of the feedback current signal FIa.

[0182] Fig. 12B It shows that according to Fig. 11B . A graph of the first driving voltage ELVDD of the feedback current signal FI shown in FIG.

[0183] Reference Figure 5 , Fig. 11B and Fig. 12B When the current level of the feedback current signal FI is lower than the current level of the first reference current signal RI1, the first driving voltage ELVDD may have a preset first voltage level (eg, 24V).

[0184] When the current level of the feedback current signal FI increases to the current level of the first reference current signal RI1 (i.e., 16A), the current sensor 160 outputs the second signal ALT of the effective level. When both the first signal ALT_EN and the second signal ALT are at the effective level, the voltage controller 170 outputs the voltage control signal VCTRL so that the voltage level of the first driving voltage ELVDD is reduced. Therefore, the voltage level of the first driving voltage ELVDD can be changed to a voltage level lower than the first voltage level.

[0185] In the skip period SKP in which the first signal ALT_EN is at the inactive level, the voltage controller 170 may not perform the voltage control operation regardless of the current level of the feedback current signal FI.

[0186] Fig.13A It shows that according to Fig.11A The feedback current signal FIa and Fig. 12A Graph of the power consumption PWRa of the first driving voltage ELVDDa shown in FIG.

[0187] Reference Fig.11A , Fig. 12A and Fig.13A The display panel DP (refer to Figure 3 )’s power consumption PWRa.

[0188] exist Fig.13A In the example shown in , the peak power PPa is 432 W (= 24 V×18 A).

[0189] Fig. 13B It shows that according to Fig. 11B The feedback current signal FI and Fig. 12B Graph of power consumption PWR of the first driving voltage ELVDD shown in FIG.

[0190] Reference Fig. 11B , Fig. 12B and Fig. 13B The display panel DP can be calculated by multiplying the feedback current signal FI and the first driving voltage ELVDD (refer to Figure 3 )’s power consumption PWR.

[0191] exist Fig. 13B In the example shown in , the peak power PP is 384 W (= 24 V×16 A).

[0192] In the low load region, since the reference current signal RI is set to the first reference current signal RI1 lower than the second reference current signal RI2, the power consumption of the display panel DP can be reduced at the time point when the overcurrent of the display panel DP is sensed. Therefore, the display panel DP can be prevented from being damaged due to a sudden increase in power consumption.

[0193] Fig.14A is a diagram showing that when a consistent reference current signal RI is applied regardless of the load (see Figure 5 ) according to the display device DD (see Figure 1 )’s operation.

[0194] Fig.14A It shows how the second signal ALT, the input image signal RGB, the first driving voltage ELVDDa, the feedback current signal FIa, and the power consumption PWRa change with time.

[0195] Reference Figure 5 and Fig.14A When the input image signal RGB has a high grayscale level (ie, when the load LD is large), the display panel DP (refer to Figure 3 ) receives an increase in the feedback current signal FIa. When the current level of the feedback current signal FIa is higher than or equal to the current level of the reference current signal RI (that is, when the current level of the maximum current IMAXa is higher than or equal to the current level of the reference current signal RI), the second signal ALT is converted to an effective level (e.g., a low level).

[0196] When both the first signal ALT_EN and the second signal ALT are at an active level, the voltage controller 170 may output the voltage control signal VCTRL such that the voltage level of the first driving voltage ELVDDa decreases.

[0197] Fig. 14B is a diagram showing that when the first reference current signal RI1 (see Figure 5 ) and the second reference current signal RI2 (see Figure 5 ) as the reference current signal RI (see Figure 5 ) according to the display device DD (see Figure 1 )’s feedback current signal FI and power consumption PWR.

[0198] Fig. 14B It shows how the second signal ALT, the input image signal RGB, the first driving voltage ELVDD, the feedback current signal FI and the power consumption PWR change with time.

[0199] Reference Figure 5 and Fig. 14B When the input image signal RGB has a high gray level (ie, when the load LD is high), the display panel DP (refer to Figure 3 ) receives an increase in the feedback current signal FI. When the current level of the feedback current signal FI is higher than or equal to the current level of the reference current signal RI (that is, when the current level of the maximum current IMAX is higher than or equal to the current level of the reference current signal RI), the second signal ALT is converted to an effective level (e.g., a low level).

[0200] When both the first signal ALT_EN and the second signal ALT are at an active level, the voltage controller 170 may output the voltage control signal VCTRL such that the voltage level of the first driving voltage ELVDD decreases.

[0201] In an embodiment, when one of the first reference current signal RI1 and the second reference current signal RI2 is selected as the reference current signal RI according to the load LD, the maximum current IMAX of the feedback current signal FI can be reduced to less than Fig.14A The maximum current IMAXa shown in FIG.

[0202] Therefore, the peak power PP of the display device DD can be lower than Fig.14A The peak power PPa shown in .

[0203] When a transient overcurrent flows in the display panel, the display device having the above configuration can inhibit the power consumption of the display panel from exceeding a reference level, thereby preventing the display panel from being damaged due to a sudden increase in power consumption.

[0204] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A drive controller, wherein: The drive controller comprises: an overcurrent load calculator configured to calculate a load of an input image signal, compare the load with a reference load, and output a first signal corresponding to a first comparison result; an overcurrent reference controller configured to analyze a grayscale of the input image signal and output one of a first reference current signal and a second reference current signal corresponding to the grayscale as a reference current signal, the second reference current signal having a current level higher than that of the first reference current signal; a current sensor configured to receive a feedback current signal, compare a current level of the feedback current signal with a current level of the reference current signal, and output a second signal corresponding to a second comparison result; and A voltage controller is configured to output a voltage control signal for adjusting a voltage level of a driving voltage based on the first signal and the second signal.

2. The drive controller according to claim 1, wherein: The overcurrent reference controller is configured to: When the load corresponding to the input image signal belongs to a first load region, outputting the first reference current signal as the reference current signal; and When the load corresponding to the input image signal belongs to a second load region different from the first load region, the second reference current signal is output as the reference current signal.

3. The drive controller according to claim 1, wherein: The overcurrent reference controller is configured to: When the voltage level of the prediction voltage signal corresponding to the gray level is lower than the voltage level of the target voltage signal, outputting the first reference current signal as the reference current signal; and When the voltage level of the prediction voltage signal corresponding to the gray level is higher than or equal to the voltage level of the target voltage signal, the second reference current signal is output as the reference current signal.

4. The drive controller according to claim 1, wherein: When the load is lower than the reference load, the overcurrent load calculator outputs the first signal of a valid level.

5. The drive controller according to claim 4, wherein: When the current level of the feedback current signal is higher than the current level of the reference current signal, the current sensor outputs the second signal of the active level.

6. The drive controller according to claim 5, wherein: When both the first signal and the second signal are at the active level, the voltage controller outputs the voltage control signal so that the voltage level of the driving voltage decreases.

7. The drive controller according to claim 1, wherein: When the load is higher than or equal to the reference load, the overcurrent load calculator outputs the first signal of a non-active level.

8. The drive controller according to claim 1, wherein: The overcurrent reference controller comprises: a gray level analyzer configured to analyze the gray level of the input image signal and output a maximum gray level in one frame; a power control block configured to output a predicted voltage signal based on the maximum gray level and the load; and An overcurrent reference setting block is configured to compare the predicted voltage signal and a target voltage signal, and output one of the first reference current signal and the second reference current signal as the reference current signal according to a third comparison result.

9. The drive controller according to claim 8, wherein: The overcurrent reference setting block is configured to: When the voltage level of the predicted voltage signal is lower than the voltage level of the target voltage signal, outputting the first reference current signal as the reference current signal; and When the voltage level of the predicted voltage signal is higher than or equal to the voltage level of the target voltage signal, the second reference current signal is output as the reference current signal.

10. A display device, wherein: The display device comprises: Display panel; a driving controller configured to receive an input image signal and output an image data signal; a data driving circuit configured to provide a data signal corresponding to the image data signal to the display panel; and a voltage generator configured to provide a driving voltage to the display panel in response to a voltage control signal, Wherein, the drive controller comprises: an overcurrent load calculator configured to calculate a load of the input image signal, compare the load with a reference load, and output a first signal corresponding to a first comparison result; an overcurrent reference controller configured to analyze a grayscale of the input image signal and output one of a first reference current signal and a second reference current signal corresponding to the grayscale as a reference current signal, the second reference current signal having a current level higher than that of the first reference current signal; a current sensor configured to receive a feedback current signal from the display panel, compare a current level of the feedback current signal with a current level of the reference current signal, and output a second signal corresponding to a second comparison result; and A voltage controller is configured to output the voltage control signal based on the first signal and the second signal.

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