Driving circuit, driving method, display panel and display device

Abstract

The invention provides a driving circuit, a driving method, a display panel and a display device. The driving circuit comprises a first switching circuit and a scanning signal generating circuit; the first switching circuit is electrically connected with a first gating control line, a data output end of a source driver and the scanning signal generation circuit, and is used for controlling a data signal provided by the data output end to be written into the scanning signal generation circuit under the control of a first gating control signal provided by the first gating control line; the scanning signal generation circuit is used for generating a scanning signal according to the data signal and outputting the scanning signal through a scanning signal output end. According to the invention, updating of local pictures of the screen can be realized.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a driving circuit, a driving method, a display panel and a display device. Background Art

[0002] OLED (organic light-emitting diode) display technology has the advantages of high contrast, fast response, and low power consumption. In order to further reduce power consumption, the LTPO (low-temperature polycrystalline oxide) display technology achieved by combining LTPS (low-temperature polycrystalline silicon) + IGZO (indium gallium zinc oxide) can achieve low frame rate display and reduce driving power consumption by reducing the repeated refresh of static images. However, when updating the screen, the existing OLED display still needs to initialize and write all pixel voltages within one frame. In some special pictures, most of the pixel voltages of the entire screen do not need to be updated, that is, the original display brightness can be maintained by the low-leakage LTPO TFT (thin film transistor). The repeated refresh of these pixels causes a waste of data line power consumption. Summary of the invention

[0003] The main purpose of the present invention is to provide a driving circuit, a driving method, a display panel and a display device to solve the problem that the existing technology cannot update the local screen image.

[0004] In one aspect, an embodiment of the present invention provides a driving circuit, including a gating circuit;

[0005] The gating circuit is electrically connected to the gating control line, the data output terminal of the source driver and the scanning line respectively, and is used to control the connection or disconnection between the data output terminal and the scanning line under the control of the gating control signal provided by the gating control line.

[0006] Optionally, the data output terminal is electrically connected to a data line.

[0007] Optionally, the gating circuit is also electrically connected to the data line, and is used to control the connection or disconnection between the data output terminal and the data line under the control of the gating control signal.

[0008] Optionally, the gating circuit includes a first gating subcircuit and a second gating subcircuit;

[0009] The first gating subcircuit is electrically connected to the gating control line, the data output terminal and the scan line respectively, and is used to control the connection or disconnection between the data output terminal and the scan line under the control of the gating control signal provided by the gating control line;

[0010] The second gating subcircuit is electrically connected to the gating control line, the data output terminal and the data line respectively, and is used to control the connection or disconnection between the data output terminal and the data line under the control of the gating control signal.

[0011] Optionally, the gating control line includes a first gating control line and a second gating control line; the gating circuit includes a first gating sub-circuit and a second gating sub-circuit;

[0012] The first gating subcircuit is electrically connected to the first gating control line, the second gating control line, the data output terminal and the scan line respectively, and is used to control the connection or disconnection between the data output terminal and the scan line under the control of a first gating control signal provided by the first gating control line and a second gating control signal provided by the second gating control line;

[0013] The second selection subcircuit is electrically connected to the first selection control line, the second selection control line, the data output end and the data line respectively, and is used to control the connection or disconnection between the data output end and the data line under the control of the first selection control signal and the second selection control signal.

[0014] Optionally, the gating circuit includes a first transistor, and the gating control line includes a first gating control line;

[0015] The gate of the first transistor is electrically connected to the first selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line; the first transistor is a p-type transistor; or;

[0016] The gating circuit includes a first transistor, and the gating control line includes a second gating control line;

[0017] The gate of the first transistor is electrically connected to the second selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line; the first transistor is an n-type transistor.

[0018] Optionally, the gating circuit includes a first transistor and a second transistor, and the gating control line includes a first gating control line;

[0019] The gate of the first transistor is electrically connected to the first selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line;

[0020] The gate of the second transistor is electrically connected to the first selection control line, the first electrode of the second transistor is electrically connected to the data output terminal, and the second electrode of the second transistor is electrically connected to the data line;

[0021] The first transistor is a p-type transistor, and the second transistor is an n-type transistor.

[0022] Optionally, the gating circuit includes a first transistor and a second transistor, and the gating control line includes a second gating control line;

[0023] The gate of the first transistor is electrically connected to the second selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line;

[0024] The gate of the second transistor is electrically connected to the second selection control line, the first electrode of the second transistor is electrically connected to the data output terminal, and the second electrode of the second transistor is electrically connected to the data line;

[0025] The first transistor is an n-type transistor, and the second transistor is a p-type transistor.

[0026] Optionally, the gating control line includes a first gating control line and a second gating control line, the first gating subcircuit includes a first transistor, and the second gating subcircuit includes a second transistor;

[0027] The gate of the first transistor is electrically connected to the first selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line;

[0028] The gate of the second transistor is electrically connected to the second selection control line, the first electrode of the second transistor is electrically connected to the data output terminal, and the second electrode of the second transistor is electrically connected to the data line;

[0029] The first transistor and the second transistor are both p-type transistors.

[0030] Optionally, the gating control line includes a first gating control line and a second gating control line, the first gating subcircuit includes a first transistor, and the second gating subcircuit includes a second transistor;

[0031] The gate of the first transistor is electrically connected to the second selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line;

[0032] The gate of the second transistor is electrically connected to the first selection control line, the first electrode of the second transistor is electrically connected to the data output terminal, and the second electrode of the second transistor is electrically connected to the data line;

[0033] The first transistor and the second transistor are both n-type transistors.

[0034] Optionally, the gating circuit includes a first transistor and a second transistor, and the gating control line includes a first gating control line and a second gating control line;

[0035] The gate of the first transistor is electrically connected to the first selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line;

[0036] The gate of the second transistor is electrically connected to the second selection control line, the second electrode of the second transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line;

[0037] The first transistor is a p-type transistor, and the second transistor is an n-type transistor.

[0038] Optionally, the gate control line includes a first gate control line and a second gate control line;

[0039] The first gating control circuit includes a first transistor and a second transistor, and the second gating control circuit includes a third transistor and a fourth transistor;

[0040] The gate of the first transistor is electrically connected to the first selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line;

[0041] The gate of the second transistor is electrically connected to the second selection control line, the first electrode of the second transistor is electrically connected to the data output terminal, and the second electrode of the second transistor is electrically connected to the scan line;

[0042] The gate of the third transistor is electrically connected to the first selection control line, the first electrode of the third transistor is electrically connected to the data output terminal, and the second electrode of the third transistor is electrically connected to the data line;

[0043] The gate of the fourth transistor is electrically connected to the second selection control line, the first electrode of the fourth transistor is electrically connected to the data output terminal, and the second electrode of the fourth transistor is electrically connected to the data line;

[0044] The first transistor and the fourth transistor are p-type transistors, and the second transistor and the third transistor are n-type transistors.

[0045] In a second aspect, an embodiment of the present invention provides a driving method, which is applied to the above-mentioned driving circuit, and the driving method comprises: during at least part of a blank period between two frames of display time,

[0046] The gating circuit controls the data output terminal to be connected to the scanning line under the control of the gating control signal provided by the gating control line.

[0047] Optionally, the data output terminal is electrically connected to a data line; and the driving method further comprises:

[0048] During a data writing period in a frame of display time, the data output terminal provides a data voltage to a data line electrically connected thereto.

[0049] Optionally, the gating circuit is also electrically connected to the data line, and the driving method further includes:

[0050] In a data writing period in a frame of display time, the gating circuit controls the connection between the data output terminal and the data line under the control of the gating control signal, so that the data output terminal provides a data voltage to the data line.

[0051] In a third aspect, an embodiment of the present invention provides a display panel, including a source driver, a plurality of columns of scan lines and the above-mentioned drive circuit;

[0052] The source driver includes a plurality of data output terminals;

[0053] The driving circuit includes a gating circuit which is electrically connected to a gating control line, the data output terminal and the scanning line respectively, and is used to control the connection or disconnection between the data output terminal and the scanning line under the control of a gating control signal provided by the gating control line.

[0054] Optionally, the display panel described in at least one embodiment of the present invention further includes a plurality of columns of pixel circuits;

[0055] A column of the scanning lines is electrically connected to a column of the pixel circuits respectively.

[0056] Optionally, the display panel includes a plurality of columns of data lines; the data output terminal is directly electrically connected to the data lines; or,

[0057] The gating circuit is also electrically connected to the data line, and is used to control the connection or disconnection between the data output terminal and the data line under the control of the gating control signal.

[0058] Optionally, the source driver is disposed on a first side of the display panel, and the driving circuit is disposed on the first side of the display panel; or,

[0059] The source driver is disposed on a first side of the display panel, and the driving circuit is disposed on a second side of the display panel. The first side and the second side are opposite sides.

[0060] Optionally, the pixel circuit includes a light-emitting element, a light-emitting driving circuit and a control circuit;

[0061] The light-emitting driving circuit is electrically connected to the first node, the second node and the third node respectively, and is used to generate a driving current flowing through the second node and the third node under the control of the potential of the first node;

[0062] The light emitting element is electrically connected to the third node;

[0063] The control circuit is electrically connected to the first gate line, the scan line, the first node and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the first gate drive signal provided by the first gate line and the scan signal provided by the scan line.

[0064] Optionally, the control circuit includes a first control circuit and a second control circuit;

[0065] The first control circuit is electrically connected to the first gate line, the first node and the intermediate node respectively, and the first control circuit is used to control the connection or disconnection between the first node and the intermediate node under the control of the first gate driving signal provided by the first gate line;

[0066] The second control circuit is electrically connected to the scan line, the intermediate node and the third node respectively, and is used to control the connection or disconnection between the intermediate node and the third node under the control of the scan signal provided by the scan line.

[0067] Optionally, the control circuit includes a first control circuit and a second control circuit;

[0068] The first control circuit is electrically connected to the first gate line, the third node and the intermediate node respectively, and is used to control the connection or disconnection between the third node and the intermediate node under the control of the first gate driving signal provided by the first gate line;

[0069] The second control circuit is electrically connected to the scan line, the intermediate node and the first node respectively, and is used to control the connection or disconnection between the intermediate node and the first node under the control of the scan signal provided by the scan line.

[0070] Optionally, the pixel circuit further includes a first initialization circuit;

[0071] The first initialization circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the second node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the second node under the control of the first initial control signal provided by the first initial control terminal.

[0072] Optionally, the pixel circuit further includes a second initialization circuit;

[0073] The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal and the third node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the third node under the control of the second initial control signal provided by the second initial control terminal.

[0074] Optionally, the pixel circuit further includes a data writing circuit, a first light emitting control circuit, a second light emitting control circuit and an energy storage circuit;

[0075] The data writing circuit is electrically connected to the second gate line, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the second gate driving signal provided by the second gate line;

[0076] The first light-emitting control circuit is electrically connected to the light-emitting control line, the power supply voltage terminal and the second node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control line;

[0077] The second light emitting control circuit is electrically connected to the light emitting control line, the third node and the first electrode of the light emitting element respectively, and is used to control the third node to be electrically connected to the first electrode of the light emitting element and the second electrode of the light emitting element to be electrically connected to the third voltage terminal under the control of the light emitting control signal;

[0078] The energy storage circuit is electrically connected to the first node and is used for storing electric energy.

[0079] Optionally, the pixel circuit further includes a third initialization circuit;

[0080] The third initialization circuit is electrically connected to the first initial control terminal, the third initial voltage terminal and the first pole of the light-emitting element respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first pole of the light-emitting element under the control of the first initial control signal provided by the first initial control terminal.

[0081] Optionally, the first control circuit includes a first control transistor, and the second control circuit includes a second control transistor;

[0082] The gate of the first control transistor is electrically connected to the first gate line, the first electrode of the first control transistor is electrically connected to the first node, and the second electrode of the first control transistor is electrically connected to the intermediate node;

[0083] A gate of the second control transistor is electrically connected to the scan line, a first electrode of the second control transistor is electrically connected to the intermediate node, and a second electrode of the second control transistor is electrically connected to the third node.

[0084] Optionally, the first control circuit includes a first control transistor, and the second control circuit includes a second control transistor;

[0085] The gate of the first control transistor is electrically connected to the first gate line, the first electrode of the first control transistor is electrically connected to the intermediate node, and the second electrode of the first control transistor is electrically connected to the third node;

[0086] A gate of the second control transistor is electrically connected to the scan line, a first electrode of the second control transistor is electrically connected to the first node, and a second electrode of the second control transistor is electrically connected to the intermediate node.

[0087] Optionally, the first initialization circuit includes a first initialization transistor;

[0088] A gate of the first initialization transistor is electrically connected to the first initial control terminal, a first electrode of the first initialization transistor is electrically connected to the first initial voltage terminal, and a second electrode of the first initialization transistor is electrically connected to the second node.

[0089] Optionally, the second initialization circuit includes a second initialization transistor;

[0090] A gate of the second initialization transistor is electrically connected to the second initial control terminal, a first electrode of the second initialization transistor is electrically connected to the second initial voltage terminal, and a second electrode of the second initialization transistor is electrically connected to the third node.

[0091] Optionally, the data writing circuit includes a writing transistor, the first light emitting control circuit includes a first light emitting control transistor, and the second light emitting control circuit includes a second light emitting control transistor; the light emitting driving circuit includes a driving transistor, and the energy storage circuit includes a storage capacitor;

[0092] The gate of the write transistor is electrically connected to the second gate line, the first electrode of the write transistor is electrically connected to the data line, and the second electrode of the write transistor is electrically connected to the second node;

[0093] The gate of the first light emission control transistor is electrically connected to the light emission control line, the first electrode of the first light emission control transistor is electrically connected to the power supply voltage terminal, and the second electrode of the first light emission control transistor is electrically connected to the second node;

[0094] The gate of the second light emission control transistor is electrically connected to the light emission control line, the first electrode of the second light emission control transistor is electrically connected to the third node, and the second electrode of the second light emission control transistor is electrically connected to the first electrode of the light emitting element;

[0095] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;

[0096] The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to a power supply voltage terminal.

[0097] Optionally, the third initialization circuit includes a third initialization transistor;

[0098] The gate of the third initialization transistor is electrically connected to the first initial control terminal, the first electrode of the third initialization transistor is electrically connected to the third initial voltage terminal, and the second electrode of the third initialization transistor is electrically connected to the first electrode of the light emitting element.

[0099] In a fourth aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned display panel.

[0100] The embodiment of the present invention can control the scanning signal on a column of scanning lines during at least part of the blank time period between two frames of display time, so as to control the transistor controlled by the scanning line to be turned on or off during the next frame of display time according to the scanning signal, so as to control whether to refresh the data voltage of the corresponding pixel circuit, thereby realizing the update of the partial screen picture, while the remaining pictures do not need to be charged and discharged multiple times, thereby further reducing the power consumption of OLED (organic light emitting diode) display, and realizing ultra-low power consumption by partially updating the display picture. BRIEF DESCRIPTION OF THE DRAWINGS

[0101] Figure 1 is a structural diagram of a driving circuit according to an embodiment of the present invention;

[0102] Figure 2 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0103] Figure 3 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0104] Figure 4 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0105] Figure 5 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0106] Figure 6 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0107] Figure 7 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0108] Figure 8 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0109] Fig. 9 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0110] Fig.10 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0111] Fig.11 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0112] Fig.12 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0113] Fig.13 yes Fig.12 An operation timing diagram of at least one embodiment of the driving circuit shown;

[0114] Fig.14 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0115] Fig.15 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0116] Fig.16 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0117] Fig.17 is a structural diagram of a display panel according to at least one embodiment of the present invention;

[0118] Fig.18 is a structural diagram of a display panel according to at least one embodiment of the present invention;

[0119] Fig.19 is a structural diagram of a display panel according to at least one embodiment of the present invention;

[0120] Fig. 20 is a structural diagram of a pixel circuit in a display panel according to at least one embodiment of the present invention;

[0121] Fig.21 is a structural diagram of at least one embodiment of the pixel circuit;

[0122] Fig. 22 is a structural diagram of at least one embodiment of the pixel circuit;

[0123] Fig.23 is a structural diagram of at least one embodiment of the pixel circuit;

[0124] Fig.24 is a structural diagram of at least one embodiment of the pixel circuit;

[0125] Fig.25 is a circuit diagram of at least one embodiment of the pixel circuit;

[0126] Fig.26A yes Fig.25 An operation timing diagram of at least one embodiment of the pixel circuit shown;

[0127] Fig.26B yes Fig.25 An operation timing diagram of at least one embodiment of the pixel circuit shown;

[0128] Fig. 27 is a circuit diagram of at least one embodiment of the pixel circuit;

[0129] Fig.28 is a circuit diagram of at least one embodiment of the pixel circuit;

[0130] Fig.29 is a circuit diagram of at least one embodiment of the pixel circuit. DETAILED DESCRIPTION

[0131] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0132] The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is called the first electrode and the other electrode is called the second electrode.

[0133] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0134] The driving circuit described in the embodiment of the present invention includes a gating circuit;

[0135] The gating circuit is electrically connected to the gating control line, the data output terminal of the source driver and the scanning line respectively, and is used to control the connection or disconnection between the data output terminal and the scanning line under the control of the gating control signal provided by the gating control line.

[0136] When the driving circuit described in the embodiment of the present invention is working, during at least part of the blank time period between two frames of display time, the selection circuit controls the connection between the data output terminal and the scan line under the control of the selection control signal provided by the selection control line, and provides a scan signal through the data output terminal to control the transistor controlled by the scan line to be turned on or off during the next frame of display time.

[0137] In a specific implementation, the scan line may extend along a vertical direction, but is not limited thereto.

[0138] In a specific implementation, when the transistor controlled by the scan line is turned off during the next frame display time, the pixel circuit where the transistor is located does not perform data voltage writing, and the original display brightness can be maintained by the low leakage transistor, thereby avoiding the waste of part of the power consumption caused by repeated rewriting of the pixel circuit;

[0139] When the transistor controlled by the scan line is turned on during the next frame display time, the pixel circuit where the transistor is located writes the data voltage and refreshes the picture normally.

[0140] When updating the screen, the relevant OLED (organic light-emitting diode) display needs to initialize and write data voltage to all pixel circuits within one frame display time. However, in some special screens (such as AOD (all-weather off-screen display) screens, static screens or screens that are updated less frequently), the data voltage of most pixel circuits on the entire screen does not need to be updated, and can be maintained at the original display brightness through low-leakage LTPO (low-temperature polycrystalline oxide) TFT (thin-film transistor). Repeated refresh of these pixel circuits results in a waste of data line power consumption.

[0141] Based on this, an embodiment of the present invention designs a driving circuit that can control the scanning signal on the scanning line during at least part of the blank time period between two frames of display time, so as to control the transistor controlled by the scanning line to be turned on or off during the next frame of display time according to the scanning signal, so as to control whether to refresh the data voltage of the corresponding pixel circuit, thereby realizing the update of the partial screen picture, while the remaining pictures do not need to be charged and discharged multiple times, thereby further reducing the power consumption of the OLED display, or realizing ultra-low power consumption by partially updating the display picture.

[0142] like Figure 1 As shown, the driving circuit described in the embodiment of the present invention includes a gating circuit 11;

[0143] The gating circuit 11 is electrically connected to the gating control line SW, the data output terminal S0 of the source driver and the scanning line CGL respectively, and is used to control the connection or disconnection between the data output terminal S0 and the scanning line CGL under the control of the gating control signal provided by the gating control line SW.

[0144] In at least one embodiment of the present invention, the data output terminal is electrically connected to a data line.

[0145] In a specific implementation, the data output terminal may be directly electrically connected to the data line.

[0146] In at least one embodiment of the present invention, the gating circuit is also electrically connected to the data line, and is used to control the connection or disconnection between the data output terminal and the data line under the control of the gating control signal.

[0147] In a specific implementation, the gating circuit can also control the connection or disconnection between the data output terminal and the data line under the control of a gating control signal.

[0148] In at least one embodiment of the present invention, during at least part of the blank time period, the high voltage value of the scan signal provided by the data output terminal may be greater than or equal to 7V and less than or equal to 9V, and the low voltage value of the scan signal may be greater than or equal to -9V and less than or equal to -7V.

[0149] like Figure 2 As shown, in Figure 1 Based on the embodiment of the driving circuit shown, the gating circuit 11 may also be electrically connected to the data line DL, and is used to control the connection or disconnection between the data output terminal S0 and the data line DL under the control of the gating control signal.

[0150] In at least one embodiment of the present invention, the gating circuit includes a first gating subcircuit and a second gating subcircuit;

[0151] The first gating subcircuit is electrically connected to the gating control line, the data output terminal and the scan line respectively, and is used to control the connection or disconnection between the data output terminal and the scan line under the control of the gating control signal provided by the gating control line;

[0152] The second gating subcircuit is electrically connected to the gating control line, the data output terminal and the data line respectively, and is used to control the connection or disconnection between the data output terminal and the data line under the control of the gating control signal.

[0153] In a specific implementation, the gating circuit may include a first gating sub-circuit and a second gating sub-circuit. The first gating sub-circuit controls the connection or disconnection between the data output terminal and the scan line under the control of a gating control signal; the second gating sub-circuit controls the connection or disconnection between the data output terminal and the data line under the control of the gating control signal.

[0154] like Figure 3 As shown, in Figure 2 Based on at least one embodiment of the driving circuit, the gating circuit includes a first gating subcircuit 31 and a second gating subcircuit 32;

[0155] The first gating subcircuit 31 is electrically connected to the gating control line SW, the data output terminal S0 and the scan line CGL respectively, and is used to control the connection or disconnection between the data output terminal S0 and the scan line CGL under the control of the gating control signal provided by the gating control line SW;

[0156] The second gating subcircuit 12 is electrically connected to the gating control line SW, the data output terminal S0 and the data line DL respectively, and is used to control the connection or disconnection between the data output terminal S0 and the data line DL under the control of the gating control signal.

[0157] In at least one embodiment of the present invention, the gating control line includes a first gating control line and a second gating control line; the gating circuit includes a first gating subcircuit and a second gating subcircuit;

[0158] The first gating subcircuit is electrically connected to the first gating control line, the second gating control line, the data output terminal and the scan line respectively, and is used to control the connection or disconnection between the data output terminal and the scan line under the control of a first gating control signal provided by the first gating control line and a second gating control signal provided by the second gating control line;

[0159] The second selection subcircuit is electrically connected to the first selection control line, the second selection control line, the data output end and the data line respectively, and is used to control the connection or disconnection between the data output end and the data line under the control of the first selection control signal and the second selection control signal.

[0160] In a specific implementation, the gating circuit may include a first gating sub-circuit and a second gating sub-circuit, wherein the first gating sub-circuit controls the connection or disconnection between the data output terminal and the scan line under the control of a first gating control signal and a second gating control signal; and the second gating sub-circuit controls the connection or disconnection between the data output terminal and the data line under the control of the first gating control signal and the second gating control signal.

[0161] like Figure 4 As shown, in Figure 2 Based on at least one embodiment of the driving circuit, the gating circuit includes a first gating subcircuit 31 and a second gating subcircuit 32;

[0162] The first gating subcircuit 31 is electrically connected to the first gating control line SW1, the second gating control line SW2, the data output terminal S0 and the scan line CGL respectively, and is used to control the connection or disconnection between the data output terminal S0 and the scan line CGL under the control of a first gating control signal provided by the first gating control line SW1 and a second gating control signal provided by the second gating control line SW2;

[0163] The second selection subcircuit 32 is electrically connected to the first selection control line SW1, the second selection control line SW2, the data output terminal S0 and the data line DL, respectively, and is used to control the connection or disconnection between the data output terminal S0 and the data line DL under the control of the first selection control signal and the second selection control signal.

[0164] Optionally, the gating circuit includes a first transistor, and the gating control line includes a first gating control line;

[0165] The gate of the first transistor is electrically connected to the first selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line; the first transistor is a p-type transistor; or;

[0166] The gating circuit includes a first transistor, and the gating control line includes a second gating control line;

[0167] The gate of the first transistor is electrically connected to the second selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line; the first transistor is an n-type transistor.

[0168] like Figure 5 As shown, the pixel circuit labeled P11 is the first row and first column, the pixel circuit labeled P21 is the second row and first column, the pixel circuit labeled P31 is the third row and first column, and the pixel circuit labeled P41 is the fourth row and first column;

[0169] The line labeled DL1 is the first column data line, the line labeled CGL1 is the first column scan line, the line labeled NG1 is the first row first gate line, the line labeled NG2 is the first row first gate line, the line labeled NG3 is the third row first gate line, and the line labeled NG4 is the fourth row first gate line;

[0170] The data output terminal S0 is directly electrically connected to the first column data line DL1;

[0171] The driving circuit described in at least one embodiment of the present invention includes a gating circuit;

[0172] The gating circuit includes a first transistor T1, and the gating control line includes a first gating control line SW1;

[0173] The gate of T1 is electrically connected to the first selection control line SW1, the source of T1 is electrically connected to the data output terminal S0 of the source driver, and the drain of T1 is electrically connected to the first column scanning line CGL1;

[0174] T1 is a p-type transistor;

[0175] T1 is disposed at the bottom of each pixel circuit.

[0176] The present invention Figure 5 When at least one embodiment of the driving circuit shown is in operation, during at least part of the blank period between two frames of display time, SW1 provides a low voltage signal, so that T1 is turned on, and a scan signal is provided to the first column scan line CGL1 through the data output terminal S0;

[0177] During a frame display time, SW1 provides a high voltage signal and T1 is turned off to control the disconnection between the data output terminal S0 and the first column scan line CGL1, and provide a data voltage to the first column data line DL1 through the data output terminal S0.

[0178] The present invention Figure 6 At least one embodiment of the driving circuit shown in the figure is consistent with the present invention Figure 5The difference of at least one embodiment of the driving circuit shown is that: T1 is an n-type transistor; the gate of T1 is electrically connected to the second gate control line SW2;

[0179] T1 is disposed at the bottom of each pixel circuit.

[0180] The present invention Figure 6 When at least one embodiment of the driving circuit shown is in operation, during at least part of the blank period between two frames of display time, SW2 provides a high voltage signal, so that T1 is turned on, and a scan signal is provided to the first column scan line CGL1 through the data output terminal S0;

[0181] During a frame display time, SW2 provides a low voltage signal and T1 is turned off to control the disconnection between the data output terminal S0 and the first column scan line CGL1, and provide a data voltage for the first column data line DL1 through the data output terminal S0.

[0182] Optionally, the gating circuit includes a first transistor and a second transistor, and the gating control line includes a first gating control line;

[0183] The gate of the first transistor is electrically connected to the first selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line;

[0184] The gate of the second transistor is electrically connected to the first selection control line, the first electrode of the second transistor is electrically connected to the data output terminal, and the second electrode of the second transistor is electrically connected to the data line;

[0185] The first transistor is a p-type transistor, and the second transistor is an n-type transistor.

[0186] like Figure 7 As shown, the pixel circuit labeled P11 is the first row and first column, the pixel circuit labeled P21 is the second row and first column, the pixel circuit labeled P31 is the third row and first column, and the pixel circuit labeled P41 is the fourth row and first column;

[0187] The line labeled DL1 is the first column data line, the line labeled CGL1 is the first column scan line, the line labeled NG1 is the first row first gate line, the line labeled NG2 is the first row first gate line, the line labeled NG3 is the third row first gate line, and the line labeled NG4 is the fourth row first gate line;

[0188] The driving circuit described in at least one embodiment of the present invention includes a gating circuit;

[0189] The gating circuit includes a first transistor T1 and a second transistor T2, and the gating control line includes a first gating control line SW1;

[0190] The gate of T1 is electrically connected to the first selection control line SW1, the source of T1 is electrically connected to the data output terminal S0 of the source driver, and the drain of T1 is electrically connected to the first column scanning line CGL1;

[0191] The gate of T2 is electrically connected to the first selection control line SW1, the source of T2 is electrically connected to the data output terminal S0, and the drain of T2 is electrically connected to the first column data line DL1;

[0192] T1 is a p-type transistor and T2 is an n-type transistor;

[0193] T1 and T2 are arranged at the bottom side of each pixel circuit.

[0194] The present invention Figure 7 In at least one embodiment shown, during operation, during at least part of the blank period between two frames of display time, SW1 provides a low voltage signal, T1 is turned on, so as to write the scan signal provided by the data output terminal S0 into the first column scan line CGL1;

[0195] During a frame display time, SW1 provides a high voltage signal and T2 is turned on to control the connection between the data output terminal S0 and the first column data line DL1, and provide a data voltage to the first column data line DL1 through the data output terminal S0.

[0196] Optionally, the gating circuit includes a first transistor and a second transistor, and the gating control line includes a second gating control line;

[0197] The gate of the first transistor is electrically connected to the second selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line;

[0198] The gate of the second transistor is electrically connected to the second selection control line, the first electrode of the second transistor is electrically connected to the data output terminal, and the second electrode of the second transistor is electrically connected to the data line;

[0199] The first transistor is an n-type transistor, and the second transistor is a p-type transistor.

[0200] like Figure 8 As shown, the pixel circuit labeled P11 is the first row and first column, the pixel circuit labeled P21 is the second row and first column, the pixel circuit labeled P31 is the third row and first column, and the pixel circuit labeled P41 is the fourth row and first column;

[0201] The line labeled DL1 is the first column data line, the line labeled CGL1 is the first column scan line, the line labeled NG1 is the first row first gate line, the line labeled NG2 is the first row first gate line, the line labeled NG3 is the third row first gate line, and the line labeled NG4 is the fourth row first gate line;

[0202] The driving circuit described in at least one embodiment of the present invention includes a gating circuit;

[0203] The gating circuit includes a first transistor T1 and a second transistor T2, and the gating control line includes a second gating control line SW2;

[0204] The gate of T1 is electrically connected to the second selection control line SW2, the source of T1 is electrically connected to the data output terminal S0 of the source driver, and the drain of T1 is electrically connected to the first column scanning line CGL1;

[0205] The gate of T2 is electrically connected to the second selection control line SW2, the source of T2 is electrically connected to the data output terminal S0, and the drain of T2 is electrically connected to the first column data line DL1;

[0206] T1 is an n-type transistor and T2 is a p-type transistor;

[0207] T1 and T2 are arranged at the bottom side of each pixel circuit.

[0208] The present invention Figure 8 In at least one embodiment shown, during operation, during at least part of the blank period between two frames of display time, SW2 provides a high voltage signal, T1 is turned on to write the scan signal provided by the data output terminal S0 into the first column scan line CGL1; T2 is turned off;

[0209] During a frame display time, SW2 provides a low voltage signal, T2 is turned on to control the connection between the data output terminal S0 and the first column data line DL1, and the data voltage is provided to the first column data line DL1 through the data output terminal S0; T1 is turned off.

[0210] In at least one embodiment of the present invention, the gating control line includes a first gating control line and a second gating control line, the first gating subcircuit includes a first transistor, and the second gating subcircuit includes a second transistor;

[0211] The gate of the first transistor is electrically connected to the first selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line;

[0212] The gate of the second transistor is electrically connected to the second selection control line, the first electrode of the second transistor is electrically connected to the data output terminal, and the second electrode of the second transistor is electrically connected to the data line;

[0213] The first transistor and the second transistor are both p-type transistors.

[0214] like Fig. 9 As shown, the pixel circuit labeled P11 is the first row and first column, the pixel circuit labeled P21 is the second row and first column, the pixel circuit labeled P31 is the third row and first column, and the pixel circuit labeled P41 is the fourth row and first column;

[0215] The line labeled DL1 is the first column data line, the line labeled CGL1 is the first column scan line, the line labeled NG1 is the first row first gate line, the line labeled NG2 is the first row first gate line, the line labeled NG3 is the third row first gate line, and the line labeled NG4 is the fourth row first gate line;

[0216] The driving circuit described in at least one embodiment of the present invention includes a gating circuit, wherein the gating circuit includes a first gating subcircuit and a second gating subcircuit;

[0217] The first gating subcircuit includes a first transistor T1, the second gating subcircuit includes a second transistor T2, and the gating control line includes a first gating control line SW1 and a second gating control line SW2;

[0218] The gate of T1 is electrically connected to the first selection control line SW1, the source of T1 is electrically connected to the data output terminal S0, and the drain of T1 is electrically connected to the first column scanning line CGL1;

[0219] The gate of T2 is electrically connected to the second selection control line SW2, the source of T2 is electrically connected to the data output terminal S0, and the drain of T2 is electrically connected to the first column data line DL1;

[0220] Both T1 and T2 are p-type transistors;

[0221] T1 and T2 are arranged at the bottom side of each pixel circuit.

[0222] The present invention Fig. 9 In at least one embodiment shown, during operation, during at least part of the blank period between two frames of display time, SW1 provides a low voltage signal, SW2 provides a high voltage signal, T1 is turned on to write the scan signal provided by the data output terminal S0 into the first column scan line CGL1, and T2 is turned off;

[0223] During a frame display time, SW1 provides a high voltage signal, SW2 provides a low voltage signal, T2 is turned on to control the connection between the data output terminal S0 and the first column data line DL1, and the data voltage is provided to the first column data line DL1 through the data output terminal S0, and T1 is turned off.

[0224] In at least one embodiment of the present invention, the gating control line includes a first gating control line and a second gating control line, the first gating subcircuit includes a first transistor, and the second gating subcircuit includes a second transistor;

[0225] The gate of the first transistor is electrically connected to the second selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line;

[0226] The gate of the second transistor is electrically connected to the first selection control line, the first electrode of the second transistor is electrically connected to the data output terminal, and the second electrode of the second transistor is electrically connected to the data line;

[0227] The first transistor and the second transistor are both n-type transistors.

[0228] like Fig.10 As shown, the pixel circuit labeled P11 is the first row and first column, the pixel circuit labeled P21 is the second row and first column, the pixel circuit labeled P31 is the third row and first column, and the pixel circuit labeled P41 is the fourth row and first column;

[0229] The line labeled DL1 is the first column data line, the line labeled CGL1 is the first column scan line, the line labeled NG1 is the first row first gate line, the line labeled NG2 is the first row first gate line, the line labeled NG3 is the third row first gate line, and the line labeled NG4 is the fourth row first gate line;

[0230] The driving circuit described in at least one embodiment of the present invention includes a gating circuit, wherein the gating circuit includes a first gating subcircuit and a second gating subcircuit;

[0231] The first gating subcircuit includes a first transistor T1, the second gating subcircuit includes a second transistor T2, and the gating control line includes a first gating control line SW1 and a second gating control line SW2;

[0232] The gate of T1 is electrically connected to the second selection control line SW2, the source of T1 is electrically connected to the data output terminal S0, and the drain of T1 is electrically connected to the first column scanning line CGL1;

[0233] The gate of T2 is electrically connected to the first selection control line SW1, the source of T2 is electrically connected to the data output terminal S0, and the drain of T2 is electrically connected to the first column data line DL1;

[0234] Both T1 and T2 are n-type transistors;

[0235] T1 and T2 are arranged at the bottom side of each pixel circuit.

[0236] The present invention Fig.10 In at least one embodiment shown, during operation, during at least part of the blank period between two frames of display time, SW2 provides a high voltage signal, SW1 provides a low voltage signal, T1 is turned on to write the scan signal provided by the data output terminal S0 into the first column scan line CGL1, and T2 is turned off;

[0237] During a frame display time, SW2 provides a low voltage signal, SW1 provides a high voltage signal, T2 is turned on to control the connection between the data output terminal S0 and the first column data line DL1, and the data voltage is provided to the first column data line DL1 through the data output terminal S0, and T1 is turned off.

[0238] Optionally, the gating circuit includes a first transistor and a second transistor, and the gating control line includes a first gating control line and a second gating control line;

[0239] The gate of the first transistor is electrically connected to the first selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line;

[0240] The gate of the second transistor is electrically connected to the second selection control line, the second electrode of the second transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line;

[0241] The first transistor is a p-type transistor, and the second transistor is an n-type transistor.

[0242] like Fig.11 As shown, the pixel circuit labeled P11 is the first row and first column, the pixel circuit labeled P21 is the second row and first column, the pixel circuit labeled P31 is the third row and first column, and the pixel circuit labeled P41 is the fourth row and first column;

[0243] The line labeled DL1 is the first column data line, the line labeled CGL1 is the first column scan line, the line labeled NG1 is the first row first gate line, the line labeled NG2 is the first row first gate line, the line labeled NG3 is the third row first gate line, and the line labeled NG4 is the fourth row first gate line;

[0244] The driving circuit described in at least one embodiment of the present invention includes a gating circuit, wherein the gating circuit includes a first gating subcircuit and a second gating subcircuit;

[0245] The first gating subcircuit includes a first transistor T1, the second gating subcircuit includes a second transistor T2, and the gating control line includes a first gating control line SW1 and a second gating control line SW2;

[0246] The gate of T1 is electrically connected to the first selection control line SW1, the source of T1 is electrically connected to the data output terminal S0, and the drain of T1 is electrically connected to the first column scanning line CGL1;

[0247] The gate of T2 is electrically connected to the second selection control line SW2, the source of T2 is electrically connected to the data output terminal S0, and the drain of T2 is electrically connected to the first column scanning line CGL1;

[0248] The data output terminal S0 is directly electrically connected to the first column data line DL1;

[0249] T1 is a p-type transistor and T2 is an n-type transistor;

[0250] T1 and T2 are arranged at the bottom side of each pixel circuit.

[0251] The present invention Fig.11 In at least one embodiment shown, during operation, during at least part of the blank period between two frames of display time, SW1 provides a low voltage signal, SW2 provides a high voltage signal, T1 and T2 are turned on, so as to write the scan signal provided by the data output terminal S0 into the first column scan line CGL1;

[0252] During a frame display time, SW1 provides a high voltage signal, SW2 provides a low voltage signal, T1 and T2 are turned off, the data output terminal S0 is disconnected from the first column scan line CGL1, and the data voltage is provided to the first column data line DL1 through the data output terminal S0.

[0253] In at least one embodiment of the present invention, the gate control line includes a first gate control line and a second gate control line;

[0254] The first gating control circuit includes a first transistor and a second transistor, and the second gating control circuit includes a third transistor and a fourth transistor;

[0255] The gate of the first transistor is electrically connected to the first selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line;

[0256] The gate of the second transistor is electrically connected to the second selection control line, the first electrode of the second transistor is electrically connected to the data output terminal, and the second electrode of the second transistor is electrically connected to the scan line;

[0257] The gate of the third transistor is electrically connected to the first selection control line, the first electrode of the third transistor is electrically connected to the data output terminal, and the second electrode of the third transistor is electrically connected to the data line;

[0258] The gate of the fourth transistor is electrically connected to the second selection control line, the first electrode of the fourth transistor is electrically connected to the data output terminal, and the second electrode of the fourth transistor is electrically connected to the data line;

[0259] The first transistor and the fourth transistor are p-type transistors, and the second transistor and the third transistor are n-type transistors.

[0260] like Fig.12 As shown, the pixel circuit labeled P11 is the first row and first column, the pixel circuit labeled P21 is the second row and first column, the pixel circuit labeled P31 is the third row and first column, and the pixel circuit labeled P41 is the fourth row and first column;

[0261] The line labeled DL1 is the first column data line, the line labeled CGL1 is the first column scan line, the line labeled NG1 is the first row first gate line, the line labeled NG2 is the first row first gate line, the line labeled NG3 is the third row first gate line, and the line labeled NG4 is the fourth row first gate line;

[0262] The driving circuit described in at least one embodiment of the present invention includes a gating circuit, wherein the gating circuit includes a first gating subcircuit and a second gating subcircuit;

[0263] The first gating subcircuit includes a first transistor T1 and a second transistor T2, the second gating subcircuit includes a third transistor T3 and a fourth transistor T4, and the gating control line includes a first gating control line SW1 and a second gating control line SW2;

[0264] The gate of T1 is electrically connected to the first selection control line SW1, the source of T1 is electrically connected to the data output terminal S0, and the drain of T1 is electrically connected to the first column scanning line CGL1;

[0265] The gate of T2 is electrically connected to the second selection control line SW2, the source of T2 is electrically connected to the data output terminal S0, and the drain of T2 is electrically connected to the first column scanning line CGL1;

[0266] The gate of T3 is electrically connected to the first selection control line SW1, the source of T3 is electrically connected to the data output terminal S0, and the drain of T3 is electrically connected to the first column data line DL1;

[0267] The gate of T4 is electrically connected to the second selection control line SW2, the source of T4 is electrically connected to the data output terminal S0, and the drain of T4 is electrically connected to the first column data line DL1;

[0268] T1 and T4 are p-type transistors, and T2 and T3 are n-type transistors;

[0269] T1, T2, T3 and T4 are arranged at the lower side of each pixel circuit.

[0270] The present invention Fig.12 In at least one embodiment shown in FIG. 1 , during at least part of the blank period between two frames of display time, SW1 provides a low voltage signal, SW2 provides a high voltage signal, T1 and T2 are turned on to write the scan signal provided by the data output terminal S0 into the first column scan line CGL1; T3 and T4 are turned off;

[0271] During a frame display time, SW1 provides a high voltage signal, SW2 provides a low voltage signal, T3 and T4 are turned on, T1 and T2 are turned off, the data output terminal S0 is disconnected from the first column scan line CGL1, and the data voltage is provided to the first column data line DL1 through the data output terminal S0.

[0272] like Fig.13 As shown, the present invention Fig.12 At least one embodiment shown in FIG. 1 is in operation.

[0273] In a partial period of time included in the first blank period B1, SW1 provides a low voltage signal, SW2 provides a high voltage signal, T1 and T2 are turned on, S0 provides a high voltage signal to the first column scan line CGL1; T3 and T4 are turned off;

[0274] During the first frame display time F1, CGL1 continuously provides a high voltage signal;

[0275] In the first frame display time F1, SW1 provides a high voltage signal, SW2 provides a low voltage signal, T3 and T4 are turned on, S0 provides a data voltage to the first column data line DL1; T1 and T2 are turned off;

[0276] In a partial period of time included in the second blank period B2, SW1 provides a low voltage signal, SW2 provides a high voltage signal, T1 and T2 are turned on, S0 provides a low voltage signal to the first column scan line CGL1; T3 and T4 are turned off;

[0277] During the second frame display time F2, CGL1 continues to provide a low voltage signal;

[0278] In the second frame display time F2, SW1 provides a high voltage signal, SW2 provides a low voltage signal, T3 and T4 are turned on, S0 provides a data voltage to the first column data line DL1; T1 and T2 are turned off.

[0279] exist Fig.13 In the first blank period B1 and the first frame display period F1, the potential of the high voltage signal output by CGL1 is greater than or equal to 7V and less than or equal to 9V;

[0280] In the second blank period B2 and the second frame display period F2, the potential of the low voltage signal output by CGL1 is greater than or equal to -9V and less than or equal to -7V.

[0281] exist Figure 5 At least one embodiment shown to Fig.12 In at least one embodiment shown, the source driver may be disposed at the bottom of each pixel circuit, and the driving circuit is disposed at the bottom of each pixel circuit.

[0282] Fig.14 At least one embodiment of the driving circuit shown is Figure 5 The difference of at least one embodiment of the driving circuit shown is that T1 is arranged on the upper side of each pixel circuit.

[0283] Fig.15 At least one embodiment of the driving circuit shown is Figure 6 The difference of at least one embodiment of the driving circuit shown is that T1 is arranged on the upper side of each pixel circuit.

[0284] Fig.16 At least one embodiment of the driving circuit shown is Fig.11 The difference of at least one embodiment of the driving circuit shown is that T1 and T2 are arranged on the upper side of each pixel circuit.

[0285] The driving method described in the embodiment of the present invention is applied to the above-mentioned driving circuit, and the driving method comprises: during at least part of the blank time period between two display frames,

[0286] The gating circuit controls the data output terminal to be connected to the scanning line under the control of the gating control signal provided by the gating control line.

[0287] In the driving method described in the embodiment of the present invention, the scanning signal on the scanning line can be controlled during at least part of the blank time period between two frames of display time, so as to control the transistor controlled by the scanning line to be turned on or off in the next frame of display time according to the scanning signal, so as to control whether to refresh the data voltage of the corresponding pixel circuit, thereby realizing the update of the partial screen picture, while the remaining pictures do not need to be charged and discharged multiple times, thereby further reducing the power consumption of the OLED display, or realizing ultra-low power consumption by partially updating the display picture.

[0288] In at least one embodiment of the present invention, the data output terminal is electrically connected to the data line; and the driving method further includes:

[0289] During a data writing period in a frame of display time, the data output terminal provides a data voltage to a data line electrically connected thereto.

[0290] In at least one embodiment of the present invention, the gating circuit is also electrically connected to the data line, and the driving method further includes:

[0291] In a data writing period in a frame of display time, the gating circuit controls the connection between the data output terminal and the data line under the control of the gating control signal, so that the data output terminal provides a data voltage to the data line.

[0292] The display panel described in the embodiment of the present invention includes a source driver, a plurality of columns of scan lines and the above-mentioned driving circuit;

[0293] The source driver includes a plurality of data output terminals;

[0294] The driving circuit includes a gating circuit which is electrically connected to a gating control line, the data output terminal and the scanning line respectively, and is used to control the connection or disconnection between the data output terminal and the scanning line under the control of a gating control signal provided by the gating control line.

[0295] In a specific implementation, the display panel may include a source driver, a plurality of columns of scan lines and the driving circuit. During at least part of the blank time period between two frames of display time, the driving circuit includes a gating circuit that controls the connection between the data output terminal and the scan line under the control of a gating control signal. During one frame of display time, the gating circuit controls the disconnection between the data output terminal and the scan line under the control of a gating control signal.

[0296] The display panel described in at least one embodiment of the present invention further includes a plurality of columns of pixel circuits;

[0297] A column of scan lines is electrically connected to a column of pixel circuits respectively.

[0298] In at least one embodiment of the present invention, the display panel includes a plurality of columns of data lines; the data output end is directly electrically connected to the data lines; or,

[0299] The gating circuit is also electrically connected to the data line, and is used to control the connection or disconnection between the data output terminal and the data line under the control of the gating control signal.

[0300] In at least one embodiment of the present invention,

[0301] The source driver is disposed on a first side of the display panel, and the driving circuit is disposed on the first side of the display panel; or,

[0302] The source driver is disposed on a first side of the display panel, and the driving circuit is disposed on a second side of the display panel. The first side and the second side are opposite sides.

[0303] For example, the first side may be a lower side, and the second side may be an upper side, but the present invention is not limited thereto.

[0304] Fig.17 As shown, the area labeled A0 is the display area of ​​the display panel;

[0305] The line labeled DL1 is the first column of data lines, the line labeled CGL1 is the first column of scan lines, the line labeled DL2 is the second column of data lines, the line labeled CGL2 is the second column of scan lines; the line labeled DL3 is the third column of data lines, the line labeled CGL3 is the third column of scan lines, the line labeled DLm is the mth column of data lines, the line labeled CGLm is the mth column of scan lines, the line labeled DLM is the Mth column of data lines, the line labeled CGLM is the Mth column of scan lines;

[0306] Both m and M are positive integers;

[0307] The one labeled SI is the source driver;

[0308] The first data output terminal of the source driver SI is labeled S1, the second data output terminal of the source driver SI is labeled S2, the third data output terminal of the source driver SI is labeled S3, the mth data output terminal of the source driver SI is labeled Sm, and the Mth data output terminal of the source driver SI is labeled SM;

[0309] The first first selection control line is labeled SW11, and the second first selection control line is labeled SW21;

[0310] The source driver SI is electrically connected to SW11 and SW21, and is used to provide a first first gating control signal to SW11 and a second first gating control signal to SW21;

[0311] exist Fig.17 , the one labeled X1 is the first driving circuit, the one labeled X2 is the second driving circuit, the one labeled X3 is the third driving circuit, the one labeled Xm is the m-th driving circuit, and the one labeled XM is the M-th driving circuit;

[0312] X1 is electrically connected to DL1 and CGL1, respectively, X2 is electrically connected to DL2 and CGL2, respectively, X3 is electrically connected to DL3 and CGL3, respectively, Xm is electrically connected to DLm and CGLm, respectively, and XM is electrically connected to DLM and CGLM, respectively;

[0313] The source driver SI is disposed below the display area A0, and the first driving circuit X1, the second driving circuit X2, the third driving circuit X3, the mth driving circuit Xm and the Mth driving circuit XM are disposed below the display area A0.

[0314] Fig.18 At least one embodiment of the display panel shown is Fig.17 The difference of at least one embodiment of the display panel shown is that the first driving circuit X1 , the second driving circuit X2 , the third driving circuit X3 , the mth driving circuit Xm and the Mth driving circuit XM are arranged above A0 .

[0315] Fig.19 At least one embodiment of the display panel shown is Fig.18 The difference of at least one embodiment of the display panel shown is that:

[0316] The data output terminals of the source driver SI are concentrated in the middle of the display panel to achieve a narrow lower frame. Fig.19 At least one embodiment of the display panel shown incorporates a FIP (Fanout In Pixel) embodiment.

[0317] An embodiment of the present invention provides a driving scheme for an OLED display. The local refresh pixel circuit cooperates with the source driving circuit and the driving scheme, and can update the local screen through the HCT control signal (the HCT control signal can be a data signal provided by the source driver through its data output terminal during the blank time period), while the remaining screens do not need to be charged and discharged multiple times, thereby further reducing the power consumption of the OLED display, or achieving ultra-low power consumption by partially updating the display screen.

[0318] In at least one embodiment of the present invention, for a display device, when it is necessary to update part of the screen, such as only the date and time part needs to be updated. In the row direction, it is possible to control whether the gate drive circuit outputs: in the row where the screen needs to be updated, the first gate drive signal is normally output to control the first control transistor in the pixel circuit in the display area to be normally turned on for data update; in the row where the screen does not need to be updated, the potential of the first gate drive signal is always maintained to turn off the first control transistor to ensure that the pixel brightness remains unchanged, thereby achieving local refresh in the row direction. In the column direction, it can be achieved by controlling whether the column scan line turns on the second control transistor in the pixel circuit: in the blank period between the two frames of display time, the source driver outputs HCT pulse (pulse) to write different scan signals to the column scan line. If the current column needs to be updated, the column scan line needs to ensure that the second control transistor is always turned on, so that the current column can be refreshed normally; if some columns do not need to be updated, the column scan line needs to ensure that the second control transistor in the pixel circuit of these columns is always turned off.

[0319] In at least one embodiment of the present invention, the pixel circuit may include a light emitting element, a light emitting driving circuit and a control circuit;

[0320] The light-emitting driving circuit is electrically connected to the first node, the second node and the third node respectively, and is used to generate a driving current flowing through the second node and the third node under the control of the potential of the first node;

[0321] The light emitting element is electrically connected to the third node;

[0322] The control circuit is electrically connected to the first gate line, the scan line, the first node and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the first gate drive signal provided by the first gate line and the scan signal provided by the scan line.

[0323] In a specific implementation, the pixel circuit may include a control circuit and a light-emitting driving circuit. The light-emitting driving circuit generates a driving current under the control of the potential of the first node. The control circuit controls the connection or disconnection between the first node and the third node under the control of a first gate driving signal provided by a first gate line and a scanning signal provided by a scanning line. The driving current may be a current that drives the light-emitting element to emit light.

[0324] like Fig. 20 As shown, the pixel circuit may include a light emitting element E0, a control circuit 201 and a light emitting driving circuit 230;

[0325] The light emitting driving circuit 200 is electrically connected to the first node N1, the second node N2 and the third node N3 respectively, and is used to generate a driving current flowing through the second node N2 and the third node N3 under the control of the potential of the first node N1;

[0326] The light emitting element E0 is electrically connected to the third node N3;

[0327] The control circuit 201 is electrically connected to the first gate line NG, the scan line CGL, the first node N1 and the third node N3, respectively, and is used to control the connection or disconnection between the first node N1 and the third node N3 under the control of the first gate driving signal provided by the first gate line NG and the scan signal provided by the scan line CGL.

[0328] Optionally, the control circuit includes a first control circuit and a second control circuit;

[0329] The first control circuit is electrically connected to the first gate line, the first node and the intermediate node respectively, and the first control circuit is used to control the connection or disconnection between the first node and the intermediate node under the control of the first gate driving signal provided by the first gate line;

[0330] The second control circuit is electrically connected to the scan line, the intermediate node and the third node respectively, and is used to control the connection or disconnection between the intermediate node and the third node under the control of the scan signal provided by the scan line.

[0331] In a specific implementation, the control circuit may include a first control circuit and a second control circuit. The first control circuit controls the connection or disconnection between the first node and the intermediate node under the control of a first gate drive signal provided by a first gate line, and the second control circuit controls the connection or disconnection between the intermediate node and the third node under the control of a scan signal provided by the scan line.

[0332] like Fig.21 As shown, in Fig. 20 Based on at least one embodiment of the pixel circuit shown, the control circuit includes a first control circuit 241 and a second control circuit 242;

[0333] The first control circuit 241 is electrically connected to the first gate line NG, the first node N1 and the middle node NZ respectively, and is used to control the connection or disconnection between the first node N1 and the middle node NZ under the control of the first gate driving signal provided by the first gate line NG;

[0334] The second control circuit 242 is electrically connected to the scan line CGL, the middle node NZ and the third node N3 respectively, and is used to control the connection or disconnection between the middle node NZ and the third node N3 under the control of the scan signal provided by the scan line CGL.

[0335] Optionally, the control circuit includes a first control circuit and a second control circuit;

[0336] The first control circuit is electrically connected to the first gate line, the third node and the intermediate node respectively, and is used to control the connection or disconnection between the third node and the intermediate node under the control of the first gate driving signal provided by the first gate line;

[0337] The second control circuit is electrically connected to the scan line, the intermediate node and the first node respectively, and is used to control the connection or disconnection between the intermediate node and the first node under the control of the scan signal provided by the scan line.

[0338] In a specific implementation, the control circuit may include a first control circuit and a second control circuit, wherein the first control circuit controls the connection or disconnection between the third node and the intermediate node under the control of a first gate drive signal provided by the first gate line; and the second control circuit controls the connection or disconnection between the intermediate node and the first node under the control of a scan signal provided by the scan line.

[0339] like Fig. 22 As shown, in Fig. 20 Based on at least one embodiment of the pixel circuit shown, the control circuit includes a first control circuit 241 and a second control circuit 242;

[0340] The first control circuit 241 is electrically connected to the first gate line NG, the third node N3 and the middle node NZ respectively, and is used to control the connection or disconnection between the third node N3 and the middle node NZ under the control of the first gate driving signal provided by the first gate line NG;

[0341] The second control circuit 242 is electrically connected to the scan line CGL, the middle node NZ and the first node N1 respectively, and is used to control the connection or disconnection between the middle node NZ and the first node N1 under the control of the scan signal provided by the scan line CGL.

[0342] Optionally, the light emitting element may be an organic light emitting diode, but the present invention is not limited thereto. In actual operation, the light emitting element may also be other types of light emitting diodes.

[0343] In at least one embodiment of the present invention, the pixel circuit may further include a first initialization circuit;

[0344] The first initialization circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the second node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the second node under the control of the first initial control signal provided by the first initial control terminal.

[0345] In a specific implementation, the display period may include a first initialization time period and a second initialization time period which are set successively;

[0346] In the first initialization time period, the control circuit controls the first node to be connected to the third node under the control of the first gate drive signal and the scan signal; the first initialization circuit writes the first initial voltage to the second node under the control of the first initial control signal; the light emitting drive circuit controls the second node to be connected to the third node under the control of the potential of the first node;

[0347] During the second initialization time period, the control circuit controls the first node and the third node to be disconnected under the control of the first gate drive signal and the scan signal; the first initialization circuit writes the first initial voltage to the second node under the control of the first initial control signal; and the light-emitting drive circuit controls the second node and the third node to be connected under the control of the potential of the first node.

[0348] When the pixel circuit described in at least one embodiment of the present invention is in operation, in a first initialization time period, before data is written, the potentials of the first node, the second node and the third node are initialized to reduce subsequent charging differences. In a second initialization time period, the first initialization circuit writes the first initial voltage to the second node, and the light-emitting driving circuit controls the connection between the second node and the third node so that the driving transistor included in the light-emitting driving circuit is in a biased state, which can improve the hysteresis phenomenon.

[0349] Optionally, the pixel circuit may further include a second initialization circuit;

[0350] The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal and the third node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the third node under the control of the second initial control signal provided by the second initial control terminal.

[0351] In a specific implementation, the pixel circuit may further include a second initialization circuit;

[0352] In a third initialization time period set between the first initialization time period and the second initialization time period, before the data writing time period, the second initialization circuit writes the second initial voltage to the third node under the control of the second initial control signal, so that at the beginning of the data writing time period, the driving transistor included in the light-emitting driving circuit can be turned on, which is convenient for data voltage writing and threshold voltage compensation.

[0353] The pixel circuit described in at least one embodiment of the present invention may further include a data writing circuit, a first light emitting control circuit, a second light emitting control circuit and an energy storage circuit;

[0354] The data writing circuit is electrically connected to the second gate line, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the second gate driving signal provided by the second gate line;

[0355] The first light-emitting control circuit is electrically connected to the light-emitting control line, the power supply voltage terminal and the second node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control line;

[0356] The second light emitting control circuit is electrically connected to the light emitting control line, the third node and the first electrode of the light emitting element respectively, and is used to control the third node to be electrically connected to the first electrode of the light emitting element and the second electrode of the light emitting element to be electrically connected to the third voltage terminal under the control of the light emitting control signal;

[0357] The energy storage circuit is electrically connected to the first node and is used for storing electric energy.

[0358] In a specific implementation, the pixel circuit may further include a data writing circuit, a first light-emitting control circuit, a second light-emitting control circuit and an energy storage circuit; the data writing circuit is used to write the data voltage into the second node, the first light-emitting control circuit and the second light-emitting control circuit are used to control the conduction light-emitting path, and the energy storage circuit is used to store electrical energy.

[0359] Optionally, the third voltage terminal may be a low level terminal or a ground terminal, but is not limited thereto.

[0360] In at least one embodiment of the present invention, the pixel circuit may further include a third initialization circuit;

[0361] The third initialization circuit is electrically connected to the first initial control terminal, the third initial voltage terminal and the first pole of the light-emitting element respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first pole of the light-emitting element under the control of the first initial control signal provided by the first initial control terminal.

[0362] In a specific implementation, the pixel circuit may further include a third initialization circuit, which, under the control of the first initial control signal, writes a third initial voltage into the first electrode of the light-emitting element to control the light-emitting element not to emit light and clear the residual charge in the first electrode of the light-emitting element.

[0363] Optionally, the first control circuit includes a first control transistor, and the second control circuit includes a second control transistor;

[0364] The gate of the first control transistor is electrically connected to the first gate line, the first electrode of the first control transistor is electrically connected to the first node, and the second electrode of the first control transistor is electrically connected to the intermediate node;

[0365] A gate of the second control transistor is electrically connected to the scan line, a first electrode of the second control transistor is electrically connected to the intermediate node, and a second electrode of the second control transistor is electrically connected to the third node.

[0366] Optionally, the first control circuit includes a first control transistor, and the second control circuit includes a second control transistor;

[0367] The gate of the first control transistor is electrically connected to the first gate line, the first electrode of the first control transistor is electrically connected to the intermediate node, and the second electrode of the first control transistor is electrically connected to the third node;

[0368] A gate of the second control transistor is electrically connected to the scan line, a first electrode of the second control transistor is electrically connected to the first node, and a second electrode of the second control transistor is electrically connected to the intermediate node.

[0369] Optionally, the first initialization circuit includes a first initialization transistor;

[0370] A gate of the first initialization transistor is electrically connected to the first initial control terminal, a first electrode of the first initialization transistor is electrically connected to the first initial voltage terminal, and a second electrode of the first initialization transistor is electrically connected to the second node.

[0371] Optionally, the second initialization circuit includes a second initialization transistor;

[0372] A gate of the second initialization transistor is electrically connected to the second initial control terminal, a first electrode of the second initialization transistor is electrically connected to the second initial voltage terminal, and a second electrode of the second initialization transistor is electrically connected to the third node.

[0373] Optionally, the data writing circuit includes a writing transistor, the first light emitting control circuit includes a first light emitting control transistor, and the second light emitting control circuit includes a second light emitting control transistor; the light emitting driving circuit includes a driving transistor, and the energy storage circuit includes a storage capacitor;

[0374] The gate of the write transistor is electrically connected to the second gate line, the first electrode of the write transistor is electrically connected to the data line, and the second electrode of the write transistor is electrically connected to the second node;

[0375] The gate of the first light emission control transistor is electrically connected to the light emission control line, the first electrode of the first light emission control transistor is electrically connected to the power supply voltage terminal, and the second electrode of the first light emission control transistor is electrically connected to the second node;

[0376] The gate of the second light emission control transistor is electrically connected to the light emission control line, the first electrode of the second light emission control transistor is electrically connected to the third node, and the second electrode of the second light emission control transistor is electrically connected to the first electrode of the light emitting element;

[0377] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;

[0378] The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to a power supply voltage terminal.

[0379] Optionally, the third initialization circuit includes a third initialization transistor;

[0380] The gate of the third initialization transistor is electrically connected to the first initial control terminal, the first electrode of the third initialization transistor is electrically connected to the third initial voltage terminal, and the second electrode of the third initialization transistor is electrically connected to the first electrode of the light emitting element.

[0381] like Fig.23 As shown, in Fig.21 Based on at least one embodiment of the pixel circuit shown in the figure, the pixel circuit described in at least one embodiment of the present invention may further include a first initialization circuit 231, a second initialization circuit 232, a data writing circuit 233, a first light emitting control circuit 234, a second light emitting control circuit 235, a storage circuit 236 and a third initialization circuit 237;

[0382] The first initialization circuit 231 is electrically connected to the first initial control terminal HR, the first initial voltage terminal I1 and the second node N2 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the second node N2 under the control of the first initial control signal provided by the first initial control terminal HR;

[0383] The second initialization circuit 232 is electrically connected to the second initial control terminal PR, the second initial voltage terminal I2 and the third node N3 respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the third node N3 under the control of the second initial control signal provided by the second initial control terminal PR;

[0384] The data writing circuit 233 is electrically connected to the second gate line PG, the data line DT and the second node N2 respectively, and is used to write the data voltage Vdata provided by the data line DT into the second node N2 under the control of the second gate driving signal provided by the second gate line PG;

[0385] The first light emitting control circuit 234 is electrically connected to the light emitting control line E1, the power supply voltage terminal ELVDD and the second node N2 respectively, and is used to control the connection or disconnection between the power supply voltage terminal ELVDD and the second node N2 under the control of the light emitting control signal provided by the light emitting control line E1;

[0386] The second light emitting control circuit 235 is electrically connected to the light emitting control line E1, the third node N3 and the first electrode of the light emitting element E0 respectively, and is used to control the third node N3 to be electrically connected to the first electrode of the light emitting element E0 and the second electrode of the light emitting element E0 to be electrically connected to the third voltage terminal V3 under the control of the light emitting control signal;

[0387] The energy storage circuit 236 is electrically connected to the first node N1 and is used to store electrical energy;

[0388] The third initialization circuit 237 is electrically connected to the first initial control terminal HR, the third initial voltage terminal I3 and the first electrode of the light-emitting element E0, respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first electrode of the light-emitting element E0 under the control of the first initial control signal provided by the first initial control terminal HR.

[0389] like Fig.24 As shown, in Fig. 22Based on at least one embodiment of the pixel circuit shown in the figure, the pixel circuit described in at least one embodiment of the present invention may further include a first initialization circuit 231, a second initialization circuit 232, a data writing circuit 233, a first light emitting control circuit 234, a second light emitting control circuit 235, a storage circuit 236 and a third initialization circuit 237;

[0390] The first initialization circuit 231 is electrically connected to the first initial control terminal HR, the first initial voltage terminal I1 and the second node N2 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the second node N2 under the control of the first initial control signal provided by the first initial control terminal HR;

[0391] The second initialization circuit 232 is electrically connected to the second initial control terminal PR, the second initial voltage terminal I2 and the third node N3 respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the third node N3 under the control of the second initial control signal provided by the second initial control terminal PR;

[0392] The data writing circuit 233 is electrically connected to the second gate line PG, the data line DT and the second node N2 respectively, and is used to write the data voltage Vdata provided by the data line DT into the second node N2 under the control of the second gate driving signal provided by the second gate line PG;

[0393] The first light emitting control circuit 234 is electrically connected to the light emitting control line E1, the power supply voltage terminal ELVDD and the second node N2 respectively, and is used to control the connection or disconnection between the power supply voltage terminal ELVDD and the second node N2 under the control of the light emitting control signal provided by the light emitting control line E1;

[0394] The second light emitting control circuit 235 is electrically connected to the light emitting control line E1, the third node N3 and the first electrode of the light emitting element E0 respectively, and is used to control the third node N3 to be electrically connected to the first electrode of the light emitting element E0 and the second electrode of the light emitting element E0 to be electrically connected to the third voltage terminal V3 under the control of the light emitting control signal;

[0395] The energy storage circuit 236 is electrically connected to the first node N1 and is used to store electrical energy;

[0396] The third initialization circuit 237 is electrically connected to the first initial control terminal HR, the third initial voltage terminal I3 and the first electrode of the light-emitting element E0, respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first electrode of the light-emitting element E0 under the control of the first initial control signal provided by the first initial control terminal HR.

[0397] like Fig.25 As shown, in Fig.23 Based on at least one embodiment of the pixel circuit shown, the first control circuit includes a first control transistor M1, the second control circuit includes a second control transistor M2, and the light emitting driving circuit includes a driving transistor M0;

[0398] A gate of the first control transistor M1 is electrically connected to the first gate line NG, a source of the first control transistor M1 is electrically connected to the first node N1, and a second electrode of the first control transistor M1 is electrically connected to the middle node NZ;

[0399] The gate of the second control transistor M2 is electrically connected to the scan line CGL, the source of the second control transistor M2 is electrically connected to the middle node NZ, and the drain of the second control transistor M2 is electrically connected to the third node N3;

[0400] The gate of the driving transistor M0 is electrically connected to the first node N1, the source of the driving transistor M0 is electrically connected to the second node N2, and the drain of the driving transistor M0 is electrically connected to the third node N3;

[0401] The first initialization circuit includes a first initialization transistor M3;

[0402] The gate of the first initialization transistor M3 is electrically connected to the first initial control terminal HR, the source of the first initialization transistor M3 is electrically connected to the first initial voltage terminal I1, and the drain of the first initialization transistor M3 is electrically connected to the second node N2; the first initial voltage terminal I1 is used to provide a first initial voltage Vinit1;

[0403] The second initialization circuit includes a second initialization transistor M4;

[0404] The gate of the second initialization transistor M4 is electrically connected to the second initial control terminal PR, the source of the second initialization transistor M4 is electrically connected to the second initial voltage terminal I2, and the drain of the second initialization transistor M4 is electrically connected to the third node N3; the second initial voltage terminal I2 is used to provide a second initial voltage Vinit2;

[0405] The data writing circuit includes a writing transistor M5, the first light emitting control circuit includes a first light emitting control transistor M6, and the second light emitting control circuit includes a second light emitting control transistor M7; the energy storage circuit includes a storage capacitor Cst; the light emitting element is an organic light emitting diode O1;

[0406] The gate of the write transistor M5 is electrically connected to the second gate line PG, the source of the write transistor M5 is electrically connected to the data line DT, and the drain of the write transistor M5 is electrically connected to the second node N2;

[0407] The gate of the first light emission control transistor M6 is electrically connected to the light emission control line E1, the source of the first light emission control transistor M6 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the first light emission control transistor M6 is electrically connected to the second node N2;

[0408] A gate of the second light emission control transistor M7 is electrically connected to the light emission control line E1, a source of the second light emission control transistor M7 is electrically connected to the third node N3, and a drain of the second light emission control transistor M7 is electrically connected to the anode of the organic light emitting diode O1;

[0409] A first end of the storage capacitor Cst is electrically connected to the first node N1, and a second end of the storage capacitor Cst is electrically connected to the power supply voltage terminal ELVDD;

[0410] The third initialization circuit includes a third initialization transistor M8;

[0411] The gate of the third initialization transistor M8 is electrically connected to the first initial control terminal HR, the source of the third initialization transistor M8 is electrically connected to the third initial voltage terminal I3, and the drain of the third initialization transistor M8 is electrically connected to the anode of the organic light emitting diode O1;

[0412] The cathode of the organic light emitting diode O1 is electrically connected to the low level end ELVSS.

[0413] exist Fig.25 In at least one embodiment of the pixel circuit shown, M1 and M2 are n-type transistors, and the other transistors are p-type transistors, but the present invention is not limited thereto.

[0414] like Fig.26A As shown, the present invention Fig.25 When at least one embodiment of the pixel circuit shown is in operation, a frame display time may include a first initialization time period TI1, a third initialization time period TI3, a data writing time period TX, a second initialization time period TI2 and a light emitting time period TF which are successively set; during the frame display time, CG may output a high voltage signal to control M2 to be turned on;

[0415] In the first initialization period TI1, the third initialization period TI3 ​​and the data writing period TX, NG outputs a high voltage signal to control M1 to be turned on;

[0416] In the first initialization period TI1, the third initialization period TI3, the data writing period TX and the second initialization period TI2, E1 provides a high voltage signal, and M6 and M7 are turned off;

[0417] In the second initialization period TI2 and the light-emitting period TF, NG outputs a low voltage signal to control M1 to turn off;

[0418] In the first initialization time period TI1, HR outputs a low voltage signal, PR and PG both output high voltage signals, M3 is turned on to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the second node N2, M0 is turned on to control the connection between N2 and N3, M1 and M2 are turned on to control the connection between N1 and N3 to initialize the potential of the first node N1, the potential of the second node N2 and the potential of the third node N3 to reduce the subsequent charging difference;

[0419] In the third initialization period TI3, PR outputs a low voltage signal, HR and PG both output high voltage signals, and M4 is turned on to write the second initial voltage Vinit2 provided by I2 into the third node N3, so that M0 can be turned on when the data writing period TX starts;

[0420] In the data writing period TX, HR and PR both output high voltage signals, PG outputs low voltage signals, M5 is turned on, and DT provides data voltage Vdata to N2;

[0421] At the beginning of the data writing period TX, M0 is turned on, Vdata charges Cst, until the potential of the first node N1 becomes Vdata+Vth, and M0 is turned off; wherein Vth is the threshold voltage of M0;

[0422] In the second initialization time period TI2, HR provides a low voltage signal, PR and PG both output high voltage signals, M3 is turned on to write Vinit1 into the second node N2, M0 is turned on to connect N2 and N3. At this time, the potential of N1 is a smaller positive voltage, the potential of N2 and the potential of N3 are higher positive voltages, M0 is in a bias state, and all driving transistors included in the display panel are in a bias state, which can improve the hysteresis phenomenon.

[0423] In at least one embodiment of the present invention, the voltage value of Vinit1 may be a positive value, for example, the voltage value of Vinit1 may be greater than or equal to 4V and less than or equal to 7V;

[0424] The voltage value of Vinit2 and the voltage value of Vinit3 may be negative values, for example, the voltage value of Vinit2 and the voltage value of Vinit3 may be greater than or equal to -5V and less than or equal to -3V;

[0425] But it is not limited to this.

[0426] The present invention Fig.25 When at least one embodiment of the pixel circuit shown is in operation, in the first initialization time period, the potential of N1, the potential of N2 and the potential of N3 are all set to the reference voltage, so that in the data writing time period, the data voltage of the previous frame display time will not affect the writing of the data voltage of the current frame.

[0427] Fig.25 At least one embodiment of the pixel circuit shown in the figure is in operation, when it is not necessary to refresh the data voltage of the pixel circuit, it is necessary to control CG to output a low voltage signal during at least part of the blank period between two frames of display time, and CG continues to output a low voltage signal during the next frame of display time to control M2 to be turned off, so that the data voltage will not be written, so as to maintain the display screen without refreshing the screen;

[0428] When the data voltage of the pixel circuit needs to be refreshed, it is necessary to control CG to output a high voltage signal during at least part of the blank time period between two frames of display time, and continue to output a high voltage signal during the next frame of display time to control M2 to turn on, so as to write the data voltage during the data writing time period to refresh the screen.

[0429] exist Fig.26A In the working timing diagram shown, one frame display time can be a refresh frame.

[0430] like Fig.26B As shown, the present invention Fig.25 When at least one embodiment of the pixel circuit shown is in operation, the holding frame may include a holding initial time period TBC and a holding light emitting time period TBF which are set successively;

[0431] In the initial time period TBC, HR outputs a low voltage signal, NG outputs a low voltage signal, PR and PG both output high voltage signals, E1 provides a high voltage signal, M1 is turned off to control the disconnection between N1 and N3, M6 and M7 are turned off, and M5 is turned off; M3 and M8 are turned on, I1 provides a first initial voltage Vinit1 to the second node N2, driving transistor M0 is turned on to control the connection between N2 and N3, and the potential of the second node N2 and the potential of the third node N3 are initialized to improve the hysteresis phenomenon; I3 provides a third initial voltage Vinit3 to the third node N3, and initializes the potential of the anode of O1, controls O1 not to emit light, and clears the residual charge of the anode of O1;

[0432] During the luminous period TBF, E1 provides a low voltage signal, HR provides a high voltage signal, NG outputs a low voltage signal, PR and PG both output high voltage signals, M1, M2, M3, M4, M5 and M8 are all turned off, M6 and M7 are turned on, and M0 drives O1 to emit light.

[0433] Fig. 27 At least one embodiment of the pixel circuit shown is Fig.25 The difference of at least one embodiment of the pixel circuit shown is that M2 is a p-type transistor.

[0434] Fig. 27 At least one embodiment of the pixel circuit shown in the figure is in operation, when it is not necessary to refresh the data voltage of the pixel circuit, it is necessary to control CG to output a high voltage signal during at least part of the blank period between two frames of display time, and CG continues to output a low voltage signal during the next frame of display time to control M2 to be turned off, so that the data voltage will not be written, so as to maintain the display screen without refreshing the screen;

[0435] When the data voltage of the pixel circuit needs to be refreshed, it is necessary to control CG to output a low voltage signal during at least part of the blank time period between two frames of display time, and continue to output a high voltage signal during the next frame of display time to control M2 to turn on, so as to write the data voltage during the data writing time period to refresh the screen. Fig.28 At least one embodiment of the pixel circuit shown is Fig.25 The difference of at least one embodiment of the pixel circuit shown is that:

[0436] The gate of the first control transistor M1 is electrically connected to the first gate line NG, the source of the first control transistor M1 is electrically connected to the middle node NZ, and the drain of the first control transistor M1 is electrically connected to the third node N3;

[0437] A gate of the second control transistor M2 is electrically connected to the scan line CGL, a source of the second control transistor M2 is electrically connected to the first node N1, and a drain of the second control transistor M2 is electrically connected to the intermediate node NZ.

[0438] exist Fig.28 In at least one embodiment of the pixel circuit shown, both M1 and M2 are n-type transistors.

[0439] Fig.28At least one embodiment of the pixel circuit shown in the figure is in operation, when it is not necessary to refresh the data voltage of the pixel circuit, it is necessary to control CG to output a low voltage signal during at least part of the blank period between two frames of display time, and CG continues to output a low voltage signal during the next frame of display time to control M2 to be turned off, so that the data voltage will not be written, so as to maintain the display screen without refreshing the screen;

[0440] When the data voltage of the pixel circuit needs to be refreshed, it is necessary to control CG to output a high voltage signal during at least part of the blank time period between two frames of display time, and continue to output a high voltage signal during the next frame of display time to control M2 to turn on, so as to write the data voltage during the data writing time period to refresh the screen.

[0441] Fig.29 At least one embodiment of the pixel circuit shown is Fig.28 The difference of at least one embodiment of the pixel circuit shown is that M2 is a p-type transistor.

[0442] Fig.29 At least one embodiment of the pixel circuit shown in the figure is in operation, when it is not necessary to refresh the data voltage of the pixel circuit, it is necessary to control CG to output a high voltage signal during at least part of the blank period between two frames of display time, and CG continuously outputs a low voltage signal during the next frame of display time to control M2 to be turned off, so that the data voltage is not written, so as to maintain the display screen without refreshing the screen;

[0443] When the data voltage of the pixel circuit needs to be refreshed, it is necessary to control CG to output a low voltage signal during at least part of the blank time period between two frames of display time, and continue to output a high voltage signal during the next frame of display time to control M2 to turn on, so as to write the data voltage during the data writing time period to refresh the screen.

[0444] The display device described in the embodiment of the present invention includes the above-mentioned display panel.

[0445] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A driving circuit, characterized in that: including a gating circuit; The gating circuit is electrically connected to the gating control line, the data output terminal of the source driver and the scanning line respectively, and is used to control the connection or disconnection between the data output terminal and the scanning line under the control of the gating control signal provided by the gating control line.

2. The driving circuit according to claim 1, characterized in that: The data output end is electrically connected to the data line.

3. The driving circuit according to claim 1, wherein: The gating circuit is also electrically connected to the data line, and is used to control the connection or disconnection between the data output terminal and the data line under the control of the gating control signal.

4. The driving circuit according to claim 3, characterized in that: The gating circuit includes a first gating subcircuit and a second gating subcircuit; The first gating subcircuit is electrically connected to the gating control line, the data output terminal and the scan line respectively, and is used to control the connection or disconnection between the data output terminal and the scan line under the control of the gating control signal provided by the gating control line; The second gating subcircuit is electrically connected to the gating control line, the data output terminal and the data line respectively, and is used to control the connection or disconnection between the data output terminal and the data line under the control of the gating control signal.

5. The driving circuit according to claim 3, characterized in that: The gating control line includes a first gating control line and a second gating control line; the gating circuit includes a first gating subcircuit and a second gating subcircuit; The first gating subcircuit is electrically connected to the first gating control line, the second gating control line, the data output terminal and the scan line respectively, and is used to control the connection or disconnection between the data output terminal and the scan line under the control of a first gating control signal provided by the first gating control line and a second gating control signal provided by the second gating control line; The second selection subcircuit is electrically connected to the first selection control line, the second selection control line, the data output end and the data line respectively, and is used to control the connection or disconnection between the data output end and the data line under the control of the first selection control signal and the second selection control signal.

6. The driving circuit according to claim 1, characterized in that: The gating circuit includes a first transistor, and the gating control line includes a first gating control line; The gate of the first transistor is electrically connected to the first selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line; the first transistor is a p-type transistor; or; The gating circuit includes a first transistor, and the gating control line includes a second gating control line; The gate of the first transistor is electrically connected to the second selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line; the first transistor is an n-type transistor.

7. The driving circuit according to claim 3, characterized in that: The gating circuit includes a first transistor and a second transistor, and the gating control line includes a first gating control line; The gate of the first transistor is electrically connected to the first selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line; The gate of the second transistor is electrically connected to the first selection control line, the first electrode of the second transistor is electrically connected to the data output terminal, and the second electrode of the second transistor is electrically connected to the data line; The first transistor is a p-type transistor, and the second transistor is an n-type transistor.

8. The driving circuit according to claim 3, characterized in that: The gating circuit includes a first transistor and a second transistor, and the gating control line includes a second gating control line; The gate of the first transistor is electrically connected to the second selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line; The gate of the second transistor is electrically connected to the second selection control line, the first electrode of the second transistor is electrically connected to the data output terminal, and the second electrode of the second transistor is electrically connected to the data line; The first transistor is an n-type transistor, and the second transistor is a p-type transistor.

9. The driving circuit according to claim 4, characterized in that: The gating control line includes a first gating control line and a second gating control line, the first gating subcircuit includes a first transistor, and the second gating subcircuit includes a second transistor; The gate of the first transistor is electrically connected to the first selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line; The gate of the second transistor is electrically connected to the second selection control line, the first electrode of the second transistor is electrically connected to the data output terminal, and the second electrode of the second transistor is electrically connected to the data line; The first transistor and the second transistor are both p-type transistors.

10. The driving circuit according to claim 4, characterized in that: The gating control line includes a first gating control line and a second gating control line, the first gating subcircuit includes a first transistor, and the second gating subcircuit includes a second transistor; The gate of the first transistor is electrically connected to the second selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line; The gate of the second transistor is electrically connected to the first selection control line, the first electrode of the second transistor is electrically connected to the data output terminal, and the second electrode of the second transistor is electrically connected to the data line; The first transistor and the second transistor are both n-type transistors.

11. The driving circuit according to claim 2, characterized in that: The gating circuit includes a first transistor and a second transistor, and the gating control line includes a first gating control line and a second gating control line; The gate of the first transistor is electrically connected to the first selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line; The gate of the second transistor is electrically connected to the second selection control line, the second electrode of the second transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line; The first transistor is a p-type transistor, and the second transistor is an n-type transistor.

12. The driving circuit according to claim 5, characterized in that: The gate control line includes a first gate control line and a second gate control line; The first gating control circuit includes a first transistor and a second transistor, and the second gating control circuit includes a third transistor and a fourth transistor; The gate of the first transistor is electrically connected to the first selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the scan line; The gate of the second transistor is electrically connected to the second selection control line, the first electrode of the second transistor is electrically connected to the data output terminal, and the second electrode of the second transistor is electrically connected to the scan line; The gate of the third transistor is electrically connected to the first selection control line, the first electrode of the third transistor is electrically connected to the data output terminal, and the second electrode of the third transistor is electrically connected to the data line; The gate of the fourth transistor is electrically connected to the second selection control line, the first electrode of the fourth transistor is electrically connected to the data output terminal, and the second electrode of the fourth transistor is electrically connected to the data line; The first transistor and the fourth transistor are p-type transistors, and the second transistor and the third transistor are n-type transistors.

13. A driving method, applied to the driving circuit according to any one of claims 1 to 12, characterized in that: The driving method comprises: during at least a portion of a blank period between two display frames, The gating circuit controls the data output terminal to be connected to the scanning line under the control of the gating control signal provided by the gating control line.

14. The driving method according to claim 13, characterized in that: The data output terminal is electrically connected to the data line; the driving method further comprises: During a data writing period in a frame of display time, the data output terminal provides a data voltage to a data line electrically connected thereto.

15. The driving method according to claim 13, characterized in that: The gating circuit is also electrically connected to the data line, and the driving method further includes: In a data writing period in a frame of display time, the gating circuit controls the connection between the data output terminal and the data line under the control of the gating control signal, so that the data output terminal provides a data voltage to the data line.

16. A display panel, characterized in that: A method comprising: comprising a source driver, a plurality of scanning lines and a driving circuit as claimed in any one of claims 1 to 12; The source driver includes a plurality of data output terminals; The driving circuit includes a gating circuit which is electrically connected to a gating control line, the data output terminal and the scanning line respectively, and is used to control the connection or disconnection between the data output terminal and the scanning line under the control of a gating control signal provided by the gating control line.

17. The display panel according to claim 16, wherein: Also included are multiple columns of pixel circuits; A column of the scanning lines is electrically connected to a column of the pixel circuits respectively.

18. The display panel according to claim 16, wherein: The display panel includes a plurality of columns of data lines; the data output terminal is directly electrically connected to the data lines; or, The gating circuit is also electrically connected to the data line, and is used to control the connection or disconnection between the data output terminal and the data line under the control of the gating control signal.

19. The display panel according to any one of claims 16 to 18, characterized in that: The source driver is disposed on a first side of the display panel, and the driving circuit is disposed on the first side of the display panel; or, The source driver is disposed on a first side of the display panel, and the driving circuit is disposed on a second side of the display panel. The first side and the second side are opposite sides.

20. The display panel according to claim 17, wherein: The pixel circuit includes a light emitting element, a light emitting driving circuit and a control circuit; The light-emitting driving circuit is electrically connected to the first node, the second node and the third node respectively, and is used to generate a driving current flowing through the second node and the third node under the control of the potential of the first node; The light emitting element is electrically connected to the third node; The control circuit is electrically connected to the first gate line, the scan line, the first node and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the first gate drive signal provided by the first gate line and the scan signal provided by the scan line.

21. The display panel according to claim 20, wherein: The control circuit includes a first control circuit and a second control circuit; The first control circuit is electrically connected to the first gate line, the first node and the intermediate node respectively, and the first control circuit is used to control the connection or disconnection between the first node and the intermediate node under the control of the first gate driving signal provided by the first gate line; The second control circuit is electrically connected to the scan line, the intermediate node and the third node respectively, and is used to control the connection or disconnection between the intermediate node and the third node under the control of the scan signal provided by the scan line.

22. The display panel according to claim 20, wherein: The control circuit includes a first control circuit and a second control circuit; The first control circuit is electrically connected to the first gate line, the third node and the intermediate node respectively, and is used to control the connection or disconnection between the third node and the intermediate node under the control of the first gate driving signal provided by the first gate line; The second control circuit is electrically connected to the scan line, the intermediate node and the first node respectively, and is used to control the connection or disconnection between the intermediate node and the first node under the control of the scan signal provided by the scan line.

23. The display panel according to any one of claims 20 to 22, characterized in that: The pixel circuit further includes a first initialization circuit; The first initialization circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the second node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the second node under the control of the first initial control signal provided by the first initial control terminal.

24. The display panel according to any one of claims 20 to 22, characterized in that: The pixel circuit also includes a second initialization circuit; The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal and the third node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the third node under the control of the second initial control signal provided by the second initial control terminal.

25. The display panel according to any one of claims 20 to 22, characterized in that: The pixel circuit also includes a data writing circuit, a first light emitting control circuit, a second light emitting control circuit and an energy storage circuit; The data writing circuit is electrically connected to the second gate line, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the second gate driving signal provided by the second gate line; The first light-emitting control circuit is electrically connected to the light-emitting control line, the power supply voltage terminal and the second node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control line; The second light emitting control circuit is electrically connected to the light emitting control line, the third node and the first electrode of the light emitting element respectively, and is used to control the third node to be electrically connected to the first electrode of the light emitting element and the second electrode of the light emitting element to be electrically connected to the third voltage terminal under the control of the light emitting control signal; The energy storage circuit is electrically connected to the first node and is used for storing electric energy.

26. The display panel according to claim 25, characterized in that: The pixel circuit further includes a third initialization circuit; The third initialization circuit is electrically connected to the first initial control terminal, the third initial voltage terminal and the first pole of the light-emitting element respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first pole of the light-emitting element under the control of the first initial control signal provided by the first initial control terminal.

27. The display panel according to claim 21, wherein: The first control circuit includes a first control transistor, and the second control circuit includes a second control transistor; The gate of the first control transistor is electrically connected to the first gate line, the first electrode of the first control transistor is electrically connected to the first node, and the second electrode of the first control transistor is electrically connected to the intermediate node; A gate of the second control transistor is electrically connected to the scan line, a first electrode of the second control transistor is electrically connected to the intermediate node, and a second electrode of the second control transistor is electrically connected to the third node.

28. The display panel according to claim 22, wherein: The first control circuit includes a first control transistor, and the second control circuit includes a second control transistor; The gate of the first control transistor is electrically connected to the first gate line, the first electrode of the first control transistor is electrically connected to the intermediate node, and the second electrode of the first control transistor is electrically connected to the third node; A gate of the second control transistor is electrically connected to the scan line, a first electrode of the second control transistor is electrically connected to the first node, and a second electrode of the second control transistor is electrically connected to the intermediate node.

29. The display panel according to claim 23, wherein: The first initialization circuit includes a first initialization transistor; A gate of the first initialization transistor is electrically connected to the first initial control terminal, a first electrode of the first initialization transistor is electrically connected to the first initial voltage terminal, and a second electrode of the first initialization transistor is electrically connected to the second node.

30. The display panel according to claim 24, wherein: The second initialization circuit includes a second initialization transistor; A gate of the second initialization transistor is electrically connected to the second initial control terminal, a first electrode of the second initialization transistor is electrically connected to the second initial voltage terminal, and a second electrode of the second initialization transistor is electrically connected to the third node.

31. The display panel according to claim 25, characterized in that: The data writing circuit includes a writing transistor, the first light emitting control circuit includes a first light emitting control transistor, and the second light emitting control circuit includes a second light emitting control transistor; the light emitting driving circuit includes a driving transistor, and the energy storage circuit includes a storage capacitor; The gate of the write transistor is electrically connected to the second gate line, the first electrode of the write transistor is electrically connected to the data line, and the second electrode of the write transistor is electrically connected to the second node; The gate of the first light emission control transistor is electrically connected to the light emission control line, the first electrode of the first light emission control transistor is electrically connected to the power supply voltage terminal, and the second electrode of the first light emission control transistor is electrically connected to the second node; The gate of the second light emission control transistor is electrically connected to the light emission control line, the first electrode of the second light emission control transistor is electrically connected to the third node, and the second electrode of the second light emission control transistor is electrically connected to the first electrode of the light emitting element; The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node; The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to a power supply voltage terminal.

32. The display panel according to claim 26, wherein: The third initialization circuit includes a third initialization transistor; The gate of the third initialization transistor is electrically connected to the first initial control terminal, the first electrode of the third initialization transistor is electrically connected to the third initial voltage terminal, and the second electrode of the third initialization transistor is electrically connected to the first electrode of the light emitting element.

33. A display device, characterized in that: Comprising a display panel as claimed in any one of claims 16 to 32.

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