Refresh circuit and method based on composite dielectric gate three-transistor memory

Abstract

The invention discloses a refreshing circuit and method based on a composite dielectric gate three-transistor memory. The refresh circuit comprises a sampling switch, a reset circuit, an inverter chain with a positive feedback loop, an output switch and a delayer, the read-out end of the memory is connected with the input end of the inverter chain through the sampling switch; the reset circuit is located between the sampling switch and the inverter chain and is connected with the input end of the inverter chain; the output end of the inverter chain is connected with the write-in end of the memory through the output switch; and the output end of the delayer is respectively connected with the inverter chain and the output switch. According to the refresh circuit, the original read-out and write-in structures of the memory are utilized to complete the operations of sensing the storage value and rewriting in the refresh process, so that the extra area overhead is avoided.

Description

Technical Field

[0001] The invention relates to a refresh circuit based on a composite dielectric gate three-transistor memory, belonging to the field of integrated circuits. Background Art

[0002] In response to the problems in the storage field where the integration of storage devices is limited by capacitance and the data retention time is short, a Chinese invention patent with application number CN202411088060.3 proposes a composite dielectric gate three-transistor memory, which is characterized by separation of writing and reading, and the read operation will not damage the stored content. Transistors are used to store charges to avoid large capacitance. The area of ​​a single memory is small, but the data retention time can reach seconds, which is better than most DRAM-type devices.

[0003] Common DRAM-type memory devices are volatile. The charge stored in the capacitor is mainly leaked in the form of transistor subthreshold leakage current, PN junction reverse bias leakage current, etc., resulting in data loss. The storage unit must be refreshed periodically to replenish the charge. Traditional 1T1C DRAM refreshes data by reading out. Although the data retention time of different DRAM units varies greatly, considering the need to meet the worst case, the array is usually refreshed in microseconds or milliseconds, which brings a large power consumption overhead. In addition, read and write operations cannot be performed during the refresh period, and the working speed of the memory is also affected. For 2T1C type DRAM units, since the capacitor charge will not be disturbed by the readout, the data does not need to be restored after the data is read out, and the existing circuit cannot be used to perform the refresh operation. The existing 2T1C DRAM solution tends to improve the data retention time. By developing new materials to make ultra-low leakage current transistors and building 3D large capacitors within the storage device area, the data retention time is extended to hundreds of microseconds to hundreds of seconds. In high-speed access applications, it can be equivalent to a "non-volatile" device, thereby reducing the refresh frequency or eliminating the refresh step. However, the non-volatility of DRAM has not changed in essence. In application scenarios that require long-term storage, the refresh circuit is still an essential part of DRAM. Summary of the invention

[0004] In order to solve the problem that multi-transistor structure memory cannot store data for a long time, the present invention provides a refresh circuit and method based on a composite dielectric gate three-transistor memory to achieve high-speed and stable refresh of the composite dielectric gate three-transistor memory with very small area overhead.

[0005] The technical solution adopted by the refresh circuit of the present invention is as follows:

[0006] A refresh circuit based on a composite dielectric gate three-transistor memory is connected to the composite dielectric gate three-transistor memory, the refresh circuit comprises a sampling switch S1, a reset circuit, an inverter chain with a positive feedback loop, an output switch S2 and a delay device; the readout end of the composite dielectric gate three-transistor memory is connected to the input end of the inverter chain with a positive feedback loop through the sampling switch S1; the reset circuit is located between the sampling switch S1 and the inverter chain with a positive feedback loop, and is connected to the input end of the inverter chain with a positive feedback loop; the output end of the inverter chain with a positive feedback loop is connected to the write end of the composite dielectric gate three-transistor memory through the output switch S2; the output end of the delay device is respectively connected to the inverter chain with a positive feedback loop and the output switch S2.

[0007] Furthermore, the composite dielectric gate three-transistor memory includes an electron write tube, an electron read tube and three series capacitors; the write end of the composite dielectric gate three-transistor memory is the write source end of the electron write tube, and the read end of the composite dielectric gate three-transistor memory is the read drain end of the electron read tube.

[0008] Furthermore, the inverter chain with a positive feedback loop includes a feedforward circuit formed by three-stage inverter cascade and a feedback switch S3; each stage of the inverter of the feedforward circuit includes a pair of P-type doped MOSFET and N-type doped MOSFET, the gates of the two are connected as input ends, and the drains are connected as output ends; one end of the feedback switch S3 is connected to the input end of the first stage of the inverter chain, and the other end is connected to the output end of the second stage of the inverter chain.

[0009] Furthermore, the width-to-length ratio of a pair of P-type doped MOSFET and N-type doped MOSFET of each stage of the inverter of the feedforward circuit increases step by step.

[0010] Furthermore, the feedback switch S3 is an N-type MOSFET, whose source terminal is connected to the output terminal of the second stage inverter in the inverter chain with a positive feedback loop, the drain terminal is connected to the input terminal of the first stage inverter in the inverter chain with a positive feedback loop, and the gate terminal is connected to the delay device.

[0011] Furthermore, both the sampling switch S1 and the output switch S2 use N-type MOSFETs; the source terminal of the sampling switch S1 is connected to the readout terminal of the composite dielectric gate three-transistor, the drain terminal thereof is connected to the input terminal of the inverter chain with a positive feedback loop, and the gate terminal is connected to an external voltage control signal; the source terminal of the output switch S2 is connected to the output terminal of the inverter chain with a positive feedback loop, the drain terminal thereof is connected to the write terminal of the composite dielectric gate three-transistor, and the gate terminal is connected to a delay device.

[0012] The present invention also provides a working method of a refresh circuit based on a composite dielectric gate three-transistor memory, wherein the refresh circuit is provided with two external connection voltages: a positive voltage VP and a negative voltage VN, and a ground level is GND, and an external voltage control signal Vrf is provided in the circuit, and the external voltage control signal Vrf generates a delay signal Vrf_dly through a delay device; the composite dielectric gate three-transistor memory includes an electronic write-in tube and an electronic read-out tube, and the voltage coordination of the external port of the composite dielectric gate three-transistor memory changes during refreshing: in the storage stage, the gate voltage of the electronic write-in tube is connected to Negative voltage VN, the source and drain of the electronic read-out tube are grounded to the GND level, and the electronic write tube and the electronic read-out tube are both turned off; in the refresh stage, first, the drain of the electronic read-out tube is grounded to the VN level, and its source is floated, and the storage value is sensed to the read-out end of the composite dielectric gate three-transistor memory, and then the voltage of the read-out end of the memory is sampled by the refresh circuit, and then the inverter chain in the refresh circuit latches, enhances and outputs the sampled value, and finally the gate of the electronic write tube is connected to the positive voltage VP to turn on the electronic write tube, and the voltage output by the refresh circuit is rewritten into the composite dielectric gate three-transistor memory.

[0013] The present invention also provides a memory chip based on a composite dielectric gate three-transistor device, comprising a composite dielectric gate three-transistor memory array, the above-mentioned refresh circuit, a write word line driver, a write bit line driver, a read word line driver and a read bit line driver; the write word line driver drives the write word line WWL formed by connecting the gates of electronic write tubes of the same row of memories in the memory array, the write bit line driver drives the write bit line WBL formed by connecting the sources of electronic write tubes of the same column of memories in the memory array, the read word line driver drives the read word line RWL formed by connecting the sources of electronic read tubes of the same row of memories in the memory array, and the read bit line driver drives the read bit line RBL formed by connecting the drains of electronic read tubes of the same column of memories in the memory array; each column of memories shares a refresh circuit, the sampling switch S1 of the refresh circuit is connected to the read bit line RBL shared by the memories in one column, and the output switch S2 is connected to the write bit line WBL shared by the memories in one column.

[0014] The working principle / process of the present invention is as follows:

[0015] The circuit of the present invention has two working phases, including a reset phase and a refresh phase;

[0016] During the reset phase, the external voltage control signal Vrf=VN, and its delay signal Vrf_dly is also equal to VN. At this time, the sampling switch S1 and the output switch S2 of the refresh circuit are disconnected, and the refresh circuit is completely isolated from the memory. Inside the sampling circuit, the reset circuit is turned on, and the voltage at the input end of the inverter chain is reset to 0V. The feedback switch S3 of the inverter chain is disconnected, so no positive feedback loop is formed.

[0017] During the refresh phase, the external voltage control signal Vrf=VP, Vrf_dly=VP, the sampling switch S1 and the output switch S2 of the refresh circuit are closed, and the refresh circuit is connected to the memory cell. During the refresh phase, the drain end (memory read-out area) of the memory cell electronic read-out tube T2 changes from being connected to GND to being floating, and the source end changes from being connected to GND to being connected to the negative voltage VN. When the stored voltage is VN, the voltage of the storage node SN remains at VN, the electronic read-out tube T2 is turned off, and the voltage of the drain end (memory read-out area) of T2 is still floating near GND, and the floating GND is maintained by the parasitic capacitance of the drain metal line; when the stored voltage is GND, the voltage of the storage node SN drops to GND-△V due to leakage. As long as GND-△V>VN+Vth, where Vth≈0.7V, T2 will turn on, and the drain end (memory read-out area) of T2 outputs a negative voltage VN. The voltage of the memory read-out area is transmitted to the input end of the inverter chain through the sampling switch S1. As mentioned above, the initial voltage of the inverter chain input is GND, so when the voltage of the memory read-out area is floating GND, the voltage of the inverter chain input is still floating GND; when the voltage of the memory read-out area is VN, the voltage of the inverter chain input is VN. The output voltage of the second stage of the inverter chain is transmitted back to the input of the first stage by the feedback switch S3, latching the voltage of the inverter chain input. After latching, the output voltage of the third stage of the inverter chain is stably equal to the inverse voltage of the inverter chain input voltage. The output voltage of the inverter chain is transmitted to the write area of ​​the memory through the output switch S2. The memory electronic write tube T1 is turned on, and the voltage driven by the refresh circuit in the write area is stored back into the storage node SN to complete the refresh.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] (1) The refresh circuit of the present invention utilizes the original read and write structure of the memory to complete the "sensing storage value" and "rewriting" operations during the refresh process, thus avoiding additional area overhead. According to the characteristics of the memory that low voltage storage is not volatile but high voltage storage is volatile, a larger fault tolerance range is set for high voltage sensing to ensure the correctness of the refresh logic. The inverter chain with a positive feedback loop in the refresh circuit can quickly latch and enhance the sensed storage value to achieve fast refresh.

[0020] (2) A reset circuit is provided in the circuit of the present invention to precharge the internal nodes. The metal wires in the memory readout area have a certain parasitic capacitance, which can temporarily maintain the floating voltage before the refresh circuit latches the sampled value, realize the distinction of binary voltage, and ensure the accuracy of sampling. The sampled voltage is subject to the positive feedback of the inverter chain and is quickly latched as a strong driving voltage, preventing the circuit from being driven by the floating voltage and eliminating the influence of noise and leakage current in the circuit on the result.

[0021] (3) Since the last stage of the inverter chain needs to drive a certain load capacitance, the width-to-length ratio of the NMOS and PMOS pairs of each stage of the inverter needs to be gradually increased to gradually improve the current driving capability. This can further speed up the establishment of the positive feedback of the inverter chain, thereby enhancing the loop stability.

[0022] In summary, the circuit structure of the present invention is simple, and part of the structure in the memory is effectively utilized to save area. The process of sensing the storage value and sampling and latching is not easily disturbed by circuit noise and leakage current. The composite dielectric gate three-transistor memory can be refreshed at a high speed and with a high tolerance, and has good application prospects in the storage field. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of a refresh circuit based on a composite dielectric gate three-transistor memory of the present invention;

[0024] Figure 2 Schematic diagram of the refresh circuit based on the composite dielectric gate three-transistor memory array. DETAILED DESCRIPTION

[0025] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0026] Example 1

[0027] Figure 1 Schematic diagram of the refresh circuit based on the composite dielectric gate three-transistor memory in this embodiment, including a sampling switch 2, a reset circuit 3, an inverter chain 4 with a positive feedback loop, an output switch 5 and a delay 6. The refresh circuit is connected to the composite dielectric gate three-transistor memory 1 (referred to as memory 1), wherein the specific structure of the memory 1 is the attached to the Chinese invention patent application number CN202411088060.3. Figure 1 and 2 The signal writing area and the reading area in the memory 1 are both N-type MOSFET transistors, the reading area is connected to one end of the sampling switch 2, and the writing area is connected to one end of the output switch 5; the other end of the sampling switch 2 is connected to the input end of the inverter chain 4 with a positive feedback loop; the reset circuit 3 is connected between the sampling switch 2 and the inverter chain 4, and is also connected to the input end of the inverter chain 4 with a positive feedback loop; the output end of the inverter chain 4 with a positive feedback loop is connected to the other end of the output switch 5; the output of the delay device 6 is respectively connected to the inverter chain 4 and the output switch 5, and is used to generate a delay signal Vrf_dly of the external voltage control signal Vrf, and the delay time needs to be greater than the time for the refresh circuit to sample the voltage at the read end of the three-transistor memory.

[0028] The memory 1 includes two N-type MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and three capacitors. The two N-type MOSFETs are the electron write tube T1 and the electron read tube T2; the three series capacitors are capacitor C1, capacitor C2, and capacitor C3 from top to bottom. The internal connection relationship of the device is: the node where the lower plate of capacitor C1 is connected to the upper plate of capacitor C2 is called node RN (Read node), and the node where the lower plate of capacitor C2 is connected to the upper plate of capacitor C3 is called node SN (Storage node). According to the capacitor voltage division relationship, the node RN voltage is approximately equal to the node SN voltage. The drain end of the electron write tube T1 is connected to the node SN, and the gate of the electron read tube T2 is connected to the node RN. The memory 1 has six external ports: the first port is the source of the electronic write tube T1; the second port is the gate of the electronic write tube T1; the third port is the source of the electronic read tube T2; the fourth port is the drain of the electronic read tube T2; the fifth port is the upper plate of the capacitor C1, connected to GND; the sixth port is the lower plate of the capacitor C3, connected to the negative voltage VN. In the memory write mode, the first port transmits GND or negative voltage VN, and the second port transmits positive voltage VP, turning on the electronic write tube T1 and transmitting the voltage transmitted by the first port to the storage node SN. In the memory retention mode, the second port transmits negative voltage VN, and the third and fourth ports transmit GND. The electronic write tube T1 and the electronic read tube T2 are both in the cut-off state. At this time, the voltage of the storage node SN gradually changes in the direction of the negative voltage VN. In the memory read mode, the third port transmits negative voltage VN. According to the different storage voltages, the electronic read tube T2 will generate significantly different leakage currents, thereby reading the stored data.

[0029] The write end of the memory 1 is the write source end of the electron write tube T1, and the read end is the read drain end of the electron read tube T2. In the write phase, a voltage is applied to the write source end of the electron write tube T1 to write or extract electrons to the node SN; in the read phase, the read current of the electron read tube T2 changes accordingly according to the amount of electrons collected.

[0030] The inverter chain 4 with a positive feedback loop includes a feedforward circuit formed by cascading three inverters and a feedback network composed of switches. The upper power rail of the inverter is GND, and the lower power rail is a negative voltage VN. Each inverter of the feedforward circuit includes a pair of P-type doped MOSFET (called PMOS) and N-type doped MOSFET (called NMOS), the source of the PMOS is connected to 0 potential, the source of the NMOS is connected to the negative voltage VN, the gates of the two are connected as input terminals, and the drains are connected as output terminals. The three-stage inverter is cascaded in sequence according to the output terminal of the previous inverter connected to the input terminal of the next inverter to form an inverter chain. The width-to-length ratio of the PMOS in the inverter is usually 2.5 times that of the NMOS, that is, the inverse ratio of the hole mobility to the electron mobility. The NMOS and PMOS pairs of each inverter need to increase the width-to-length ratio step by step, so as to improve the current driving capability step by step. The feedback network is composed of a feedback switch S3, one end of the feedback switch S3 is connected to the input terminal of the first stage of the inverter chain, and the other end is connected to the output terminal of the second stage of the inverter chain.

[0031] The sampling switch 2 includes a switch S1, and the output switch 5 includes a switch S2. In this embodiment, switches S1, S2 and S3 are all composed of N-type MOSFETs. The source terminal of the NMOS switch S1 is connected to the drain terminal of the memory electronic read-out tube T2, the drain terminal of S1 is connected to the input terminal of the inverter chain 4 with a positive feedback loop, and the gate terminal of S1 is connected to the external voltage control signal Vrf. The output of the delay device 6 is respectively connected to the gate of the feedback switch S3 and the gate of the switch 2. The source terminal of the switch S2 is connected to the output terminal of the inverter chain 4, the drain terminal is connected to the source terminal of the memory electronic write tube T1, and the gate terminal is connected to the voltage control signal Vrf_dly. The source terminal of the feedback switch S3 is connected to the output terminal of the second-stage inverter in the inverter chain 4, the drain terminal is connected to the input terminal of the first-stage inverter in the inverter chain 4, and the gate terminal is connected to the voltage control signal Vrf_dly.

[0032] The reset circuit 3 is composed of a P-type MOSFET, with a source terminal connected to GND, a drain terminal connected to the input terminal of an inverter chain 4 with a positive feedback loop, and a gate terminal connected to an external voltage control signal Vrf.

[0033] The circuit of this embodiment needs to change the voltage of the external port of the memory when refreshing: in the storage stage, the external port voltage control turns off the electronic read-out tube and the electronic write-in tube of the memory; in the refresh stage, first the external port voltage control turns on the electronic read-out tube of the memory, senses the stored value to the memory read-out end, then uses the refresh circuit to sample the voltage of the memory read-out end, then the inverter chain in the refresh circuit latches, enhances and outputs the sampled value, and finally the external port voltage control turns on the electronic write-in tube of the memory, and rewrites the voltage output by the refresh circuit into the memory. The specific working process is as follows.

[0034] There are two external connection voltages in the circuit: the positive voltage VP needs to satisfy the relationship VP-GND ≥ Vth (Vth ≈ 0.7V), and VP = 3V is used in this embodiment; the negative voltage VN needs to be clearly distinguished from GND, which is conducive to data storage. In this embodiment, VN = -3V is used. GND is the ground voltage 0V. The inverter chain 4 is powered by GND and VN = -3V, and the delay 6 is powered by VP = 3V and VN = -3V. There is an external voltage control signal Vrf in the circuit, which is VP = 3V or VN = -3V.

[0035] The sampling switch 2 and reset circuit 3 in the circuit are controlled by the voltage control signal Vrf, and the feedback switch S3 and output switch 5 of the inverter chain 4 are controlled by the voltage signal Vrf_dly, so as to latch and output the voltage sampled by the refresh circuit after it becomes stable.

[0036] When the refresh circuit is in the reset phase, the voltage control signal Vrf = Vrf_dly = -3V, which is the global minimum voltage. Sampling switch 2 is NMOS, the gate is connected to Vrf, and sampling switch 2 is disconnected; reset circuit 3 is PMOS, the gate is connected to Vrf, the source is connected to GND, the reset circuit is turned on, and GND is transmitted to the drain of PMOS, that is, the input of inverter chain 4; the feedback switch S3 of inverter chain 4 is NMOS, the gate is connected to Vrf_dly, S3 is disconnected, so the positive feedback loop in inverter chain 4 is not established; output switch 5 is NMOS, the gate is connected to Vrf_dly, and output switch 5 is disconnected. During reset, the refresh circuit is not connected to the memory 1, and the internal nodes of the refresh circuit are provided with a stable level by the reset circuit 3 to ensure that the initial state of the refresh circuit in the refresh phase is determined. When the refresh circuit is reset, the memory 1 can be written, read, or stored.

[0037] Before refreshing, the memory 1 is in the holding stage, the gate of the electron write tube T1 of the memory 1 is connected to the negative voltage VN=-3V, and the source and drain of the electron read tube T2 are connected to GND.

[0038] When the refresh circuit is in the refresh phase, the first step is to change the source of the electronic readout tube T2 of the memory 1 from GND to -3V, and the drain from GND to floating. If the voltage stored in the memory 1 is -3V, and -3V tends to remain at -3V, then the gate-source voltage of the electronic readout tube T2 is 0V, T2 is turned off, and the voltage at the drain end of T2 (the readout area of ​​the memory 1) will float near GND and be temporarily stored by the parasitic capacitance of the metal wire at the drain end; if the voltage stored in the memory 1 is GND, although it has shifted in the direction of the negative voltage VN, as long as the current voltage is still higher than -3V by a threshold voltage Vth, T2 can be turned on, and the voltage at the drain end of T2 (the readout area of ​​the memory 1) is equal to the source voltage -3V.

[0039] In the second step of refreshing, the voltage signal Vrf flips from -3V to 3V, which is the global highest voltage. The NMOS sampling switch 2 and the PMOS reset circuit 3 are controlled by the voltage signal Vrf, the sampling switch 2 is turned on, and the reset circuit 3 is disconnected. The sampling switch 2 transmits the voltage of the readout area of ​​the memory 1 to the input end of the inverter chain 4, and the initial voltage of the input end of the inverter chain 4 is 0V. When the voltage of the readout area of ​​the memory 1 is floating GND, the input voltage of the inverter chain 4 is still floating GND. At this time, the input state of the inverter chain 4 is not stable, and the floating GND may gradually deviate to -3V over time; when the voltage of the readout area of ​​the memory 1 is -3V, the input voltage of the inverter chain 4 becomes -3V.

[0040] In the third step of refreshing, the voltage signal Vrf_dly also flips to 3V after a certain delay, and the NMOS feedback switch S3 and the NMOS output switch 5 in the inverter chain 4 are controlled by the voltage signal Vrf_dly, and both are closed. After S3 is closed, the voltage outputted by the second stage in the inverter chain 4 is fed back to become the input voltage of the first stage, and the input voltage of the first stage is latched, eliminating the unstable state of the refresh link; at the same time, the input switch 5 will be turned on, and the output voltage of the third stage of the inverter chain 4 will be transmitted to the source end of the electronic write tube T1 of the memory 1 (the write area of ​​the memory 1).

[0041] In the fourth step of refreshing, the gate voltage of the electronic write tube T1 of the memory 1 is changed from -3V to 3V, T1 is turned on, and the voltage at the source end of T1 is transmitted to the storage node SN of the memory 1 to complete the refreshing. The overall refresh logic is as follows: when the voltage stored in the memory 1 is GND, the voltage in the read-out area of ​​the memory 1 is -3V, which is sampled to the input end of the inverter chain 4, and the output voltage GND is transmitted after three-stage inversion, and finally transmitted back to the storage node of the memory 1; when the voltage stored in the memory 1 is -3V, the voltage in the read-out area of ​​the memory 1 is floating GND, which is sampled to the input end of the inverter chain 4, latched as a strong drive GND, and output -3V after three-stage inversion, and finally transmitted back to the storage node of the memory 1.

[0042] Example 2

[0043] In this embodiment, the refresh circuit described in Embodiment 1 is used to refresh a composite dielectric gate three-transistor memory array (referred to as a memory array for short), such as Figure 2As shown, it includes a memory array, a refresh circuit, a write word line driver, a write bit line driver, a read word line driver and a read bit line driver. The write word line driver drives the write word line WWL formed by connecting the gates of the electronic write tubes of the same row of memories in the memory array, the write bit line driver drives the write bit line WBL formed by connecting the sources of the electronic write tubes of the same row of memories in the memory array, the read word line driver drives the read word line RWL formed by connecting the sources of the electronic read tubes of the same row of memories in the memory array, and the read bit line driver drives the read bit line RBL formed by connecting the drains of the electronic read tubes of the same row of memories in the memory array; each row of memories shares a refresh circuit, the sampling switch S1 of the refresh circuit is connected to the read bit line RBL shared by the memories in one row, and the output switch S2 is connected to the write bit line WBL shared by the memories in one row.

[0044] The memory array has i rows and j columns. The gates of the electronic write transistors T1 of the memory in the same row are connected to form a write word line WWL, the sources of the electronic write transistors T1 of the memory in the same column are connected to form a write bit line WBL, the sources of the electronic read transistors T2 of the memory cells in the same row are connected to form a read word line RWL, and the drains of the electronic read transistors T2 of the memory in the same column are connected to form a read bit line RBL. A write word line WWL controls the opening and closing of the input transistor T1 of a row of memory. When T1 is turned off, WWL transmits a negative voltage VN = -3V, and when T1 is turned on, WWL transmits a positive voltage VP = 3V. A write bit line WBL is responsible for time-sharing the write voltage of a column of memory. WBL transmits a negative voltage VN = -3V or GND. A read word line RWL controls the opening and closing of the electronic read transistor T2 of a row of memory. When T2 is turned off, RWL transmits GND, and when T2 is turned on, RWL transmits a negative voltage VN = -3V.

[0045] Each column of memory in the storage array shares a refresh circuit, that is, there are j refresh circuits in total. The sampling switch S1 of each refresh circuit is connected to the read bit line RBL of the corresponding column, and the output switch S2 is connected to the write bit line WBL of the corresponding column. When refreshing, the write word line WWL and the read word line RWL of the refreshed row need to change the voltage in coordination, resulting in changes in the write and electronic readout tube states of a row of memory. Therefore, array-level refresh must use a row of memory as the basic operation unit, and memories in different rows are refreshed in time-sharing. The control signals Vrf and Vrf_dly of the refresh operation are global signals that control j refresh circuits at the same time. When performing row-by-row refresh, Vrf and Vrf_dly flip back and forth between -3V and 3V.

[0046] Taking row-by-row refresh as an example, the process of array-level refresh is as follows:

[0047] When the array does not perform a refresh operation, Vrf = -3V, and all j refresh circuits are in a reset state: the sampling switch S1 and the output switch S2 are disconnected from the read bit line RBL and the write bit line WBL of the corresponding column, and the input voltage of the inverter chain inside the refresh circuit is GND.

[0048] When refreshing, refresh starts from the 1st row of memory: the first step is that all write bit lines WBL and read bit lines RBL of the array are floating. The second step is that the read word line RWL of the 1st row of memory transmits -3V; at the same time, Vrf = 3V, and the sampling switch S1 of each refresh circuit is connected to the RBL of the corresponding column. At this time, the refresh circuits 1, 2, 3, ..., j sense and sample the storage values ​​of the 1st, 2nd, 3rd, ..., j memories of the 1st row. The third step is Vrf_dly = 3V, and the output switch S2 of each column refresh circuit is connected to the WBL of the corresponding column to drive each column WBL to reach the target voltage. The fourth step is that the write word line WWL of the 1st row of memory transmits 3V, and each memory in this row stores the voltage on the corresponding WBL to complete the refresh; at the same time, the read word line RWL of the 1st row transmits GND to turn off the electronic readout tube. In the fifth step, the WWL of the first row transmits -3V to turn off the electron write tube; at the same time, Vrf = -3V, the sampling switches S1 of all refresh circuits are disconnected from the RBL of the corresponding column, and the internal nodes are reset; at the same time, all read bit lines RBL of the array transmit GND to precharge for the next refresh. In the sixth step, Vrf_dly = -3V, the output switches S2 of all refresh circuits are disconnected from the WBL of the corresponding column, and WBL remains floating. The above is the complete process of refreshing the first row of memory. Next, refresh the second row of memory: starting from the second step above, repeat the above steps. You only need to change the operation of RWL and WWL of the first row in the process to the operation of RWL and WWL of the second row. The refresh of the 3rd, 4th, ..., i rows is analogous.

[0049] It should be noted that the memory array must be refreshed row by row at a time, but it is not necessary to refresh row by row, and a row can be refreshed in any order.

[0050] In this embodiment, the timing control of the refresh circuit can be implemented by software, and the corresponding software program can be stored in a readable storage medium, such as a CD or a hard disk.

[0051] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A refresh circuit based on a composite dielectric gate three-transistor memory, connected to the composite dielectric gate three-transistor memory, characterized in that: The refresh circuit includes a sampling switch S1, a reset circuit, an inverter chain with a positive feedback loop, an output switch S2 and a delay device; the read end of the composite dielectric gate three-transistor memory is connected to the input end of the inverter chain with a positive feedback loop through the sampling switch S1; the reset circuit is located between the sampling switch S1 and the inverter chain with a positive feedback loop, and is connected to the input end of the inverter chain with a positive feedback loop; the output end of the inverter chain with a positive feedback loop is connected to the write end of the composite dielectric gate three-transistor memory through the output switch S2; the output end of the delay device is respectively connected to the inverter chain with a positive feedback loop and the output switch S2.

2. A refresh circuit based on a composite dielectric gate three-transistor memory according to claim 1, characterized in that: The composite dielectric gate three-transistor memory comprises an electron write tube, an electron read tube and three series capacitors; the write end of the composite dielectric gate three-transistor memory is the write source end of the electron write tube, and the read end of the composite dielectric gate three-transistor memory is the read drain end of the electron read tube.

3. A refresh circuit based on a composite dielectric gate three-transistor memory according to claim 1, characterized in that: The inverter chain with a positive feedback loop includes a feedforward circuit formed by three-stage inverter cascade and a feedback switch S3; each stage of the inverter of the feedforward circuit includes a pair of P-type doped MOSFET and N-type doped MOSFET, the gates of the two are connected as input ends, and the drains are connected as output ends; one end of the feedback switch S3 is connected to the input end of the first stage of the inverter chain, and the other end is connected to the output end of the second stage of the inverter chain.

4. A refresh circuit based on a composite dielectric gate three-transistor memory according to claim 3, characterized in that: The width-to-length ratio of a pair of P-type doped MOSFET and N-type doped MOSFET of each stage of the inverter of the feedforward circuit increases step by step.

5. The refresh circuit based on composite dielectric gate three-transistor memory according to claim 3, characterized in that: The feedback switch S3 is an N-type MOSFET, with a source terminal connected to the output terminal of the second stage inverter in the inverter chain with a positive feedback loop, a drain terminal connected to the input terminal of the first stage inverter in the inverter chain with a positive feedback loop, and a gate terminal connected to a delay device.

6. A refresh circuit based on a composite dielectric gate three-transistor memory according to claim 1, characterized in that: The sampling switch S1 and the output switch S2 both use N-type MOSFET; the source terminal of the sampling switch S1 is connected to the readout terminal of the composite dielectric gate three-transistor, the drain terminal is connected to the input terminal of the inverter chain with a positive feedback loop, and the gate terminal is connected to an external voltage control signal; the source terminal of the output switch S2 is connected to the output terminal of the inverter chain with a positive feedback loop, the drain terminal is connected to the write terminal of the composite dielectric gate three-transistor, and the gate terminal is connected to a delay device.

7. A working method of a refresh circuit based on a composite dielectric gate three-transistor memory as claimed in claim 1, characterized in that: The refresh circuit is provided with two external connection voltages: a positive voltage VP and a negative voltage VN, and the ground level is GND. An external voltage control signal Vrf is provided in the circuit, and the external voltage control signal Vrf generates a delay signal Vrf_dly through a delay device; the composite dielectric gate three-transistor memory includes an electronic write tube and an electronic read tube, and the voltage coordination of the external port of the composite dielectric gate three-transistor memory changes during refreshing: in the storage stage, the gate voltage of the electronic write tube is connected to the negative voltage VN, the source and drain of the electronic read tube are connected to the ground level GND, and the electronic write tube and the electronic read tube are both turned off; in the refresh stage, firstly, the drain of the electronic read tube is connected to the negative voltage VN, and its source is made floating, and the storage value is sensed to the read-out end of the composite dielectric gate three-transistor memory, and then the voltage of the read-out end of the memory is sampled by the refresh circuit, and then the inverter chain in the refresh circuit latches, enhances and outputs the sampled value, and finally the gate of the electronic write tube is connected to the positive voltage VP, so that the electronic write tube is turned on, and the voltage output by the refresh circuit is re-written into the composite dielectric gate three-transistor memory.

8. The working method according to claim 7, characterized in that: The composite dielectric gate three-transistor memory has six external ports: the first port is the source of the electron write tube T1; the second port is the gate of the electron write tube T1; the third port is the source of the electron read tube T2; the fourth port is the drain of the electron read tube T2; the fifth port is the upper plate of the capacitor C1, connected to GND; the sixth port is the lower plate of the capacitor C3, connected to the negative voltage VN; in the composite dielectric gate three-transistor memory write mode, the first port transmits GND or negative voltage VN, the second port transmits positive voltage VP, the electron write tube T1 is turned on, and the voltage transmitted by the first port is transmitted to the storage node SN; In the composite dielectric gate three-transistor memory retention mode, the second port transmits a negative voltage VN, the third and fourth ports transmit GND, the electron write tube T1 and the electron read tube T2 are both in the cut-off state, and the voltage of the storage node SN gradually changes toward the negative voltage VN; in the composite dielectric gate three-transistor memory read mode, the third port transmits a negative voltage VN, and according to the different storage voltages, the electronic read tube T2 will generate significantly different leakage currents, thereby reading the stored data.

9. The working method according to claim 7, characterized in that: The positive voltage VP needs to satisfy the relationship: VP-GND≥Vth, wherein Vth≈0.7V, and GND is a ground voltage of 0V.

10. A memory chip based on a composite dielectric gate three-transistor device, characterized in that: The invention comprises a composite dielectric gate three-transistor memory array, a refresh circuit as claimed in any one of claims 1 to 6, a write word line driver, a write bit line driver, a read word line driver and a read bit line driver; the write word line driver drives a write word line WWL formed by connecting the gates of electronic write tubes of the same row of memories in the memory array, the write bit line driver drives a write bit line WBL formed by connecting the sources of electronic write tubes of the same column of memories in the memory array, the read word line driver drives a read word line RWL formed by connecting the sources of electronic read tubes of the same row of memories in the memory array, and the read bit line driver drives a read bit line RBL formed by connecting the drains of electronic read tubes of the same column of memories in the memory array; each column of memories shares a refresh circuit, the sampling switch S1 of the refresh circuit is connected to the read bit line RBL shared by the memories in one column, and the output switch S2 is connected to the write bit line WBL shared by the memories in one column.

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