Low parasitic inductance power module and manufacturing method thereof

Abstract

The invention discloses a low-parasitic inductance power module and a manufacturing method thereof. The low-parasitic inductance power module comprises a ceramic copper-clad plate, a solid-state switch chip and an input / output port, the double-layer ceramic copper-clad plate is used for performing integrated connection on the solid-state switch, the bottom layer plate is used for connecting a drain electrode of the solid-state switch array, and the top layer plate is used for connecting a source electrode and a grid electrode of the solid-state switch array; through selection of on-off states of the solid-state switches and unilateral conductivity of the diodes, current can circulate in a fixed path between the ceramic copper-clad plates and flows in opposite directions at an input port and an output port, parasitic inductances at module ports counteract each other, and thus the overall parasitic inductance of the module is reduced; according to the invention, a double-layer ceramic copper-clad plate is used as a connection mode, the layout of the solid-state switch and the input and output ports is optimally designed, and the parasitic inductance of the module is reduced, so that the turn-on and turn-off speed of the solid-state switch is accelerated.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor power modules, and in particular relates to a low parasitic inductance power module and a manufacturing method thereof. Background Art

[0002] Semiconductor power modules are widely used in electric vehicles, biomedicine, rail transportation, photovoltaic energy and other fields.

[0003] The current mainstream power module packaging technology usually uses traditional leads for electrical connections. Although the use of aluminum bonding wires has low manufacturing costs and mature production processes, its reliability is insufficient and its overcurrent capability is weak. In addition, aluminum bonding wires will bring large parasitic inductance, causing serious overshoot and ringing when the solid-state switch is turned off, which may cause device breakdown and reduce system reliability. Compared with the traditional bonding wire structure with higher parasitic inductance, the flat-plate structure is one of the packaging structures with the lowest parasitic inductance value, but there are still problems such as overshoot and ringing, and there is still room for optimization in the device structure layout. Summary of the invention

[0004] In order to solve the shortcomings of the prior art and achieve the purpose of avoiding overshoot and ringing caused by high parasitic inductance and causing device damage, the present invention adopts the following technical solution: A low parasitic inductance power module comprises a substrate, a lower ceramic copper-clad plate, and an upper ceramic copper-clad plate which are arranged in coordination from bottom to top. A solid-state switch chip connected to the lower ceramic copper-clad plate is arranged inside the upper ceramic copper-clad plate. Two pairs of input and output ports are arranged on the upper surface of the upper ceramic copper-clad plate. Two non-inductive capacitor ports are arranged between the two pairs of input and output port connections as ports for external non-inductive capacitors. Non-inductive capacitors with corresponding capacitance values ​​can be selected according to actual needs such as pulse width and frequency of pulses, thereby increasing the flexibility of the module, as well as a solid-state switch chip connected in parallel with the non-inductive capacitor. The two pairs of input and output ports are respectively a first port and a second port as input ports and a third port and a fourth port as output ports. The first port corresponds to the third port, and the second port corresponds to the fourth port. The current directions of each combined port pair are opposite. The parasitic inductance at the port is reduced to a great extent by utilizing the mutual inductance cancellation principle. The transistor drain at the bottom of the solid-state switch chip is connected to the upper copper foil of the lower ceramic copper-clad plate, and the transistor source and gate at the top of the solid-state switch chip are connected to the upper copper foil of the upper ceramic copper-clad plate. The substrate is connected to the lower copper foil of the lower ceramic copper clad board, the lower ceramic copper clad board is connected to the upper ceramic copper clad board, the upper device on the upper surface of the upper ceramic copper clad board is connected to the upper copper foil of the upper ceramic copper clad board through solder, the close layout of the upper device can reduce the self-inductance of the overall module, the ceramic copper clad board is used as the middle layer, and the high voltage and current of the upper and lower layers are electrically isolated. A diode D1 is provided between the point on the line connecting the first port and the third port of the non-inductive capacitor and the first port, and a diode D2 is provided between the point on the line connecting the second port and the fourth port of the non-inductive capacitor and the solid-state switch chip. The diode D1 is in the same direction as the diode D2. Through the unidirectional conductivity of the diode and the selection of the on-off state of the solid-state switch chip, the current can flow between the ceramic copper clad boards in a fixed path, and the current flows in opposite directions at the input and output ports. The parasitic inductances at the power module ports cancel each other, thereby reducing the overall parasitic inductance of the power module.

[0005] Furthermore, a group of parallel solid-state switch chips are provided inside the upper ceramic copper-clad board to improve the overcurrent capacity of the power module, separate and lead out the solid-state switch gate control port and the solid-state switch Kelvin source port for external connection, separate the source of the power part and the source of the driving part, and avoid the influence of the large current of the power part on the small signal of the driving part; the number of solid-state switch chips can be designed according to the required voltage level and current level.

[0006] Furthermore, the gate and source of the solid-state switch chip are metallized, and the metal layer material is Ti / Ni / Ag, which is to ensure better adhesion of the solder during welding and ensure the reliability of the module.

[0007] Furthermore, by adding laminated busbars, multi-stage module connections are made at the ports to achieve the effect of superimposing the output voltage.

[0008] A method for manufacturing a low parasitic inductance power module comprises the following steps: Step 1: Connect the substrate, the lower ceramic copper clad laminate and the upper ceramic copper clad laminate from bottom to top by reflow soldering; Step 2: slot the upper ceramic copper clad laminate, add solder resist oil to the slotted area to set a solid-state switch chip connected to the lower ceramic copper clad laminate, weld the solid-state switch chip to the upper copper foil of the lower ceramic copper clad laminate, and sinter and clean the welded solid-state switch chip; the material of the upper ceramic copper clad laminate and the lower ceramic copper clad laminate is AlN, with a thermal conductivity of 180-240W / m*K, a breakdown field strength of 25kV / mm, and a thermal expansion coefficient (at 20°C) of 4.5. The higher thermal conductivity of the AlN material helps the device to dissipate heat, and can effectively improve the thermal management efficiency of the module at high power density; the higher breakdown field strength can effectively isolate the high voltage generated during circuit operation; the thermal expansion coefficient of AlN is similar to that of the silicon material used for the solid-state switch chip. When the temperature changes, the stress generated between AlN and the chip can be effectively reduced, thereby reducing the probability of failure in the thermal cycle.

[0009] Step 3, two pairs of input and output ports are arranged on the upper surface of the upper ceramic copper-clad board, and two non-inductive capacitor ports are arranged between the two pairs of input and output port connections as ports for external non-inductive capacitors. Non-inductive capacitors with corresponding capacitance values ​​can be selected according to actual needs, thereby increasing the flexibility of the module, as well as a solid-state switch chip connected in parallel with the non-inductive capacitor, wherein the two pairs of input and output ports are respectively the first port and the second port as input ports and the third port and the fourth port as output ports, the first port corresponds to the third port, the second port corresponds to the fourth port, and the current direction of each combined port pair is opposite. By utilizing the mutual inductance cancellation principle, the parasitic inductance at the port is greatly reduced, the transistor drain at the bottom of the solid-state switch chip is connected to the upper copper foil of the lower ceramic copper-clad board, and the transistor source and gate at the top of the solid-state switch chip are connected to the upper copper foil of the upper ceramic copper-clad board; a diode D1 is arranged between the point on the line connecting the first port and the third port of the non-inductive capacitor and the first port, and a diode D2 is arranged between the point on the line connecting the second port and the fourth port of the non-inductive capacitor and the solid-state switch chip, and the diode D1 and the diode D2 are made to be in the same direction.

[0010] Furthermore, the gate and source on the top of the solid-state switch chip are metallized by sputtering 0.2um titanium Ti, 0.2um nickel Ni, and 1um silver Ag in sequence, so that the properties of the upper gate and source of the solid-state switch chip after metallization are consistent with the metal layer of the drain at the bottom of the solid-state switch chip, further ensuring the integrity of subsequent welding and the reliability of the module.

[0011] Furthermore, a group of parallel solid-state switch chips are provided inside the upper ceramic copper-clad board to improve the current capacity of the power module, and the solid-state switch gate control port and the solid-state switch Kelvin source port are separated and brought out for external connection, so that the on and off of each solid-state switch can be synchronously controlled.

[0012] Furthermore, when the power supply charges the non-inductive capacitor through the first port, the solid-state switch chip is in an off state; when the solid-state switch chip is turned on, the non-inductive capacitor begins to discharge, and the current flows through the solid-state switch chip and flows out from the fourth port; the second port is the same as the third port; when the power module is cascaded in multiple stages, the fourth port of the previous power module is connected to the second port of the next power module, and the third port of the previous power module is connected to the first port of the next power module, so as to realize the function of voltage superposition.

[0013] Furthermore, the reflow soldering is divided into three soldering processes, in which the lower ceramic copper clad laminate is sintered with the substrate in the first reflow soldering process; the upper ceramic copper clad laminate, the bottom of the solid-state switch chip and the lower ceramic copper clad laminate are sintered together in the second reflow soldering process; the first port, the second port, the third port, the fourth port, the port of the non-inductive capacitor and the upper ceramic copper clad laminate are sintered together in the third reflow soldering process, and the top of the solid-state switch chip is soldered with the solid-state switch gate control port and the solid-state switch Kelvin source port; the liquidus points of the materials of the two adjacent soldering processes in the three reflow soldering processes are all above 30°C to prevent the solder at the previous soldering process from melting.

[0014] The advantages and beneficial effects of the present invention are: A low parasitic inductance power module and a manufacturing method thereof of the present invention uses a double-layer ceramic copper-clad laminate and a flat structure to design a power module, optimizes the layout of upper-layer devices and input and output ports, reduces the overall parasitic inductance of the module, optimizes the overshoot and ringing problems generated by the solid-state switch during the shutdown process, reduces switching losses, and at the same time, the arrangement of the two pairs of port combinations is conducive to the stacked busbar design and multi-stage module cascading, further achieving the effect of voltage superposition, thereby improving the reliability and flexibility of the module. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 FIG. 4 is a perspective view of a power module according to an embodiment of the present invention.

[0016] Figure 2 Schematic diagram of the structure of a power module in an embodiment of the present invention.

[0017] Figure 3 Schematic diagram of the upper surface of a solid-state switch chip in an embodiment of the present invention.

[0018] Figure 4 Schematic diagram of a power module in an embodiment of the present invention.

[0019] In the figure: 1-substrate, 2-lower ceramic copper clad board, 3-upper ceramic copper clad board, 4-diode D1, 5-diode D2, 6-first port, 7-third port, 8-fourth port, 9-second port, 10-first non-inductive capacitor port, 11-second non-inductive capacitor port, 12-solid-state switch chip, 13-solid-state switch gate control port, 14-solid-state switch Kelvin source port. DETAILED DESCRIPTION

[0020] The specific implementation of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the present invention, and is not used to limit the present invention.

[0021] like Figure 1 , Figure 2 As shown, a low parasitic inductance power module includes a substrate 1, a ceramic copper-clad board, a 1×6 solid-state switch chip parallel array, an input port, an output port, an external non-inductive capacitor port, a potting glue, and a shell. The bottom layer is the substrate 1, the material is silicon carbide aluminum, the density is 3.0~3.2g / cm, the thermal expansion coefficient is 6.5~9.5ppm / ℃, and the thermal conductivity is 170~200W / m*K. The lower ceramic copper-clad board 2 is fixed on the upper side of the substrate by reflow soldering. The ceramic copper-clad board material is AlN, the thermal conductivity is 180-240W / m*K, the breakdown field strength is 25kV / mm, and the thermal expansion coefficient (at 20℃) is 4.5. The thickness of the lower ceramic copper-clad board 2 is 254um, the thickness of the upper ceramic copper-clad board 3 is 418um, the thickness of the copper foil on the upper and lower surfaces of the ceramic copper-clad board is 70um, and the thickness of the solder is 100um. The upper ceramic copper-clad board 3 is slotted, and solder resist oil is added to the copper foil of the lower ceramic copper-clad board 2 corresponding to the slot position to prevent short circuit. The upper ceramic copper-clad board 3 is fixed on the lower ceramic copper-clad board 2 by reflow soldering, and the solid-state switch chip 12 is placed in the slot and sintered with the lower ceramic copper-clad board 2. In order to prevent air breakdown in harsh environments and protect the device from stable and long-term operation, potting glue can be poured into the power module to isolate the power device from the external environment. The potting glue is Qgel 310.

[0022] The solid-state switch chip parallel array in the present invention uses SiC MOSFET. This is just an example. It is not limited to SiCMOSFET, but can also include electronic switches such as IGBT and GaN MOSFET. In this example, the single-tube voltage and current level of SiC MOSFET is 1200V / 58A, so the voltage and current level of a 1×6 array is 1200V / 348A. The number of solid-state switch chips 12 in the array can be designed according to the required voltage and current levels, and is not limited to a 1×6 array. In order to allow the solder to better adhere to the welding metal layer of the solid-state switch chip 12 during welding, the solid-state switch chip 12 needs to be metallized. Figure 3 As shown, firstly, 0.2um titanium Ti is sputtered at the source and gate of the upper surface of the solid-state switch chip, then 0.2um nickel Ni, and finally 1um silver Ag, to ensure that the properties of the upper gate and source of the solid-state switch chip after metallization are consistent with the metal layer of the lower drain of the solid-state switch chip, further ensuring the integrity of subsequent welding and the reliability of the module. In addition, the anodes of the diodes D14 and D25 are also metallized in the same way. After the gate and source of the solid-state switch chip 12 are metallized, the solid-state switch gate control port 13 is connected to the gates of each chip, and the solid-state switch Kelvin source port 14 is connected to the source of each chip, so that the on and off of each solid-state switch can be synchronously controlled.

[0023] like Figure 4 As shown, the construction of the power module can be roughly divided into two steps: ① The power supply charges the non-inductive capacitor through the first port 6, and the solid-state switch is in the off state; ② The solid-state switch is turned on, the non-inductive capacitor begins to discharge, and the current flows through the solid-state switch and flows out from the fourth port 8. When the power module is cascaded in multiple stages, the fourth port 8 of the previous stage module and the second port 9 of the next stage module are connected together, and the third port 7 of the previous stage module and the first port 6 of the next stage module are connected together, which can realize the function of voltage superposition.

[0024] In order to reduce the parasitic inductance of the power module, the layout of the power module needs to be optimized. Figure 4As shown, the electrical connection is performed, the first port 6 and the second port 9 are input ports, and the current flows in from these ports. The third port 7 and the fourth port 8 are output ports, and the current flows out from these ports. According to the mutual inductance cancellation principle, the two ports with opposite current flows are combined, that is, the first port 6 and the third port 7 are combined, and the second port 9 and the fourth port 8 are combined. Each port has the same structure, and the two ports in each pair of combinations are symmetrical. The spacing between the ports of the combination is 1mm, which is to maximize the mutual inductance and reduce the parasitic inductance, while ensuring that no breakdown occurs at high voltage. In addition, these ports can also be used as connection ports for laminated busbars, which facilitates the cascading of multi-stage modules to achieve the purpose of increasing the output voltage. The first and second non-inductive capacitor ports 10 and 11 are welded to the edge of the upper ceramic copper-clad board. The non-inductive capacitors of corresponding capacitance can be selected according to the needs later, which has high flexibility.

[0025] The size of the power module is 53mm*27mm*10mm. The module is imported into Ansys Q3D Extractor software for parasitic parameter extraction. The parasitic inductance value of the module power circuit is 5.29nH. Under similar size specifications, the parasitic inductance value of the traditional packaging structure is above 10nH.

[0026] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low parasitic inductance power module, comprising a substrate (1), a lower ceramic copper-clad laminate (2), and an upper ceramic copper-clad laminate (3) arranged in a coordinated manner from bottom to top, characterized in that: The upper ceramic copper-clad board (3) is provided with a solid-state switch chip (12) connected to the lower ceramic copper-clad board (2) inside, and the upper surface of the upper ceramic copper-clad board (3) is provided with two pairs of input and output ports, and a non-inductive capacitor and a solid-state switch chip (12) connected in parallel therewith are provided between the two pairs of input and output port connections, wherein the two pairs of input and output ports are respectively a first port (6) and a second port (9) as input ports and a third port (7) and a fourth port (8) as output ports, the first port (6) corresponds to the third port (7), and the second port (9) corresponds to the fourth port ( 8), the transistor drain at the bottom of the solid-state switch chip (12) is connected to the lower ceramic copper-clad plate (2), and the transistor source and gate at the top of the solid-state switch chip (12) are connected to the upper ceramic copper-clad plate (3); a diode D1 (4) is provided between the point on the line connecting the first port (6) and the third port (7) of the non-inductive capacitor and the first port (6), and a diode D2 (5) is provided between the point on the line connecting the second port (9) and the fourth port (8) of the non-inductive capacitor and the solid-state switch chip (12), and the diode D1 (4) and the diode D2 (5) are in the same direction.

2. The low parasitic inductance power module according to claim 1, characterized in that: A group of parallel solid-state switch chips (12) are arranged inside the upper ceramic copper-clad plate (3), and a solid-state switch gate control port (13) and a solid-state switch Kelvin source port (14) are separated and led out for external connection.

3. The low parasitic inductance power module according to claim 1, characterized in that: The gate and source of the solid-state switch chip (12) are metallized.

4. The low parasitic inductance power module according to claim 3, characterized in that: By adding stacked busbars, multi-level module connections are made at the ports to superimpose the output voltage.

5. A method for manufacturing a low parasitic inductance power module, characterized in that The steps include: Step 1, connecting the substrate (1), the lower ceramic copper-clad laminate (2) and the upper ceramic copper-clad laminate (3) from bottom to top by reflow soldering; Step 2: slotting the upper ceramic copper-clad board (3) to provide a solid-state switch chip (12) connected to the lower ceramic copper-clad board (2); Step 3: two pairs of input and output ports are arranged on the upper surface of the upper ceramic copper-clad board (3); a non-inductive capacitor and a solid-state switch chip (12) connected in parallel with the capacitor are arranged between the two pairs of input and output ports; the two pairs of input and output ports are a first port (6) and a second port (9) as input ports and a third port (7) and a fourth port (8) as output ports; the first port (6) corresponds to the third port (7), the second port (9) corresponds to the fourth port (8), and the three ports at the bottom of the solid-state switch chip (12) are connected to the capacitor. The transistor drain is connected to the lower ceramic copper-clad plate (2), and the transistor source and gate on the top of the solid-state switch chip (12) are connected to the upper ceramic copper-clad plate (3); a diode D1 (4) is arranged between the point on the line connecting the first port (6) and the third port (7) of the non-inductive capacitor and the first port (6), and a diode D2 (5) is arranged between the point on the line connecting the second port (9) and the fourth port (8) of the non-inductive capacitor and the solid-state switch chip (12), and the diode D1 (4) and the diode D2 (5) are arranged in the same direction.

6. The method for manufacturing a low parasitic inductance power module according to claim 5, characterized in that: The gate and source at the top of the solid-state switch chip (12) are metallized by sputtering titanium Ti, nickel Ni, and silver Ag in sequence, so that the properties of the gate and source at the top of the solid-state switch chip (12) after the metallization treatment are consistent with the metal layer at the bottom drain of the solid-state switch chip (12).

7. The method for manufacturing a low parasitic inductance power module according to claim 5, characterized in that: A group of parallel solid-state switch chips (12) are arranged inside the upper ceramic copper-clad plate (3), and a solid-state switch gate control port (13) and a solid-state switch Kelvin source port (14) are separated and led out for external connection.

8. The method for manufacturing a low parasitic inductance power module according to claim 5, characterized in that: When the power supply charges the non-inductive capacitor through the first port (6), the solid-state switch chip (12) is in an off state; when the solid-state switch chip (12) is turned on, the non-inductive capacitor begins to discharge, and the current flows through the solid-state switch chip (12) and flows out from the fourth port (8); the second port (9) and the third port (7) are the same as above; when the power modules are cascaded in multiple stages, the fourth port (8) of the previous stage power module is connected to the second port (9) of the next stage power module, and the third port (7) of the previous stage power module is connected to the first port (6) of the next stage power module.

9. The method for manufacturing a low parasitic inductance power module according to claim 5, characterized in that: The reflow soldering is divided into three soldering steps. The first reflow soldering sintered the lower ceramic copper-clad board (2) and the substrate (1) together. The second reflow soldering sintered the upper ceramic copper-clad board (3), the bottom of the solid-state switch chip and the lower ceramic copper-clad board (2) together. The third reflow soldering sintered the first port (6), the second port (9), the third port (7), the fourth port (8), the port of the non-inductive capacitor and the upper ceramic copper-clad board (3) together, and simultaneously soldered the top of the solid-state switch chip to the solid-state switch gate control port (13) and the solid-state switch Kelvin source port (14) together.

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