A low parasitic inductance power module and its fabrication method

Abstract

The present invention discloses a low parasitic inductance power module and a manufacturing method thereof, comprising a ceramic copper-clad laminate, a solid-state switch chip, and input / output ports. The present invention utilizes a double-layer ceramic copper-clad laminate to perform integrated connection of the solid-state switch, wherein the bottom plate is used to connect the drain of the solid-state switch array, and the top plate is used to connect the source and gate of the solid-state switch array. By selecting the on / off state of the solid-state switch and the unidirectional conductivity of the diode, current can flow through the ceramic copper-clad laminate in a fixed path, and the current flows in opposite directions at the input and output ports, and the parasitic inductances at the module ports cancel each other, thereby reducing the overall parasitic inductance of the module. The present invention optimizes the design of the solid-state switch and the input / output port layout by using the double-layer ceramic copper-clad laminate as a connection method, reducing the parasitic inductance of the module, thereby accelerating the on / off speed of the solid-state switch.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power module technology, specifically relating to a low parasitic inductance power module and its manufacturing method. Background Technology

[0002] Semiconductor power modules are widely used in electric vehicles, biomedicine, rail transportation, photovoltaic energy and other fields.

[0003] Current mainstream power module packaging technologies typically use traditional leads for electrical connections. Although aluminum bonding wires are low-cost and have mature manufacturing processes, their reliability is insufficient and their overcurrent capability is weak. In addition, aluminum bonding wires introduce significant parasitic inductance, causing severe overshoot and ringing when solid-state switches are turned off, which can lead to device breakdown and reduce system reliability. Compared to the traditional bonding wire structure with its high parasitic inductance, the planar structure is one of the packaging structures with the lowest parasitic inductance, but it still has problems such as overshoot and ringing, and there is still room for optimization in device structure layout. Summary of the Invention

[0004] To overcome the shortcomings of existing technologies and avoid device damage caused by overshoot and ringing due to high parasitic inductance, the present invention adopts the following technical solution:

[0005] A low parasitic inductance power module includes a substrate, a lower ceramic copper-clad laminate, and an upper ceramic copper-clad laminate arranged from bottom to top. The upper ceramic copper-clad laminate houses a solid-state switch chip connected to the lower ceramic copper-clad laminate. Two pairs of input / output ports are located on the upper surface of the upper ceramic copper-clad laminate. Two non-inductive capacitor ports are located between the two pairs of input / output ports as ports for connecting external non-inductive capacitors. The appropriate capacitance value of the non-inductive capacitor can be selected according to actual needs such as pulse width and frequency, increasing the module's flexibility. The solid-state switch chip is connected in parallel with the non-inductive capacitor. The two pairs of input / output ports are designated as first and second ports as input ports, and third and fourth ports as output ports. The first port corresponds to the third port, and the second port corresponds to the fourth port. The current direction of each port pair is opposite. Utilizing the mutual inductance cancellation principle, the parasitic inductance at the ports is greatly reduced. The drain of the transistor at the bottom of the solid-state switch chip is connected to the upper copper foil of the lower ceramic copper-clad laminate, and the source and gate of the transistor at the top of the solid-state switch chip are connected to the upper copper foil of the upper ceramic copper-clad laminate. The substrate is connected to the lower copper foil of the lower ceramic copper-clad board, and the lower ceramic copper-clad board is connected to the upper ceramic copper-clad board. The upper devices on the upper surface of the upper ceramic copper-clad board are connected to the upper copper foil of the upper ceramic copper-clad board by solder. The close arrangement of the upper devices can reduce the self-inductance of the overall module. The ceramic copper-clad board is used as an intermediate layer to electrically isolate the large voltage and current of the upper and lower layers. A diode D1 is provided between the point on the line connecting the first and third ports and the first port. A diode D2 is provided between the point on the line connecting the second and fourth ports of the non-inductive capacitor and the solid-state switch chip. Diode D1 and diode D2 are in the same direction. Through the unidirectional conductivity of the diode and the selection of the on and off state of the solid-state switch chip, the current can flow in a fixed path between the ceramic copper-clad boards, and the current flows in opposite directions at the input and output ports. The parasitic inductance at the power module ports cancels each other out, thereby reducing the overall parasitic inductance of the power module.

[0006] Furthermore, the upper ceramic copper-clad laminate contains a set of parallel solid-state switch chips to improve the overcurrent capability of the power module. The gate control port and Kelvin source port of the solid-state switch are separated and brought out for external connection. Separating the source of the power section from the source of the drive section can avoid the influence of the large current of the power section on the small signal of the drive section. The number of solid-state switch chips can be designed according to the required voltage and current levels.

[0007] Furthermore, the gate and source of the solid-state switch chip are metallized with Ti / Ni / Ag as the metal layer material. This is to improve the adhesion of the solder during welding and ensure the reliability of the module.

[0008] Furthermore, by adding stacked busbars and connecting multiple modules at the ports, the output voltage can be superimposed.

[0009] A method for fabricating a low parasitic inductance power module includes the following steps:

[0010] Step 1: Connect the substrate, the lower ceramic copper-clad laminate, and the upper ceramic copper-clad laminate from bottom to top using reflow soldering;

[0011] Step 2: Grooves are cut into the upper ceramic copper-clad laminate, and solder resist is added to the grooved area to set up the solid-state switch chip connected to the lower ceramic copper-clad laminate. The solid-state switch chip is soldered to the upper copper foil of the lower ceramic copper-clad laminate, and the soldered solid-state switch chip is sintered and cleaned. The materials of the upper and lower ceramic copper-clad laminates are AlN, with a thermal conductivity of 180-240W / m*K, a breakdown field strength of 25kV / mm, and a coefficient of thermal expansion (at 20℃) of 4.5. The high thermal conductivity of AlN helps the device dissipate heat and can effectively improve the thermal management efficiency of the module at high power density. The high breakdown field strength can effectively isolate the high voltage generated during circuit operation. The coefficient of thermal expansion of AlN is similar to that of silicon used in solid-state switch chips. When the temperature changes, the stress generated between AlN and the chip can be effectively reduced, thereby reducing the probability of failure during thermal cycling.

[0012] Step 3: Set two pairs of input / output ports on the upper ceramic copper-clad laminate. Set two non-inductive capacitor ports between the two pairs of input / output ports as ports for external non-inductive capacitors. The appropriate capacitance value of the non-inductive capacitor can be selected according to actual needs, which increases the flexibility of the module. A solid-state switch chip is connected in parallel with the non-inductive capacitor. The two pairs of input / output ports are the first and second ports as input ports and the third and fourth ports as output ports. The first port corresponds to the third port, and the second port corresponds to the fourth port. The current direction of each combination port pair is opposite. Using the mutual inductance cancellation principle, the parasitic inductance at the port is greatly reduced. The drain of the transistor at the bottom of the solid-state switch chip is connected to the upper copper foil of the lower ceramic copper-clad laminate. The source and gate of the transistor at the top of the solid-state switch chip are connected to the upper copper foil of the upper ceramic copper-clad laminate. A diode D1 is set between the point on the line connecting the non-inductive capacitor and the third port and the first port. A diode D2 is set between the point on the line connecting the non-inductive capacitor and the solid-state switch chip and the second and fourth ports, and diodes D1 and D2 are in the same direction.

[0013] Furthermore, the gate and source at the top of the solid-state switch chip are metallized by sputtering 0.2µm titanium (Ti), 0.2µm nickel (Ni), and 1µm silver (Ag) in sequence. This ensures that the properties of the upper gate and source metallized layers of the solid-state switch chip are consistent with the metal layer of the bottom drain of the solid-state switch chip, thereby further guaranteeing the integrity of subsequent soldering and the reliability of the module.

[0014] Furthermore, a set of parallel solid-state switch chips is installed inside the upper ceramic copper-clad laminate to improve the overcurrent capability of the power module. The gate control port and Kelvin source port of the solid-state switch are separated and brought out for external connection, so that the on and off of each solid-state switch can be synchronously controlled.

[0015] Furthermore, when the power supply charges the non-inductive capacitor through the first port, the solid-state switch chip is in the off state; when the solid-state switch chip is turned on, the non-inductive capacitor begins to discharge, and the current flows through the solid-state switch chip and out from the fourth port; the second and third ports are the same; when the power modules are cascaded in multiple stages, the fourth port of the previous stage power module is connected to the second port of the next stage power module, and the third port of the previous stage power module is connected to the first port of the next stage power module, which can realize the function of voltage superposition.

[0016] Furthermore, the reflow soldering is divided into three soldering processes. The first reflow soldering sintersects the lower ceramic copper-clad laminate with the substrate. The second reflow soldering sintersects the upper ceramic copper-clad laminate, the bottom of the solid-state switch chip, and the lower ceramic copper-clad laminate. The third reflow soldering sintersects the first port, the second port, the third port, the fourth port, and the port of the non-inductive capacitor with the upper ceramic copper-clad laminate, while simultaneously soldering the top of the solid-state switch chip with the gate control port and the Kelvin source port of the solid-state switch. The liquidus point of the materials in the two adjacent soldering processes in the three reflow soldering processes exceeds 30°C to prevent the solder at the previous soldering point from melting.

[0017] The advantages and beneficial effects of this invention are as follows:

[0018] This invention discloses a low parasitic inductance power module and its manufacturing method. By using a double-layer ceramic copper-clad laminate and a flat panel structure design, the layout of upper-layer devices and input / output ports is optimized, reducing the overall parasitic inductance of the module. This optimizes the overshoot and ringing problems generated by solid-state switches during turn-off, reducing switching losses. At the same time, the arrangement of the two pairs of ports facilitates the design of stacked busbars and the cascading of multi-level modules, further realizing the effect of voltage superposition, thereby improving the reliability and flexibility of the module. Attached Figure Description

[0019] Figure 1 This is a perspective view of the power module in an embodiment of the present invention.

[0020] Figure 2 This is a schematic diagram of the power module in an embodiment of the present invention.

[0021] Figure 3 This is a schematic diagram of the upper surface of the solid-state switch chip in an embodiment of the present invention.

[0022] Figure 4 This is a schematic diagram of the power module in an embodiment of the present invention.

[0023] In the figure: 1-substrate, 2-lower ceramic copper-clad laminate, 3-upper ceramic copper-clad laminate, 4-diode D1, 5-diode D2, 6-first port, 7-third port, 8-fourth port, 9-second port, 10-first non-inductive capacitor port, 11-second non-inductive capacitor port, 12-solid-state switch chip, 13-solid-state switch gate control port, 14-solid-state switch Kelvin source port. Detailed Implementation

[0024] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0025] like Figure 1 , Figure 2 As shown, a low parasitic inductance power module includes a substrate 1, a ceramic copper-clad laminate, a 1×6 solid-state switch chip parallel array, an input port, an output port, an external non-inductive capacitor port, potting compound, and a housing. The bottom layer is the substrate 1, made of silicon carbide aluminum, with a density of 3.0~3.2 g / cm³, a coefficient of thermal expansion of 6.5~9.5 ppm / ℃, and a thermal conductivity of 170~200 W / m*K. A lower ceramic copper-clad laminate 2 is fixed on top of the substrate by reflow soldering. The ceramic copper-clad laminate is made of AlN, with a thermal conductivity of 180-240 W / m*K, a breakdown field strength of 25 kV / mm, and a coefficient of thermal expansion (at 20℃) of 4.5. The lower ceramic copper-clad laminate 2 has a thickness of 254 μm, the upper ceramic copper-clad laminate 3 has a thickness of 418 μm, the copper foil on the upper and lower surfaces of the ceramic copper-clad laminate is 70 μm thick, and the solder is 100 μm thick. A groove is cut into the upper ceramic copper-clad laminate 3. Solder resist is applied to the copper foil of the lower ceramic copper-clad laminate 2 corresponding to the groove location to prevent short circuits. The upper ceramic copper-clad laminate 3 is fixed above the lower ceramic copper-clad laminate 2 by reflow soldering. The solid-state switch chip 12 is placed in the groove and sintered together with the lower ceramic copper-clad laminate 2. To prevent air breakdown in harsh environments and protect the device for stable and long-term operation, potting compound can be poured into the power module to isolate the power device from the external environment. Qgel 310 potting compound is selected.

[0026] The parallel array of solid-state switch chips in this invention uses SiC MOSFETs. This is just one example; it is not limited to SiC MOSFETs and can also include IGBTs, GaN MOSFETs, and other electronic switches. In this example, the single-transistor voltage and current rating of the SiC MOSFET is 1200V / 58A. Therefore, the voltage and current rating of a 1×6 array is 1200V / 348A. The number of solid-state switch chips 12 in the array can be designed according to the required voltage and current ratings, and is not limited to a 1×6 array. To ensure better adhesion of the solder to the soldering metal layer of the solid-state switch chip 12 during soldering, the solid-state switch chip 12 needs to undergo metallization treatment. For example... Figure 3 As shown, firstly, 0.2µm of titanium (Ti) is sputtered onto the source and gate of the solid-state switch chip, followed by 0.2µm of nickel (Ni), and finally 1µm of silver (Ag). This ensures that the properties of the upper gate and source layers of the solid-state switch chip after metallization are consistent with the metal layer of the lower drain layer, further guaranteeing the integrity of subsequent soldering and the reliability of the module. Furthermore, the anodes of diodes D14 and D25 are also subjected to the same metallization treatment. After the gate and source metallization of the solid-state switch chip 12, the solid-state switch gate control port 13 is connected to the gate of each chip, and the solid-state switch Kelvin source port 14 is connected to the source of each chip, thereby enabling synchronous control of the on / off state of each solid-state switch.

[0027] like Figure 4 As shown, the construction of the power module can be roughly divided into two steps: ① The power supply charges the non-inductive capacitor through the first port 6, at which time the solid-state switch is in the off state; ② The solid-state switch turns on, the non-inductive capacitor begins to discharge, and the current flows through the solid-state switch and out from the fourth port 8. When the power modules are cascaded in multiple stages, the fourth port 8 of the previous stage module and the second port 9 of the next stage module are connected together, and the third port 7 of the previous stage module and the first port 6 of the next stage module are connected together, which can realize the function of voltage superposition.

[0028] To reduce the parasitic inductance of the power module, its layout needs to be optimized. The entire module should be designed according to the following... Figure 4The electrical connections are shown. Ports 6 and 9 are input ports, through which current flows in. Ports 7 and 8 are output ports, through which current flows out. Based on the principle of mutual inductance cancellation, ports with opposite current flows are combined: port 6 and port 7 are combined, and port 9 and port 8 are combined. Each port has the same structure, and the two ports in each pair are symmetrical. The spacing between the combined ports is 1mm. This is to maximize mutual inductance and reduce parasitic inductance while ensuring no breakdown occurs at high voltages. Furthermore, these ports can also serve as connection ports for multi-stage busbars, facilitating cascading of multiple modules to increase output voltage. The first and second non-inductive capacitor ports 10 and 11 are soldered to the edge of the upper ceramic copper-clad laminate. Appropriate non-inductive capacitors can be selected later as needed, providing high flexibility.

[0029] The power module measures 53mm*27mm*10mm. When the module was imported into Ansys Q3D Extractor software for parasitic parameter extraction, the parasitic inductance of the power circuit was found to be 5.29nH. In contrast, the parasitic inductance of traditional packaging structures with similar dimensions is above 10nH.

[0030] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low parasitic inductance power module, comprising two pairs of input / output ports, namely a first port (6) and a second port (9) as input ports, and a third port (7) and a fourth port (8) as output ports, wherein a non-inductive capacitor and a solid-state switch chip (12) connected in parallel are provided between the two pairs of input / output ports, and further comprising a diode D1 (4), wherein the anode of the diode D1 (4) is connected to the first port (6), and the cathode is connected to the point on the line connecting the non-inductive capacitor and the solid-state switch chip (12) between the first port (6) and the third port (7); the other end of the non-inductive capacitor is connected to the second port (9); a diode D2 (5) is provided, wherein the anode of the diode D2 (5) is connected to the second port (9), and the cathode is connected to the point on the line connecting the solid-state switch chip (12) between the second port (9) and the fourth port (8); characterized in that: In terms of structural distribution, the power module includes a substrate (1), a lower ceramic copper-clad board (2), and an upper ceramic copper-clad board (3) arranged from bottom to top. The substrate is connected to the lower copper foil of the lower ceramic copper-clad board, and the lower ceramic copper-clad board is connected to the upper ceramic copper-clad board. The upper devices on the upper surface of the upper ceramic copper-clad board are connected to the upper copper foil of the upper ceramic copper-clad board by solder. The ceramic copper-clad board is used as an intermediate layer to electrically isolate the high-voltage circuits of the upper and lower layers. The upper ceramic copper-clad board (3) is equipped with a solid-state switch chip (12) connected to the lower ceramic copper-clad board (2). The upper surface of the upper ceramic copper-clad board (3) is equipped with the two pairs of input and output ports. The first port (6) corresponds to the third port (7), and the second port (9) corresponds to the fourth port (8). The first port (6) and the third port (7) are combined, and the second port (9) and the fourth port (8) are combined. Each port has the same structure, the two ports in each pair are symmetrical, and the current direction of each pair of ports is opposite. By using the mutual inductance cancellation principle, the parasitic inductance at the port is reduced. The solid-state switch chip (12) is set on one side of the upper ceramic copper-clad plate (3), and the drain of the transistor at its bottom is connected to the lower ceramic copper-clad plate (2). The source and gate of the transistor at the top of the solid-state switch chip (12) are connected to the upper ceramic copper-clad plate (3). Diodes D1 (4) and D2 (5) are set on the other side of the upper ceramic copper-clad plate (3), and diodes D1 (4) and D2 (5) are in the same direction. Through the unidirectional conductivity of the diodes and the selection of the on and off state of the solid-state switch chip, the current flows through the ceramic copper-clad plates in a fixed path, and the current flows in opposite directions at the input and output ports. The parasitic inductance at the power module ports cancels each other out, thereby reducing the overall parasitic inductance of the power module.

2. The low parasitic inductance power module according to claim 1, characterized in that: The upper ceramic copper-clad board (3) has a set of parallel solid-state switch chips (12) inside, and the solid-state switch gate control port (13) and solid-state switch Kelvin source port (14) are separated and brought out for external connection.

3. A low parasitic inductance power module according to claim 1, characterized in that: The gate and source of the solid-state switch chip (12) are metallized.

4. A low parasitic inductance power module according to claim 3, characterized in that: By adding a multi-level busbar, multiple modules are connected at the port to superimpose the output voltage.

5. A method for manufacturing a low parasitic inductance power module based on any one of claims 1 to 4, characterized in that... Includes the following steps: Step 1: Connect the substrate (1), the lower ceramic copper-clad laminate (2) and the upper ceramic copper-clad laminate (3) from bottom to top by reflow soldering. Step 2: Slot the upper ceramic copper-clad board (3) to set the solid-state switch chip (12) connected to the lower ceramic copper-clad board (2). Step 3: Two pairs of input / output ports are set on the upper surface of the upper ceramic copper-clad laminate (3). A non-inductive capacitor and a solid-state switch chip (12) connected in parallel are set between the two pairs of input / output ports. The two pairs of input / output ports are respectively the first port (6) and the second port (9) as input ports and the third port (7) and the fourth port (8) as output ports. The first port (6) corresponds to the third port (7), and the second port (9) corresponds to the fourth port (8). The three solid-state switch chips (12) are located at the bottom of the three The drain of the transistor is connected to the lower ceramic copper-clad plate (2), and the source and gate of the transistor at the top of the solid-state switch chip (12) are connected to the upper ceramic copper-clad plate (3). A diode D1 (4) is set between the point on the line connecting the first port (6) and the third port (7) of the non-inductive capacitor and the first port (6). A diode D2 (5) is set between the point on the line connecting the non-inductive capacitor and the solid-state switch chip (12) between the second port (9) and the fourth port (8), and diodes D1 (4) and D2 (5) are in the same direction.

6. The method for manufacturing a low parasitic inductance power module according to claim 5, characterized in that: The gate and source of the solid-state switch chip (12) are metallized by sputtering titanium (Ti), nickel (Ni), and silver (Ag) in sequence, so that the properties of the upper gate and source of the solid-state switch chip (12) after metallization are consistent with the metal layer of the bottom drain of the solid-state switch chip (12).

7. The method for manufacturing a low parasitic inductance power module according to claim 5, characterized in that: The upper ceramic copper-clad board (3) has a set of parallel solid-state switch chips (12) inside, and the solid-state switch gate control port (13) and solid-state switch Kelvin source port (14) are separated and brought out for external connection.

8. The method for manufacturing a low parasitic inductance power module according to claim 5, characterized in that: When the power supply charges the non-inductive capacitor through the first port (6), the solid-state switch chip (12) is in the off state. When the solid-state switch chip (12) is turned on, the non-inductive capacitor begins to discharge, and the current flows through the solid-state switch chip (12) and out from the fourth port (8). When the power modules are cascaded in multiple stages, the fourth port (8) of the previous stage power module is connected to the second port (9) of the next stage power module, and the third port (7) of the previous stage power module is connected to the first port (6) of the next stage power module.

9. The method for manufacturing a low parasitic inductance power module according to claim 5, characterized in that: The reflow soldering is divided into three soldering processes. The first reflow soldering sintersects the lower ceramic copper-clad laminate (2) with the substrate (1). The second reflow soldering sintersects the upper ceramic copper-clad laminate (3), the bottom of the solid-state switch chip with the lower ceramic copper-clad laminate (2). The third reflow soldering sintersects the first port (6), the second port (9), the third port (7), the fourth port (8), and the port of the non-inductive capacitor with the upper ceramic copper-clad laminate (3), and simultaneously solders the top of the solid-state switch chip with the solid-state switch gate control port (13) and the solid-state switch Kelvin source port (14).

Images