Groove type super junction field effect transistor and preparation method thereof

Abstract

According to the trench-type super-junction field effect transistor and the preparation method thereof provided by the invention, an air gap exists in a lower conductive column region of a conductive column, and the doping concentration of the lower conductive column is smaller than that of an upper conductive column, so that the resistance of the lower conductive column of the conductive column is larger than that of the upper conductive column; when the device is turned off, that is, when majority carriers are compositely extracted, the lower conductive column region is affected by a larger resistance value, and the moving speed is slowed down, so that the reverse recovery current peak is reduced when the device is turned off, and especially when minority carrier lifetime control of the device is improved, the reverse recovery softness of the super junction diode is improved, and the service life of the super junction diode is prolonged. And the switching loss and the current oscillation are reduced. And meanwhile, the height of the lower conductive column is smaller than that of the upper conductive column, so that the specific on-resistance of the device can be reduced or even avoided, and the influence on the conductive efficiency, the power loss, the switching speed, the voltage endurance capability and the like of the device caused by the specific on-resistance can be reduced or even avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device preparation, and in particular to a trench type super junction field effect transistor and a preparation method thereof. Background Art

[0002] As an advanced power MOSFET device technology, the trench super junction field effect transistor (Super Junction Trench MOSFET) forms a space charge region by introducing a vertical P pillar and N-type epitaxial depletion. When subjected to reverse voltage, the charge balance between the N-type epitaxial and the P pillar expands the depletion region, thereby increasing the breakdown voltage.

[0003] The P column of the existing trench superjunction field effect transistor is formed by deep trench etching of N-type epitaxy and then filling with P-type epitaxy. The body diode formed by the P-well P column and N-epitaxial of the superjunction plays the role of a freewheeling diode in the switch. In order to enhance the body diode performance of the superjunction, electron irradiation and platinum diffusion processes are usually used to improve the minority carrier lifetime of the device and reduce the reverse recovery current and switching loss during the reverse recovery of the device. However, there are problems such as large reverse recovery current spikes when the device is turned off and reverse recovery current oscillation. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a trench type super junction field effect transistor and a preparation method thereof, so as to solve the problems of large reverse recovery current spike and current oscillation of the trench type super junction field effect transistor when it is turned off in the prior art.

[0005] To achieve the above-mentioned purpose and other related purposes, the present invention provides a trench superjunction field effect transistor, which comprises, from bottom to top, a first conductivity type drain, a first conductivity type lower epitaxial layer, a first conductivity type upper epitaxial layer, a second conductivity type well region and a first conductivity type source; wherein the doping concentration of the lower epitaxial layer is less than the doping concentration of the upper epitaxial layer, and the thickness of the lower epitaxial layer is less than the thickness of the upper epitaxial layer;

[0006] It also includes: a conductive column and a trench gate of a second conductive type; wherein the conductive column extends downward from the surface of the source to a preset depth in the lower epitaxial layer, and the conductive column is divided into a lower conductive column and an upper conductive column from bottom to top, the top of the lower conductive column is not higher than the top of the lower epitaxial layer, the doping concentration of the lower conductive column is the same as the doping concentration of the lower epitaxial layer, an air gap is formed in the lower conductive column, the doping concentration of the upper conductive column extending from bottom to top to the part flush with the top of the upper epitaxial layer is the same as the doping concentration of the upper epitaxial layer, and the trench gate extends downward from the surface of the source to a preset depth in the upper epitaxial layer.

[0007] Optionally, the thickness of the lower epitaxial layer is 15 μm to 20 μm, the height of the lower conductive column is 5 μm to 10 μm; the doping concentration of the upper epitaxial layer is 0.99E15 NA / cm 3 ~1.21E15 NA / cm 3 , the doping concentration of the lower epitaxial layer is less than the doping concentration of the upper epitaxial layer by 15% of the doping concentration of the upper epitaxial layer.

[0008] Optionally, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0009] Optionally, the top of the lower conductive column is flush with the top of the lower epitaxial layer.

[0010] Optionally, the trench type super junction field effect transistor further includes:

[0011] an interlayer dielectric layer covering the conductive pillar, the trench gate and the source;

[0012] An electrical lead-out structure penetrating the interlayer dielectric layer, the electrical lead-out structure electrically leads the conductive pillar, the trench gate and the source electrode;

[0013] A back metal layer is located on the lower surface of the drain electrode.

[0014] Furthermore, the electrical lead-out structure includes:

[0015] A plurality of conductive contact holes formed in the interlayer dielectric layer, the conductive contact holes being connected to the trench gates and the conductive pillars;

[0016] A front metal layer disposed above the interlayer dielectric layer and the conductive contact hole;

[0017] A passivation layer is disposed on the front metal layer, and a plurality of pad windows are disposed in the passivation layer.

[0018] Optionally, the depth of the trench gate is 3 μm to 5 μm.

[0019] The present invention also provides a method for preparing a trench type super junction field effect transistor, the method comprising:

[0020] Providing a first conductive type substrate, the substrate comprising, from bottom to top, a substrate layer, a lower epitaxial layer and an upper epitaxial layer; wherein the doping concentration of the lower epitaxial layer is less than the doping concentration of the upper epitaxial layer, and the thickness of the lower epitaxial layer is less than the thickness of the upper epitaxial layer;

[0021] A plurality of deep trenches are formed extending downward from the upper surface of the upper epitaxial layer of the substrate to a preset depth in the lower epitaxial layer;

[0022] A conductive column of a second conductive type is formed in the deep trench; wherein the conductive column is divided into a lower conductive column and an upper conductive column from bottom to top, the top of the lower conductive column is not higher than the top of the lower epitaxial layer, the doping concentration of the lower conductive column is the same as the doping concentration of the lower epitaxial layer, an air gap is formed in the lower conductive column, and the doping concentration of the portion of the upper conductive column extending from bottom to top to be flush with the top of the upper epitaxial layer is the same as the doping concentration of the upper epitaxial layer;

[0023] Performing ion implantation at a preset depth on the upper surface of the upper epitaxial layer to form a second conductivity type well region;

[0024] A trench gate is formed by extending downward from the upper surface of the well region to a preset depth in the upper epitaxial layer;

[0025] Ions are implanted into the upper surface of the well region to a preset depth to form a first conductive type source.

[0026] Optionally, the method of forming the lower conductive pillar includes:

[0027] Based on the CVD process, epitaxial gas, doping gas and etching gas are introduced to deposit the lower conductive column in the deep trench. After a preset deposition time, the supply of the etching gas is stopped and the CVD process is continued to seal the lower conductive column at a position not higher than the top of the lower epitaxial layer, so that the top of the lower conductive column is not higher than the top of the lower epitaxial layer, and the air gap is formed inside the lower conductive column in the deep trench.

[0028] Optionally, the step of forming the deep trench in the substrate comprises:

[0029] forming a first hard mask layer of an ONO structure on the upper surface of the substrate;

[0030] Defining the deep trench region based on the first hard mask layer, and etching the substrate to form the deep trench;

[0031] The remaining first hard mask layer is removed.

[0032] Optionally, after forming the source electrode, the following steps are further included:

[0033] forming an interlayer dielectric layer on the upper surface of the obtained structure;

[0034] Forming an electrical lead-out structure penetrating the interlayer dielectric layer, wherein the electrical lead-out structure electrically leads the conductive pillar, the trench gate and the source electrode;

[0035] Performing backside thinning on the substrate layer to form a drain electrode;

[0036] A back-metal process is performed on the lower surface of the drain electrode to form a back metal layer.

[0037] Furthermore, the method of forming the electrical lead-out structure includes:

[0038] forming a plurality of conductive contact holes in the interlayer dielectric layer, wherein the conductive contact holes are connected to the trench gates and the conductive pillars;

[0039] forming a front metal layer covering the interlayer dielectric layer and the conductive contact hole;

[0040] A passivation layer is formed on the front metal layer, and a plurality of pad windows are formed penetrating the passivation layer.

[0041] Optionally, the step of forming the trench gate includes:

[0042] forming a second hard mask layer of an ONO structure on the upper surface of the obtained structure;

[0043] Defining a shallow trench region based on the second hard mask layer, and etching the well region and the upper epitaxial layer to form the shallow trench;

[0044] removing the remaining second hard mask layer;

[0045] forming a gate oxide layer on the bottom wall and sidewall of the shallow trench;

[0046] A gate conductive layer filling the shallow trench is formed on the gate oxide layer.

[0047] Optionally, the step of forming the source electrode includes:

[0048] Forming a photoresist layer on the surface of the obtained structure, and patterning the photoresist, wherein the patterned photoresist layer covers the trench gate, the well region and the conductive column and exposes the source region;

[0049] Performing ion implantation on the upper surface of the well region based on the patterned photoresist layer to form the source in the source region;

[0050] The remaining photoresist layer is removed.

[0051] As described above, the present invention provides a trench-type superjunction field effect crystal and a preparation method thereof, which have the following beneficial effects: by setting an air gap inside the lower conductive column region of the conductive column, and setting the doping concentration of the lower conductive column to be lower than the doping concentration of the upper conductive column, so that the resistance of the lower conductive column of the conductive column is greater than that of the upper conductive column, it can be achieved that when the device is turned off, that is, when the majority carriers are recombined and extracted, the lower conductive column region is affected by a greater resistance value, and the speed of movement is slowed down, thereby making the reverse recovery current spike when the device is turned off smaller, especially when the device improves the minority carrier lifetime control, to achieve the effect of improving the reverse recovery softness of the super junction diode, reducing switching loss and current oscillation. At the same time, setting the height of the lower conductive column to be less than the height of the upper conductive column can reduce or even avoid affecting the specific on-resistance of the device, thereby reducing or even avoiding the resulting impact on the conductive efficiency, power loss, switching speed and withstand voltage of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 Shown is a schematic diagram of the cross-sectional structure of the trench superjunction field effect transistor of the present invention.

[0053] Figure 2 It is a schematic flow chart of the method for preparing the trench type super junction field effect transistor of the present invention.

[0054] Figure 3 It is a schematic cross-sectional structure diagram of forming a first hard mask layer on a substrate according to the present invention.

[0055] Figure 4 It is a schematic diagram showing the cross-sectional structure of forming a deep trench according to the present invention.

[0056] Figure 5 It is a schematic diagram showing the cross-sectional structure of forming the lower conductive column according to the present invention.

[0057] Figure 6 It is a schematic diagram of the cross-sectional structure of forming the upper conductive pillar and the well region according to the present invention.

[0058] Figure 7 It is a schematic diagram showing the cross-sectional structure of forming a second hard mask layer according to the present invention.

[0059] Figure 8 It is a schematic diagram of the cross-sectional structure of forming a shallow trench according to the present invention.

[0060] Fig. 9Shown is a schematic diagram of a cross-sectional structure of forming a trench gate and a source electrode according to the present invention.

[0061] Fig.10 It is a schematic diagram showing the cross-sectional structure of forming an interlayer dielectric layer according to the present invention.

[0062] Fig.11 It is a schematic cross-sectional structure diagram of forming a conductive contact hole in an interlayer dielectric layer according to the present invention.

[0063] Fig.12 It is a schematic diagram showing the cross-sectional structure of forming an adhesion layer and an interconnection metal layer in a conductive contact hole according to the present invention.

[0064] Fig.13 It is a schematic diagram showing the cross-sectional structure of forming the front metal layer according to the present invention.

[0065] Fig.14 Shown is a schematic diagram of the cross-sectional structure of the front metal layer of the present invention after etching.

[0066] Fig.15 Shown is a schematic diagram of the cross-sectional structure of forming a passivation layer and a pad window according to the present invention.

[0067] Fig.16 It is a schematic diagram showing the cross-sectional structure of forming the drain electrode and the back metal layer according to the present invention.

[0068] Component number description

[0069] 11 Base

[0070] 111 substrate layer

[0071] 112 Lower epitaxial layer

[0072] 113 Upper epitaxial layer

[0073] 12 Deep Grooves

[0074] 13 Conductive column

[0075] 131 Lower conductive column

[0076] 132 upper conductive column

[0077] 133 Air Gap

[0078] 14 Well region

[0079] 15 Trench Gate

[0080] 151 Gate Oxide

[0081] 152 gate conductive layer

[0082] 16 Source

[0083] 17 Interlayer dielectric layer

[0084] 171 Silicon dioxide layer

[0085] 172 borophosphosilicate glass layer

[0086] 18 First hard mask layer

[0087] 19 Second hard mask layer

[0088] 181, 191 bottom silicon dioxide layer

[0089] 183, 193 Top silicon dioxide layer

[0090] 182, 192 Silicon nitride layer

[0091] 20 Shallow groove

[0092] 21 Conductive contact hole

[0093] 211 First contact hole

[0094] 212 second contact hole

[0095] 22 Interconnect Metal Layer

[0096] 23. Front metal layer

[0097] 24 Passivation layer

[0098] 241 Silicon Nitride Layer

[0099] 242 Polyimide

[0100] 25 Pad Window

[0101] 26 Drain

[0102] 27 Back metal layer

[0103] Steps S1 to S6 DETAILED DESCRIPTION

[0104] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0105] See also Figures 1 to 16It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0106] like Figure 1 As shown, this embodiment provides a trench super junction field effect transistor, which includes, from bottom to top, a first conductivity type drain 26, a first conductivity type lower epitaxial layer 112, a first conductivity type upper epitaxial layer 113, a second conductivity type well region 14 and a first conductivity type source 16; wherein the doping concentration of the lower epitaxial layer 112 is less than the doping concentration of the upper epitaxial layer 113, and the thickness of the lower epitaxial layer 112 is less than the thickness of the upper epitaxial layer 113;

[0107] It also includes: a conductive column 13 of a second conductive type and a trench gate 15; wherein the conductive column 13 extends downward from the surface of the source 16 to a preset depth in the lower epitaxial layer 112, and the conductive column 13 is divided from bottom to top into a lower conductive column 131 and an upper conductive column 132, the top of the lower conductive column 131 is not higher than the top of the lower epitaxial layer 112, the doping concentration of the lower conductive column 131 is the same as the doping concentration of the lower epitaxial layer 112, an air gap 133 is formed in the lower conductive column 131, the doping concentration of the upper conductive column 132 extending from bottom to top to the portion flush with the top of the upper epitaxial layer 113 is the same as the doping concentration of the upper epitaxial layer, and the trench gate 15 extends downward from the surface of the source 16 to a preset depth in the upper epitaxial layer 113.

[0108] The trench superjunction field effect transistor of the present embodiment forms an air gap inside the lower conductive column region of the conductive column, and sets the doping concentration of the lower conductive column to be lower than the doping concentration of the upper conductive column, so that the resistance of the lower conductive column is larger than that of the upper conductive column. This can achieve that when the device is turned off, that is, when the majority carriers are recombined and extracted, they are affected by a greater resistance in the lower conductive column region, and the speed of movement is slowed down, thereby reducing the reverse recovery current spike when the device is turned off. In particular, when the device improves the minority carrier lifetime control, the reverse recovery softness of the super junction diode is improved, and the switching loss and current oscillation are reduced. At the same time, the height of the lower conductive column is set to be smaller than the height of the upper conductive column, which can reduce or even avoid affecting the specific on-resistance of the device, thereby reducing or even avoiding the resulting impact on the conductive efficiency, power loss, switching speed and withstand voltage of the device.

[0109] In this embodiment, the first conductivity type includes N type and P type, the second conductivity type includes P type and N type, and the first conductivity type is different from the second conductivity type, for example, the first conductivity type is N type and the second conductivity type is P type, or the first conductivity type is P type and the second conductivity type is N type. In this embodiment, the first conductivity type is N type and the second conductivity type is P type. In addition, the N-type doping ions can be pentavalent ions such as nitrogen, phosphorus, arsenic, and antimony, and the P-type doping ions can be trivalent ions such as boron, aluminum, gallium, and indium. The selection is based on actual needs and is not excessively limited here.

[0110] The drain 26 is a semiconductor material doped with a first conductivity type, and the doped ions may be trivalent and pentavalent ions such as nitrogen, phosphorus, arsenic, antimony, boron, aluminum, gallium and indium. As an example, the drain 26 may be formed of N-type or P-type doped semiconductor materials such as silicon and germanium.

[0111] The doping concentration of the lower conductive column 131 is the same as the doping concentration of the lower epitaxial layer 112, and the doping concentration of the portion of the upper conductive column 132 extending from bottom to top to be flush with the top of the upper epitaxial layer 113 is the same as the doping concentration of the upper epitaxial layer 113, which can keep the charge in the device balanced. In the on state, it helps to reduce the on-resistance of the device, and helps to reduce or even avoid excessive electric field concentration near the PN junction that causes device breakdown or performance degradation, thereby helping to maintain the stability and reliability of the device in long-term operation.

[0112] As an example, the doping concentration of the upper epitaxial layer 113 is 0.99E15 NA / cm 3 ~1.21E15 NA / cm 3 The doping concentration of the lower epitaxial layer 112 is lower than the doping concentration of the upper epitaxial layer 113 by 15% of the doping concentration of the upper epitaxial layer 113. Preferably, in this embodiment, the doping concentrations of the lower epitaxial layer 112 and the lower conductive pillar 131 are 1.00E15 NA / cm3, and the doping concentration of the upper conductive pillar 132 extending from bottom to top to be flush with the top of the upper epitaxial layer 113 is 1.18E15 NA / cm3.

[0113] While setting the lower conductive column 131 of the conductive column 13 to have a larger resistance, in order to reduce or even avoid affecting the specific on-resistance (Rsp) of the device, the thickness of the lower epitaxial layer 112 is set to be smaller than the thickness of the upper epitaxial layer 113, and then the thickness of the lower conductive column 131 is set to be smaller than the thickness of the upper conductive column 132, and the top of the lower conductive column 131 is set to be no higher than the top of the lower epitaxial layer 112, so as to reduce or even avoid affecting the Rsp of the device. As an example, the thickness of the lower epitaxial layer 112 can be set to 15μm to 20μm, the height of the lower conductive pillar 131 can be set to 5μm to 10μm, the bottom of the lower epitaxial layer 112 is 10μm away from the bottom of the lower epitaxial layer 112, and the thickness of the upper epitaxial layer 113 can be adjusted according to the performance of the target device. Preferably, in this embodiment, the thickness of the lower epitaxial layer 112 is set to 15μm, and the thickness of the upper epitaxial layer 113 is set to 25μm, so as to reduce or even avoid the impact on the device Rsp, thereby reducing or even avoiding the impact on the device's conductive efficiency, power loss, switching speed and withstand voltage. In addition, based on the purpose of being easier to achieve in the process, this embodiment sets the top of the lower conductive pillar 131 to be flush with the top of the lower epitaxial layer 112.

[0114] As an example, Figure 1 As shown, the trench type super junction field effect transistor also includes:

[0115] an interlayer dielectric layer 17 covering the conductive pillar 13, the trench gate 15 and the source 16;

[0116] An electrical lead-out structure penetrating the interlayer dielectric layer 17, wherein the electrical lead-out structure electrically leads the conductive pillar 13, the trench gate 15 and the source 16;

[0117] A back metal layer 27 is located on the lower surface of the drain electrode 26 .

[0118] like Figure 1 and Fig.11 As shown, as an example, the electrical lead-out structure includes: a plurality of conductive contact holes 21 formed in the interlayer dielectric layer, the conductive contact holes 21 are connected to the trench gates 15 and the conductive pillars 13;

[0119] A front metal layer 23 disposed above the interlayer dielectric layer 17 and the conductive contact hole 21;

[0120] A passivation layer 24 is disposed on the front metal layer 23 , and a plurality of pad windows 25 are disposed in the passivation layer 24 .

[0121] like Figure 1 and Fig.11 As shown, the conductive contact hole 21 includes a first contact hole 211 connected to the trench gate 15 and a second contact hole 212 connected to the conductive column 13. Fig.12 As shown, as an example, the surfaces of the first contact hole 211 and the second contact hole 212 have an adhesion layer and an interconnection metal layer 22 formed in sequence, and the first contact hole 211 is filled with the interconnection metal layer 22 to enhance the electrical connection between the electrical lead-out structure and the trench gate 15, thereby reducing the switching loss of the device and improving the device performance. As an example, the adhesion layer can be a titanium layer and / or a titanium nitride layer, the interconnection metal layer can be a tungsten layer, or the adhesion layer can be a tantalum and / or a tantalum nitride layer, and the interconnection metal layer can be a copper layer and / or a copper alloy layer.

[0122] By optimizing the geometric parameters of the trench gate 15 of the trench superjunction field effect transistor, such as width, depth and spacing, the injection efficiency of electrons and holes can be improved, the conduction loss and switching loss can be reduced, and the stability and durability of the device can be improved. As an example, the depth of the trench gate 15 can be set to 3μm~5μm.

[0123] As an example, the interlayer dielectric layer 17 may be a single structure layer, or as shown in this embodiment, a composite laminate structure layer including a silicon dioxide layer 171 and a borophosphosilicate glass layer 172. The silicon dioxide layer 171 helps to improve the interlayer stress, and its thickness is preferably The thickness of the borophosphosilicate glass layer 172 is preferably

[0124] As an example, the passivation layer 24 can be a single-layer or multi-layer stacked structure. As an example, the passivation layer 24 can include only a silicon nitride layer, or it can include a silicon nitride layer and a polymer layer located on the silicon nitride layer. Preferably, in this embodiment, the passivation layer 24 is selected to include a silicon nitride layer 241 and a polyimide layer 242, so that the passivation layer 24 can better protect the underlying structure.

[0125] As an example, the front metal layer 23 can be an aluminum-copper alloy layer, the back metal layer 27 can be at least one of a copper layer, a gold layer, a nickel layer and other material layers, and there can also be an adhesion layer between the back metal layer 27 and the drain electrode 26, for example, a titanium layer and / or a titanium nitride layer, to enhance the adhesion between the back metal layer 27 and the drain electrode 26.

[0126] This embodiment also provides a method for preparing a trench super junction field effect transistor, which is used to prepare the above trench super junction field effect transistor, but is not limited thereto, and other suitable preparation methods are also possible. The above content can be quoted in full here, and will not be repeated below for the purpose of brevity. Figure 2 As shown, the preparation method comprises the following steps:

[0127] S1, providing a first conductive type substrate, the substrate comprising, from bottom to top, a substrate layer, a lower epitaxial layer and an upper epitaxial layer; wherein the doping concentration of the lower epitaxial layer is less than the doping concentration of the upper epitaxial layer, and the thickness of the lower epitaxial layer is less than the thickness of the upper epitaxial layer;

[0128] S2, forming a plurality of deep trenches extending downward from the upper surface of the upper epitaxial layer of the substrate to a preset depth in the lower epitaxial layer;

[0129] S3, forming a conductive column of a second conductive type in the deep trench; wherein the conductive column is divided into a lower conductive column and an upper conductive column from bottom to top, the top of the lower conductive column is not higher than the top of the lower epitaxial layer, the doping concentration of the lower conductive column is the same as the doping concentration of the lower epitaxial layer, an air gap is formed in the lower conductive column, and the doping concentration of the portion of the upper conductive column extending from bottom to top to be flush with the top of the upper epitaxial layer is the same as the doping concentration of the upper epitaxial layer;

[0130] S4, performing ion implantation to a preset depth on the upper surface of the upper epitaxial layer to form a well region of a second conductivity type;

[0131] S5, extending downward from the upper surface of the well region to a preset depth in the upper epitaxial layer to form a trench gate;

[0132] S6, performing ion implantation to a preset depth on the upper surface of the well region to form a first conductivity type source.

[0133] The preparation method of the trench superjunction field effect transistor of the present embodiment forms an air gap inside the lower conductive column region of the conductive column in the trench superjunction field effect transistor, and sets the doping concentration of the lower conductive column to be lower than that of the upper conductive column, so that the resistance of the lower conductive column is greater than that of the upper conductive column, so that when the device is turned off, that is, when the majority carriers are recombined and extracted, the lower conductive column region is affected by a greater resistance value, and the movement speed is slowed down, thereby making the reverse recovery current spike when the device is turned off smaller, especially when the device improves the minority carrier lifetime control, to achieve the effect of improving the reverse recovery softness of the super junction diode, reducing the switching loss and current oscillation. At the same time, setting the height of the lower conductive column to be less than the height of the upper conductive column can reduce or even avoid affecting the specific on-resistance of the device, thereby reducing or even avoiding the resulting impact on the conductive efficiency, power loss, switching speed and withstand voltage of the device.

[0134] The method for preparing the trench super junction field effect transistor of this embodiment is described in detail below with reference to the specific drawings.

[0135] like Figure 3 As shown, firstly, step S1 is performed: providing a first conductive type substrate 11, wherein the substrate 11 includes, from bottom to top, a substrate layer 111, a lower epitaxial layer 112, and an upper epitaxial layer 113; wherein the doping concentration of the lower epitaxial layer 112 is less than the doping concentration of the upper epitaxial layer 113, and the thickness of the lower epitaxial layer 112 is less than the thickness of the upper epitaxial layer 113;

[0136] The substrate layer 111 is a semiconductor material doped with a first conductivity type, and the doped ions may be trivalent and pentavalent ions such as nitrogen, phosphorus, arsenic, antimony, boron, aluminum, gallium and indium. As an example, the drain 26 may be formed of N-type or P-type doped semiconductor materials such as silicon and germanium.

[0137] Before executing subsequent processes, the substrate 11 can be cleaned first, for example, by successively using an organic solvent such as acetone and deionized water to remove pollutants on the surface of the substrate 11, and then drying it, or first using a dilute acid solution to remove the natural oxide layer on the surface of the substrate 11, and then cleaning it with deionized water, and finally drying it, or using the aforementioned cleaning methods for multiple cleanings.

[0138] like Figure 4 As shown, step S2 is then performed: a plurality of deep trenches 12 are formed extending downward from the upper surface of the upper epitaxial layer 113 of the substrate 11 to a preset depth in the lower epitaxial layer 112 .

[0139] As a specific example, Figure 3 and Figure 4 As shown, the steps of forming the deep trench 12 include:

[0140] like Figure 3As shown, a mask layer is first formed on the substrate 11. The mask layer is preferably a hard mask, which helps to improve the etching accuracy. In this embodiment, a hard mask layer with an ONO structure is preferably used, which is defined as a first hard mask layer 18. The first hard mask layer 18 includes a bottom silicon dioxide layer 181, a silicon nitride layer 182 and a top silicon dioxide layer 183 from bottom to top. The thickness of the top silicon dioxide layer 183 is generally greater than the thickness of the bottom silicon dioxide layer 181. The structural layers of the first hard mask layer 18 can be formed in sequence by chemical vapor deposition process, or by thermal oxidation process to form the bottom silicon dioxide layer 181, and the silicon nitride layer 182 and the top silicon dioxide layer 183 can be formed by chemical vapor deposition process. The bottom silicon dioxide layer 181 serves as a buffer layer to buffer the stress between the silicon nitride layer 182 and the substrate 11, and the silicon nitride layer 182 serves as an etching stop layer for the top silicon dioxide layer 183. After the deep trench 12 is defined in the mask layer, the top silicon dioxide layer 183 will be consumed as a hard mask when etching the deep trench 12 in the substrate 11. Therefore, the use of a hard mask layer with an ONO structure can not only help to improve the etching accuracy, but also help to protect the substrate 11.

[0141] like Figure 4 As shown, after the first hard mask layer 18 of the ONO structure is formed on the upper surface of the substrate 11, the deep trench 12 area is defined based on the first hard mask layer 18, and the substrate 11 is etched to form the deep trench 12; then, the remaining first hard mask layer 18 is removed by using including but not limited to etching processes.

[0142] like Figure 6 As shown, step S3 is then performed: a conductive column 13 of a second conductive type is formed in the deep trench 12; wherein the conductive column 13 is divided into a lower conductive column 131 and an upper conductive column 132 from bottom to top, the top of the lower conductive column 131 is not higher than the top of the lower epitaxial layer 112, the doping concentration of the lower conductive column 131 is the same as the doping concentration of the lower epitaxial layer 112, an air gap 133 is formed in the lower conductive column 131, and the doping concentration of the upper conductive column 132 extending from bottom to top to the top flush with the top of the upper epitaxial layer 113 is the same as the doping concentration of the upper epitaxial layer 113.

[0143] As a preferred example, the process method for preparing the conductive pillar 13 is: based on the chemical vapor deposition (CVD) process, in order to make the epitaxial layer fill the entire deep trench and avoid premature sealing during epitaxial growth, the etching gas will be introduced at the same time as the epitaxial gas and the doping gas, and the flow rate of the etching gas is adjusted, for example, increased to about 1800sccm, and the method of etching while depositing is adopted to reduce the overall epitaxial growth rate. The side wall of the deep trench is almost not long, and the epitaxy grows only from the bottom to the top. The epitaxial gas can be selected as needed. For example, when it is silicon epitaxy, the epitaxial gas can be silane. If it is germanium epitaxy, the epitaxial gas can be germane. The doping gas can be N-containing gas or B-containing gas when depositing an N-type epitaxial layer, and the etching gas can be hydrogen chloride gas.

[0144] The specific method is as follows: first, using the above-mentioned process method, introducing epitaxial gas, doping gas and etching gas, and depositing the lower conductive column 131 in the deep trench 12, wherein the flow of the introduced doping gas needs to be adjusted to make the doping concentration of the lower conductive column 131 equal to the doping concentration of the lower epitaxial layer 112, and after the preset deposition time, stop supplying etching gas and continue the deposition process, so that the formed lower conductive column 131 is sealed at a position not higher than the top of the lower epitaxial layer 112, and the air gap 133 is formed inside the lower conductive column 131; then continue to introduce epitaxial gas, doping gas and etching gas, and form the upper conductive column 132 extending from bottom to top in the deep trench 12 to be flush with the top of the upper epitaxial layer 113, and adjust the flow of doping gas so that the doping concentration of the portion of the upper conductive column 132 flush with the top of the upper epitaxial layer 113 is the same as the doping concentration of the upper epitaxial layer 113.

[0145] As an example, the top of the formed upper conductive column 132 may be higher than or flush with the top of the upper epitaxial layer 113. After the upper conductive column 132 is formed, the surface of the upper conductive column 132 may be flattened by methods including but not limited to chemical mechanical polishing to remove the epitaxial material of the upper conductive column 132 and the epitaxial material of the lower conductive column 131 on the surface of the substrate 11 outside the deep trench 12 to expose the substrate 11, so that the surface of the upper conductive column 132 is flush with the surface of the upper epitaxial layer 113. The chemical mechanical polishing process combines the effects of mechanical grinding and chemical etching to form a smooth and flat surface on the substrate 11, providing a good surface foundation for subsequent processes.

[0146] like Figure 6As shown, step S4 is then performed to perform ion implantation at a preset depth on the upper surface of the upper epitaxial layer 113 to form a second conductive type well region 14; as an example, an ion implantation process can be used and a well can be pushed at a preset depth in the substrate 11 outside the deep trench 12 at high temperature to form the second conductive type well region 14.

[0147] like Fig. 9 As shown, step S5 is then performed to form a trench gate 15 extending downward from the upper surface of the well region 14 to a predetermined depth in the upper epitaxial layer 113 .

[0148] As a specific example, Figures 7 to 9 As shown, the steps of forming the trench gate 15 include:

[0149] like Figure 7 As shown, a second hard mask layer 19 of an ONO structure is formed on the upper surface of the obtained structure;

[0150] like Figure 8 As shown, a shallow trench 20 region is defined based on the second hard mask layer 19, and the well region 14 and the upper epitaxial layer 113 are etched to form the shallow trench 20;

[0151] removing the remaining second hard mask layer 19;

[0152] like Fig. 9 As shown, a gate oxide layer 151 is formed on the bottom wall and side wall of the shallow trench 20;

[0153] like Fig. 9 As shown, a gate conductive layer 152 is formed on the gate oxide layer 151 to fill the shallow trench 20 .

[0154] In the above specific example, the second hard mask layer 19 has the same ONO structure as the first hard mask layer 18, and the second hard mask layer 19 includes a silicon dioxide layer 191, a silicon nitride layer 192 and a silicon dioxide layer 193 from bottom to top. With the hard mask layer of this structure, the bottom silicon dioxide layer 191 is used as a buffer layer to buffer the stress between the silicon nitride layer 192 and the well region 14 and the conductive pillar 13, and the silicon nitride layer 192 is used as an etching stop layer for the top silicon dioxide layer 193. After the shallow trench 20 is defined in the second hard mask layer 19, the top silicon dioxide layer 193 will be consumed as a hard mask when etching the shallow trench 20. Therefore, the hard mask layer with an ONO structure is helpful to improve the etching accuracy and protect the well region 14 and the conductive pillar 13.

[0155] like Figure 8As shown, the positions of the formed deep groove 12 and the shallow groove 20 are staggered in the longitudinal direction, a deep groove 12 is arranged between two adjacent shallow grooves 20, and the shallow groove 20 penetrates the well region 14 and extends downward into the upper epitaxial layer 113, and then the remaining second hard mask layer 19 is removed by using including but not limited to etching processes.

[0156] like Fig. 9 As shown, as an example, a gate oxide layer 151 can be formed on the bottom wall and side wall of the shallow trench 20 by using a process including but not limited to thermal oxidation, and then a gate conductive layer 152 that fills the shallow trench 20 is formed on the gate oxide layer 151 by using a process including but not limited to chemical vapor deposition, for example, a polysilicon layer, and the gate conductive layer 152 fills the remaining space of the shallow trench 20, and the gate oxide layer 151 and the gate conductive layer 152 located in the shallow trench 20 constitute the trench gate 15. In practical applications, the geometric parameters of the trench gate 15, such as width, depth and spacing, can be optimized to improve the injection efficiency of electrons and holes, reduce conduction loss and switching loss, and improve the stability and durability of the device. As an example, the depth of the trench gate 15 can be set to 3μm to 5μm.

[0157] like Fig. 9 As shown, step S6 is then performed to form a first conductive type source 16 by performing ion implantation to a preset depth on the upper surface of the well region 14 .

[0158] As a specific example, the steps of forming the source 16 include:

[0159] Forming a photoresist layer on the surface of the obtained structure, and patterning the photoresist layer, wherein the patterned photoresist layer covers the trench gate 15, the well region 14 and the conductive column 13 and exposes the source electrode 16 region;

[0160] Performing ion implantation on the upper surface of the well region 14 based on the patterned photoresist layer to form the source 16 in the source 16 region;

[0161] The remaining photoresist layer is removed.

[0162] The source 16 is formed by a patterned photoresist layer, which can effectively prevent the first conductive type ion implantation from implanting the first conductive type ions into the conductive pillar 13 and the trench gate 15 when forming the source 16, thereby changing the doping state of the corresponding structure and affecting the device performance.

[0163] As an example, before forming the source electrode 16, a step of flattening the surface of the trench gate 15 is also included, so that the upper surface of the trench gate 15 is flush with the upper surface of the well region 14. The surface of the trench gate 15 can be flattened by methods including but not limited to chemical mechanical polishing to remove excess gate oxide layer 151 and gate conductive layer 152, thereby exposing the upper surface of the well region 14.

[0164] As an example, Figures 11 to 16 As shown, after forming the source electrode 16, the following steps are also included:

[0165] S7, forming an interlayer dielectric layer 17 on the upper surface of the obtained structure;

[0166] S8, forming an electrical lead-out structure penetrating the interlayer dielectric layer 17, wherein the electrical lead-out structure electrically leads the conductive pillar 13, the trench gate 15 and the source 16;

[0167] S9, performing backside thinning on the substrate layer 111 to form a drain electrode 26;

[0168] S10 , performing a back metal process on the lower surface of the drain electrode 26 to form a back metal layer 27 .

[0169] like Fig.10 As shown, in step S7, the interlayer dielectric layer 17 covers the conductive pillar 13, the trench gate 15 and the source 16. The interlayer dielectric layer 17 can be a single structure layer or a composite laminated structure layer. In this embodiment, a composite laminated structure layer including a silicon dioxide layer 171 and a borophosphosilicate glass layer 172 is preferably used. The silicon dioxide layer 171 helps to improve the interlayer stress, and its thickness is preferably The thickness of the borophosphosilicate glass layer 172 is preferably

[0170] like Figures 11 to 15 As shown, the method for forming the electrical lead-out structure in step S8 includes:

[0171] like Fig.12 As shown, a plurality of conductive contact holes 21 are formed in the interlayer dielectric layer 17, and the conductive contact holes 21 are connected to the trench gates 15 and the conductive pillars 13;

[0172] like Fig.13 and Fig.14 As shown, a front metal layer 23 covering the interlayer dielectric layer 17 and the conductive contact hole 21 is formed;

[0173] like Fig.15As shown, a passivation layer 24 is formed on the front metal layer 23 , and a plurality of pad windows 25 penetrating the passivation layer 24 are formed.

[0174] As an example, Fig.11 As shown, a plurality of the conductive contact holes 21 may be formed in the interlayer dielectric layer 17 by using processes including but not limited to etching.

[0175] like Fig.12 As shown, the conductive contact hole 21 includes a first contact hole 211 connected to the trench gate 15 and a second contact hole 212 connected to the conductive column 13. As an example, the surfaces of the first contact hole 211 and the second contact hole 212 have an adhesion layer and an interconnection metal layer 22 formed in sequence, and the first contact hole 211 is filled with the interconnection metal layer to enhance the electrical connection between the electrical lead-out structure and the trench gate, thereby reducing the switching loss of the device and improving the device performance.

[0176] As an example, an adhesion layer and an interconnection metal layer may be sequentially formed on the surface of the conductive contact hole 21 by using, but not limited to, a physical vapor deposition process, and the obtained structure is as follows: Fig.11 As shown; the adhesion layer may be a titanium and / or titanium nitride layer, the interconnection metal layer may be a copper layer and / or a copper alloy layer, or the adhesion layer may be a tantalum and / or tantalum nitride layer, and the interconnection metal layer may be a tungsten layer.

[0177] As an example, Fig.13 As shown, the front metal layer 23 covering the interlayer dielectric layer 17 and the conductive contact hole 21 may be formed by processes including but not limited to physical vapor deposition, and the front metal layer 23 may be an aluminum-copper alloy layer.

[0178] like Fig.14 As shown, in order to realize electrical extraction, the front metal layer 23 is further etched to form an opening penetrating the front metal layer 23 .

[0179] As an example, Fig.15 As shown, the passivation layer 24 is formed on the front metal layer 23. The passivation layer 24 can be a single layer or a multi-layer stacked structure, for example, it can only include a silicon nitride layer, or it can include a silicon nitride layer and a polymer layer located on the silicon nitride layer. Preferably, in this embodiment, a silicon nitride layer 241 and a polyimide 242 are selected to form a higher quality dielectric film layer. The silicon nitride layer 241 can be formed by a chemical vapor deposition process, and the polyimide 242 can be formed by a spin coating process. The formation of the passivation layer 24 can better protect the underlying structure, and then etching is performed to form the pad window 25.

[0180] like Fig.16As shown, the back metal layer 27 can be made of several materials such as copper layer, gold layer, nickel layer, etc., and an adhesion layer can also be formed between the back metal layer 27 and the drain electrode 26, such as a titanium layer and / or a titanium nitride layer.

[0181] In summary, the present invention provides a trench-type superjunction field effect transistor and a preparation method thereof, wherein the trench-type superjunction field effect transistor is provided to include, from bottom to top, a first conductive type drain, a first conductive type lower epitaxial layer, a first conductive type upper epitaxial layer, a second conductive type well region and a first conductive type source; wherein the doping concentration of the lower epitaxial layer is less than the doping concentration of the upper epitaxial layer, and the thickness of the lower epitaxial layer is less than the thickness of the upper epitaxial layer; and further includes: a second conductive type conductive column and a trench gate; wherein the conductive column extends downward from the surface of the source to a preset depth in the lower epitaxial layer, and the conductive column is divided from bottom to top into a lower conductive column and an upper conductive column, the top of the lower conductive column is not higher than the top of the lower epitaxial layer, and the doping of the lower conductive column is The concentration is the same as the doping concentration of the lower epitaxial layer, an air gap is formed in the lower conductive column, the doping concentration of the upper conductive column extending from bottom to top to the top of the upper epitaxial layer is the same as the doping concentration of the upper epitaxial layer, and the trench gate extends from the source surface downward to a preset depth in the upper epitaxial layer, so that the lower conductive column region of the conductive column has a greater resistance due to the presence of the air gap and the lower doping concentration, which can make the lower conductive column region be affected by a greater resistance when the device is turned off, that is, when the majority carriers are recombined and extracted, the movement speed is slowed down, thereby making the reverse recovery current peak when the device is turned off smaller, especially when the device improves the minority carrier lifetime control, to achieve the effect of improving the reverse recovery softness of the super junction diode, reducing the switching loss and current oscillation. At the same time, the height of the lower conductive column is set to be less than the height of the upper conductive column, which can reduce or even avoid affecting the specific on-resistance of the device, thereby reducing or even avoiding the resulting influence on the conductive efficiency, power loss, switching speed and withstand voltage of the device. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0182] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A trench superjunction field effect transistor, characterized in that: The trench superjunction field effect transistor comprises, from bottom to top, a first conductivity type drain, a first conductivity type lower epitaxial layer, a first conductivity type upper epitaxial layer, a second conductivity type well region and a first conductivity type source; wherein the doping concentration of the lower epitaxial layer is less than the doping concentration of the upper epitaxial layer, and the thickness of the lower epitaxial layer is less than the thickness of the upper epitaxial layer; It also includes: a conductive column and a trench gate of a second conductive type; wherein the conductive column extends downward from the surface of the source to a preset depth in the lower epitaxial layer, and the conductive column is divided into a lower conductive column and an upper conductive column from bottom to top, the top of the lower conductive column is not higher than the top of the lower epitaxial layer, the doping concentration of the lower conductive column is the same as the doping concentration of the lower epitaxial layer, an air gap is formed in the lower conductive column, the doping concentration of the upper conductive column extending from bottom to top to the part flush with the top of the upper epitaxial layer is the same as the doping concentration of the upper epitaxial layer, and the trench gate extends downward from the surface of the source to a preset depth in the upper epitaxial layer.

2. The trench type superjunction field effect transistor according to claim 1, characterized in that: The thickness of the lower epitaxial layer is 15 μm to 20 μm, and the height of the lower conductive column is 5 μm to 10 μm; The doping concentration of the upper epitaxial layer is 0.99E15 NA / cm 3 ~1.21E15 NA / cm 3 , the doping concentration of the lower epitaxial layer is less than the doping concentration of the upper epitaxial layer by 15% of the doping concentration of the upper epitaxial layer.

3. The trench type superjunction field effect transistor according to claim 1, characterized in that: The first conductivity type is N type and the second conductivity type is P type, or the first conductivity type is P type and the second conductivity type is N type.

4. The trench type superjunction field effect transistor according to claim 1, characterized in that: The top of the lower conductive column is flush with the top of the lower epitaxial layer.

5. The trench type super junction field effect transistor according to claim 1, characterized in that: The trench type super junction field effect transistor further comprises: an interlayer dielectric layer covering the conductive pillar, the trench gate and the source; An electrical lead-out structure penetrating the interlayer dielectric layer, the electrical lead-out structure electrically leads the conductive pillar, the trench gate and the source electrode; A back metal layer is located on the lower surface of the drain electrode.

6. The trench type super junction field effect transistor according to claim 5, characterized in that: The electrical lead-out structure comprises: A plurality of conductive contact holes formed in the interlayer dielectric layer, the conductive contact holes being connected to the trench gates and the conductive pillars; A front metal layer disposed above the interlayer dielectric layer and the conductive contact hole; A passivation layer is disposed on the front metal layer, and a plurality of pad windows are disposed in the passivation layer.

7. The trench type super junction field effect transistor according to claim 1, characterized in that: The depth of the trench gate is 3 μm to 5 μm.

8. A method for preparing a trench superjunction field effect transistor, characterized in that: The preparation method comprises: Providing a first conductive type substrate, the substrate comprising, from bottom to top, a substrate layer, a lower epitaxial layer and an upper epitaxial layer; wherein the doping concentration of the lower epitaxial layer is less than the doping concentration of the upper epitaxial layer, and the thickness of the lower epitaxial layer is less than the thickness of the upper epitaxial layer; A plurality of deep trenches are formed extending downward from the upper surface of the upper epitaxial layer of the substrate to a preset depth in the lower epitaxial layer; A conductive column of a second conductive type is formed in the deep trench; wherein the conductive column is divided into a lower conductive column and an upper conductive column from bottom to top, the top of the lower conductive column is not higher than the top of the lower epitaxial layer, the doping concentration of the lower conductive column is the same as the doping concentration of the lower epitaxial layer, an air gap is formed in the lower conductive column, and the doping concentration of the portion of the upper conductive column extending from bottom to top to be flush with the top of the upper epitaxial layer is the same as the doping concentration of the upper epitaxial layer; Performing ion implantation at a preset depth on the upper surface of the upper epitaxial layer to form a second conductivity type well region; A trench gate is formed by extending downward from the upper surface of the well region to a preset depth in the upper epitaxial layer; Ions are implanted into the upper surface of the well region to a preset depth to form a first conductive type source.

9. The method for preparing a trench type super junction field effect transistor according to claim 8, characterized in that: The method of forming the lower conductive pillar includes: Based on the CVD process, epitaxial gas, doping gas and etching gas are introduced to deposit the lower conductive column in the deep trench. After a preset deposition time, the supply of the etching gas is stopped and the CVD process is continued to seal the lower conductive column at a position not higher than the top of the lower epitaxial layer, so that the top of the lower conductive column is not higher than the top of the lower epitaxial layer, and the air gap is formed inside the lower conductive column in the deep trench.

10. The method for preparing a trench type super junction field effect transistor according to claim 8, characterized in that: The step of forming the deep trench in the substrate comprises: forming a first hard mask layer of an ONO structure on the upper surface of the substrate; Defining the deep trench region based on the first hard mask layer, and etching the substrate to form the deep trench; The remaining first hard mask layer is removed.

11. The method for preparing a trench superjunction field effect transistor according to claim 8, characterized in that: After forming the source electrode, the following steps are also included: forming an interlayer dielectric layer on the upper surface of the obtained structure; Forming an electrical lead-out structure penetrating the interlayer dielectric layer, wherein the electrical lead-out structure electrically leads the conductive pillar, the trench gate and the source electrode; Performing backside thinning on the substrate layer to form a drain electrode; A back-metal process is performed on the lower surface of the drain electrode to form a back metal layer.

12. The method for preparing a trench type super junction field effect transistor according to claim 11, characterized in that: The method of forming the electrical lead-out structure includes: forming a plurality of conductive contact holes in the interlayer dielectric layer, wherein the conductive contact holes are connected to the trench gates and the conductive pillars; forming a front metal layer covering the interlayer dielectric layer and the conductive contact hole; A passivation layer is formed on the front metal layer, and a plurality of pad windows are formed penetrating the passivation layer.

13. The method for preparing a trench type super junction field effect transistor according to claim 8, characterized in that: The step of forming the trench gate comprises: forming a second hard mask layer of an ONO structure on the upper surface of the obtained structure; Defining a shallow trench region based on the second hard mask layer, and etching the well region and the upper epitaxial layer to form the shallow trench; removing the remaining second hard mask layer; forming a gate oxide layer on the bottom wall and sidewall of the shallow trench; A gate conductive layer filling the shallow trench is formed on the gate oxide layer.

14. The method for preparing a trench superjunction field effect transistor according to claim 8, characterized in that: The steps of forming the source electrode include: Forming a photoresist layer on the surface of the obtained structure, and patterning the photoresist, wherein the patterned photoresist layer covers the trench gate, the well region and the conductive column and exposes the source region; Performing ion implantation on the upper surface of the well region based on the patterned photoresist layer to form the source in the source region; The remaining photoresist layer is removed.

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