Battery preparation method, back contact battery and photovoltaic module

Abstract

The invention discloses a battery preparation method, a back contact battery and a photovoltaic module, and relates to the technical field of back contact batteries. According to the preparation method of the cell, the intrinsic amorphous silicon layer is pretreated through the plasma of the mixed gas of carbon dioxide and hydrogen, so that the contact effect between the intrinsic amorphous silicon layer and the doping layer is improved, the passivation quality is improved, the light transmittance is improved, the current density and the cell conversion efficiency of the back contact cell are improved, and the cell quality is ensured.

Description

Technical Field

[0001] The present invention belongs to the technical field of back-contact batteries, and in particular relates to a battery preparation method, a back-contact battery and a photovoltaic module. Background Art

[0002] At present, in the preparation process of back-contact batteries, an N-type or P-type doped layer is generally deposited directly on the intrinsic amorphous silicon layer by plasma enhanced chemical vapor deposition. However, this results in poor contact between the intrinsic amorphous silicon layer and the doped layer, poor passivation quality, and low transmittance, resulting in low current density of the back-contact battery and low battery conversion efficiency.

[0003] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0004] The purpose of the present invention is to overcome the defects of the prior art, such as poor contact effect between the intrinsic amorphous silicon layer and the doped layer, poor passivation quality, and low transmittance, which lead to low current density of the back contact battery and low battery conversion efficiency. A battery preparation method, a back contact battery and a photovoltaic module are provided. The battery preparation method pretreats the intrinsic amorphous silicon layer by a mixed gas plasma of carbon dioxide and hydrogen to improve the contact effect between the intrinsic amorphous silicon layer and the doped layer, improve the passivation quality, and improve the transmittance, thereby improving the current density and battery conversion efficiency of the back contact battery and ensuring the battery quality.

[0005] In order to achieve the above object, in a first aspect, the present invention provides a method for preparing a battery, comprising: S1. Provide double-sided polished silicon wafers; S2. forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer, wherein the first semiconductor layer comprises a first tunneling oxide layer and a first doping layer disposed in sequence; S3. Etching an opening on the first tunneling oxide layer, the first doping layer and the mask layer to form a first opening region; S4. Cleaning and removing the first tunneling oxide layer, the first doping layer and the mask layer remaining in the first opening region, and forming a velvet surface in the first opening region and on the front side of the silicon wafer, and then cleaning and removing the mask layer outside the first opening region; S5. forming a first intrinsic amorphous silicon layer on the back side of the silicon wafer; S6. forming a second intrinsic amorphous silicon layer on the front side of the silicon wafer, pre-treating the second intrinsic amorphous silicon layer with a mixed gas plasma of carbon dioxide and hydrogen, and then forming a second doped layer on the second intrinsic amorphous silicon layer, wherein the second intrinsic amorphous silicon layer and the second doped layer together form a second semiconductor layer; S7. Forming a third doped layer on the first intrinsic amorphous silicon layer, wherein the first intrinsic amorphous silicon layer and the third doped layer together form a third semiconductor layer.

[0006] Preferably, S6 includes: S61. Depositing a second intrinsic amorphous silicon layer on the front side of the silicon wafer by plasma enhanced chemical vapor deposition, wherein the thickness of the second intrinsic amorphous silicon layer is 4nm-10nm; S62. A mixed gas plasma of carbon dioxide and hydrogen is introduced to reach a preset pressure, and the pressure is maintained for a preset time to pre-treat the second intrinsic amorphous silicon layer; S63. Depositing a second doping layer on the second intrinsic amorphous silicon layer by plasma enhanced chemical vapor deposition, wherein the thickness of the second doping layer is 10 nm-20 nm.

[0007] Preferably, the pretreatment conditions are: the preset gas pressure is 100Pa-300Pa, the preset time is 10s-60s, the treatment temperature is 140°C-200°C, and the ratio of hydrogen flow rate to carbon dioxide flow rate is 10-50.

[0008] Preferably, the ratio of the thickness increase ratio of the second intrinsic amorphous silicon layer to the preset time increase ratio is 0.08-0.1.

[0009] Preferably, in S63, silane, phosphine, hydrogen and carbon dioxide are introduced and reacted under the condition of turning on the glow to form a second doping layer, and the phosphorus doping concentration of the second doping layer is 1e18cm -3 -2e20cm -3 , the refractive index of the second doping layer is 2.1-2.8.

[0010] Preferably, the reaction conditions for forming the second doping layer are: reaction temperature of 140°C-200°C, reaction pressure of 100Pa-1000Pa, ratio of hydrogen flow to silane flow of 100-500, and ratio of carbon dioxide flow to silane flow of 1-4.

[0011] Preferably, S2 includes: S21. Forming a first tunneling oxide layer on the back of the silicon wafer by a dry method, wherein the thickness of the first tunneling oxide layer is 1nm-2nm; S22. depositing an intrinsic polysilicon layer on the first tunnel oxide layer by low pressure chemical vapor deposition, and then forming a first doped layer by diffusion, wherein the thickness of the first doped layer is 100nm-200nm; S23. Depositing a mask layer on the first doping layer by plasma enhanced chemical vapor deposition, wherein the thickness of the mask layer is 60nm-80nm.

[0012] Preferably, in S5, a first intrinsic amorphous silicon layer is deposited on the back side of the silicon wafer by plasma enhanced chemical vapor deposition, wherein the thickness of the first intrinsic amorphous silicon layer is 5 nm-12 nm.

[0013] Preferably, after S7, the battery preparation method further includes: S8. forming an anti-reflection layer on the second semiconductor layer; S9. Etching openings on the third semiconductor layer to form second opening regions that are alternately arranged with the first opening regions and spaced apart; S10. forming a conductive film layer on the back side of the silicon wafer; S11. An isolation groove is formed on the conductive film layer so that a portion of the conductive film layer separated from each other extends into the first opening region and covers the third semiconductor layer, and another portion extends into the second opening region and covers the first semiconductor layer; S12. Form a first electrode on the portion of the conductive film layer extending into the first opening region, and form a second electrode on the portion of the conductive film layer extending into the second opening region.

[0014] In a second aspect, the present invention provides a back-contact battery, which is prepared by the above-mentioned battery preparation method.

[0015] In a third aspect, the present invention provides a photovoltaic module comprising the above-mentioned back contact cell.

[0016] Beneficial effects: It has been found through research that, in the preparation process of a back contact cell, if an N-type or P-type doped layer is deposited directly on the intrinsic amorphous silicon layer, the contact effect between the intrinsic amorphous silicon layer and the doped layer will be poor, the passivation quality will be poor, and the light transmittance will be low, resulting in a low current density of the back contact cell and a low cell conversion efficiency. Based on this, further research has been conducted and the present invention is proposed.

[0017] The present invention adopts the above-mentioned technical scheme, especially pre-treating the intrinsic amorphous silicon layer through a mixed gas plasma of carbon dioxide and hydrogen, so as to improve the contact effect between the intrinsic amorphous silicon layer and the doping layer, improve the passivation quality, and improve the transmittance, thereby improving the current density and battery conversion efficiency of the back contact battery and ensuring the battery quality.

[0018] The back contact battery provided by the present invention is produced by the above-mentioned battery preparation method, has a better passivation effect, and has good product quality.

[0019] The photovoltaic module provided by the present invention includes the above-mentioned back contact cell, has better photoelectric conversion efficiency and high photovoltaic power generation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 This is a schematic diagram of the structure of a silicon wafer after double-sided polishing and cleaning according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of forming a first semiconductor layer and a mask layer on the back side of a silicon wafer according to an embodiment of the present invention; Figure 3 This is a schematic diagram of a structure in which a first opening area is formed on the back side of a silicon wafer according to an embodiment of the present invention; Figure 4 It is a schematic diagram of a structure in which a first intrinsic amorphous silicon layer is formed on the back side of a silicon wafer and a second intrinsic amorphous silicon layer is formed on the front side according to an embodiment of the present invention; Figure 5 This is a schematic diagram of a structure in which a second opening area is formed on the back side of a silicon wafer according to an embodiment of the present invention; Figure 6 This is a schematic diagram of a structure in which an isolation groove is formed on the back side of a silicon wafer according to an embodiment of the present invention; Figure 7 It is a schematic diagram of the structure of forming a first electrode and a second electrode on the back side of a silicon wafer according to an embodiment of the present invention.

[0022] Description of reference numerals: 1-silicon wafer; 2-first tunneling oxide layer; 3-first doping layer; 4-mask layer; 5-first opening area; 6-first intrinsic amorphous silicon layer; 7-second intrinsic amorphous silicon layer; 8-second doping layer; 9-third doping layer; 10-anti-reflection layer; 11-second opening area; 12-conductive film layer; 13-isolation groove; 14-first electrode; 15-second electrode. DETAILED DESCRIPTION

[0023] In the present invention, unless otherwise specified, directional words such as "up, down, left, right" are generally understood in combination with the directions shown in the drawings and actual applications.

[0024] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0025] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0026] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0027] In the first aspect, the present invention provides a battery preparation method, which pretreats the intrinsic amorphous silicon layer by a mixed gas plasma of carbon dioxide and hydrogen to improve the contact effect between the intrinsic amorphous silicon layer and the doping layer, improve the passivation quality, and improve the transmittance, thereby improving the current density and battery conversion efficiency of the back contact battery and ensuring the battery quality.

[0028] The battery preparation method comprises the following steps: S1. Provide double-sided polished silicon wafers; S2. forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer, wherein the first semiconductor layer comprises a first tunneling oxide layer and a first doping layer disposed in sequence; S3. Etching an opening on the first tunneling oxide layer, the first doping layer and the mask layer to form a first opening region; S4. Cleaning and removing the first tunneling oxide layer, the first doping layer and the mask layer remaining in the first opening region, and forming a velvet surface in the first opening region and on the front side of the silicon wafer, and then cleaning and removing the mask layer outside the first opening region; S5. forming a first intrinsic amorphous silicon layer on the back side of the silicon wafer; S6. forming a second intrinsic amorphous silicon layer on the front side of the silicon wafer, pre-treating the second intrinsic amorphous silicon layer with a mixed gas plasma of carbon dioxide and hydrogen, and then forming a second doped layer on the second intrinsic amorphous silicon layer, wherein the second intrinsic amorphous silicon layer and the second doped layer together form a second semiconductor layer; S7. Forming a third doped layer on the first intrinsic amorphous silicon layer, wherein the first intrinsic amorphous silicon layer and the third doped layer together form a third semiconductor layer.

[0029] It should be noted that, in S1, the silicon wafer is preferably an N-type single crystal silicon wafer, and the silicon wafer can be a Czochralski single crystal silicon wafer or a cast single crystal silicon wafer.

[0030] S2 includes three steps: S21. Forming a first tunneling oxide layer on the back side of the silicon wafer by a dry method, wherein the thickness of the first tunneling oxide layer is 1 nm-2 nm.

[0031] S22. Depositing an intrinsic polysilicon layer on the first tunnel oxide layer by low pressure chemical vapor deposition, and then forming a first doped layer by diffusion, wherein the first doped layer is an N-type doped polysilicon layer with a thickness of 100nm-200nm.

[0032] S23. Depositing a mask layer on the first doping layer by plasma enhanced chemical vapor deposition, wherein the mask layer is a silicon nitride layer having a thickness of 60 nm-80 nm.

[0033] In S3, laser etching or mask etching is used to etch openings on the first tunneling oxide layer, the first doping layer and the mask layer on the back side of the silicon wafer to form a first opening area, and the first tunneling oxide layer, the first doping layer and the mask layer in the first opening area are etched away.

[0034] In S4, the first tunneling oxide layer, the first doping layer and the mask layer remaining in the first opening area are removed by texturing and cleaning, and a texturing surface is simultaneously formed in the first opening area and on the front side of the silicon wafer; then, the mask layer outside the first opening area is cleaned and removed.

[0035] In S5, a first intrinsic amorphous silicon layer is deposited on the back side of the silicon wafer by plasma enhanced chemical vapor deposition, wherein the thickness of the first intrinsic amorphous silicon layer is 5 nm-12 nm.

[0036] S6 includes three steps: S61. Depositing a second intrinsic amorphous silicon layer on the front side of the silicon wafer by plasma enhanced chemical vapor deposition, wherein the thickness of the second intrinsic amorphous silicon layer is 4 nm-10 nm.

[0037] S62. A mixed gas plasma of carbon dioxide and hydrogen is introduced to reach a preset pressure, and the pressure is maintained for a preset time to pre-treat the second intrinsic amorphous silicon layer.

[0038] In S62, the second intrinsic amorphous silicon layer is pretreated with a mixed gas plasma of carbon dioxide and hydrogen to improve the contact effect between the second intrinsic amorphous silicon layer and the second doped layer, improve the interface characteristics between the second intrinsic amorphous silicon layer and the second doped layer, reduce interface defects, thereby reducing the recombination of photogenerated carriers, increasing the short-circuit current of the battery, and improving the battery conversion efficiency. Specifically, pretreatment of the second intrinsic amorphous silicon layer with carbon dioxide plasma can transform the intrinsic amorphous silicon part into a nanocrystalline state, and the hydrogen atoms in the mixed gas plasma can spontaneously diffuse into the second intrinsic amorphous silicon layer to prevent the reverse epitaxial growth of nanocrystals in the second intrinsic amorphous layer, which leads to a decrease in passivation quality, and is conducive to the subsequent formation of the second doped layer. With the help of the nanocrystal growth induction process, as the crystallinity increases, the carrier conductivity of the contact interface between the second intrinsic amorphous silicon layer and the second doped layer increases exponentially, effectively improving the current density and battery conversion efficiency of the back contact battery, and ensuring the battery quality.

[0039] Furthermore, in the process of pre-treating the second intrinsic amorphous silicon layer with the mixed gas plasma of carbon dioxide and hydrogen, the mixed gas plasma of carbon dioxide and hydrogen will also affect the first intrinsic amorphous silicon layer on the back side of the silicon wafer, thereby improving the contact effect between the first intrinsic amorphous silicon layer and the third doped layer, increasing the hydrogen content in the first intrinsic amorphous silicon layer, improving the microstructure factor, improving the passivation quality, facilitating the formation of the subsequent third doped layer, and further increasing the current density of the back contact battery and improving the battery conversion efficiency.

[0040] Preferably, the pretreatment conditions are: the preset gas pressure is 100Pa-300Pa, the preset time is 10s-60s, the treatment temperature is 140℃-200℃, the ratio of hydrogen flow rate to carbon dioxide flow rate is 10-50, and a reasonable ratio of hydrogen flow rate to carbon dioxide flow rate can increase the hydrogen content in the second intrinsic amorphous silicon layer, prevent reverse epitaxial growth of nanocrystals in the second intrinsic amorphous layer, help improve the passivation quality, and help the formation of the second doping layer, further improve the current density of the back contact battery, and improve the battery conversion efficiency.

[0041] Preferably, the ratio of the increase in the thickness of the second intrinsic amorphous silicon layer to the increase in the preset time is 0.08-0.1, that is, the longer the preset time is, the thicker the thickness of the second intrinsic amorphous silicon layer is, so as to ensure the pretreatment effect and avoid affecting the passivation effect of the underlying silicon wafer. At the same time, the thickness of the second intrinsic amorphous silicon layer should also be controlled. If the second intrinsic amorphous silicon layer is too thick, it will affect the transmittance and cause the resistance of the second intrinsic amorphous silicon layer to be too large, affecting the battery conversion efficiency. Specifically, taking the preset time as 10s and the thickness of the second intrinsic amorphous silicon layer as 6nm as an example, when the preset time increases by 100%-500%, that is, when the preset time is adjusted to 20s-60s, the corresponding increase in the thickness of the second intrinsic amorphous silicon layer is 10%-40%, that is, the thickness of the second intrinsic amorphous silicon layer is adjusted to 6.6nm-8.4nm.

[0042] S63. Depositing a second doping layer on the second intrinsic amorphous silicon layer by plasma enhanced chemical vapor deposition, wherein the thickness of the second doping layer is 10 nm-20 nm.

[0043] In S63, silane, phosphine, hydrogen and carbon dioxide are introduced and reacted under the condition of turning on the glow to form a second doping layer, wherein the second doping layer is an N-type doped microcrystalline silicon oxide layer, and the phosphorus doping concentration of the second doping layer is 1e18cm -3 -2e20cm -3 , the refractive index of the second doping layer is 2.1-2.8.

[0044] Preferably, the reaction conditions for forming the second doping layer are: reaction temperature of 140°C-200°C, reaction pressure of 100Pa-1000Pa, ratio of hydrogen flow rate to silane flow rate of 100-500, ratio of carbon dioxide flow rate to silane flow rate of 1-4, a reasonable ratio of hydrogen flow rate to silane flow rate can control the dilution ratio of the film layer, which is conducive to forming a thin film with a target crystallization rate, and a reasonable ratio of carbon dioxide flow rate to silane flow rate can control the oxygen doping amount of the film layer, which is conducive to improving the transmittance of the film layer.

[0045] It should be noted that since there is no electrode on the front side of the back-contact battery, the conductivity requirements for the film layer are lower than those for conventional batteries. Therefore, by increasing the oxygen doping ratio in the second doping layer, its optical band gap can be increased, the transmittance of sunlight can be increased, and the light transmittance can be increased, thereby increasing the short-circuit current of the battery and thus improving the battery conversion efficiency.

[0046] In S7, a third doped layer is deposited on the first intrinsic amorphous silicon layer by plasma enhanced chemical vapor deposition, wherein the third doped layer is a P-type doped silicon layer, and the thickness of the third doped layer is 8 nm-15 nm.

[0047] Preferably, after S7, the battery preparation method further includes: S8. forming an anti-reflection layer on the second semiconductor layer; S9. Etching openings on the third semiconductor layer to form second opening regions that are alternately arranged with the first opening regions and spaced apart; S10. forming a conductive film layer on the back side of the silicon wafer; S11. An isolation groove is formed on the conductive film layer so that a portion of the conductive film layer separated from each other extends into the first opening region and covers the third semiconductor layer, and another portion extends into the second opening region and covers the first semiconductor layer; S12. Form a first electrode on the portion of the conductive film layer extending into the first opening region, and form a second electrode on the portion of the conductive film layer extending into the second opening region.

[0048] It should be noted that in S8, the anti-reflection layer is a silicon nitride layer, and the thickness of the anti-reflection layer is 150nm-250nm.

[0049] In S9, laser etching or mask etching is used to etch openings in the third semiconductor layer on the back side of the silicon wafer to form second opening areas that are alternately arranged with the first opening areas and spaced apart, and the third semiconductor layer in the second opening areas is etched away.

[0050] In S10, a conductive film layer is deposited on the back of the silicon wafer using physical vapor deposition technology (PVD) or activated plasma deposition technology (RPD). The thickness of the conductive film layer is 50nm-150nm. The material of the conductive film layer can be an indium oxide film doped with tin oxide, titanium oxide, zinc oxide or gallium oxide, or a zinc oxide film doped with aluminum oxide, gallium oxide or boron oxide.

[0051] In S11, an isolation groove is formed on the conductive film layer by laser or etching. The isolation groove is used to achieve the insulation function between two adjacent parts of the conductive film layer. The isolation groove is located between the first opening area and the second opening area to separate the first semiconductor layer and the third semiconductor layer to avoid short circuit.

[0052] In S12, a first electrode is formed on a portion of the conductive film layer located in a first opening area on the back side of the silicon wafer by using screen printing technology, and a second electrode is formed on a portion of the conductive film layer located in a second opening area on the back side of the silicon wafer.

[0053] In a second aspect, the present invention provides a back-contact battery, which is prepared by the above-mentioned battery preparation method.

[0054] In a third aspect, the present invention provides a photovoltaic module comprising the above-mentioned back contact cell.

[0055] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0056] Example 1 A back contact battery is prepared by the following steps: S1. Figure 1 As shown, the N-type single crystal silicon wafer 1 is double-sided polished and cleaned, and the silicon wafer 1 is a Czochralski single crystal silicon wafer 1.

[0057] S2. Figure 2 As shown, a first semiconductor layer and a mask layer 4 are sequentially formed on the back side of the silicon wafer 1, wherein the first semiconductor layer includes a first tunneling oxide layer 2 and a first doping layer 3 which are sequentially arranged, the thickness of the first tunneling oxide layer 2 is 1.5 nm, the thickness of the first doping layer 3 is 150 nm, and the thickness of the mask layer 4 is 70 nm.

[0058] S3. Figure 3 As shown, laser etching is used to etch openings on the first tunneling oxide layer 2 , the first doping layer 3 and the mask layer 4 to form a first opening region 5 .

[0059] S4. Figure 4 As shown, the first tunneling oxide layer 2, the first doping layer 3 and the mask layer 4 remaining in the first opening area 5 are cleaned and removed, and a velvet surface is simultaneously formed in the first opening area 5 and on the front side of the silicon wafer 1, and then the mask layer 4 outside the first opening area 5 is cleaned and removed.

[0060] S5. Figure 4 As shown, a first intrinsic amorphous silicon layer 6 is formed on the back side of the silicon wafer 1 , wherein the thickness of the first intrinsic amorphous silicon layer 6 is 8 nm.

[0061] S6. Figure 4 and Figure 5 As shown, a second intrinsic amorphous silicon layer 7 is formed on the front side of the silicon wafer 1, and then the second intrinsic amorphous silicon layer 7 is pretreated using a mixed gas plasma of carbon dioxide and hydrogen, and then a second doped layer 8 is formed on the second intrinsic amorphous silicon layer 7, wherein the second intrinsic amorphous silicon layer 7 and the second doped layer 8 together form a second semiconductor layer. Specifically, a second intrinsic amorphous silicon layer 7 is first deposited on the front side of the silicon wafer 1 by plasma enhanced chemical vapor deposition, and the thickness of the second intrinsic amorphous silicon layer 7 is 7nm; then, a mixed gas plasma of carbon dioxide and hydrogen is introduced to reach a preset gas pressure, and the pressure is maintained for a preset time to pre-treat the second intrinsic amorphous silicon layer 7, and the pre-treatment conditions are: the preset gas pressure is 200Pa, the preset time is 35s, the treatment temperature is 170°C, the ratio of hydrogen flow rate to carbon dioxide flow rate is 30, and the ratio of the increase in thickness of the second intrinsic amorphous silicon layer 7 to the increase in preset time is 0.09; then, a second doped layer 8 is deposited on the second intrinsic amorphous silicon layer 7 by plasma enhanced chemical vapor deposition, and the thickness of the second doped layer 8 is 15nm, and the phosphorus doping concentration is 1e20cm -3The refractive index of the second doping layer 8 is 2.4, and the reaction conditions are: the reaction temperature is 170° C., the reaction pressure is 500 Pa, the ratio of hydrogen flow rate to silane flow rate is 300, and the ratio of carbon dioxide flow rate to silane flow rate is 2.

[0062] S7. Figure 5 As shown, a third doped layer 9 is formed on the first intrinsic amorphous silicon layer 6 , wherein the first intrinsic amorphous silicon layer 6 and the third doped layer 9 together form a third semiconductor layer, and the thickness of the third doped layer 9 is 11 nm.

[0063] S8. Figure 5 As shown, an anti-reflection layer 10 is formed on the second semiconductor layer, wherein the thickness of the anti-reflection layer 10 is 200 nm.

[0064] S9. Figure 5 As shown, laser etching is used to etch openings on the third semiconductor layer to form second opening areas 11 that are alternately arranged with the first opening areas 5 and spaced apart, and the third semiconductor layer in the second opening areas 11 is etched away.

[0065] S10. Figure 6 As shown, a conductive film layer 12 is formed on the back of the silicon wafer 1 by physical vapor deposition (PVD) technology, wherein the thickness of the conductive film layer 12 is 100 nm, and the material of the conductive film layer 12 is a tin oxide-doped indium oxide film.

[0066] S11. Figure 6 As shown, an isolation groove 13 is opened on the conductive film layer 12 by laser etching, so that a portion of the conductive film layer 12 separated from each other extends into the first opening area 5 and covers the third semiconductor layer, and another portion extends into the second opening area 11 and covers the first semiconductor layer.

[0067] S12. Figure 7 As shown, a first electrode 14 is formed on a portion of the conductive film layer 12 extending into the first opening area 5 , and a second electrode 15 is formed on a portion of the conductive film layer 12 extending into the second opening area 11 by using screen printing technology.

[0068] Example 2 The method of Example 1 is referred to, except that the pretreatment conditions in S6 are adjusted so that the preset gas pressure is 100 Pa, the preset time is 10 s, the treatment temperature is 140°C, the ratio of hydrogen flow rate to carbon dioxide flow rate is 10, and the ratio of the increase in thickness of the second intrinsic amorphous silicon layer 7 to the increase in preset time is 0.1.

[0069] Example 3 The method of Example 1 is referred to, except that the thickness of the second intrinsic amorphous silicon layer 7 is adjusted to 10 nm.

[0070] Example 4 The method of Example 1 is followed, except that the reaction conditions for forming the second doping layer 8 in S6 are adjusted so that the reaction temperature is 140°C, the reaction pressure is 100 Pa, the ratio of the hydrogen flow rate to the silane flow rate is 100, and the ratio of the carbon dioxide flow rate to the silane flow rate is 1.

[0071] Comparative Example 1 The method of Example 1 is referred to, except that the pre-processing step in S6 (step S62) is eliminated.

[0072] Comparative Example 2 The method of Example 1 is followed, except that the pretreatment conditions in S6 are adjusted so that the preset gas pressure is 50 Pa, the preset time is 5 s, the treatment temperature is 100°C, the ratio of hydrogen flow rate to carbon dioxide flow rate is 5, and the ratio of the increase in thickness of the second intrinsic amorphous silicon layer 7 to the increase in preset time is 0.2.

[0073] Comparative Example 3 The method of Example 1 is referred to, except that the thickness of the second intrinsic amorphous silicon layer 7 is adjusted to 15 nm.

[0074] Comparative Example 4 The method of Example 1 is referred to, except that the reaction conditions for forming the second doping layer 8 in S6 are adjusted so that the reaction temperature is 100°C, the reaction pressure is 50 Pa, the ratio of hydrogen flow to silane flow is 50, and the ratio of carbon dioxide flow to silane flow is 0.5.

[0075] Test Case The back contact cells obtained in the above examples and comparative examples were subjected to performance tests, and the results are shown in the following performance index comparison table.

[0076] Performance index comparison table:

[0077] It can be seen from the above performance index comparison table that, relative to the comparative example, the embodiment scheme of the present invention is adopted to pretreat the intrinsic amorphous silicon layer by a mixed gas plasma of carbon dioxide and hydrogen to improve the contact effect between the intrinsic amorphous silicon layer and the doping layer, improve the passivation quality, and improve the transmittance, thereby improving the current density and battery conversion efficiency of the back contact battery and ensuring the battery quality.

[0078] Furthermore, according to Example 1 and Examples 2-4, it can be seen that the preferred battery structure of the present invention is more conducive to improving contact interface characteristics, reducing interface defects, increasing light transmittance, improving passivation quality, increasing short-circuit current, and improving battery conversion efficiency.

[0079] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, the technical solution of the present invention can be subjected to a variety of simple modifications, including the combination of various technical features in any other suitable manner, and these simple modifications and combinations should also be regarded as the contents disclosed by the present invention and belong to the protection scope of the present invention.

Claims

1. A method for preparing a battery, characterized in that: include: S1. Provide double-sided polished silicon wafers; S2. sequentially forming a first semiconductor layer and a mask layer on the back side of the silicon wafer, wherein the first semiconductor layer comprises a first tunneling oxide layer and a first doping layer sequentially arranged; S3. Etching an opening on the first tunneling oxide layer, the first doping layer and the mask layer to form a first opening region; S4. cleaning and removing the first tunneling oxide layer, the first doping layer and the mask layer remaining in the first opening region, and forming a velvet surface in the first opening region and on the front side of the silicon wafer, and then cleaning and removing the mask layer outside the first opening region; S5. forming a first intrinsic amorphous silicon layer on the back side of the silicon wafer; S6. forming a second intrinsic amorphous silicon layer on the front side of the silicon wafer, pre-treating the second intrinsic amorphous silicon layer with a mixed gas plasma of carbon dioxide and hydrogen, and then forming a second doped layer on the second intrinsic amorphous silicon layer, wherein the second intrinsic amorphous silicon layer and the second doped layer together form a second semiconductor layer; S7. Forming a third doped layer on the first intrinsic amorphous silicon layer, wherein the first intrinsic amorphous silicon layer and the third doped layer together form a third semiconductor layer.

2. The battery preparation method according to claim 1, characterized in that S6 include: S61. Depositing the second intrinsic amorphous silicon layer on the front side of the silicon wafer by plasma enhanced chemical vapor deposition, wherein the thickness of the second intrinsic amorphous silicon layer is 4nm-10nm; S62. A mixed gas plasma of carbon dioxide and hydrogen is introduced to reach a preset pressure, and the pressure is maintained for a preset time to pre-treat the second intrinsic amorphous silicon layer; S63. Depositing a second doping layer on the second intrinsic amorphous silicon layer by plasma enhanced chemical vapor deposition, wherein the thickness of the second doping layer is 10 nm-20 nm.

3. The battery preparation method according to claim 2, characterized in that: The pretreatment conditions are: the preset gas pressure is 100Pa-300Pa, the preset time is 10s-60s, the treatment temperature is 140°C-200°C, and the ratio of hydrogen flow rate to carbon dioxide flow rate is 10-50.

4. The battery preparation method according to claim 2, characterized in that: The ratio of the increase ratio of the thickness of the second intrinsic amorphous silicon layer to the increase ratio of the preset time length is 0.08-0.

1.

5. The battery preparation method according to claim 2, characterized in that: In S63, silane, phosphine, hydrogen and carbon dioxide are introduced and reacted under the condition of turning on the glow to form the second doping layer, and the phosphorus doping concentration of the second doping layer is 1e18cm -3 -2e20cm -3 , the refractive index of the second doping layer is 2.1-2.

8.

6. The battery preparation method according to claim 5, characterized in that: The reaction conditions for forming the second doping layer are: reaction temperature of 140°C-200°C, reaction pressure of 100Pa-1000Pa, ratio of hydrogen flow to silane flow of 100-500, and ratio of carbon dioxide flow to silane flow of 1-4.

7. The method for preparing a battery according to claim 1, characterized in that S2 include: S21. Forming the first tunneling oxide layer on the back side of the silicon wafer by a dry method, wherein the thickness of the first tunneling oxide layer is 1nm-2nm; S22. depositing an intrinsic polysilicon layer on the first tunneling oxide layer by low pressure chemical vapor deposition, and then forming the first doped layer by diffusion, wherein the thickness of the first doped layer is 100nm-200nm; S23. Depositing the mask layer on the first doping layer by plasma enhanced chemical vapor deposition, wherein the thickness of the mask layer is 60nm-80nm.

8. The battery preparation method according to claim 1, characterized in that: In S5, the first intrinsic amorphous silicon layer is deposited on the back side of the silicon wafer by plasma enhanced chemical vapor deposition, wherein the thickness of the first intrinsic amorphous silicon layer is 5 nm-12 nm.

9. The battery preparation method according to claim 1, characterized in that: After S7, the battery preparation method further includes: S8. forming an anti-reflection layer on the second semiconductor layer; S9. Etching openings on the third semiconductor layer to form second opening regions that are alternately and spaced apart from the first opening regions; S10 forming a conductive film layer on the back side of the silicon wafer; S11. An isolation groove is formed on the conductive film layer so that a portion of the conductive film layer separated from each other extends into the first opening area and covers the third semiconductor layer, and another portion extends into the second opening area and covers the first semiconductor layer; S12. Form a first electrode on the portion of the conductive film layer extending into the first opening region, and form a second electrode on the portion of the conductive film layer extending into the second opening region.

10. A back contact battery, characterized in that: The battery is prepared by the battery preparation method according to any one of claims 1 to 9.

11. A photovoltaic module, characterized in that: Comprising a back contact cell as claimed in claim 10.

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