High-voltage integrated circuit with transient suppression
By introducing a level shift circuit and a transient suppression circuit into the high-voltage integrated circuit, the problems of mis-opening of the output on the high-voltage side and poor reliability are solved, and the reliability and competitiveness of the HVIC chip are improved.
Patent Information
- Application Number
- CN202411457210.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2024-12-24
AI Technical Summary
The existing high-voltage integrated circuits are incorrectly turned on when operating, and are kept in a high-level state after latch, which is extremely harmful. If the low-voltage tube is turned on, it will directly lead to direct through, resulting in poor reliability.
A high-voltage integrated circuit with transient suppression is designed, including HVIC driving circuit, pulse circuit, level shift circuit and transient suppression circuit. By adding a transient suppression circuit after the level shift circuit, it prevents the parasitic capacitance caused by parasitic capacitance. Transient noise influence ensures that current is generated on both sides of ON_PLUSE/SET and OFF_PLUSE/RESET.
Effectively prevent the high-voltage side output from being turned on, improve the reliability and market competitiveness of the HVIC chip, and avoid the problems of missing opening and direct access caused by transient noise.
Smart Images
Figure CN119182282A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of high-voltage integrated circuits, and in particular to a high-voltage integrated circuit with transient suppression. Background Art
[0002] High voltage integrated circuit, or HVIC, is an integrated circuit product that converts MCU signals into driving IGBT or MOS signals. HVIC integrates PMOS tubes, NMOS tubes, triodes, diodes, voltage regulator tubes, resistors, and capacitors to form Schmitt, low voltage level, high voltage level, pulse generation circuit, delay circuit, filter circuit, overcurrent protection circuit, overheat protection circuit, undervoltage protection circuit, bootstrap circuit and other circuits. The single pulse GEN circuit in the high-side drive circuit of the existing HVIC generates pulses at the rising and falling edges of the HIN signal to drive DMOS. The pulse width is generally several hundred nanoseconds, so that HIN corresponds to HO.
[0003] In the existing HVIC, transient dVs / dt noise will affect the normal working process of the low-voltage to high-voltage conversion inside the power device driver chip (HVIC), causing failure states such as latch-on and latch-off on the high-voltage side. When the OFF_PLUSE / RESET and ON_PLUSE / SET of the pulse circuit generate low levels respectively, VOUT generates logic 0 and logic 1 signals respectively; and when VS suddenly changes, due to the existence of parasitic capacitance, I = C*dvs / dt, so that current is generated on both sides of ON_PLUSE / SET and OFF_PLUSE / RESET at the same time, resulting in low levels on both sides at the same time; this state directly causes the high-voltage side output to be turned on by mistake, and remains at a high level after latching, which is extremely harmful. If the low-voltage side tube is turned on, it will directly lead to direct conduction.
[0004] Therefore, the working state of the above-mentioned high-voltage integrated circuit directly causes the high-voltage side output to be mistakenly turned on, and it remains in a high-level state after being latched, which is extremely harmful. If the low-voltage side tube is turned on, it will directly lead to direct conduction, thereby making the overall high-voltage integrated circuit reliability poor. Summary of the invention
[0005] The present invention provides a high-voltage integrated circuit with transient suppression, aiming to solve the problem that the existing high-voltage integrated circuit directly causes the high-voltage side output to be mistakenly turned on during operation, and remains in a high-level state after being latched, which is extremely harmful. If the low-voltage side tube is turned on, it will directly lead to direct conduction, thereby causing poor reliability.
[0006] An embodiment of the present invention provides a high-voltage integrated circuit with transient suppression, comprising: an HVIC driving circuit, a pulse circuit, a level shifting circuit, a transient suppression circuit and an RS trigger electrically connected in sequence; the input end of the HVIC driving circuit is used to connect to a power supply, and the output end of the RS trigger is used to output a driving signal;
[0007] The transient suppression circuit includes a first transient suppression circuit and a second transient suppression circuit. The pulse circuit is used to output a first pulse signal and a second pulse signal to the level shift circuit through a rising edge pulse and a falling edge pulse respectively. The first pulse signal is output to the input end of the first transient suppression circuit and the input end of the second transient suppression circuit respectively through the level shift circuit. The output end of the first transient suppression circuit is connected to the R end of the RS trigger, and the output end of the second transient suppression circuit is connected to the S end of the RS trigger.
[0008] Preferably, the level shift circuit comprises a first resistor, a first transistor, a second resistor and a second transistor;
[0009] The gate of the first transistor is used as the first input terminal of the level shift circuit to connect the rising edge pulse, the gate of the second transistor is used as the second input terminal of the level shift circuit to connect the falling edge pulse, the source of the first transistor is connected to the source of the second transistor and is grounded together; the drain of the first transistor is connected to the first end of the first resistor, the drain of the second transistor is connected to the first end of the second resistor, and the second end of the first resistor is connected to the second end of the second resistor; the drain of the first transistor is also connected to the input end of the first transient suppression circuit as the first output end of the level shift circuit, and the drain of the second transistor is also connected to the input end of the first transient suppression circuit as the second output end of the level shift circuit.
[0010] Preferably, both the first transistor and the second transistor are LDMOS transistors.
[0011] Preferably, the first transient suppression circuit includes: a transistor PM1, a transistor NM1, a transistor PM2, a transistor NM2, a transistor PM3, a transistor NM3, a transistor PM4, a transistor NM4, a transistor PM5, a transistor NM5, a transistor PM6, a transistor NM6, a third resistor, and a first capacitor;
[0012] The gate of the transistor PM1 and the gate of the transistor NM1 are connected and serve together as the input end of the first transient suppression circuit; the source of the transistor PM1 is respectively connected to the first end of the first resistor, the source of the transistor PM2, the source of the transistor PM3, the drain of the transistor NM5 and the source of the transistor PM6; the drain of the transistor PM1 is respectively connected to the drain of the transistor NM1, the gate of the transistor PM2 and the gate of the transistor NM2, and the drain of the transistor PM2 is respectively connected to the first end of the third resistor, the first end of the first capacitor, the gate of the transistor PM3, the gate of the transistor PM4, the gate of the transistor NM3 and the gate of the transistor NM4;
[0013] The drain of the transistor NM2 is connected to the second end of the third resistor, and the source of the transistor NM1 is respectively connected to the source of the transistor NM2, the second end of the first capacitor, the source of the transistor NM4, the drain of the transistor PM5 and the source of the transistor NM6;
[0014] The drain of the transistor PM3 is respectively connected to the source of the transistor PM4 and the source of the transistor PM5; the drain of the transistor PM4 is respectively connected to the drain of the transistor NM3, the gate of the transistor PM5, the gate of the transistor NM5, the gate of the transistor PM6 and the gate of the transistor NM6; the source of the transistor NM3 is respectively connected to the drain of the transistor NM4 and the source of the transistor NM5;
[0015] The drain of the transistor PM6 is connected to the drain of the transistor NM6 and serves as the output terminal of the first transient suppression circuit.
[0016] Preferably, the second transient suppression circuit includes: a transistor PM7, a transistor NM7, a transistor PM8, a transistor NM8, a transistor PM9, a transistor NM11, a transistor PM10, a transistor NM12, a transistor PM11, a transistor NM13, a transistor PM12, a transistor NM14, a fourth resistor, and a second capacitor;
[0017] The gate of the transistor PM7 and the gate of the transistor NM7 are connected and serve together as the input end of the second transient suppression circuit; the source of the transistor PM7 is respectively connected to the first end of the second resistor, the source of the transistor PM8, the source of the transistor PM9, the drain of the transistor NM13 and the source of the transistor PM12; the drain of the transistor PM7 is respectively connected to the drain of the transistor NM7, the gate of the transistor PM8 and the gate of the transistor NM8, and the drain of the transistor PM8 is respectively connected to the first end of the fourth resistor, the first end of the second capacitor, the gate of the transistor PM9, the gate of the transistor PM10, the gate of the transistor NM11 and the gate of the transistor NM12;
[0018] The drain of the transistor NM8 is connected to the second end of the fourth resistor, and the source of the transistor NM7 is respectively connected to the source of the transistor NM8, the second end of the second capacitor, the source of the transistor NM12, the drain of the transistor PM11 and the source of the transistor NM14;
[0019] The drain of the transistor PM9 is respectively connected to the source of the transistor PM10 and the source of the transistor PM11; the drain of the transistor PM10 is respectively connected to the drain of the transistor NM11, the gate of the transistor PM11, the gate of the transistor NM13, the gate of the transistor PM12 and the gate of the transistor NM14; the source of the transistor NM11 is respectively connected to the drain of the transistor NM12 and the source of the transistor NM13;
[0020] The drain of the transistor PM12 is connected to the drain of the transistor NM14 and serves as an output terminal of the second transient suppression circuit.
[0021] Compared with the prior art, the invention has the beneficial effect that, by sequentially electrically connecting the HVIC driving circuit, the pulse circuit, the level shift circuit, the transient suppression circuit and the RS trigger; the input end of the HVIC driving circuit is used to connect the power supply, and the output end of the RS trigger is used to output the driving signal; the pulse circuit is used to output the first pulse signal and the second pulse signal to the level shift circuit through the rising edge pulse and the falling edge pulse respectively, and the first pulse signal is output to the input end of the first transient suppression circuit and the input end of the second transient suppression circuit respectively through the level shift circuit, the output end of the first transient suppression circuit is connected to the R end of the RS trigger, and the output end of the second transient suppression circuit is connected to the S end of the RS trigger. In this way, by adding a corresponding transient suppression (pulse filtering) circuit after the high-voltage level shift circuit, it is prevented that when VS suddenly changes, due to the existence of parasitic capacitance, I=C*dvs / dt, the current is generated on both sides of ON_PLUSE / SET and OFF_PLUSE / RESET at the same time, resulting in a low level on both sides at the same time; so as to improve the reliability of the HVIC chip and its market competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The present invention will be described in detail below in conjunction with the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made in conjunction with the following drawings. In the accompanying drawings:
[0023] Figure 1 is a circuit diagram of a high-voltage integrated circuit with transient suppression provided by an embodiment of the present invention;
[0024] Figure 2 is a circuit diagram of a transient suppression circuit provided by an embodiment of the present invention;
[0025] Figure 3 yes Figure 2 A partial enlarged view of
[0026] Figure 4 It is a waveform diagram of the transient suppression circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0027] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.
[0028] Combined with Figure 1-Figure 4As shown, an embodiment of the present invention provides a high-voltage integrated circuit with transient suppression, comprising: an HVIC driving circuit 100, a pulse circuit 0107, a level shift circuit 2, a transient suppression circuit 3 and an RS trigger 0115 electrically connected in sequence; the input end of the HVIC driving circuit 100 is used to connect to a power supply VCC, and the output end of the RS trigger 0115 is used to output a driving signal. By outputting the driving signal to the output circuit 0116, it is convenient to drive an external device.
[0029] The transient suppression circuit 3 includes a first transient suppression circuit 31 and a second transient suppression circuit 32. The pulse circuit 0107 is used to output a first pulse signal and a second pulse signal to the level shift circuit 2 through a rising edge pulse (SET / G1) and a falling edge pulse (SET / G1), respectively. The first pulse signal is output to the input end of the first transient suppression circuit 31 and the input end of the second transient suppression circuit 32 through the level shift circuit 2. The output end of the first transient suppression circuit 31 is connected to the R end of the RS trigger 0115, and the output end of the second transient suppression circuit 32 is connected to the S end of the RS trigger 0115. By adding a corresponding transient suppression (pulse filtering) circuit after the level shift circuit 2, it is prevented that when VS suddenly changes, due to the existence of parasitic capacitance, I=C*dvs / dt, current is generated on both sides of ON_PLUSE / SET and OFF_PLUSE / RESET at the same time, resulting in low levels on both sides at the same time; so as to improve the reliability and market competitiveness of the HVIC chip.
[0030] In this embodiment, HIN and LIN input drive signals, through the circuit in the HVIC drive circuit, sequentially pass through the RC filter 0102, the Schmitt circuit 0103, the filter 0104, the level conversion circuit 0105, the dead zone interlock circuit 0106 and output HINa pulse signal, the pulse circuit GEN 0107 outputs ON_PLUSE / SET and OFF_PLUSE / RESET short pulse signals respectively through the rising edge and falling edge of the HINa pulse signal to drive UVWQ1 and UVWQ2 high-voltage LDMOS, the high-voltage LDMOS conduction and shutdown trigger RS trigger 0115005 to output pulse signals, control HO to output drive pulse signals; output LINa pulse signals, through the RC delay circuit 0108 and the AND gate 0117, control LO to output drive pulse signals. The output of the drive signals HO and LO are protected by the undervoltage protection circuit 0110, the temperature protection circuit 0111, the current protection ITRIP circuit 0112, and the fault logic circuit 0113. The bootstrap circuit 0109 provides bootstrap voltage to HO. The fault output circuit 0114 outputs a fault signal.
[0031] In this embodiment, the level shift circuit 2 includes a first resistor R1, a first transistor Q1, a second resistor R2 and a second transistor Q2; the gate of the first transistor Q1 is used as a first input end of the level shift circuit 2 to connect the rising edge pulse, the gate of the second transistor Q2 is used as a second input end of the level shift circuit 2 to connect the falling edge pulse, the source of the first transistor Q1 is connected to the source of the second transistor Q2 and is grounded together; the drain of the first transistor Q1 is connected to the first end of the first resistor R1, the drain of the second transistor Q2 is connected to the first end of the second resistor R2, and the second end of the first resistor R1 is connected to the second end of the second resistor R2; the drain of the first transistor Q1 is also connected to the input end of the first transient suppression circuit 31 as the first output end of the level shift circuit 2, and the drain of the second transistor Q2 is also connected to the input end of the first transient suppression circuit 31 as the second output end of the level shift circuit 2.
[0032] In this embodiment, both the first transistor Q1 and the second transistor Q2 are LDMOS transistors.
[0033] Specifically, when the above dVs / dt noise is coupled to the VCCA port through the capacitor, its influence on the level shift circuit 2 is as follows: Figure 2 As shown, if the voltage at the VCCA end rises, a voltage-resistant device must be required between VCCA and ground, and LDMOS undertakes all the voltage-resistant tasks. Therefore, as the VCCA voltage rises, the voltage at the drain end of LDMOS will inevitably rise. During this process, a displacement current will flow through the load resistors R1 and R2 to charge the drain-source capacitance of LDMOS. The dVs / dt noise intensity at the VCCA end determines the size of the displacement currents I1 and I2, as shown in the formula:
[0034] I1=I2=C DS *dvcc / dt;
[0035] Among them C DS is the drain-source capacitance of LDMOS.
[0036] Parasitic C DS The size of the capacitor is greatly affected by the process. When the C of Q1 and Q2 of the high-voltage level shift circuit 2 is DS When the capacitance varies greatly due to process deviation, I1 will not be equal to I2, which will affect the voltage drop across R1 and R2.
[0037] V R1 =I1*R1=C DS Q1 *d VCCA / dt*R1;
[0038] V R2 =I2*R2=C DS Q2 *d VCCA / dt*R2;
[0039] The size of VR1 and VR2 will directly affect the operation of the subsequent RS flip-flop 0115. When VR1 and VR2 are lower than the response threshold of the subsequent RS flip-flop 0115, the output of the entire chip will be affected.
[0040] In this embodiment, the first transient suppression circuit 31 includes: a transistor PM1, a transistor NM1, a transistor PM2, a transistor NM2, a transistor PM3, a transistor NM3, a transistor PM4, a transistor NM4, a transistor PM5, a transistor NM5, a transistor PM6, a transistor NM6, a third resistor R3, and a first capacitor C1;
[0041] The gate of the transistor PM1 and the gate of the transistor NM1 are connected and serve together as the input end of the first transient suppression circuit 31; the source of the transistor PM1 is respectively connected to the first end of the first resistor R1, the source of the transistor PM2, the source of the transistor PM3, the drain of the transistor NM5 and the source of the transistor PM6; the drain of the transistor PM1 is respectively connected to the drain of the transistor NM1, the gate of the transistor PM2 and the gate of the transistor NM2, and the drain of the transistor PM2 is respectively connected to the first end of the third resistor R3, the first end of the first capacitor C1, the gate of the transistor PM3, the gate of the transistor PM4, the gate of the transistor NM3 and the gate of the transistor NM4;
[0042] The drain of the transistor NM2 is connected to the second end of the third resistor R3, and the source of the transistor NM1 is respectively connected to the source of the transistor NM2, the second end of the first capacitor C1, the source of the transistor NM4, the drain of the transistor PM5 and the source of the transistor NM6;
[0043] The drain of the transistor PM3 is respectively connected to the source of the transistor PM4 and the source of the transistor PM5; the drain of the transistor PM4 is respectively connected to the drain of the transistor NM3, the gate of the transistor PM5, the gate of the transistor NM5, the gate of the transistor PM6 and the gate of the transistor NM6; the source of the transistor NM3 is respectively connected to the drain of the transistor NM4 and the source of the transistor NM5;
[0044] The drain of the transistor PM6 is connected to the drain of the transistor NM6 and serves as the output terminal of the first transient suppression circuit 31 .
[0045] In this embodiment, the second transient suppression circuit 32 includes: a transistor PM7, a transistor NM7, a transistor PM8, a transistor NM8, a transistor PM9, a transistor NM11, a transistor PM10, a transistor NM12, a transistor PM11, a transistor NM13, a transistor PM12, a transistor NM14, a fourth resistor R4, and a second capacitor C2;
[0046] The gate of the transistor PM7 and the gate of the transistor NM7 are connected and serve together as the input end of the second transient suppression circuit 32; the source of the transistor PM7 is respectively connected to the first end of the second resistor R2, the source of the transistor PM8, the source of the transistor PM9, the drain of the transistor NM13 and the source of the transistor PM12; the drain of the transistor PM7 is respectively connected to the drain of the transistor NM7, the gate of the transistor PM8 and the gate of the transistor NM8, and the drain of the transistor PM8 is respectively connected to the first end of the fourth resistor R4, the first end of the second capacitor C2, the gate of the transistor PM9, the gate of the transistor PM10, the gate of the transistor NM11 and the gate of the transistor NM12;
[0047] The drain of the transistor NM8 is connected to the second end of the fourth resistor R4, and the source of the transistor NM7 is respectively connected to the source of the transistor NM8, the second end of the second capacitor C2, the source of the transistor NM12, the drain of the transistor PM11 and the source of the transistor NM14;
[0048] The drain of the transistor PM9 is respectively connected to the source of the transistor PM10 and the source of the transistor PM11; the drain of the transistor PM10 is respectively connected to the drain of the transistor NM11, the gate of the transistor PM11, the gate of the transistor NM13, the gate of the transistor PM12 and the gate of the transistor NM14; the source of the transistor NM11 is respectively connected to the drain of the transistor NM12 and the source of the transistor NM13;
[0049] The drain of the transistor PM12 is connected to the drain of the transistor NM14 and serves as an output terminal of the second transient suppression circuit 32 .
[0050] In this embodiment, the instantaneous dv / dt noise suppression circuit is mainly composed of MOS, resistors, capacitors, and RC parameter selection circuits. The pulse circuit outputs a narrow pulse SET connected to the G pole of the LDMOS tube Q1, and a narrow pulse RESET connected to the G pole of the LDMOS tube Q2.
[0051] The S poles of LDMOS tubes Q1 and Q2 are grounded;
[0052] The D terminal of the LDMOS tube Q1, one end of the resistor R1, the G terminal of PM1 and the G terminal of NM1 are connected together;
[0053] The D terminal of the LDMOS tube Q2, one end of the resistor R2, the G terminal of PM7 and the G terminal of NM7 are connected together;
[0054] The other end of the resistor R1, the other end of the resistor R2, the D pole of PM1, the D pole of PM2, the D pole of PM3, the D pole of PM6, the D pole of PM7, the D pole of PM8, the D pole of PM9, the D pole of PM12, the D pole of NM5, and the D pole of NM6 are connected together and connected to VCCA;
[0055] The S pole of NM1, the S pole of NM2, one end of capacitor C1, the S pole of NM4, the S pole of PM5, the S pole of NM6, the S pole of NM7, the S pole of NM8, one end of capacitor C2, the S pole of NM12, the S pole of PM11, and the S pole of NM14 are connected together and connected to VS;
[0056] The S pole of PM1, the D pole of NM1, the G pole of PM2 and the G pole of NM2 are connected together;
[0057] The S pole of PM2, one end of the resistor R3, the G pole of PM3, the G pole of PM3, the G pole of NM3 and the G pole of NM4 are connected together;
[0058] The D pole of NM2 is connected to the other end of the resistor R3;
[0059] The S pole of PM3, the D pole of PM4 and the S pole of PM5 are connected together;
[0060] The S pole of PM4, the D pole of NM3, the G pole of PM5, the G pole of PM6, the G pole of NM5 and the G pole of NM6 are connected together;
[0061] The S pole of PM6, the D pole of PM6 and the R input terminal of RS flip-flop 0115 are connected together;
[0062] The S pole of PM7, the D pole of NM7, the G pole of PM8 and the G pole of NM8 are connected together;
[0063] The S pole of PM8, one end of the resistor R4, the G pole of PM9, the G pole of PM10, the G pole of NM11 and the G pole of NM12 are connected together;
[0064] The D pole of NM8 is connected to the other end of the resistor R4;
[0065] The S pole of PM9, the D pole of PM10 and the S pole of PM11 are connected together;
[0066] The S pole of PM10, the D pole of NM11, the G pole of PM11, the G pole of PM12, the G pole of NM13, and the G pole of NM14 are connected together;
[0067] The S pole of PM12, the D pole of PM14 are connected to the R input terminal of the RS flip - flop 0115R;
[0068] When the falling - edge pulse of the SET narrow pulse output by the pulse circuit appears, Figure 3 The transient - response expression of the voltage at point A is as follows:
[0069] V A (t)=V A (0)e -t / + = V A (∞)*(1 - e -t / ) ;
[0070] During charging, its expression can be rewritten as:
[0071] V A (t)=(VCCA - VS)*(1 - e -t / Req(pmos).C ) ;
[0072] Where Req(PMOS) is the equivalent on - resistance of PMOS PM2.
[0073] During discharging, its expression is as follows:
[0074] V A (t)=(VCCA - VS)*e -t / ((Req(NMOS)+R).C) ;
[0075] Where Req(NMOS) represents the equivalent on - resistance of NMOS NMN. It is assumed that Req(PMOS)<<R and Req(NMOS)<<R. Therefore, the falling time of VA is much greater than the rising time of VA, so that the time t for VA to drop to the reverse threshold voltage VL of the Schmitt trigger becomes longer. This time t corresponds to the effective filtering time length (instantaneous noise width) of the pulse - filtering circuit as follows:
[0076] t=(R eq(NMOS) +R)*C*ln((VCCA - VS) / V L )≈R*C*ln((VCCA - VS) / V L ) ;
[0077] At the same time, this filtering - time width t also corresponds to the delay generated by the pulse - filtering circuit, as Figure 4 shown. Where t1 to t2 correspond to the time length of the noise signal, and t3 to t6 correspond to the time length of the valid signal (detecting the rising - edge / falling - edge pulse signal). Figure 4 In the figure, the waveforms of A, B and OUT correspond to the signals in two cases respectively. The dotted lines represent the signal waveforms of each point when the RC filter width is small, and the solid lines represent the signal waveforms of each point when the filter width is large. The following first analyzes the waveforms of the noise signal area. For the case of a small filter width ( Figure 4 EST represents the input of the RC filter circuit. A noise signal is generated in the noise area. Due to the small filter width, the voltage at point A will still drop below the Schmitt reverse threshold VL. Therefore, the output of the Schmitt trigger 0115 at point B will generate a positive pulse signal. Finally, after being shaped by the inverter, it is output to the input of the RS trigger 0115, which affects the entire chip. For the case where the filter width is large ( Figure 4 The solid line waveform in the figure shows that during the time t1 to t2 when the noise signal exists, the voltage at point A cannot drop below the reverse threshold VL of the Schmitt trigger 0115. Therefore, the Schmitt trigger 0115 does not flip, and the OUT point does not output a noise waveform, and the noise signal is filtered out. The effective signal area corresponds to the time period t3 to t6, and the pulse filter circuit will introduce additional delay. For the case where the filter width is small ( Figure 4 The waveform at point A drops rapidly, and the signal delay time is between t3 and t4. However, for the case where the filter width is larger ( Figure 4 The waveform at point A decreases very slowly, and the corresponding delay time is from t3 to t5.
[0078] In summary, the larger the filter width of the noise signal, the easier it is to filter out the noise signal. The minimum filter width of the transient noise suppression circuit (pulse filter circuit) must meet the following two conditions: First, the filter width must be smaller than the width of the effective signal during normal operation to ensure that the effective signal will not be filtered out and can trigger the subsequent RS trigger 0115. Second, the filter width must be larger than the maximum width of the noise signal to ensure that the noise signal is completely filtered out.
[0079] The beneficial effects of the present invention are as follows:
[0080] Add a corresponding transient dV / dt suppression (pulse filtering) circuit after the level shift circuit 2 to prevent the current from being generated on both sides of ON_PLUSE / SET and OFF_PLUSE / RESET at the same time due to the existence of parasitic capacitance, I=C*dvs / dt, when VS suddenly changes. This will cause the high-voltage side output to be turned on by mistake, and it will remain at a high level after being latched, which is extremely harmful. If the low-voltage side tube is turned on, it will directly cause the problem of direct conduction. This will improve the reliability of the HVIC chip and its market competitiveness.
[0081] In this way, the transient noise suppression circuit is designed using CADENCE's VIRTUOSO for layout design and MMSIM for DRC and LVS error checking; the transient noise suppression circuit is integrated into the HVIC, and the circuit function simulation of the HVIC complete circuit and MMSIM are used to perform DRC and LVS error checking; the transient noise suppression circuit layout is integrated into the HVIC layout, and the layout circuit connections are connected according to the circuit schematic diagram.
[0082] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, article or device. In the absence of more restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, article or device including the element.
[0083] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.
Claims
1. A high voltage integrated circuit with transient suppression, characterized in that: include: An HVIC driving circuit, a pulse circuit, a level shift circuit, a transient suppression circuit and an RS trigger electrically connected in sequence; the input end of the HVIC driving circuit is used to connect to a power supply, and the output end of the RS trigger is used to output a driving signal; The transient suppression circuit includes a first transient suppression circuit and a second transient suppression circuit. The pulse circuit is used to output a first pulse signal and a second pulse signal to the level shift circuit through a rising edge pulse and a falling edge pulse respectively. The first pulse signal is output to the input end of the first transient suppression circuit and the input end of the second transient suppression circuit respectively through the level shift circuit. The output end of the first transient suppression circuit is connected to the R end of the RS trigger, and the output end of the second transient suppression circuit is connected to the S end of the RS trigger.
2. The high voltage integrated circuit with transient suppression according to claim 1, characterized in that: The level shift circuit includes a first resistor, a first transistor, a second resistor and a second transistor; The gate of the first transistor is used as the first input terminal of the level shift circuit to connect the rising edge pulse, the gate of the second transistor is used as the second input terminal of the level shift circuit to connect the falling edge pulse, the source of the first transistor is connected to the source of the second transistor and is grounded together; the drain of the first transistor is connected to the first end of the first resistor, the drain of the second transistor is connected to the first end of the second resistor, and the second end of the first resistor is connected to the second end of the second resistor; the drain of the first transistor is also connected to the input end of the first transient suppression circuit as the first output end of the level shift circuit, and the drain of the second transistor is also connected to the input end of the first transient suppression circuit as the second output end of the level shift circuit.
3. The high voltage integrated circuit with transient suppression as claimed in claim 2, characterized in that: The first transistor and the second transistor are both LDMOS transistors.
4. The high voltage integrated circuit with transient suppression as claimed in claim 2, characterized in that: The first transient suppression circuit includes: a transistor PM1, a transistor NM1, a transistor PM2, a transistor NM2, a transistor PM3, a transistor NM3, a transistor PM4, a transistor NM4, a transistor PM5, a transistor NM5, a transistor PM6, a transistor NM6, a third resistor, and a first capacitor; The gate of the transistor PM1 and the gate of the transistor NM1 are connected and serve together as the input end of the first transient suppression circuit; the source of the transistor PM1 is respectively connected to the first end of the first resistor, the source of the transistor PM2, the source of the transistor PM3, the drain of the transistor NM5 and the source of the transistor PM6; the drain of the transistor PM1 is respectively connected to the drain of the transistor NM1, the gate of the transistor PM2 and the gate of the transistor NM2, and the drain of the transistor PM2 is respectively connected to the first end of the third resistor, the first end of the first capacitor, the gate of the transistor PM3, the gate of the transistor PM4, the gate of the transistor NM3 and the gate of the transistor NM4; The drain of the transistor NM2 is connected to the second end of the third resistor, and the source of the transistor NM1 is respectively connected to the source of the transistor NM2, the second end of the first capacitor, the source of the transistor NM4, the drain of the transistor PM5 and the source of the transistor NM6; The drain of the transistor PM3 is respectively connected to the source of the transistor PM4 and the source of the transistor PM5; the drain of the transistor PM4 is respectively connected to the drain of the transistor NM3, the gate of the transistor PM5, the gate of the transistor NM5, the gate of the transistor PM6 and the gate of the transistor NM6; the source of the transistor NM3 is respectively connected to the drain of the transistor NM4 and the source of the transistor NM5; The drain of the transistor PM6 is connected to the drain of the transistor NM6 and serves as the output terminal of the first transient suppression circuit.
5. The high voltage integrated circuit with transient suppression as claimed in claim 2, characterized in that: The second transient suppression circuit includes: a transistor PM7, a transistor NM7, a transistor PM8, a transistor NM8, a transistor PM9, a transistor NM11, a transistor PM10, a transistor NM12, a transistor PM11, a transistor NM13, a transistor PM12, a transistor NM14, a fourth resistor, and a second capacitor; The gate of the transistor PM7 and the gate of the transistor NM7 are connected and serve together as the input end of the second transient suppression circuit; the source of the transistor PM7 is respectively connected to the first end of the second resistor, the source of the transistor PM8, the source of the transistor PM9, the drain of the transistor NM13 and the source of the transistor PM12; the drain of the transistor PM7 is respectively connected to the drain of the transistor NM7, the gate of the transistor PM8 and the gate of the transistor NM8, and the drain of the transistor PM8 is respectively connected to the first end of the fourth resistor, the first end of the second capacitor, the gate of the transistor PM9, the gate of the transistor PM10, the gate of the transistor NM11 and the gate of the transistor NM12; The drain of the transistor NM8 is connected to the second end of the fourth resistor, and the source of the transistor NM7 is respectively connected to the source of the transistor NM8, the second end of the second capacitor, the source of the transistor NM12, the drain of the transistor PM11 and the source of the transistor NM14; The drain of the transistor PM9 is respectively connected to the source of the transistor PM10 and the source of the transistor PM11; the drain of the transistor PM10 is respectively connected to the drain of the transistor NM11, the gate of the transistor PM11, the gate of the transistor NM13, the gate of the transistor PM12 and the gate of the transistor NM14; the source of the transistor NM11 is respectively connected to the drain of the transistor NM12 and the source of the transistor NM13; The drain of the transistor PM12 is connected to the drain of the transistor NM14 and serves as an output terminal of the second transient suppression circuit.