Space-based 6G signal processing system

Abstract

The invention relates to the technical field of signal processing. The invention specifically relates to a space-based 6G signal processing system. Comprising an upper computer and a lower computer, wherein the lower computer comprises a 10-gigabit network card, a gigabit network card, a data processing circuit, a satellite down converter and a power supply circuit for supplying power to the lower computer; the satellite down converter is used for converting the high-frequency satellite signal into a low and medium-frequency satellite signal; the data processing circuit is connected with the down converter and used for demodulating low and medium frequency satellite signals so as to extract original information, and the lower computer is connected with the upper computer through the 10-gigabit network card and used for sending the original information to the upper computer through the 10-gigabit network card. The gigabit network card is connected with the upper computer so as to receive a control instruction issued by the upper computer; and the upper computer is also used for displaying and storing the received original information. By adopting the space-based 6G signal processing system provided by the invention, rapid processing of data transmitted by a 6G network can be realized.

Description

Technical Field

[0001] The present invention generally relates to the field of signal processing technology. More specifically, the present invention relates to a space-based 6G signal processing system. Background Art

[0002] 6G, the sixth generation of mobile communication standards, is also known as the sixth generation of mobile communication technology. The 6G space-ground integrated network refers to the use of satellite communication networks as an important supplement and extension of ground communication networks. By deeply integrating air-based, space-based and ground-based network resources, a global, ubiquitous, high-speed, intelligent, safe and reliable communication network is built. Compared with the 5G network, the data transmission rate of the 6G network can reach fifty times that of the 5G network, and the latency is shortened to one tenth of that of the 5G network; it is far superior to the 5G network in terms of peak rate, latency, traffic density, connection density, mobility, spectrum efficiency, and positioning capabilities. With the development of science and technology, the application of 6G networks in some high-end technology fields will become more and more common. For example, 6G networks can be used in the fields of Internet of Things, big data, smart car networking, artificial intelligence, virtual reality, etc.

[0003] Since the data generation and transmission speeds under 6G networks are very fast, the analysis and processing efficiency of data are also required to be high. There is an urgent need to develop a special device specifically for processing 6G network data to process large amounts of dynamic data streams in real time. Summary of the invention

[0004] In order to solve the technical problems of increased energy consumption and deteriorated working performance of 6G network intelligent terminals during use, the present invention provides solutions in the following aspects.

[0005] In a first aspect, the present invention provides a space-based 6G signal processing system, comprising: an upper computer and a lower computer, the lower computer comprising a 10 Gigabit network card, a 1 Gigabit network card, a data processing circuit, a satellite downconverter and a power supply circuit for powering the lower computer; the satellite downconverter is used to convert high-frequency satellite signals into medium and low-frequency satellite signals; the data processing circuit is connected to the downconverter, and is used to demodulate the medium and low-frequency satellite signals to extract original information; the lower computer is connected to the upper computer through the 10 Gigabit network card, and is used to send the original information to the upper computer through the 10 Gigabit network card, and is connected to the upper computer through the 1 Gigabit network card to receive control instructions issued by the upper computer; the upper computer is also used to display and store the received original information.

[0006] The data processing circuit can adopt FPGA chip or single chip microcomputer.

[0007] In one embodiment, a 10 Gigabit network switch is further included, and the 10 Gigabit network switch is respectively connected to the 10 Gigabit network card, the 1 Gigabit network card and the data processing circuit.

[0008] In one embodiment, the data processing circuit performs modulation and demodulation on the satellite signal by binary phase shift keying, quadrature phase shift keying or orthogonal frequency division multiplexing.

[0009] In one embodiment, the lower computer also includes a serial port board connected to the data processing circuit, the serial port board includes an RS422 sending circuit, an RS422 receiving circuit, an RS485 transceiver circuit, an FPGA chip and a power management circuit for powering the serial port board, the input end of the power management circuit is connected to a protection circuit, and the protection circuit is used to perform overcurrent protection, overvoltage protection and undervoltage protection on the serial port board; the input end of the RS422 sending circuit, the output end of the RS422 receiving circuit and one end of the RS485 transceiver circuit are respectively connected to the data processing circuit through an isolation circuit, and the output end of the RS422 sending circuit, the input end of the RS422 receiving circuit and the other end of the RS485 transceiver circuit are respectively connected to a connector.

[0010] In one embodiment, the RS485 transceiver circuit includes an RS485 transceiver, a receiver output end of the RS485 transceiver is connected in series with a thirteenth resistor, a receiver output enable end and a driver output enable end are connected to each other and then connected in series with a fourteenth resistor, a driver input end is connected in series with a fifteenth resistor, a power supply end is connected to a power supply voltage and is grounded through a first capacitor, a sixteenth resistor is connected in series between the in-phase driver output end and the inverting driver output end, a bidirectional TVS transient suppression diode is connected in parallel at both ends of the sixteenth resistor, one end of the sixteenth resistor is connected to the power supply voltage through a pull-up resistor, and the other end is grounded through a grounding resistor.

[0011] In one embodiment, the host computer includes a network communication module, a communication parameter configuration module, a configuration file module, a communication protocol processing module, a protocol framing module, a protocol deframing module, a human-machine interface and an interface management module; wherein the human-machine interface is used to display the data transmission rate between the host computer and the slave computer, and to draw the data uploaded by the slave computer in real time as a waveform and display it; the network communication module is used to complete the establishment of a network communication link and the reception and transmission of data; the configuration file module is used to complete the creation, closing, data writing and data reading of the configuration file; the communication protocol processing module is used to parse and process the upper-layer protocol, process the data received from the protocol deframing module, and then display it on the human-machine interface, and also to process the data sent from the human-machine interface and then send it to the protocol framing module.

[0012] In one embodiment, it also includes a device control system log module, which is used to record all output information of the operation process of each module.

[0013] In one embodiment, it also includes a scheduling management module, which is used for the management and scheduling of all functional modules.

[0014] In one embodiment, the scheduling management module is designed and implemented in a class manner, and the class attributes include module status and module global attributes. The public interface includes the module initialization function, module opening and closing functions, and module method calling function.

[0015] The technical effects of the present invention are as follows: the space-based 6G signal processing system of the present invention can convert high-frequency 6G signals into medium- and low-frequency signals and demodulate them; the demodulated data can be quickly sent to the host computer through the 10 Gigabit network card for intuitive display and storage; therefore, the space-based 6G signal processing system of the present invention can realize rapid processing of a large number of dynamic data streams transmitted by the 6G network. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0017] Figure 1 is a schematic diagram schematically showing the structure of a space-based 6G signal processing system according to an embodiment of the present invention;

[0018] Figure 2 is a block diagram schematically illustrating a QPSK modulation implementation of an embodiment of the present invention;

[0019] Figure 3 is a schematic diagram schematically showing the structure of a serial port board according to an embodiment of the present invention;

[0020] Figure 4 Schematically shows the structure of the RS485 transceiver circuit of an embodiment of the present invention;

[0021] Figure 5 FIG. 4 is a flowchart schematically showing a network communication module working process of an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0023] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0024] Space-based 6G signal processing system implementation example:

[0025] like Figure 1 As shown, the space-based 6G signal processing system of the present invention includes: an upper computer and a lower computer, the lower computer includes a 10 Gigabit network card, a 1 Gigabit network card, a data processing circuit, a satellite downconverter and a power supply circuit for powering the lower computer; the satellite downconverter is used to convert high-frequency satellite signals into medium and low-frequency satellite signals; the data processing circuit is connected to the downconverter, and is used to demodulate the medium and low-frequency satellite signals to extract original information, the lower computer is connected to the upper computer through the 10 Gigabit network card, and is used to send the original information to the upper computer through the 10 Gigabit network card, and is connected to the upper computer through the 1 Gigabit network card to receive control instructions issued by the upper computer; the upper computer is also used to display and store the received original information.

[0026] Both 10 Gigabit and 1 Gigabit network cards include multiple data transmission channels.

[0027] The space-based 6G signal processing system of the present invention can convert high-frequency 6G signals into medium- and low-frequency signals and demodulate them; the demodulated data can be quickly sent to the host computer through the 10 Gigabit network card for intuitive display and storage; therefore, the space-based 6G signal processing system of the present invention can realize rapid processing of large amounts of dynamic data streams transmitted over the 6G network.

[0028] In one embodiment, a 10 Gigabit network switch is further included, and the 10 Gigabit network switch is respectively connected to the 10 Gigabit network card, the 1 Gigabit network card and the data processing circuit.

[0029] By setting up a 10 Gigabit network switch, it is convenient to connect and transmit data between the lower computer and other intelligent devices.

[0030] In one embodiment, the data processing circuit performs modulation and demodulation on the satellite signal by binary phase shift keying, quadrature phase shift keying or orthogonal frequency division multiplexing.

[0031] Binary phase shift keying is abbreviated as BPSK. BPSK uses binary digital signals 0 or 1 to control the phase of a sine carrier or a cosine carrier. Its modulation process only requires the use of one carrier: cos(ω0t) or sin(ω0t), and cos(ω0t) is commonly used. According to the characteristics of BPSK modulation, when the input binary signal is digital "0", s(t) = cos(ω0t); when the input binary signal is data "1", s(t) = -cos(ω0t), that is, the BPSK modulation waveform and the input signal have the following mapping relationship:

[0032] Table 1

[0033] Input binary signal Corresponding I and Q signals Modulated waveform 0 I=1;Q=0 <![CDATA[s(t)=cos(ω0t)]]> 1 I=-1;Q=0 <![CDATA[s(t)=cos(ω0t+π)]]>

[0034] When performing BPSK signal modulation and demodulation, a parallel processing method is used because of the fast transmission rate. That is, when a 1Gbps signal arrives, it is first received through the optical port, then cached and divided into 8 channels (each 125Mbps) before BPSK modulation. The modulated data is then sent out in sequence at a rate of 1Gbps.

[0035] Quadrature Phase Shift Keying (QPSK) is abbreviated as "QPSK". It is divided into two types: absolute phase shift and relative phase shift. Since the absolute phase shift method has phase ambiguity, the relative phase shift method QDPSK is mainly used in practice. It has a series of unique advantages and has been widely used in wireless communications, becoming a very important modulation and demodulation method in modern communications.

[0036] Quaternary phase shift modulation uses four different phase differences of the carrier to characterize the input digital information. It is quaternary phase shift keying, which stipulates four carrier phases, namely 45°, 135°, 225°, and 275°. The data input to the modulator is a binary digital sequence. In order to match the quaternary carrier phase, the binary data needs to be converted into quaternary data, which means that every two bits in the binary digital sequence need to be divided into a group. There are four combinations, namely 00, 01, 11, and 10, each of which is called a two-bit codeword. Each two-bit codeword is composed of two binary information bits, which represent one of the four symbols in the quaternary system. In QPSK, each modulation can transmit 2 information bits, and these information bits are transmitted through the four phases of the carrier. The information bits are shown in the following table:

[0037] Table 1 Information bits

[0038] Binary signal I.Q Phase 00 +1，+1 π / 4 01 －1，+1 3π / 4 11 －1，－1 5π / 4 10 +1，－1 7π / 4

[0039] The block diagram of QPSK modulation is as follows Figure 2 As shown. First, the input serial binary information sequence is converted into two parallel data streams through serial-to-parallel conversion (mapping). The data rate of each channel is R / 2, where R is the data rate of the serial input code. Bipolar two-level signals I(t) and Q(t) are generated respectively, and then cos(wt) and sin(wt) are modulated. After subtraction, the QPSK signal is obtained.

[0040] Orthogonal frequency division multiplexing is abbreviated as OFDM. OFDM is a multi-carrier modulation method. First, the input signal is converted into parallel data in the frequency domain through serial-to-parallel conversion, and then converted into a time domain signal through inverse Fourier transform (IFFT) for transmission. At the receiving end, the signal is converted to the frequency domain through Fourier transform (FFT) and then demodulated. The demodulation process of OFDM mainly includes three steps: synchronization, channel estimation and data demodulation.

[0041] like Figure 3 As shown, in one embodiment, the lower computer also includes a serial port board connected to the data processing circuit, the serial port board includes an RS422 sending circuit, an RS422 receiving circuit, an RS485 transceiver circuit, an FPGA chip and a power management circuit for powering the serial port board, the input end of the power management circuit is connected to a protection circuit, and the protection circuit is used to perform overcurrent protection, overvoltage protection and undervoltage protection on the serial port board; the input end of the RS422 sending circuit, the output end of the RS422 receiving circuit and one end of the RS485 transceiver circuit are respectively connected to the data processing circuit through an isolation circuit, and the output end of the RS422 sending circuit, the input end of the RS422 receiving circuit and the other end of the RS485 transceiver circuit are respectively connected to a connector.

[0042] The connector may be a J14A connector. The RS422 sending circuit uses a DS26C31TM chip; the RS422 receiving circuit uses a DS26C31TM chip; and the RS485 transceiver circuit uses a MAX485EESA chip.

[0043] By setting up a protection circuit, it is possible to prevent the components on the serial port board from being burned out due to excessive current or voltage. By setting up an isolation circuit between the serial port interface and the data processing circuit, the safety of the RS422 sending interface, RS422 receiving interface and RS485 interface can be guaranteed.

[0044] By setting up a serial port board, the data transmission channels between the lower computer and the upper computer or other intelligent terminals are more diversified. When one of the data transmission channels fails, other data transmission channels can be used.

[0045] In one embodiment, in order to monitor the working status of the serial port board, a board status acquisition circuit is also provided on the serial port board, and the board status acquisition circuit is connected to the data processing circuit to send the collected board working status to it; the data processing circuit is also used to upload the board working status to the host computer for display.

[0046] like Figure 4As shown, the RS485 transceiver circuit includes an RS485 transceiver U1, a receiver output terminal RO of the RS485 transceiver is connected in series with a thirteenth resistor R13, a receiver output enable terminal RE and a driver output enable terminal DE are connected to each other and then connected in series with a fourteenth resistor R14, a driver input terminal DI is connected in series with a fifteenth resistor R15, a power supply terminal VDD is connected to a power supply voltage VCC and is grounded through a first capacitor C1, a sixteenth resistor R16 is connected in series between the in-phase driver output terminal A and the inverting driver output terminal B, a bidirectional TVS transient suppression diode D3 is connected in parallel at both ends of the sixteenth resistor R16, one end of the sixteenth resistor R16 is connected to the power supply voltage VCC through a pull-up resistor R18, and the other end is grounded through a grounding resistor R17.

[0047] By connecting resistors in series at the receiver output, receiver output enable, driver output enable and driver input, respectively, excessive current can be prevented from burning out the RS485 transceiver; by connecting a sixteenth resistor in series between the in-phase driver output A and the inverting driver output B of the RS485 transceiver, short circuit can be prevented; by connecting a bidirectional TVS transient suppression diode in series between the in-phase driver output A and the inverting driver output B of the RS485 transceiver, overvoltage protection can be provided to the RS485 transceiver.

[0048] In one embodiment, the host computer includes a network communication module, a communication parameter configuration module, a configuration file module, a communication protocol processing module, a protocol framing module, a protocol deframing module, a human-machine interface, and an interface management module.

[0049] The human-machine interface is used to display the data transmission rate between the upper computer and the lower computer, and to draw the data uploaded by the lower computer into a waveform in real time and display it. The waveforms displayed are different depending on the data sent by the lower computer, mainly including BPSK time domain diagram, BPSK spectrum diagram, BPSK constellation diagram, QPSK time domain diagram, QPSK spectrum diagram, QPSK constellation diagram, OFDM time domain diagram, OFDM spectrum diagram, and DFDM constellation diagram.

[0050] The network communication module is used to complete the establishment of the network communication link and the reception and transmission of data. After the software is running, the module establishes a connection with the lower computer through the configured network parameters. After the connection is established, the network communication module starts the sending thread and the receiving thread at the same time. When there is data in the communication link, the received data is first saved in real time. Then the data is processed and parsed, and then the parsed data is given to the upper layer in the form of function callback. The sending thread scans the sending data queue in real time. If there is sending data in the sending queue, the sending data is sent to the upper computer through the network.

[0051] The network communication module is designed and implemented in a class manner. The class attributes include communication IP, communication port, communication status, receive data callback function, send data function, callback function after communication is established, and callback function after communication is closed. Figure 5 As shown, the network communication module workflow is:

[0052] a. First, initialize the communication interface;

[0053] b. Establish the connection between the upper computer and the lower computer;

[0054] c. Start the receiving thread and sending thread after the connection is successful;

[0055] d. The receiving thread detects in real time whether there is data sent by the lower computer, and caches the data in response to the lower computer sending data; the sending thread detects in real time whether there is data in the sending queue, and sends the data in the sending queue in response to the sending queue having data.

[0056] The configuration file module is used to complete the creation, closing, data writing and data reading of the configuration file. After the software is running, the configuration file module instantiates the configuration file object, and after the configuration file is successfully created and opened normally, the required configuration information parameters are written in sequence.

[0057] The configuration file module is designed and implemented in a class manner. The class attributes include file name, file status, and file path. The class interface functions include reading integer parameters, reading floating-point parameters, reading string parameters, reading Boolean parameters, reading time parameters, writing integer parameters, writing floating-point parameters, writing string parameters, writing Boolean parameters, and writing time parameters.

[0058] The communication protocol processing module is responsible for parsing and processing the upper layer protocol. It processes the data received from the protocol de-framing module and displays it on the user interface. It processes the data sent from the user interface and sends it to the protocol framing module.

[0059] The protocol framing module is mainly used to complete the software framing of the device protocol data in the test process according to the data frame specifications agreed by the device. After the software is running, the device parameters are read through the interface and the parameter values ​​are combined into corresponding executable data frames.

[0060] The protocol de-framing module mainly parses the data packets fed back by the device. After the software is running, the device protocol parsing module receives the data fed back by the device and parses and processes the data according to the data protocol format of the device. The parsed data needs to be displayed in the user interface and refreshed on the interface.

[0061] In one embodiment, it also includes a device control system log module, which is used to record all output information of the operation process of each module, which is crucial for future data statistics and abnormal problem analysis. All other modules will send their log information to the device control system log module.

[0062] The design of the equipment control system log module meets the following requirements:

[0063] 1) Multithreading: The first requirement for the logging system is that it must support multithreading, that is, the logging interface must be thread-safe, and all modules can directly use the logging interface to output information in an orderly manner.

[0064] 2) Log Cache: The log module can provide a buffered way to write log files. Generally speaking, log output operations involve writing files, which are slow to execute. Some modules require the called log interface to return quickly. Therefore, the log module needs to store the output information in the buffer first, and then output the log information when the software is idle.

[0065] 3) Good format: A good log output format is convenient for reading and log analysis using scripts, so the following requirements need to be met:

[0066] a) Row mode: one log message occupies one row and does not cross rows;

[0067] b) Time information: Display time information to make the statistical results clearer.

[0068] c) Information classification: classified into general information, warning information, and error information;

[0069] d) Date segmentation: Store daily logs into one log file by date, and switch files across days to facilitate daily statistical data.

[0070] In one embodiment, a scheduling management module is also included, and the scheduling management module is mainly used for the management and scheduling of all functional modules. After the software is run, all modules are initialized, the module opening function is called, and the configuration file is loaded.

[0071] The scheduling management module is designed and implemented in the form of a class. The class attributes include module status and module global attributes. The public interface includes the module initialization function, module opening and closing functions, and module method calling functions.

[0072] In the description of this specification, "plurality" or "several" means at least two, such as two, three or more, etc., unless otherwise clearly and specifically defined.

[0073] Although this specification has shown and described a number of embodiments of the present invention, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art will conceive of many modifications, changes and alternatives without departing from the ideas and spirit of the present invention. It should be understood that in the practice of the present invention, various alternatives to the embodiments of the present invention described herein may be employed.

Claims

1. A space-based 6G signal processing system, characterized in that: include: An upper computer and a lower computer, wherein the lower computer includes a 10G network card, a 1G network card, a data processing circuit, a satellite downconverter, and a power supply circuit for supplying power to the lower computer; The satellite downconverter is used to convert high-frequency satellite signals into medium- and low-frequency satellite signals; the data processing circuit is connected to the downconverter and is used to demodulate the medium- and low-frequency satellite signals to extract original information; the lower computer is connected to the upper computer through the 10 Gigabit network card and is used to send the original information to the upper computer through the 10 Gigabit network card, and is connected to the upper computer through the 1 Gigabit network card to receive control instructions issued by the upper computer; the upper computer is also used to display and store the received original information.

2. The space-based 6G signal processing system according to claim 1, characterized in that: It also includes a 10 Gigabit network switch, which is connected to the 10 Gigabit network card, the 1 Gigabit network card and the data processing circuit respectively.

3. The space-based 6G signal processing system according to claim 1, characterized in that: The data processing circuit modulates and demodulates the satellite signal in a manner of binary phase shift keying, quadrature phase shift keying or orthogonal frequency division multiplexing.

4. The space-based 6G signal processing system according to claim 1, characterized in that: The lower computer also includes a serial port board connected to the data processing circuit, the serial port board includes an RS422 sending circuit, an RS422 receiving circuit, an RS485 transceiver circuit, an FPGA chip and a power management circuit for powering the serial port board, the input end of the power management circuit is connected to a protection circuit, and the protection circuit is used to perform overcurrent protection, overvoltage protection and undervoltage protection on the serial port board; the input end of the RS422 sending circuit, the output end of the RS422 receiving circuit and one end of the RS485 transceiver circuit are respectively connected to the data processing circuit through an isolation circuit, and the output end of the RS422 sending circuit, the input end of the RS422 receiving circuit and the other end of the RS485 transceiver circuit are respectively connected to a connector.

5. The space-based 6G signal processing system according to claim 4, characterized in that: The RS485 transceiver circuit includes an RS485 transceiver, wherein a thirteenth resistor is connected in series to a receiver output end of the RS485 transceiver, a receiver output enable end and a driver output enable end are connected to each other and then connected in series to a fourteenth resistor, a driver input end is connected in series to a fifteenth resistor, a power supply end is connected to a power supply voltage and is grounded through a first capacitor, a sixteenth resistor is connected in series between an in-phase driver output end and an inverting driver output end, a bidirectional TVS transient suppression diode is connected in parallel to both ends of the sixteenth resistor, one end of the sixteenth resistor is connected to the power supply voltage through a pull-up resistor, and the other end is grounded through a grounding resistor.

6. The space-based 6G signal processing system according to any one of claims 1 to 5, characterized in that: The host computer includes a network communication module, a communication parameter configuration module, a configuration file module, a communication protocol processing module, a protocol framing module, a protocol deframing module, a human-machine interface and an interface management module; wherein the human-machine interface is used to display the data transmission rate between the host computer and the slave computer, and to draw the data uploaded by the slave computer in real time as a waveform and display it; the network communication module is used to complete the establishment of a network communication link and the reception and transmission of data; the configuration file module is used to complete the creation, closing, data writing and data reading of the configuration file; the communication protocol processing module is used to parse and process the upper layer protocol, process the data received from the protocol deframing module, and then display it on the human-machine interface, and also to process the data sent from the human-machine interface and then send it to the protocol framing module.

7. The space-based 6G signal processing system according to claim 6, characterized in that: It also includes a device control system log module, which is used to record all output information of the operation process of each module.

8. The space-based 6G signal processing system according to claim 6, characterized in that: It also includes a scheduling management module, which is used for the management and scheduling of all functional modules.

9. The space-based 6G signal processing system according to claim 8, characterized in that: The scheduling management module is designed and implemented in a class manner, and the class attributes include module status and module global attributes. The public interface includes the module initialization function, module opening and closing functions, and module method calling function.

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