A coding method, a decoding method and related devices

Abstract

Disclosed are an encoding method, a decoding method, and related devices designed to independently encode each of z second data streams without performing operations such as de-skewing and reordering, thereby reducing operational complexity and latency. The encoding method includes: obtaining m first data streams through m input channels, where m is a positive integer; processing the m first data streams to obtain z second data streams, where z is a positive integer; independently encoding each of the z second data streams to obtain z third data streams; and multiplexing the z third data streams to obtain n fourth data streams, where n is a positive integer.

Description

[0001] This application is a divisional application of the application submitted to the China Intellectual Property Office with an application date of September 18, 2021, application number 202111127055.5, and invention name “A coding method, a decoding method and related devices”. Technical Field

[0002] The embodiments of the present application relate to the field of communication technology, and specifically to an encoding method, a decoding method, and related devices. Background Art

[0003] Current applications such as fifth-generation mobile communication technology (5G), artificial intelligence, and virtual reality are driving continued rapid growth in data center traffic. Existing 400GE technology cannot meet the underlying interconnection architecture of future data centers. Therefore, next-generation Ethernet technology with throughput exceeding 400Gbps is needed to meet the bandwidth demands of future data centers. As Ethernet transmission rates increase, the bit error rate (BER) increases, making forward error correction (FEC) a key core technology for addressing transmission errors. Designing efficient, low-complexity, and low-latency FEC coding algorithms and implementation architectures is a major technical challenge facing next-generation Ethernet technology.

[0004] In existing Ethernet communication architectures, the physical sublayer of the Ethernet communication architecture can be divided into the physical coding sublayer (PCS), the physical medium attachment sublayer (PMA), and the physical media dependent (PMD) layer. At the PCS layer, the data stream undergoes key data stream operations, including 64B / 66B encoding, 256B / 257B transcoding, alignment marker insertion, and Reed-Solomon (RS) encoding. The resulting RS-encoded data stream is then distributed to the physical coding sublayer lanes (PCS lanes). After multiplexing through a multiplexer (MUX), the resulting data stream is sent to the PMA layer via m output channels. At the PMA layer, clock data recovery (CDR), transmitting-side bit multiplexing, and signal driving are performed on the received data stream. The data stream output from the PMA layer completes optical modulation, electro-optical conversion and other operations on the PMD layer, outputs the optical signal to the transmission medium, and completes the data operation of the entire sending end.

[0005] However, in existing Ethernet communication architectures, data streams are transmitted from the PCS layer through m output channels to the optical module's PMA layer, resulting in delay skew between the physical channels. To ensure data stream alignment, multiple physical coding sublayer channels must be aligned, de-skewed, and reordered, incurring significant complexity and latency costs. Furthermore, existing Ethernet communication architectures are only suitable for scenarios with throughput rates up to 400 Gbps. As Ethernet transmission rates increase, existing Ethernet communication architectures cannot meet the system error correction performance requirements of next-generation Ethernet communications exceeding 400 Gbps. Summary of the Invention

[0006] The embodiments of the present application disclose an encoding method, a decoding method, and related devices, which aim to independently perform inner code encoding processing on each of the z second data streams, eliminating the need to perform de-skew, reordering, and other operations on the z second data streams, thereby reducing operational complexity and latency.

[0007] In the first aspect, an embodiment of the present application provides a coding method that can be applied to an optical module or other coding device. In this coding method, m-way first data streams are obtained through m-way input channels, where m is a positive integer; the m-way first data streams are processed to obtain z-way second data streams, where z is a positive integer; each second data stream in the z-way second data streams is independently coded to obtain z-way third data streams; the z-way third data streams are multiplexed to obtain n-way fourth data streams, where n is a positive integer. It should be noted that each second data stream may include Y data blocks to be coded, and the data blocks to be coded can be understood as information bits to be coded. For each data block to be coded in the second data stream, the mapping relationship between it and the RS codeword satisfies: Y×the length of the data block to be coded=X×(N×the codeword length of the RS codeword) / z, where Y and X are positive integers greater than or equal to 1. It should be noted that the length of each data block to be encoded is k, the length of the check bit is p, and the total codeword length is n, where n, k, and p satisfy n=k+p, and n, k, and p are integers greater than 0. For example, if the length k of the data block to be encoded is 170 bits, and after adding a 10-bit check bit, the total codeword length of the data block to be encoded is 180 bits. Alternatively, if the length k of the data block to be encoded is 170 bits, and after adding a 9-bit check bit, the total codeword length of the data block to be encoded is 179 bits. Alternatively, if the length k of the data block to be encoded is 170 bits, and after adding an 11-bit check bit, the total codeword length of the data block to be encoded is 181 bits. Alternatively, if the length k of the data block to be encoded is 120 bits, and after adding an 8-bit check bit, the total codeword length of the data block to be encoded is 128 bits, and so on. This is only used as an example for illustration and is not specifically limited in this application.

[0008] Through the above method, the embodiment of the present application independently performs inner code encoding processing on each of the z second data streams, and the FEC codewords in the third data stream obtained after each encoding contain boundary identifiers, which not only ensures the decoupling of the inner code encoding from the data encoded by the upper PCS layer, but also ensures the decoupling of the inner code encoding from the transmission of the lower PMD layer, which can save the delay of processing delay skew and disorder, making the inner code encoding and decoding of the present application suitable for scenarios that are sensitive to transmission delay.

[0009] In some possible implementations, each of the z second data streams includes a data block to be encoded. In this encoding method, encoding the z second data streams can be performed as follows: performing inner code encoding on a first data block to obtain an FEC codeword, where the first data block is at least C / z consecutive data blocks to be encoded in the corresponding second data stream, where C is a positive integer and C is an integer multiple of z. The encoding method further includes inserting a first identifier at a codeword boundary position of any FEC codeword, the first identifier being used to identify the codeword boundary of the FEC codeword, and the throughput rate or baud rate of the FEC codeword after inserting the first identifier being an integer multiple of a reference clock. It should be noted that the codeword boundary position can be understood as the beginning and / or end of the codeword, and is not limited here. Identifying the codeword boundary of the FEC codeword using the first identifier allows direct identification of the first identifier during subsequent decoding, thereby clearly identifying the boundary position of each FEC codeword and avoiding the failure of inner code decoding due to delay skew and unknown data starting position.

[0010] In other possible implementations, each of the z second data streams includes a data block to be encoded. In this encoding method, encoding the z second data streams can also be performed in the following manner: inserting a first identifier into each data block to be encoded in the first data block to obtain a second data block, wherein the first data block is at least C / z consecutive data blocks to be encoded in the corresponding second data stream; encoding the second data block to obtain an FEC codeword, wherein the throughput rate or baud rate of the FEC codeword is an integer multiple of the reference clock. In the above manner, the codeword boundary of the encoded FEC codeword is identified by the first identifier, so that the first identifier can be directly identified in the subsequent decoding process, and the boundary position of each FEC codeword can be clearly determined, thereby avoiding the failure of inner code decoding in the case of delay skew and unknown data starting position.

[0011] In other possible implementations, the first identifier is a preset identifier sequence. For example, the first identifier can be a sequence of "1"s and "0"s, or a sequence such as "101010" or "1010," or another known sequence, without limitation. By setting the first identifier as a preset identifier sequence in the above manner, the requirements of different scenarios can be met.

[0012] In other possible implementations, the first identifier is obtained based on the value of the first bit of the first data block, where the first bit is any one of at least one bit in the first data block; or, the first identifier is obtained based on the values of at least L second bits in the first data block, where each two adjacent bits of the L second bits are separated by s bits, where L ≥ 2, s ≥ 0, and L and s are integers. For example, the first bit may be bit 0 in the first data block. If the value of bit 0 is "0," the first identifier, i.e., "1," can be obtained by directly inverting the value of bit 0. Alternatively, if the value of bit 0 is "1," the first identifier, i.e., "0," can be obtained by directly inverting the value of bit 0. The specifics are not limited here. In practical applications, the first bit may also be bit 1, bit 2, or the like in the first data block, and the specifics are not limited here. For example, if the codeword length of the first data block is 180 bits, the last bit may be inverted, i.e., the value of bit 179 may be directly inverted to obtain the first identifier. The first identifier is obtained by performing an inverting operation on the bit at the very beginning or the very end of the codeword, which helps the receiving end to quickly determine the codeword boundary. Alternatively, when L=4 and s=2, the four second bits selected from the first data block are bit 0, bit 2, bit 4, and bit 6. In this way, the bit values corresponding to bit 0, bit 2, bit 4, and bit 6 are processed by an XOR operation, and the result of the processing can be used as the first identifier. It should be noted that in some examples, the four second bits selected can also be bit 1, bit 3, bit 5, bit 7, etc., which is not limited here. In actual applications, L can also be 8 and s can be 3, or L can be 6 and s can be 4, etc. The value of L is not limited in this application, nor is the value of s. In the above manner, the first identifier is determined based on the bits in the first data block, which can also be applied to different scenarios.

[0013] In other possible implementations, m-channel first data streams are processed to obtain z-channel second data streams. The following method can be used, namely: the m-channel first data streams are demultiplexed according to a second ratio to obtain z-channel second data streams, where the second ratio is the ratio of m to z. For example, if the first ratio is 16:4, the second ratio should be 4:16. This is only illustrated by using 4:16 as an example. In actual applications, other values are possible and are not limited by this application. Through the above method, the m-channel first data streams are directly demultiplexed, providing multiple possible implementation methods for obtaining the z-channel second data streams.

[0014] In other possible implementations, demultiplexing the m first data streams according to a second ratio to obtain z second data streams includes: demultiplexing the m first data streams according to the second ratio to obtain z fifth data streams, and independently performing Q-level processing on each fifth data stream in the z third data streams to obtain z second data streams. Each level of processing in the Q-level processing includes: performing round-robin distribution processing on the data stream obtained at the previous level to obtain at least two sub-data streams, delaying the first sub-data stream to obtain a sixth data stream, and multiplexing the second sub-data stream and the sixth data stream to obtain an output data stream after processing at this level, wherein the first sub-data stream is at least one sub-data stream of the at least two sub-data streams, the second sub-data stream is one sub-data stream of the at least two sub-data streams that has not been delayed, Q is a positive integer, and the second data stream is a data stream after Q-level processing. Through the above method, multiple possible implementation methods for obtaining z second data streams are provided.

[0015] In some other possible implementations, the bit length of the sixth data stream is at least (N×codeword length of the RS codeword) / (z×i) bits, where N is a positive integer and i is the number of the sub-data streams.

[0016] In other possible implementations, the encoding method further includes: obtaining m seventh data streams through the m physical channels; demultiplexing the m seventh data streams according to the second ratio to obtain z eighth data streams; and processing the m first data streams to obtain z second data streams, including: multiplexing the z second data streams and the z eighth data streams to obtain z multiplexed second data streams. The above method provides multiple possible implementations for obtaining the z second data streams.

[0017] In some other possible implementations, the encoding method further includes: identifying an alignment marker in each of the second data streams, the alignment marker being used to identify a symbol boundary in the corresponding second data stream, and determining a symbol boundary in the corresponding second data stream based on the alignment marker. For example, a 120-bit AM alignment block with a known sequence is added to each of the first data streams, and within this 120-bit AM alignment block with a known sequence, there is a 48-bit common alignment marker. In an operation requiring only RS codeword symbol boundaries, alignment can be locked by identifying the 48-bit common alignment marker.

[0018] In other possible implementations, the m first data streams are obtained by multiplexing z data streams after Reed-Solomon (RS) encoding using a first ratio. It should be noted that the first ratio can be understood as the ratio of z to m. For example, the first ratio is 16:4, 32:4, 32:16, 16:8, etc., which are not limited here. In addition, the m first data streams collectively include N RS codewords, wherein each first data stream may include (N × codeword length of the RS codeword) / m bits.

[0019] In a second aspect, an embodiment of the present application provides a decoding method that can be applied to an optical module or other decoding device. In the decoding method, n fourth data streams are obtained through n input channels; the n fourth data streams are demultiplexed to obtain z third data streams; each of the z third data streams is independently decoded to obtain the z second data streams; and the z second data streams are multiplexed according to a first ratio to obtain the m first data streams, where the first ratio and the second ratio are reciprocal of each other.

[0020] In some other possible implementations, the z-channel third data stream includes a first identifier, where the first identifier is used to identify a codeword boundary of an FEC codeword. In the decoding method, the decoding method further includes: identifying the FEC codeword boundary based on the first identifier and / or a decoding flag, where the decoding flag is used to indicate whether inner code decoding processing is successful.

[0021] In some other possible implementations, before identifying the codeword boundary of the FEC codeword based on the first identifier and / or the decoding flag, the decoding method further includes: generating a first signal based on the first identifier and / or the decoding flag, wherein the first signal is used to determine the data clock information. It should be noted that the data clock information can be determined through the first signal, so that the CDR unit accelerates the data and clock recovery process, determines the data clock information in advance, reduces the time required for system locking, and facilitates the early determination of the system transmission frequency. In addition, since the first identifier of the present application is designed in a sequence generation method, it not only takes into account the autocorrelation characteristics of the sequence corresponding to the first identifier, which helps the first identifier to be detected more quickly; but also takes into account the fact that the first identifier contains a fixed 0,1 jump characteristic, which improves the convergence speed of the data clock recovery of the CDR unit. It should be noted that if the CDR unit receives its own feedback signal for normal data and clock recovery before receiving the first signal, the CDR unit can enter a locked state based on the signal for normal data and clock recovery, thereby completing the data and clock recovery operation.

[0022] In a third aspect, embodiments of the present application provide another encoding method. In this encoding method, a data stream to be transmitted is obtained and RS encoding is performed on the data stream to be transmitted to obtain z data streams, each of which corresponds to a physical coding sublayer channel. The z data streams are then multiplexed according to the first ratio to obtain m first data streams, and the m first data streams are transmitted through the m output channels.

[0023] In other possible implementations, the encoding method may further include: performing Q-level processing on each of the z data streams to obtain z ninth data streams. Each level of the Q-level processing includes performing round-robin distribution processing on the ninth data stream obtained in the previous level to obtain at least two sub-data streams, performing delay processing on the third sub-data stream to obtain a tenth data stream, and multiplexing the fourth sub-data stream and the tenth data stream to obtain a ninth data stream after the current level of processing, wherein the third sub-data stream is at least one of the at least two sub-data streams, and the fourth sub-data stream is one of the at least two sub-data streams that has not undergone delay processing. Then, the z ninth data streams are multiplexed according to the first ratio to obtain the m first data streams.

[0024] In a fourth aspect, an embodiment of the present application provides an encoding device, comprising a first acquisition unit and a first processing unit. The first acquisition unit is configured to acquire m first data streams through m input channels, where m is a positive integer. The first processing unit is configured to process the m first data streams to obtain z second data streams, where z is a positive integer; independently encode each of the z second data streams to obtain z third data streams; and multiplex the z third data streams to obtain n fourth data streams, where n is a positive integer.

[0025] In other possible implementations, each of the z second data streams includes a data block to be encoded; the first processing unit is configured to: encode the first data block to obtain an FEC codeword, wherein the first data block corresponds to at least C / z consecutive data blocks to be encoded in the corresponding second data stream, where C is a positive integer and C is an integer multiple of z; and insert a first identifier at a codeword boundary position of any FEC codeword in the FEC codewords, the first identifier being used to identify the codeword boundary of the FEC codeword, and the throughput rate or baud rate of the FEC codeword after inserting the first identifier being an integer multiple of a reference clock. In this manner, the codeword boundary of the encoded FEC codeword is identified by the first identifier, so that the first identifier can be directly identified in the subsequent decoding process, thereby clearly identifying the boundary position of each FEC codeword, thereby avoiding the failure of inner code decoding in the case of delay skew and unknown data starting position.

[0026] In other possible implementations, each of the z second data streams includes a data block to be encoded; the first processing unit is configured to: insert a first identifier into each data block to be encoded in the first data block to obtain a second data block, where the first data block is C / z consecutive data blocks to be encoded, where C is a positive integer and C is an integer multiple of z; and encode the second data block to obtain an FEC codeword, where the throughput or baud rate of the FEC codeword is an integer multiple of a reference clock. In this manner, the codeword boundary of the FEC codeword is identified by the first identifier, so that the first identifier can be directly identified in the subsequent decoding process, thereby clearly determining the boundary position of each FEC codeword, thereby avoiding the failure of inner code decoding due to delay skew and unknown data starting position.

[0027] In some other possible implementations, the first identifier is a preset identifier sequence. By setting the first identifier as a preset identifier sequence in the above manner, the requirements of different scenarios can be met.

[0028] In some other possible embodiments, the first identifier is obtained based on the value of the first bit of the first data block, where the first bit is any one of at least one bit in the first data block; or, the first identifier is obtained based on the bit values of at least L second bits in the first data block, where there is an interval of s bits between each two adjacent second bits of the L second bits, L≥2, s≥0, and L and s are integers.

[0029] In some other possible implementations, the first processing unit is configured to perform demultiplexing processing on the m first data streams according to a second ratio to obtain z second data streams, where the second ratio is a ratio of m to z.

[0030] In other possible embodiments, the first processing unit is used to demultiplex the m first data streams according to the second ratio to obtain z fifth data streams; independently perform Q-level processing on each of the z fifth data streams to obtain z second data streams; wherein each level of processing in the Q-level processing includes: performing round-robin distribution processing on the data stream obtained at the previous level to obtain at least two sub-data streams, and delaying the first sub-data stream to obtain a sixth data stream, and multiplexing the second sub-data stream and the sixth data stream to obtain an output data stream after processing at this level, the first sub-data stream is at least one sub-data stream of the at least two sub-data streams, the second sub-data stream is one sub-data stream of the at least two sub-data streams that has not been delayed, Q is a positive integer, and the second data stream is the data stream after Q-level processing.

[0031] In some other possible implementations, the bit length of the sixth data stream is at least (N×codeword length of the RS codeword) / (z×i) bits, where N is a positive integer and i is the number of the sub-data streams.

[0032] In some other possible implementations, the first acquisition unit is further configured to acquire m seventh data streams through the m input channels. The first processing unit is configured to demultiplex the m seventh data streams according to the second ratio to obtain z eighth data streams, and multiplex the z second data streams and the z eighth data streams to obtain z multiplexed second data streams.

[0033] In some other possible implementations, the first processing unit is further configured to identify an alignment mark in each of the second data streams, the alignment mark being used to identify a symbol boundary in the corresponding second data stream; and determine a symbol boundary in the corresponding second data stream based on the alignment mark.

[0034] In some other possible implementations, the m-channel first data streams are obtained by multiplexing z-channel data streams that are Reed-Solomon (RS) encoded with a first ratio.

[0035] In a fifth aspect, an embodiment of the present application provides a decoding device, comprising a second acquisition unit and a second processing unit. The second acquisition unit is configured to acquire n fourth data streams through n input channels. The second processing unit is configured to: demultiplex the n fourth data streams to obtain z third data streams; independently decode each of the z third data streams to obtain the z second data streams; and multiplex the z second data streams according to a first ratio to obtain the m first data streams, where the first ratio and the second ratio are reciprocal of each other.

[0036] In other possible embodiments, the z-path third data stream includes a first identifier, which is used to identify the codeword boundary of the FEC codeword; the second processing unit is also used to: identify the codeword boundary of the FEC codeword based on the first identifier and / or the decoding flag bit, and the decoding flag bit is used to indicate whether the decoding processing is successful.

[0037] In other possible embodiments, the second processing unit is further configured to generate a first signal based on the first identifier and / or the decoding flag before identifying the codeword boundary of the FEC codeword based on the first identifier and / or the decoding flag, wherein the first signal is used to determine data clock information. It should be noted that determining the data clock information through this first signal accelerates the data and clock recovery process of the CDR unit, pre-determines the data clock information, reduces the time required for system lock, and facilitates pre-determining the system transmission frequency. Furthermore, the design of the sequence generation method for the first identifier of this application takes into account both the autocorrelation characteristics of the sequence corresponding to the first identifier, which facilitates faster detection of the first identifier, and the fixed 0,1 transition characteristics of the first identifier, which improves the convergence speed of the CDR unit's data clock recovery. It should be noted that if the CDR unit receives its own feedback signal for normal data and clock recovery before receiving the first signal, the CDR unit can enter a lock state based on the signal for normal data and clock recovery, thereby completing the data and clock recovery operation.

[0038] In a sixth aspect, embodiments of the present application provide an encoding device, which may include a memory for storing computer-readable instructions. The device may also include a processor coupled to the memory for executing the computer-readable instructions in the memory, thereby causing the encoding device to perform the encoding method described in the first aspect or any possible implementation of the first aspect.

[0039] In a seventh aspect, embodiments of the present application provide a decoding device, which may include a memory for storing computer-readable instructions. The device may also include a processor coupled to the memory for executing the computer-readable instructions in the memory, thereby causing the decoding device to perform the method described in the second aspect or any possible implementation of the second aspect.

[0040] In an eighth aspect, an embodiment of the present application provides a computer-readable storage medium comprising instructions, which, when executed on a computer, enables the computer to execute a method such as the first aspect, any one of the first aspects, the second aspect, or any possible implementation of the second aspect.

[0041] In the ninth aspect, an embodiment of the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute a method such as the first aspect, any one of the first aspects, the second aspect, or any possible implementation of the second aspect.

[0042] In the tenth aspect of the present application, a chip system is provided, which may include a processor for supporting an encoding device to implement the functions involved in the encoding method described in the first aspect or any possible implementation of the first aspect, or supporting a decoding device to implement the functions involved in the decoding method described in the second aspect or any possible implementation of the second aspect.

[0043] Optionally, in combination with the tenth aspect above, in a first possible implementation, the chip system may further include a memory for storing program instructions and data necessary for the encoding device and the decoding device. The chip system may be composed of a chip, or may include a chip and other discrete devices. Among them, the chip system may include an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, etc. Furthermore, the chip system may also include an interface circuit, etc.

[0044] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0045] In an embodiment of the present application, m first data streams are obtained through m input channels, where m is a positive integer, and the m first data streams are processed to obtain z second data streams, where z is a positive integer. Then, each second data stream in the z second data streams is independently encoded to obtain z third data streams, and the z third data streams are multiplexed to obtain n fourth data streams, where n is a positive integer. Through the above-mentioned method, in an embodiment of the present application, each second data stream in the z second data streams is independently encoded, and the FEC codeword in each encoded third data stream contains a boundary identifier, which ensures the decoupling of the inner code encoding from the data encoded by the upper PCS layer and the decoupling of the inner code encoding from the transmission of the lower PMD layer. There is no need to perform de-skewing, reordering, and other operations on the second data stream, saving the delay of processing delay skew and disorder, making the inner code encoding and decoding of the present application suitable for scenarios sensitive to transmission delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application.

[0047] Figure 1A Schematic diagram of Ethernet communication architecture provided in relevant solutions;

[0048] Figure 1B This is a diagram showing the skew and disorder of data flow;

[0049] Figure 2 A schematic diagram of an application scenario provided in an embodiment of the present application;

[0050] Figure 3 A flowchart of a compilation method provided in an embodiment of the present application;

[0051] Figure 4A A transmission diagram of a data stream in the encoding process provided in an embodiment of the present application;

[0052] Figure 4B This is another transmission diagram of data streams in the encoding process provided in an embodiment of the present application;

[0053] Figure 4C This is another transmission diagram of data streams in the encoding process provided in an embodiment of the present application;

[0054] Figure 4D This is another transmission diagram of data streams in the encoding process provided in an embodiment of the present application;

[0055] Figure 4E This is another transmission diagram of data streams in the encoding process provided in an embodiment of the present application;

[0056] Figure 4F This is another transmission diagram of data streams in the encoding process provided in an embodiment of the present application;

[0057] Figure 5A A schematic diagram of performing an inner code encoding process in an embodiment of the present application;

[0058] Figure 5B Another schematic diagram of performing an inner code encoding process in an embodiment of the present application;

[0059] Figure 6A This is a schematic diagram of adding a first identifier provided in an embodiment of the present application;

[0060] Figure 6B A schematic diagram of a method for obtaining a value of a first identifier provided in an embodiment of the present application;

[0061] Figure 6C A schematic diagram of another method for obtaining a value of the first identifier provided in an embodiment of the present application;

[0062] Figure 7 Another transmission diagram of data stream in the encoding process provided in an embodiment of the present application;

[0063] Figure 8 A schematic diagram of the overall transmission of data flow in the PMA layer;

[0064] Figure 9 A flowchart of a decoding method provided in an embodiment of the present application;

[0065] Figure 10A A transmission diagram of data streams during the decoding process provided in an embodiment of the present application;

[0066] Figure 10B Another transmission diagram of data stream in the decoding process provided by an embodiment of the present application;

[0067] Figure 11 A schematic diagram of the hardware structure of the communication device provided in the embodiment of the present application;

[0068] Figure 12 A schematic diagram of the structure of the encoding device provided in an embodiment of the present application;

[0069] Figure 13 A schematic diagram of the structure of a receiving device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0070] The embodiments of the present application disclose an encoding method, a decoding method, and related devices, which are intended to independently encode each of the z second data streams without the need to perform de-skewing, reordering, and other operations on the z second data streams, thereby reducing operational complexity and latency.

[0071] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0072] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the implementation of the application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. In this application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c can be single or multiple. It is worth noting that "at least one" can also be interpreted as "one or more."

[0073] In the relevant existing Ethernet communication architecture, the physical sublayer of the Ethernet communication architecture can be divided into a PCS layer, a PMA layer and a PMD layer. Figure 1A This is a schematic diagram of the Ethernet communication architecture provided in the relevant solution. Figure 1A As shown, the data stream is obtained from the MAC module and sequentially processed at the PCS layer through 64B / 66B encoding, 256B / 257B transcoding, alignment marker (AM) insertion, and RS encoding. The resulting RS-encoded data stream is then multiplexed and transmitted to the PMA layer via m output channels. The PMA layer sequentially performs CDR and bit multiplexing on the data stream received via m input channels and transmits the processed data stream from the PMA layer to the PMD layer. The PMD layer then performs optical modulation and other processing on the data stream and outputs the optical signal to the transmission medium, completing the entire data operation at the transmitter. The data stream processing at the receiver is a reverse operation, namely, the processing at the PMD layer and then the PMA layer is completed sequentially at the receiver. The data stream is then transmitted to the PCS layer via m output channels.

[0074] However, in Figure 1AIn the related Ethernet communication architecture shown, the data stream processed by the PCS layer is transmitted to the PMA layer through m output channels. Delay skew occurs between these m output channels, causing the data streams obtained from the m output channels to be out of sync in time. This also causes the data streams received at the PMA layer to be misaligned. For details, please refer to Figure 1B The diagram shows that the data flow is skewed and out of order. Figure 1A In the Ethernet communication architecture shown, aligning data streams between input channels requires completing multiple physical coding sublayer channel alignment, deskewing, and reordering operations before encoding can proceed. The latency required to complete these data alignment, deskewing, and reordering operations requires 180ns, increasing both operational complexity and latency. Furthermore, as Ethernet transmission rates increase, existing Ethernet communication architectures are only suitable for scenarios with throughput rates up to 400 Gbps and cannot meet the system error correction performance requirements of next-generation Ethernet communications exceeding 400 Gbps.

[0075] Therefore, in order to solve the above Figure 1A and Figure 1B The problem described in , if the inner code sublayer and the physical coding sublayer channel can be formed into a one-to-one correspondence in the PMA layer, so as to independently encode the data stream in each physical coding sublayer channel, then the Figure 1B The de-skew, reordering and other processing operations shown effectively reduce latency and complexity. Based on this, an embodiment of the present application provides a coding method and a decoding method, which are applied to various optical communication scenarios such as medium and short-distance interconnection communications, long-distance interconnection communications, cloud storage, cloud computing, 5G base station backbone networks, optical transmission, optical access, and base station fronthaul in data centers. The described coding method and decoding method can also be applied to the next generation Ethernet communication architecture with a throughput rate exceeding 400Gbps (for example, 800Gbps throughput, 1600Gbps throughput, etc.). The medium and short-distance interconnection communications described include but are not limited to optical transmission scenarios less than or equal to 40KM. Figure 2 This is a schematic diagram of an application scenario provided by an embodiment of the present application. Figure 2As shown, data communication is achieved between any two hosts via optical modules. For example, taking the case of a data stream transmitted from host A to host B, optical module a is inserted into host A, and optical module b is inserted into host B. Host A can then send the data stream to host B through optical modules a and b, respectively. To eliminate processing operations such as de-skew and reordering, effectively reduce latency and complexity, and maintain the host processing flow as unchanged as possible, it is necessary to modify the optical module's data stream processing process. This process aims to process the m first data streams acquired through the m input channels, recover the original z second data streams, and then independently perform inner coding on each of the z second data streams to obtain z third data streams. The independent inner coding of each second data stream eliminates the need for complex de-skew and reordering processes on the z second data streams. When the system requires a breakout mode, it is only necessary to uniquely correspond each input channel and each output channel of the PMA layer to a transmission medium, thereby ensuring that each second data stream can be transmitted independently, which is better adapted to the breakout mode.

[0076] It should be noted that the above-mentioned optical modules can be understood as optical modules used when transmitting data streams to the receiving end, and can also be understood as optical modules used when receiving data streams from the receiving end, such as the above-mentioned optical modules a and optical modules b. In actual applications, data streams can also be transmitted from host B to host A, and this is not intended to be a limitation here. In addition, the hosts described (such as host A, host B, etc.) can include but are not limited to switching chips or interface chips used in routers, switches, and optical transport network (OTN) transmission equipment, and can also be mobile phone chips, CPU chips, and interface chips that require high-speed communication, etc., and this is not intended to be a limitation here.

[0077] Figure 3 This is a flow chart of an encoding method provided in an embodiment of the present application. Figure 3 As shown, the encoding method may include the following steps:

[0078] 301. Obtain m first data streams through m input channels, where m is a positive integer.

[0079] In this example, after the PCS layer obtains the data stream to be transmitted sent by the MAC module, it sequentially processes the data stream to be transmitted through 64B / 66B encoding, 256B / 257B transcoding, and RS encoding to obtain z data streams. Moreover, each of the z data streams corresponds to a physical coding sublayer channel (PCS lane) in the PCS layer, so that one data stream can be transmitted through one physical coding sublayer channel. Then, after obtaining the z RS-encoded data streams, the z RS-encoded data streams can be multiplexed according to a first ratio to obtain m first data streams (for example: D1, D2, ... D m ), please refer to the above Figure 1A It should be noted that the RS coding described here can be understood as the first coding in the concatenated code, that is, the coding included in the PCS layer.

[0080] In other possible examples, at the PCS layer, before multiplexing z RS-encoded data streams according to a first ratio to obtain m first data streams, the following operation may be performed: performing Q-level processing on each of the z RS-encoded data streams to obtain z ninth data streams; wherein each level of the Q-level processing includes performing round-robin distribution processing on the data stream obtained at the previous level to obtain at least two sub-data streams, performing delay processing on the third sub-data stream to obtain a tenth data stream, and multiplexing the fourth sub-data stream and the tenth data stream to obtain an output data stream after the current level of processing, wherein the third sub-data stream is at least one of the at least two sub-data streams, the fourth sub-data stream is a sub-data stream of the at least two sub-data streams that has not been delayed, Q is a positive integer, and the ninth data stream is a Q-level processed data stream. Then, at the PCS layer, the z ninth data streams are multiplexed again according to the first ratio to obtain m first data streams.

[0081] It should be noted that the specific process of Q-level processing at the PCS layer can be referred to in the subsequent Figure 4B-4D You can understand the contents described in the , so I will not go into details here.

[0082] The first ratio described above is the ratio of z to m, which can also be understood as the ratio of the number of physical coding sublayer channels to the number of input channels. For example, to send 16 data streams to the PMA layer via four output channels at the PCS layer, these 16 data streams must be multiplexed according to a first ratio of 16:4, resulting in four first data streams. It should be noted that the first ratio of 16:4 is used as an example here. In practical applications, this first ratio can also be other values, such as 32:4, 32:16, 16:8, etc., and this is not a limitation here.

[0083] In addition, these m first data streams collectively include N RS codewords, for example, N can be 2, 4, 6, etc., which is not limited here. Among them, each first data stream can include (N×codeword length of RS codeword) / m bits. For example, the data block length of the RS codeword can be 514 symbols, the check bit length is 62 symbols, the total codeword length is 576 symbols, the size of each symbol is 10 bits, and the error correction capability of the codeword is 31 error symbols that can be corrected. Alternatively, the data block length of the RS codeword can be 514 symbols, the check bit length is 30 symbols, the total codeword length is 544 symbols, the size of each symbol is 10 bits, and the error correction capability of the codeword is 15 error symbols that can be corrected. It should be noted that this application does not limit the codeword length of the RS codeword. In actual applications, other codeword lengths may also be included to achieve error correction of different error symbols.

[0084] In this way, after acquiring m first data streams at the PCS layer, these m first data streams are transmitted from the PCS layer to the PMA layer. At this point, the PMA layer can acquire the m first data streams via m input channels. It should be noted that the input channels described herein can be understood as physical medium attachment sublayer channels, physical channels of the AUI interface, or output channels of the upper PMA layer, and this description is not limited in this application.

[0085] 302. Process the m first data streams to obtain z second data streams, where z is a positive integer.

[0086] In this example, the PMA layer passes through m input channels (for example: E1, E2, ... E m ) After receiving the m first data streams sent by the PCS layer, the m first data streams can be processed to obtain z second data streams (for example: F1, F2, ... F z It should be noted that the number of data streams in the described z-lane second data stream is equal to the number of data streams in the z-lane data stream obtained after the PCS layer performs RS encoding on the data stream to be transmitted in the aforementioned step 301. In addition, in some possible examples, these z-lane second data streams may also be referred to as PCS lane data streams.

[0087] Each second data stream may include Y data blocks to be encoded, where each data block to be encoded can be understood as information bits to be encoded. Furthermore, for each data block to be encoded in the second data stream, the mapping relationship between the data block to be encoded and the RS codeword satisfies the following equation: Y × length of the data block to be encoded = X × (N × codeword length of the RS codeword) / z, where Y and X are positive integers.

[0088] In addition, the length of each data block to be encoded is k, the length of the check bit is p, and the total codeword length is n, wherein n, k, and p satisfy n=k+p, and n, k, and p are integers greater than 0. For example, if the length k of the data block to be encoded is 170 bits, and after adding a 10-bit check bit, the total codeword length of the data block to be encoded is 180 bits. Alternatively, if the length k of the data block to be encoded is 170 bits, and after adding a 9-bit check bit, the total codeword length of the data block to be encoded is 179 bits. Alternatively, if the length k of the data block to be encoded is 170 bits, and after adding an 11-bit check bit, the total codeword length of the data block to be encoded is 181 bits. Alternatively, if the length k of the data block to be encoded is 120 bits, and after adding an 8-bit check bit, the total codeword length of the data block to be encoded is 128 bits, and so on. This is only used as an example for illustration and is not specifically limited in this application.

[0089] In other possible examples, different processing operations can be performed on the m first data streams at the PMA layer to obtain z second data streams. For example, these z second data streams can be obtained by directly demultiplexing the m first data streams; or by further delaying and multiplexing the demultiplexed data streams; or by multiplexing data streams derived from different RS encoding processes. The following will describe in detail different embodiments:

[0090] (1) Direct demultiplexing processing to obtain z second data streams.

[0091] In some optional examples, m first data streams are processed to obtain z second data streams by demultiplexing the m first data streams according to a second ratio to obtain z second data streams, where the second ratio is the reciprocal of the first ratio.

[0092] In this example, the second ratio is the ratio of m to z, and is the reciprocal of the first ratio. After the PMA layer obtains m first data streams through m input channels, it can directly demultiplex according to the second ratio to obtain data streams with the same number of physical coding sublayer channels, that is, z second data streams. For example, if the first ratio is 16:4, the second ratio should be 4:16. After obtaining 4 first data streams through 4 input channels, 16 second data streams can be demultiplexed according to the second ratio of 4:16. It should be noted that the bit length of each of the z second data streams is (N×codeword length of RS codeword) / z bits.

[0093] See Figure 4A , is a schematic diagram of a data stream transmission provided by an embodiment of the present application. Figure 4A As can be seen, in the PMA layer, after acquiring m first data streams through m input channels, a first demultiplexing process is performed on the m first data streams according to a second ratio (e.g., m / z) to obtain z second data streams. It should be noted that the first demultiplexing process may include, but is not limited to, DeMUX. Then, an inner-FEC sublayer independently performs inner-coding processing on each of the z demultiplexed second data streams. For details, please refer to the description of subsequent step 303 and will not be repeated here. Then, the z third data streams are multiplexed to obtain n fourth data streams. For details, please refer to the description of subsequent step 304 and will not be repeated here.

[0094] (2) The data stream obtained by the demultiplexing process is further delayed and multiplexed to obtain z second data streams.

[0095] In some optional examples, m first data streams are demultiplexed at the PMA layer according to a second ratio to obtain z second data streams. Alternatively, the following method may be employed: m first data streams are demultiplexed according to the second ratio to obtain z fifth data streams. Then, each of the z fifth data streams is subjected to Q-level processing to obtain z second data streams. Each level of the Q-level processing includes performing round-robin distribution processing on the data stream obtained at the previous level to obtain at least two sub-data streams, performing delay processing on the first sub-data stream to obtain a sixth data stream, and multiplexing the second sub-data stream and the sixth data stream to obtain an output data stream after processing at the current level. The first sub-data stream is at least one of the at least two sub-data streams, and the second sub-data stream is one of the at least two sub-data streams that has not been subjected to delay processing. Q is a positive integer, and the second data stream is the data stream after Q-level processing.

[0096] In this example, m first data streams are demultiplexed according to the second ratio to obtain z fifth data streams (eg, G1, G2, ..., G z ), please refer to the above Figure 4A Demultiplexing obtains the z-way second data stream for understanding, which will not be described in detail here.

[0097] Taking one of the fifth data streams (e.g., G1) as an example, the PMA layer performs first-level round-robin processing on the previously acquired data stream to obtain at least two sub-data streams. At least one of these sub-data streams is then delayed to obtain the first-level sixth data stream. It should be noted that the previously acquired data stream is obtained by sequentially performing round-robin processing, delay processing, and multiplexing on the previous fifth data stream. The previously acquired data stream input to the first-level round-robin processing can be understood as the fifth data stream G1. The previously acquired data stream input to the second-level round-robin processing can be understood as the output data stream after the first-level first multiplexing processing. Then, the sub-data stream (i.e., the second sub-data stream) of the at least two sub-data streams that has not undergone delay processing is multiplexed with the first-level sixth data stream to obtain the output data stream after this level of processing. This process continues in this manner until the Qth level of processing is performed, resulting in a corresponding second data stream, i.e., the second data stream is the data stream after Q-level processing.

[0098] It should be noted that the Q-level processing described above can be understood as Q-level cascade processing or Q-level iterative processing. Figure 4B-4D The Q-level iterative process can refer to the subsequent Figure 4E The following will explain the present invention from different embodiments.

[0099] 1) Q-level cascade processing

[0100] Figure 4B Another schematic diagram of data stream transmission provided in the embodiment of the present application. Figure 4B It can be seen that in the above Figure 4ABased on the structure shown, in the inner code sublayer, the first m-way first data stream is first processed by the first demultiplexing process to obtain the z-way fifth data stream. Then, the z-way fifth data stream is processed together by the Q-level round-robin distribution process, the Q-level first delay process and the Q-level first multiplexing process to obtain the z-way second data stream. Specifically, after the first demultiplexing process demultiplexes the z-way fifth data stream, it can transmit the z-way fifth data stream to the first-level round-robin distribution process through the z-way physical medium additional sublayer channel. It should be noted that the data stream obtained the previous time input to the first-level round-robin distribution process can be understood as the fifth data stream. In addition, the bit length of each level of processing in the Q-level cascade processing is (N×codeword length of RS codeword) / z bits.

[0101] Taking one of the fifth data streams (e.g., G1) as an example, the fifth data stream G1 is used as the input of the first-level round-robin distribution process, and the first-level round-robin distribution process is used to perform round-robin distribution processing on the fifth data stream G1 to obtain at least two first-level sub-data streams (e.g., G 11 1 , G 12 1 , G 13 1 , G 14 1 etc.). 11 1 and G 12 1 For example, one of the first-level sub-data streams (such as G 11 1 ) as the input of the first-stage first delay processing, and the sub-data stream G is processed by the first-stage first delay processing. 11 1 Delay processing is performed to output a first-level sixth data stream (for example: J1 1 ). Then, the first-level sixth data stream J1 1 and another first-level sub-data stream G 12 1 As the input of the first-stage first multiplexing process, the first-stage sixth data stream J1 is processed by the first-stage first multiplexing process. 1 and another data stream G 12 1 After multiplexing, the first-level output data stream (for example, P1 1 ). It should be noted that the G 11 1 It can be understood as the first sub-data stream described above, the G 12 1 It can be understood as the second sub-data stream described above.

[0102] Then, the first-level output data stream P1 1 As the input of the second-stage round-robin distribution process, the first-stage output data stream P1 is processed by the second-stage round-robin distribution process. 1 Perform round-robin distribution processing to obtain at least two second-level sub-data streams (for example: G 11 2 , G 12 2 , G 13 2 , G 14 2 etc.). 11 2 and G 12 2 For example, one of the sub-data streams (such as: G 11 2 ) as the input of the second-stage first delay processing, and the sub-data stream G is processed by the second-stage first delay processing. 11 2 Perform delay processing to obtain a second-level sixth data stream (for example: J1 2 ). At this time, the second level sixth data stream J1 2 and another second-level sub-data stream G 12 2 As the input of the second-level second multiplexing process, through the multiplexing process of the second-level second multiplexing process, a second-level output data stream (for example: P1 2 ).

[0103] And so on, until the Q-1 level output data stream (for example: P1 Q-1 ) performs the Q-level round-robin distribution processing, and the Q-level can obtain at least two Q-level sub-data streams (for example: G 11 Q , G 12 Q , G 13 Q , G 14 Q etc.). 11 Q and G 12 Q For example, one of the Q-level sub-data streams (such as: G 11 Q ) as the input of the Q-th level first delay process, and the Q-th level sub-data stream G is processed by the Q-th level first delay process. 11 Q Delay processing is performed to output a Q-level sixth data stream (for example: J1 Q). Then, the Q-th level sixth data stream J1 Q and another Q-level sub-data stream G 12 Q As the input of the Q-th level first multiplexing process, the Q-th level sixth data stream J1 is processed by the Q-th level first multiplexing process. Q and another Q-level sub-data stream G 12 Q By performing the multiplexing process, a data stream that is ultimately input into the encoding process, namely the second data stream (eg, F1), can be obtained.

[0104] Similarly, for the fifth data streams of the remaining paths (eg, G2, ... G z ), or they can be processed through the corresponding Q-level first delay processing and Q-level first multiplexing processing to obtain the corresponding second data stream. The specific processing process can be understood by referring to the processing process of the fifth data stream G1, which will not be described here.

[0105] Then, in the inner code sublayer, the resulting z second data streams are independently inner-coded to obtain the corresponding z third data streams. For details, refer to the subsequent description of step 303 and are not further elaborated here. Then, these z third data streams are multiplexed to obtain n fourth data streams. For details, refer to the subsequent description of step 304 and are not further elaborated here.

[0106] It should be noted that in the process of performing any level of round-robin distribution processing, the data stream input by the round-robin distribution processing at this level can be subjected to round-robin distribution processing with a granularity of U bits. The mentioned U = w × N × (the bit length of a symbol in the RS code word), w is a positive integer greater than or equal to 1. For example, taking the aforementioned first-level round-robin distribution processing as an example, if a fifth data stream (such as G1) contains 4 RS code words, a total of 136 symbols, and the bit length of each symbol is 10 bits. At this time, when w = 2, the granularity U = 80 bits. The sub-data stream G obtained after the round-robin distribution processing 11 1 , G 12 1 The length of each is 680 bits.

[0107] It should be noted that each stage of the first multiplexing process in the aforementioned Q-stage first multiplexing process may include, but is not limited to, a symbol multiplexing unit (symbol MUX) or a bit multiplexing unit (bit MUX). Each stage of the first delay unit in the described Q-stage first delay process may also be understood as a buffer unit.

[0108] For example, Figure 4C Another schematic diagram of data stream transmission provided by the embodiment of the present application is shown. Figure 4C As shown, taking Q=1, z=16 as an example, after the 4-way first data stream undergoes the first demultiplexing process, 16-way fifth data streams (eg, G1, G2, ... G 16 ). With the fifth data stream G 16 For example, in the inner code sublayer, the fifth data stream G 16 As the input of the first-level round-robin distribution process, the fifth data stream G1 is subjected to round-robin distribution processing by the first-level round-robin distribution process to obtain at least two first-level sub-data streams (for example: G 161 1 , G 162 1 , G 163 1 , G 164 1 etc.). 161 1 and G 162 1 For example, one of the first-level sub-data streams (such as G 161 1 ) as the input of the first-stage first delay processing, and the sub-data stream G is processed by the first-stage first delay processing. 161 1 Delay processing is performed to output a first-level sixth data stream (for example: J 16 1 ). Then, the first-level sixth data stream J 16 1 and another first-level sub-data stream G 162 1 As the input of the first-stage first multiplexing process, the first-stage sixth data stream J is processed by the first-stage first multiplexing process. 161 1 and another data stream G 162 1 After multiplexing, the data stream that is finally input into the encoding process can be obtained, that is, the second data stream F 16 Then, the second data stream F after the multiplexing process is processed 16 The inner code encoding process is performed, and the details can be understood by referring to the content described in the subsequent step 303, which will not be described here. 15 The processing process can also refer to the G 16 The processing process can be understood through the , which will not be described here.

[0109] Alternatively, see Figure 4D, shows another schematic diagram of data stream transmission provided by an embodiment of the present application. Figure 4D As shown, taking Q=2, z=16 as an example, after the 4-way first data stream undergoes the first demultiplexing process, 16-way fifth data streams (eg, G1, G2, ... G 16 ). With the fifth data stream G 16 For example, the fifth data stream G 16 As the input of the first-level round-robin distribution process, the fifth data stream G1 is subjected to round-robin distribution processing by the first-level round-robin distribution process to obtain at least two first-level sub-data streams (for example: G 161 1 , G 162 1 , G 163 1 , G 164 1 etc.). 161 1 and G 162 1 For example, one of the first-level sub-data streams (such as G 161 1 ) as the input of the first-stage first delay processing, and the sub-data stream G is processed by the first-stage first delay processing. 161 1 Delay processing is performed to output a first-level sixth data stream (for example: J 16 1 ). Then, the first-level sixth data stream J 16 1 and another first-level sub-data stream G 162 1 As the input of the first-stage first multiplexing process, the first-stage sixth data stream J is processed by the first-stage first multiplexing process. 161 1 and another data stream G 162 1 After multiplexing, the first-level output data stream (e.g., P 16 1 ). Further, the first-level output data stream P 16 1 As the input of the second-stage round-robin distribution process, the first-stage output data stream P1 is processed by the second-stage round-robin distribution process. 1 Perform round-robin distribution processing to obtain at least two second-level sub-data streams (for example: G 161 2 , G 162 2 , G 163 2 , G 1642 etc.). 161 2 and G 162 2 For example, one of the sub-data streams (such as G 161 2 ) as the input of the first-stage first delay processing, and the sub-data stream G is processed by the first-stage first delay processing. 161 2 Perform delay processing to obtain a second-level sixth data stream (for example: J 16 2 ). At this time, the second level sixth data stream J 16 2 and another second-level sub-data stream G 162 2 As the input of the second-stage second multiplexing process, the second-stage second multiplexing process finally outputs a data stream that is finally input into the encoding process, that is, the second data stream, such as F 16 It should be noted that, then, the second data stream after the z-way multiplexing process is subjected to inner code encoding. For details, please refer to the content described in the subsequent step 303, which will not be described here.

[0110] Exemplarily, the number of bits of the sixth data stream described above is at least (N×codeword length of RS codeword) / (z×i) bits, where N is a positive integer and i is the number of sub-data streams. Figure 4C For example, when Q=1, if the number of sub-data streams obtained after the first-level round-robin distribution process is 4, then the first-level sub-data stream (such as G 161 1 , G 162 1 , G 163 1 , G 164 1 ) is (N×codeword length of RS codeword) / (z×4). Then the first-level sixth data stream J 16 1 The bit length of is at least (N×codeword length of RS codeword) / (z×4) bits.

[0111] It should be understood that the above Figure 4C Taking the first level as an example, Figure 4D In practical applications, the value of Q can be any integer greater than or equal to 1, and the specific value can be determined according to the needs and is not limited here.

[0112] 2) Q-level iterative processing

[0113] Figure 4E Another schematic diagram of data stream transmission provided in the embodiment of the present application. Figure 4E It can be seen that in the above Figure 4A Based on the structure shown, in the inner code sublayer, m first data streams are first demultiplexed to obtain z fifth data streams. Then, these z fifth data streams are respectively subjected to Q-level iterative processing to obtain z second data streams.

[0114] Specifically, after the first demultiplexing process obtains the z fifth data streams through demultiplexing, it can transmit these z fifth data streams to the first-level round-robin distribution process via z physical medium additional sublayer channels. It should be noted that the previously acquired data stream input to the first-level round-robin distribution process can be understood as the fifth data stream. Furthermore, the bit length of each stage of the Q-level iterative processing is (N × codeword length of the RS codeword) / z bits.

[0115] Taking one of the fifth data streams (e.g., G1) as an example, the fifth data stream G1 is used as the input of the first-level round-robin distribution process, and the first-level round-robin distribution process is used to perform round-robin distribution processing on the fifth data stream G1 to obtain at least two first-level sub-data streams (e.g., G 11 1 , G 12 1 etc.). 11 1 and G 12 1 For example, one of the first-level sub-data streams (such as G 11 1 ) as the input of the first-stage first delay processing, and the sub-data stream G is processed by the first-stage first delay processing. 11 1 Delay processing is performed to output a first-level sixth data stream (for example: J1 1 ). Then, the first-level sixth data stream J1 1 and another first-level sub-data stream G 12 1 As the input of the first-stage first multiplexing process, the first-stage sixth data stream J1 is processed by the first-stage first multiplexing process. 1 and another data stream G 12 1 After multiplexing, the first-level output data stream (for example, P1 1 ). It should be noted that the G 11 1 It can be understood as the first sub-data stream described above, the G 12 1It can be understood as the second sub-data stream described above.

[0116] Then, the first-level output data stream P1 1 Continue to serve as the input of the first-level round-robin distribution process, and continue to process the first-level output data stream P1 through the first-level round-robin distribution process. 1 Perform round-robin distribution processing to obtain at least two second-level sub-data streams (for example: G 11 2 , G 12 2 etc.). 11 2 and G 12 2 For example, one of the sub-data streams (such as G 11 2 ) continues to be the input of the first stage first delay process, through which the sub-data stream G is processed. 11 2 Perform delay processing to obtain a second-level sixth data stream (for example: J1 2 ). At this time, the second level sixth data stream J1 2 and another second-level sub-data stream G 12 2 Continue to serve as the input of the first-level second multiplexing process, and through the multiplexing process of the first-level second multiplexing process, a second-level output data stream can be obtained (for example: P1 2 ).

[0117] And so on, until the Q-1 level output data stream (for example: P1 Q-1 ) performs the Q-level round-robin distribution processing, and the Q-level can obtain at least two Q-level sub-data streams (for example: G 11 Q , G 12 Q etc.). 11 Q and G 12 Q For example, one of the Q-level sub-data streams (such as: G 11 Q ) continues to be the input of the first-stage first delay processing, and the Q-th stage sub-data stream G is processed by the first-stage first delay processing. 11 Q Delay processing is performed to output a Q-level sixth data stream (for example: J1 Q ). Then, the Q-th level sixth data stream J1 Q and another Q-level sub-data stream G 12 QAs the input of the first-stage first multiplexing process, the Q-stage sixth data stream J1 is processed by the first-stage first multiplexing process. Q and another Q-level sub-data stream G 12 Q By performing multiplexing processing, a second data stream (for example, F1) can be obtained.

[0118] Similarly, for the fifth data streams of the remaining paths (eg, G2, ... G z ), or the corresponding Q-level iterative processing can be performed to obtain the corresponding second data stream. The specific processing process can be understood by referring to the processing process of the fifth data stream G1, which will not be described here.

[0119] Then, in the inner code sublayer, the resulting z second data streams are independently inner-coded to obtain the corresponding z third data streams. For details, refer to the subsequent description of step 303 and are not further elaborated here. Then, these z third data streams are multiplexed to obtain n fourth data streams. For details, refer to the subsequent description of step 304 and are not further elaborated here.

[0120] It should be noted that the bit length of the sixth data stream obtained in the Q-level iterative processing can also be understood with reference to the bit length of the sixth data stream obtained in the aforementioned Q-level cascade processing, which will not be elaborated here.

[0121] (3) Multiplexing the data streams obtained from different RS encoding processes to obtain z second data streams.

[0122] In some optional examples, the encoding method may also include: obtaining m-way seventh data streams through m-way first input channels; demultiplexing the m-way seventh data streams according to the second ratio to obtain z-way eighth data streams; processing the m-way first data streams to obtain z-way second data streams, including: multiplexing the z-way second data streams and the z-way eighth data streams to obtain the multiplexed z-way second data streams.

[0123] In this example, the m-channel seventh data stream is obtained by multiplexing the z-channel data stream after RS encoding at the first ratio. For details, refer to the m-channel first data stream in step 301 above and will not be further described here. At the PCS layer, the data stream obtained from the MAC module is divided into two equal data streams. For each z-channel data stream, the PCS layer sequentially performs 64B / 66B encoding, 256B / 257B transcoding, alignment marker insertion, and RS encoding. The two RS-encoded z-channel data streams are then multiplexed at the first ratio to obtain the m-channel first data stream and the m-channel seventh data stream. The PCS layer then transmits the m-channel first data stream to the PMA layer via the m-channel output channels and transmits the m-channel seventh data stream to the PMA layer via the m-channel first output channels. In this way, after the PMA layer receives the m-way first data stream sent by the PCS layer through the m-way input channel, it demultiplexes the m-way first data stream according to the second ratio to obtain the z-way second data stream. Figure 4A Furthermore, after receiving the m-way seventh data stream through the m-way first input channel, the PMA layer also demultiplexes the m-way seventh data stream according to the second ratio to obtain the B-way eighth data stream. For details, please refer to the aforementioned Figure 4A Then, the PMA layer can multiplex the z-way second data stream and the z-way eighth data stream to obtain the multiplexed z-way second data stream.

[0124] For example, Figure 4F Another schematic diagram of data stream transmission provided by an embodiment of the present application is shown. Figure 4F It can be seen that in the above Figure 4A Based on the structure shown in FIG. 1 , in the PMA layer, the m seventh data streams are first demultiplexed according to the second ratio to obtain z eighth data streams. Then, in the inner code sublayer of the PMA layer, the z second data streams and the z eighth data streams are multiplexed to obtain z second data streams after multiplexing. For example, taking z = 16, the 16 second data streams are represented as F1, F2, ..., F 16 , these 16 eighth data streams are represented as W1, W2, ..., W 16. The second data stream F1 and the eighth data stream W1 can be subjected to a second multiplexing process to obtain a second data stream after processing. Similarly, the second data stream F2 and the eighth data stream W2 can also be subjected to a second multiplexing process to obtain another second data stream after processing. And so on, 16 second data streams after multiplexing can be obtained. Then, the z second data streams after multiplexing are subjected to inner code encoding processing. For details, please refer to the content described in the subsequent step 303, which will not be described here.

[0125] In some possible examples, after multiplexing the z-way second data stream and the z-way eighth data stream to obtain the multiplexed z-way second data stream, the encoding method may further include: independently performing Q-level processing on each of the multiplexed z-way second data streams to obtain a z-way twelfth data stream; wherein each level of processing in the Q-level processing includes performing round-robin distribution processing on the data stream obtained at the previous level to obtain at least two sub-data streams, and delaying the fifth sub-data stream to obtain a thirteenth data stream, and multiplexing the sixth sub-data stream and the thirteenth data stream to obtain the output data stream after processing at this level, the fifth sub-data stream is at least one sub-data stream among the at least two sub-data streams, the sixth sub-data stream is a sub-data stream among the at least two sub-data streams that has not been delayed, Q is a positive integer, and the multiplexed second data stream is a Q-level processed data stream; each of the z-way twelfth data streams is independently encoded to obtain a z-way third data stream.

[0126] It should be noted that, here, each of the z second data streams after the multiplexing process is independently subjected to Q-level processing. The specific process of this Q-level processing can be understood with reference to the content described in (2) above, and will not be described in detail here. In addition, each of the z twelfth data streams is independently subjected to encoding processing. The specific process can also be understood with reference to the content described in the subsequent step 303, and will not be described in detail here.

[0127] The bit length of the above-mentioned thirteenth data stream is at least (N×codeword length of RS codeword) / (z×i) bits, where N is a positive integer and i is the number of the sub-data streams. The specific understanding can also be made by referring to the sixth data stream described in (2) above, which will not be repeated here.

[0128] It should be noted that the obtained z-way second data stream can be understood as a data stream that has not undergone data alignment, de-skew, or reordering. In the embodiment of the present application, in addition to processing the m-way first data stream using any of the above methods (1) to (3) to obtain the z-way second data stream, in actual applications, there may be other processing methods, which are not limited here.

[0129] 303. Independently encode each of the z second data streams to obtain z third data streams.

[0130] In this example, C inner code sublayers are instantiated in the PMA layer as an integer multiple of the number of physical coding sublayer channels, i.e., C is an integer multiple of B. Thus, after the PMA layer obtains z second data streams, a one-to-one correspondence is established between C / z inner code sublayers and one second data stream for each second data stream. Furthermore, the C / z inner code sublayers are used independently to perform inner code encoding on the corresponding second data stream to generate a corresponding inner code-encoded data stream, i.e., the third data stream.

[0131] It should be understood that after the inner code encoding process, the z-way third data stream is obtained, which can also be understood as each encoded data stream including FEC codewords. In some possible examples, the inner code sublayer of the present application can also be referred to as the inner-forward error correction (Inner-FEC) coding sublayer. In practical applications, other names can also be used, which are not specifically limited in this application. In addition, the inner code encoding process described can be understood as the second code in the concatenated code, which constitutes a concatenated code with the RS code described in the aforementioned step 301.

[0132] For example, if the second data stream obtained by processing is 16 channels, namely F1, F2, ..., F 16 At this time, in the inner code sublayer of the PMA layer, 16 inner code encoding processing operations are performed respectively, namely H1, H2, ... H 16 Then, the data stream F1 is processed by the inner code encoding operation H1, the data stream F2 is processed by the inner code encoding operation H2, and so on. 16 This inner code encoding operation is performed on the data stream F 16 In other examples, 32 inner code encoding operations can also be performed in the inner code sublayer, namely H1, H2, H3, H4, ... H 31 、H 32 The data stream F1 is processed by the two inner code encoding operations H1 and H2, and the data stream F2 is processed by the two inner code encoding operations H3 and H4, and so on. 31 and H 32 These two inner code encoding operations have an impact on the data stream F 16Inner coding is performed. It should be noted that only 16 and 32 inner coding operations are used as examples for the description here. In actual applications, 64 inner coding operations can be performed in the inner coding sublayer for 16 second data streams, and each second data stream can be inner-coded using four different inner coding operations. Alternatively, 128 inner coding operations can be performed, as long as C is an integer multiple of z. This is not a limitation here.

[0133] Alternatively, if the processed second data stream is 32 channels, namely F1, F2, ..., F 16 ,……,F 31 、F 32 At this time, in the inner code sublayer of the PMA layer, 32 inner code encoding processing operations are performed, namely H1, H2, ... H 32 Then, the data stream F1 is subjected to inner code encoding by the inner code encoding operation H1, and the data stream F2 is subjected to inner code encoding by the inner code encoding operation H2, ..., and so on. 16 This inner code encoding operation is performed on the data stream F 16 Perform internal code encoding, ... and so on, through H 32 This inner code encoding operation is performed on the data stream F 32 In other examples, 64 inner code encoding operations can also be performed in the inner code sublayer, namely H1, H2, H3, H4, ... H 31 、H 64 , and perform inner code encoding on data stream F1 through the two inner code sublayers H1 and H2, and perform inner code encoding on data stream F2 through the two inner code encoding operations H3 and H4, and so on. 63 and H 64 These two inner code encoding operations have an impact on the data stream F 32 Inner coding is performed. Note that this description uses the example of performing 32 or 64 inner coding operations in the inner coding sublayer. In actual applications, 128 inner coding operations may be performed for 32 second data streams, and inner coding may be performed on each second data stream using four different inner coding operations. This is not a limitation here.

[0134] It should be noted that the above description only uses 16-way second data streams and 32-way second data streams as examples. In actual applications, other z-way second data streams may also be included. The value of z depends on the requirements and is not limited here.

[0135] In some possible examples, the inner coding process can actually be understood as performing inner coding on the data blocks to be encoded in the second data stream, and in order to enable the decoding sublayer to directly determine the boundary position of each codeword in the subsequent decoding process to improve decoding accuracy, different methods can be used for inner coding in different scenarios. For example, the following two methods can be used for understanding:

[0136] 1) Encoding a first data block to obtain an FEC codeword, where the first data block corresponds to at least C / z consecutive data blocks to be encoded in the second data stream, where C is a positive integer and C is an integer multiple of z; inserting a first marker at a codeword boundary position of any FEC codeword in the FEC codeword, where the first marker is used to identify the codeword boundary of the FEC codeword, and a throughput rate or a baud rate of the FEC codeword after inserting the first marker is an integer multiple of a reference clock.

[0137] In this example, the first data block is at least C / z consecutive data blocks to be encoded in the corresponding second data stream, or can be understood as consisting of C / z consecutive data blocks to be encoded. Moreover, the length of the first data block is the sum of the lengths of these C / z consecutive data blocks to be encoded. For example, for each second data stream, a total of Y data blocks to be encoded are included, namely I1, I2, ..., I Y If the data blocks to be coded are I1, I2, ..., I Y The length of each is k, then when the first data block is I1, the length of the corresponding first data block is k. Similarly, when the first data block is composed of I1 and I2, the length of the corresponding first data block is 2k. It should be noted that the above only uses I1, I2, ..., I Y The length of each block is k, which is used as an example for illustration. In practical applications, the length of each data block to be encoded may also be different, which is not limited here.

[0138] In addition, the number of obtained FEC codewords is related to the number of data blocks to be encoded that constitute the first data block.

[0139] For example, if the second data stream obtained by processing is 16 channels, namely F1, F2, ..., F 16 Then, for the second data stream F1, there are a total of Y data blocks to be encoded, namely I1, I2, ..., I Y If at this time, 16 inner code encoding processing operations are performed in the inner code sublayer, namely H1, H2, ... H 16 , then the first data block can be understood as I1, I2, ..., I YOne of the Y data blocks to be encoded. In this way, each inner code encoding operation can be performed on one of the first data blocks to obtain a corresponding FEC codeword. At this time, the FEC codeword obtained by each inner code encoding operation is one. For example, Figure 5A Schematic diagram of the inner code encoding operation performed in the embodiment of the present application. Figure 5A It can be seen that the inner coding processing operation H1 can be performed on the data block to be coded I1 (for example, k bits) in the second data stream F1, and an FEC codeword (for example, FEC codeword 1) can be obtained. The inner coding processing operation H2 can be performed on the data block to be coded I2 in the second data stream F2, and an FEC codeword can be obtained. And so on, the inner coding processing operation H1 can be performed on the data block to be coded I2 in the second data stream F2, and an FEC codeword can be obtained. 16 The second data stream F 16 The data block to be encoded I 16 Perform inner code encoding, and one FEC codeword can be obtained at this time. It should be noted that in this application, only the inner code encoding operation H1 is used to perform inner code encoding on the coded data block I1 as an example. In actual applications, the inner code encoding operation H1 can also perform inner code encoding on the coded data block I2 or I3, etc., and this is not limited here. In addition, the remaining inner code encoding operations can also be understood with reference to the inner code encoding operation H1, and will not be described in detail here. In addition, the remaining second data streams F2, ..., F 16 In fact, it can also be understood by referring to the second data stream F1, which will not be described here.

[0140] Alternatively, if the second data stream obtained by processing is still 16-channel, but 32 inner code encoding processing operations are performed in the inner code sublayer, then the first data block can be understood as I1, I2, ..., I Y At least two consecutive data blocks to be encoded among the Y data blocks to be encoded. For example, the first data block can be composed of I1 and I2, or I3 and I4, etc., which is not limited here. Figure 5B This is another schematic diagram of performing inner code encoding processing operations in the embodiment of the present application. Figure 5B It can be seen that the inner coding processing operations H1 and H2 can be performed on the first data block (for example, k+k bits) composed of I1 and I2 in the second data stream F1, and two FEC codewords (for example, FEC codeword 1 and FEC codeword 2) can be obtained. The inner coding processing operations H3 and H4 can be performed on the first data block composed of I3 and I4 in the second data stream F2, and two FEC codewords can be obtained. And so on, the inner coding processing operations H1 and H2 can be performed on the first data block (for example, k+k bits) composed of I1 and I2 in the second data stream F1, and two FEC codewords can be obtained. 31 and H32 The second data stream F 16 In, by I 31 and I 32 It should be noted that in this application, only the inner coding operation H1 is used to perform inner coding on the first data block composed of I1 and I2 as an example. In actual applications, the inner coding operations H1 and H2 can also be performed on the first data block composed of I3 and I4 in the second data stream F1, or on the first data block composed of I3 and I4 in the second data stream F1. 31 and I 32 The first data block composed of the inner code encoding process is processed, which is not limited here. In addition, the remaining inner code encoding process operations can also be understood with reference to the inner code encoding process operation H1, which is not described here. In addition, the remaining second data streams F2, ..., F 16 In fact, it can also be understood by referring to the second data stream F1, which will not be described here.

[0141] Alternatively, if the processed second data stream is still 16-channel, 64 inner code encoding processing operations can also be performed in the inner code sublayer, and the first data block can be understood as I1, I2, ..., I Y Four consecutive data blocks to be encoded among the Y data blocks to be encoded. For example: the first data block can be composed of I1, I2, I3 and I4, or it can be composed of I5, I6, I7 and I8, and so on, which is not limited here. At this time, executing the inner code encoding processing operations H1 to H4 can perform inner code encoding processing on the first data block (for example: k+k+k+k bits) composed of I1, I2, I3 and I4 in the second data stream F1, and at this time 4 FEC code words can be obtained. Executing the inner code encoding processing operations H5 to H8 can perform inner code encoding processing on the first data block composed of I5, I6, I7 and I8 in the second data stream F2, and at this time 4 FEC code words can be obtained; ... and so on, executing the inner code encoding processing operations H 61 To H 64 The second data stream F 16 In, by I 61 , I 62 , I 63 and I 64It should be noted that in this application, only the inner coding operations H1 to H4 are used to perform inner coding on the first data block composed of I1, I2, I3 and I4 in the second data stream F1. In actual applications, the inner coding operations H1 to H4 can also be performed on the first data block composed of I5, I6, I7 and I8 in the second data stream F1, or the first data block composed of I 61 , I 62 , I 63 and I 64 The first data block composed of the inner code encoding process is processed, which is not limited here. In addition, the remaining inner code encoding process operations can also be understood with reference to the inner code encoding process operation H1, which is not described here. In addition, the remaining second data streams F2, ..., F 16 In fact, it can also be understood by referring to the second data stream F1, which will not be described here.

[0142] It should be noted that the above only takes B=16 as an example. In actual applications, it can also be 32-way second data streams, 64-way second data streams, etc. The specific details can be understood by referring to the content of the aforementioned 16-way second data streams, which will not be repeated here.

[0143] In this way, after obtaining the FEC codeword, the first identifier can be inserted into the codeword boundary position of any FEC codeword in the FEC codeword. Figure 5A As shown, the first marker can be inserted into the codeword boundary position of the FEC codeword (for example, FEC codeword 1) obtained by performing the inner code encoding operation H1. Alternatively, as described above Figure 5B As shown, the first marker can also be inserted at the codeword boundary of any one of the two FEC codewords (e.g., FEC codeword 1 and FEC codeword 2) obtained by performing the inner code encoding operation H1. For example, the first marker can be inserted at the codeword boundary of FEC codeword 1, or at the codeword boundary of FEC codeword 2, etc., without limitation herein. It should be noted that inserting the first marker at the codeword boundary of any one of the FEC codewords can also be understood as inserting a first marker every C / z FEC codewords.

[0144] It should be noted that the throughput or baud rate of the FEC codeword after the first identifier is inserted is an integer multiple of the reference clock. For example, if the data transmission rate is expressed as throughput, assuming the data stream throughput in the PCS layer is 850 Gbps, then the throughput of the FEC codeword after the first identifier is inserted can be 910 Gbps. Alternatively, if the data transmission rate is expressed as baud rate, the baud rate of each physical coding sublayer channel in the PCS layer is 26.5625 Gbaud. After inner coding, the total length of the resulting FEC codeword is 180 bits. After inserting the first identifier, the total length of the FEC codeword after the first identifier is inserted can be increased to 182 bits. At this time, the baud rate of each physical coding sublayer channel becomes 28.4375 Gbaud. For another example, assuming the data stream throughput in the PCS layer is 850 Gbps, then the throughput of the FEC codeword after the first identifier is inserted can be 900 Gbps. Alternatively, when the data transmission rate is expressed in baud rate, the baud rate of each physical coding sublayer channel in the PCS layer is 26.5625 Gbaud. After inner coding, the total length of the FEC codeword is 179 bits. After inserting the first identifier, the total length of the FEC codeword after the first identifier is inserted can become 180 bits. At this time, the baud rate of each corresponding physical coding sublayer channel becomes 28.125 Gbaud.

[0145] Here, only the throughput rate of 850Gbps and the baud rate of 26.5625Gbaud are used as examples for illustration. In actual applications, the transmission rate of the data stream in the PCS layer should be related to the load of the RS codeword. In addition, here, only the throughput rates of the FEC codewords after inserting the first identifier are 910Gbps and 900Gbps as examples, and only the baud rate of each physical coding sublayer channel is changed to 26.5625Gbaud and 28.125Gbaud as examples for illustration. This application does not make specific limitations. The reference clock described can be understood as 156.25 megahertz (MHz). In actual applications, it may also have other values, which are not limited here.

[0146] The reference clock represents the frequency of data transmission, that is, the number of times a data stream can be transmitted per second. Both baud rate and throughput rate indicate the transmission rate of a data stream. Throughput rate represents the number of bits transmitted per second, while baud rate represents the number of symbols transmitted per second. For example, if five symbols can be transmitted at a time and 10 transmissions can be made per second, a total of 50 symbols can be transmitted per second.

[0147] In addition, the codeword boundary position can be understood as the codeword beginning and / or codeword end, which is not limited here. By using the first identifier to identify the codeword boundary of the FEC codeword, the first identifier can be directly identified in the subsequent decoding process, so that the boundary position of each FEC codeword can be clearly determined, thereby avoiding the situation where inner code decoding fails in the case of delay skew and unknown data starting position.

[0148] It should be understood that the first identifier mentioned above may be a preset identifier sequence, or may be obtained according to the bit value of the first data block.

[0149] ①The first identifier is a preset identifier sequence.

[0150] In this example, the first identifier can be a sequence of "1" and "0", or other known sequences, which are not limited here. Figure 6A This is a schematic diagram of inserting a first identifier provided in an embodiment of the present application. Figure 6A As shown, the first identifier, a sequence of "1"s and "0"s, is added to the beginning of the FEC codeword. This first identifier occupies two bits. Therefore, after adding the first identifier to the codeword boundary of the FEC codeword, the total length of the codeword increases from n bits to n+2 bits. For example, if the length of the first data block is 170, after inner code encoding, the total length of the FEC codeword is 180. Now, after inserting the first identifier, the length of the entire FEC codeword after the first identifier is inserted becomes 182 bits.

[0151] It should be noted that when the first identifier is a preset identifier sequence, the first identifier can also be selected as a sequence such as "101010", "1010", etc., which is not limited here.

[0152] ② The first identifier is obtained based on the bit value of the first data block.

[0153] In this example, different first identifiers can be obtained for different bit values in the first data block. Specifically, the first identifier can be determined in the following two ways:

[0154] The first method: the first identifier is obtained according to the value of the first bit of the first data block. It should be noted that the first bit is any one of the at least one bit in the first data block.

[0155] For example, Figure 6B A schematic diagram showing a method for obtaining a value of a first identifier provided in an embodiment of the present application is shown. Figure 6BIt can be seen that the first bit can be the 0th bit in the first data block. If the value of the 0th bit is "0", the first identifier, i.e., "1", can be obtained by directly inverting the value of the 0th bit. Alternatively, if the value of the 0th bit is "1", the first identifier, i.e., "0", can be obtained by directly inverting the value of the 0th bit. The specifics are not limited here. In addition, Figure 6B For this explanation, we'll use bit 0 as the first bit. In practice, the first bit can also be bit 1, bit 2, or similar in the first data block, without limitation. For example, if the first data block is 180 bits long, the last bit can be inverted, that is, the value of bit 179 can be directly inverted to obtain the first identifier. Obtaining the first identifier by inverting the bits at the very beginning or very end of the first data block helps the PMA layer at the receiving end more quickly determine codeword boundaries.

[0156] The second method: The first identifier is obtained based on the bit values of at least L second bits in the first data block, wherein there are s bits between each two adjacent second bits of the L second bits, L≥2, s≥0, and L and s are integers.

[0157] In this example, in the first data block, a second bit is selected every s bits, and a total of L second bits are selected. In this way, the first identifier can be obtained by processing these L second bits through an exclusive-OR operation, an OR operation, or an AND operation.

[0158] For example, Figure 6C A schematic diagram showing another method for obtaining the value of the first identifier provided in an embodiment of the present application is shown. Figure 6C It can be seen that when L = 4 and s = 2, the four second bits selected from the first data block are bit 0, bit 2, bit 4, and bit 6, respectively. Thus, the bit values corresponding to bit 0, bit 2, bit 4, and bit 6 are processed through an XOR operation, and the result of the processing can be used as the first identifier. It should be noted that in some examples, the four second bits selected can also be bit 1, bit 3, bit 5, bit 7, etc., and this is not limited here.

[0159] Need to explain, Figure 6C The following description only takes L being 4 and s being 2 as an example. In practical applications, L may also be 8 and s may be 3, or L may be 6 and s may be 4, etc. The present application does not limit the value of L or the value of s.

[0160] In addition, in addition to the above-mentioned ① and ② to determine the first identifier, there may be other ways to clarify the first identifier in actual applications, which are not specifically limited in this application.

[0161] The above 1) mainly describes the solution of first performing inner code encoding on the first data block and then inserting the first identifier. The following describes the solution of also participating in the inner code encoding of the first identifier. The details are as follows:

[0162] 2) Inserting a first identifier into each data block to be encoded in the first data block to obtain a second data block, where the first data block is C / z consecutive data blocks to be encoded, where C is a positive integer and C is an integer multiple of z; performing inner coding on the second data block to obtain an FEC codeword. It should be noted that the throughput rate or baud rate of the FEC codeword is an integer multiple of the reference clock.

[0163] In this example, the second data block can be understood as consisting of the first data block and the first identifier, and the length of the second data block is the sum of the length of the first data block and the bits occupied by the first identifier. In this way, the first identifier is inserted into each data block to be encoded in the first data block. For example, Figure 5B In the example where the first data block consists of data blocks I1 and I2 to be encoded, a first identifier can be inserted at the codeword boundary of data block I1, and a first identifier can be inserted at the codeword boundary of data block I2 to be encoded. If the length of the first data block is k (i.e., the first data block occupies k bits) and the first identifier occupies 1 bit, the length of the second data block is k+2 bits.

[0164] For each second data block in the second data stream, the second data block can be subjected to inner coding. This can be understood by referring to the inner coding process for the first data block in 1) above, and is not further described here. Furthermore, the first data block can be understood by referring to the content in 1) above, and is not further described here. Furthermore, the first identifier can also be understood by referring to the content described in ① and ② above, and is not further described here.

[0165] In some other possible examples, the described encoding method may further include: identifying an alignment marker in each second data stream, the alignment marker being used to identify a symbol boundary in the corresponding second data stream; and determining a symbol boundary in the corresponding second data stream based on the alignment marker.

[0166] In this example, the PCS layer adds a common alignment marker of the AM alignment block to each of the m first data streams. After mapping the m first data streams to obtain z second data streams, each second data stream includes a corresponding alignment marker, which identifies the symbol boundary in each second data stream. Therefore, after the PMA layer passes through the aforementioned Figures 4A to 4FAfter processing the m first data streams in any possible way to obtain the z second data streams, the alignment marker included in each second data stream can also be identified. After identifying the corresponding alignment marker, the alignment marker is locked to determine the symbol boundary in the corresponding second data stream. For example, a 120-bit AM alignment block with a known sequence is added to each first data stream, and in this 120-bit AM alignment block with a known sequence, there is a 48-bit public alignment marker. Then, in an operation that only requires the symbol boundary of the RS code word, the alignment can be locked by identifying the 48-bit public alignment marker.

[0167] Then, the z second data streams are independently subjected to inner code encoding processing. Please refer to the contents described in the aforementioned step 303 for detailed understanding, which will not be described here in detail.

[0168] For example, Figure 7 Another schematic diagram of data stream transmission provided in the embodiment of this application. Figure 7 As shown in the aforementioned Figures 4A-4F Based on any of the described embodiments, in the inner code sublayer of the PMA layer, the z second data streams may be aligned and then independently inner code encoded.

[0169] 304. Multiplex the z third data streams to obtain n fourth data streams, where n is a positive integer.

[0170] In this example, after the PMA layer obtains z third data streams, if it wants to send them to the receiving end through n output channels, the PMA layer still needs to multiplex these z third data streams to obtain n fourth data streams, and then transmit these n fourth data streams to the PMA layer at the receiving end through these n output channels.

[0171] Exemplarily, the PMA layer multiplexes z third data streams at a third ratio (i.e., z / n) to obtain n fourth data streams. Alternatively, the PMA layer may first multiplex z third data streams at a fourth ratio (i.e., z / m) to obtain m data streams, and then multiplex these m data streams at a fifth ratio (i.e., m / n) to obtain n fourth data streams. This application does not limit the specific method used. It should be noted that the value of n described herein can be 4, 8, 16, etc., and this is not limited here.

[0172] For example, Figure 8 This is a schematic diagram of the overall transmission of data streams in the PMA layer. Figure 8As shown, z first data streams are acquired through m input channels and demultiplexed according to the ratio m / z, resulting in z PCS lane data streams, or z second data streams. C inner code encoding operations are then performed within the inner code sublayer to independently encode these z PCS lane data streams, yielding z third data streams. Each PCS lane data stream is encoded using C / z inner code encoding operations. These z third data streams are then multiplexed according to the ratio z / n, yielding n fourth data streams, which are then transmitted through n output channels.

[0173] above Figure 3-Figure 8 The encoding method provided by the embodiment of the present application is mainly described. The decoding method provided by the embodiment of the present application will be described below. Figure 9 This is a flowchart of a decoding method provided in an embodiment of the present application. Figure 9 As shown, the decoding method may include the following steps:

[0174] 901. Obtain n fourth data streams through n input channels.

[0175] In this example, after receiving n fourth data streams, the PMA layer at the transmitting end can send these n fourth data streams to the PMD layer. After undergoing optical-to-electrical conversion and other processing at the PMD layer, these n fourth data streams can be transmitted via a transmission medium to the PMD layer at the receiving end. At the receiving end, the PMD layer then converts and processes the signals received from the transmission medium to obtain n fourth data streams. The PMD layer then transmits these n fourth data streams to the PMA layer at the receiving end via n output channels. In this way, the PMA layer can obtain n fourth data streams via n input channels.

[0176] 902. Demultiplex the n fourth data streams to obtain z third data streams.

[0177] After the PMA layer obtains n fourth data streams, it can demultiplex these n fourth data streams according to the inverse of the third ratio to obtain z third data streams. Figure 3 Step 304 in FIG. 1 is understood for simplicity and will not be described in detail here.

[0178] 903. Independently decode each of the z third data streams to obtain z second data streams.

[0179] In this example, the decoding process is as follows Figure 3For the z third data streams, C inner code decoding operations can also be performed in the inner code sublayer, so that the inner code decoding process can be independently performed on the third data stream by performing different C / z inner code decoding operations.

[0180] In some other possible examples, the decoding method may further include: identifying a codeword boundary of the encoded FEC according to the first identifier and / or a decoding flag bit, where the decoding flag bit is used to indicate whether the inner code decoding process is successful.

[0181] Because each of the z third data streams includes a corresponding first identifier, during the decoding process of the corresponding third data stream, the codeword boundary position of the FEC codeword in each third data stream can be determined by identifying the first identifier and / or the decoding flag, further improving decoding efficiency and accuracy. For example, when the PMA layer determines that each identifier value in the first identifier is correct, it can further determine whether the inner code decoding process is successful using the decoding flag. If the decoding flag indicates that the inner code decoding process is successful, the codeword boundary of the FEC codeword is identified based on the first identifier, and then the encoded FEC codeword is decoded.

[0182] It should be noted that identifying the encoded FEC codeword boundary based on the first identifier and / or the decoding flag can be understood in three ways. Specifically, ① the encoded FEC codeword boundary can be identified based on the first identifier; ② the encoded FEC codeword boundary can be identified based on the decoding flag; and ③ the encoded FEC codeword boundary can be identified based on the first identifier and the decoding flag. This application does not specify which method is used. Furthermore, the aforementioned decoding flag may or may not be fed back during the decoding process, which is not a limitation here.

[0183] 904. Multiplex the z second data streams according to the first ratio to obtain m first data streams.

[0184] In this example, after obtaining z second data streams, the PMA layer multiplexes the z second data streams according to a first ratio to obtain m first data streams. For example, when z=16, the first ratio can be 16:4, and the multiplexing process obtains 4 first data streams.

[0185] See Figure 10A , is a transmission diagram of data flow in the decoding process provided by the embodiment of the present application. Figure 10A As can be seen, the n fourth data streams are first demultiplexed to obtain z third data streams. Then, these z third data streams are individually inner-coded in the inner code sublayer to obtain z second data streams. Finally, these z second data streams are processed.

[0186] In other optional examples, after the photoelectric conversion at the PMD layer, an electrical signal is obtained, and the electrical signal first needs to pass through the CDR unit for data and clock recovery. The shorter the time required for the CDR unit to recover the clock and data, the more beneficial it is to the system. Based on this, the decoding method may further include: before identifying the codeword boundary of the FEC codeword based on the first identifier and / or the decoding flag bit, generating a first signal based on the first identifier and / or the decoding flag bit, wherein the first signal is used to determine data clock information.

[0187] Figure 10B Another transmission diagram of data stream in the decoding process provided by the embodiment of the present application is shown. Figure 10B It can be seen that in the above Figure 10A Based on the illustration, before demultiplexing the resulting z third data streams, the n fourth data streams are first subjected to clock and data recovery. The n fourth data streams after clock recovery are then demultiplexed to obtain z third data streams, which are then independently subjected to inner code decoding. It should be noted that the CDR unit uniquely corresponds to the data stream transmitted in the input channel. Since each input channel uniquely corresponds to a physical coding sublayer channel, and each physical coding sublayer channel corresponds to C / z inner code decoding operations, the decoding units connected to each CDR unit are also fixed and can be connected via wires. For example, if the PMD layer has four input channels and the PMA layer has 16 physical coding sublayer channels, and 32 inner code decoding operations can be performed in the inner code sublayer, then each physical coding sublayer channel is connected to two decoding units. During data and clock recovery by the CDR unit, the inner code sublayer can first detect the first identifier and / or decoding flag to generate a feedback signal, i.e., the first signal. At this time, when the CDR unit receives the first signal, it can accelerate the CDR unit's data and clock recovery process, determine the data clock information in advance, and reduce the time required for system lock. In addition, because the first identifier of this application is designed to generate a sequence, it takes into account the autocorrelation characteristics of the sequence corresponding to the first identifier, which helps the first identifier to be detected more quickly; and also takes into account the fixed 0,1 jump characteristics of the first identifier, which improves the convergence speed of the CDR unit's data clock recovery.

[0188] In addition, if the CDR unit receives its own feedback signal for normal data and clock recovery before receiving the first signal, the CDR unit can enter a locked state based on the signal for normal data and clock recovery to complete the data and clock recovery operation.

[0189] In other examples, after obtaining m-channel first data streams, the PMA layer can also send the m-channel first data streams to the PCS layer through m-channel output channels. In this way, after the PCS layer obtains the m-channel first data streams through the m-channel input channels, it demultiplexes the m-channel first data streams according to the second ratio, thereby obtaining z-channel eleventh data streams. It should be noted that the described z-channel eleventh data stream corresponds to the z-channel data stream obtained after RS encoding processing. The PCS layer can also further process the z-channel eleventh data stream in sequence through RS decoding processing, 256B / 257B transcoding processing, and 64B / 66B encoding processing. For details, please refer to the aforementioned Figure 1A Understand.

[0190] Compared to Figure 1A-1B In the existing solution shown, in the embodiment of the present application, each of the z second data streams is independently inner-coded in the PMA layer to obtain z third data streams; and the FEC codewords in each encoded third data stream contain boundary identifiers, which ensures both the decoupling of the inner-coding from the data encoded by the upper PCS layer and the transmission decoupling from the lower PMD layer. This can save processing delay skew and out-of-order delays, making the inner-coding of the present application suitable for scenarios sensitive to transmission delays. In addition, by simply identifying the boundary identifiers in each third data stream, the codeword boundaries of each third data stream can be clearly determined, enabling independent inner-coding decoding of each of the z third data streams, eliminating the need for de-skewing, reordering, and other operations on the data stream, thereby reducing operational complexity and latency.

[0191] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of the method. It can be understood that in order to realize the above functions, the above-mentioned PMA layer includes the corresponding hardware structure and / or software modules for performing each function. Those skilled in the art should easily realize that, in combination with the functions described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0192] From the perspective of a physical device, the above-mentioned PMA layer can be implemented by a physical device, such as an optical module, or other encoding device, decoding device, etc., or it can be implemented by multiple physical devices together, or it can be a logical functional unit within a physical device. The embodiments of the present application do not make specific limitations on this.

[0193] For example, the above-mentioned PMA layer can be made of Figure 11This is achieved by the communication equipment in. Figure 11 Schematic diagram of the hardware structure of a communication device provided in an embodiment of the present application. The communication device includes at least one processor 1101, a memory 1102, and a transceiver 1103.

[0194] Processor 1101 can be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of the program of the present application. Processor 1101 is capable of performing operations such as judgment, analysis, and calculation, including processing m first data streams to obtain z second data streams; and independently performing inner code encoding on each of the z second data streams to obtain z third data streams.

[0195] Transceiver 1103, which may be any transceiver, is configured to communicate with other devices or communication networks, such as Ethernet, a radio access network (RAN), or a wireless local area network (WLAN). Transceiver 1103 may be connected to processor 1101. Transceiver 1103 may obtain m first data streams, etc.

[0196] The memory 1102 may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, an optical disc storage (including a compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 1102 may exist independently or be connected to the processor 1101. The memory 1102 may also be integrated with the processor 1101.

[0197] The memory 1102 is used to store computer-executable instructions for executing the solution of the present application, and the execution is controlled by the processor 1101. The processor 1101 is used to execute the computer-executable instructions stored in the memory 1102, thereby implementing the encoding method and decoding method provided by the above-mentioned method embodiment of the present application.

[0198] In one possible implementation, the computer-executable instructions in the embodiments of the present application may also be referred to as application code, which is not specifically limited in the embodiments of the present application.

[0199] In a specific implementation, as an embodiment, the processor 1101 may include one or more CPUs, such as Figure 11 CPU0 and CPU1 in.

[0200] From the perspective of functional units, the present application can divide the PMA layer into functional units according to the above method embodiments. For example, each functional unit can be divided according to each function, or two or more functions can be integrated into one functional unit. The above integrated functional units can be implemented in the form of hardware or software functional units.

[0201] For example, when the functional units are divided in an integrated manner, Figure 12 FIG. 1 shows a schematic diagram of the structure of an encoding device provided in an embodiment of the present application. Figure 12 As shown, an embodiment of the encoding device of the present application may include: a first acquisition unit 1201 and a first processing unit 1202.

[0202] The first acquisition unit 1201 is used to acquire m first data streams through m input channels, where m is a positive integer. Figure 3 The content of step 301 in FIG. 1 can be understood through the steps of FIG.

[0203] The first processing unit 1202 is used to process the m-way first data stream to obtain z-way second data streams, and independently encode each of the z-way second data streams to obtain z-way third data streams; multiplex the z-way third data streams to obtain n-way fourth data streams, where n and z are both positive integers. Figure 3 The contents of steps 302-304 in FIG. 3 can be understood through the example of FIG.

[0204] In some possible implementations, each of the z second data streams includes a data block to be encoded; the first processing unit 1202 is used to: encode the first data block to obtain an FEC codeword, the first data block is at least C / z consecutive data blocks to be encoded in the corresponding second data stream, C is a positive integer, and C is an integer multiple of z; insert a first identifier at the codeword boundary position of any FEC codeword in the FEC codeword, the first identifier is used to identify the codeword boundary of the FEC codeword, and the throughput rate or baud rate of the FEC codeword after inserting the first identifier is an integer multiple of the reference clock. For details, please refer to the aforementioned Figure 3 The contents of step 303 in FIG. 3 can be understood for simplicity and will not be described in detail here.

[0205] In some possible implementations, each of the z second data streams includes a data block to be encoded; the first processing unit 1202 is used to: insert a first identifier into each data block to be encoded in the first data block to obtain a second data block, the first data block is C / z consecutive data blocks to be encoded, C is a positive integer, and C is an integer multiple of z; encode the second data block to obtain an FEC codeword, the throughput rate or baud rate of the FEC codeword is an integer multiple of the reference clock. For details, please refer to the aforementioned Figure 3 The contents of step 303 in FIG. 3 can be understood for simplicity and will not be described in detail here.

[0206] In some possible implementations, the first identifier is a preset identifier sequence. Figure 3 The contents of step 303 in FIG. 3 can be understood for simplicity and will not be described in detail here.

[0207] In some possible implementations, the first identifier is obtained based on the value of the first bit of the first data block, where the first bit is any one of at least one bit in the first data block; or, the first identifier is obtained based on the bit values of at least L second bits in the first data block, where there is an interval of s bits between each two adjacent second bits of the L second bits, L ≥ 2, s ≥ 0, and L and s are integers. For details, please refer to the aforementioned Figure 3 The contents of step 303 in FIG. 3 can be understood for simplicity and will not be described in detail here.

[0208] In some possible implementations, the first processing unit 1202 is configured to perform demultiplexing processing on m first data streams according to a second ratio to obtain z second data streams, where the second ratio is a ratio of m to z.

[0209] In some possible embodiments, the first processing unit 1202 is used to: demultiplex the m first data streams according to the second ratio to obtain z fifth data streams; independently perform Q-level processing on each of the z fifth data streams to obtain z second data streams; wherein each level of processing in the Q-level processing includes round-robin distribution processing on the data stream obtained at the previous level to obtain at least two sub-data streams, and delaying the first sub-data stream to obtain a sixth data stream, and multiplexing the second sub-data stream and the sixth data stream to obtain an output data stream after processing at this level, the first sub-data stream is at least one sub-data stream of the at least two sub-data streams, the second sub-data stream is a sub-data stream of the at least two sub-data streams that has not been delayed, Q is a positive integer, and the second data stream is a data stream after Q-level processing.

[0210] In some possible implementations, the bit length of the sixth data stream is at least (N×codeword length of the RS codeword) / (z×i) bits, where N is a positive integer and i is the number of the sub-data streams.

[0211] In some possible implementations, the first acquiring unit 1201 is further configured to acquire m seventh data streams through the m input channels. The first processing unit 1202 is configured to demultiplex the m seventh data streams according to the second ratio to obtain z eighth data streams, and multiplex the z second data streams and the z eighth data streams to obtain z multiplexed second data streams.

[0212] In some possible implementations, the first processing unit 1202 is further configured to: identify an alignment marker in each second data stream, the alignment marker being used to identify a symbol boundary in the corresponding second data stream; and determine a symbol boundary in the corresponding second data stream based on the alignment marker.

[0213] In some possible implementations, the m-channel first data streams are obtained by multiplexing z-channel data streams that are Reed-Solomon (RS) encoded with a first ratio.

[0214] The encoding device provided in the embodiment of the present application is used to perform Figure 3 The encoding method in the corresponding method embodiment, so the embodiment of this application can refer to Figure 3 Please understand the relevant parts of the corresponding method embodiments.

[0215] The above mainly describes the encoding device provided by the embodiment of the present application from the perspective of functional modules. The following describes the decoding device provided by the embodiment of the present application from the perspective of functional modules. Figure 13 FIG. 1 shows a schematic diagram of the structure of a decoding device provided in an embodiment of the present application. Figure 13As shown, an embodiment of the decoding device of the present application may include: a second acquisition unit 1301 and a second processing unit 1302.

[0216] The second acquisition unit 1301 is configured to acquire n fourth data streams through n input channels. Figure 9 The contents of step 901 in FIG. 1 can be understood for simplicity and will not be described in detail here.

[0217] The second processing unit 1302 is used to: demultiplex the n-way fourth data stream to obtain z-way third data stream; independently decode each of the z-way third data streams to obtain the z-way second data stream; multiplex the z-way second data stream according to the first ratio to obtain the m-way first data stream, wherein the first ratio and the second ratio are reciprocal of each other. Figure 9 The contents of steps 902-904 in FIG. 1 can be understood for simplicity and will not be described in detail here.

[0218] In some possible embodiments, the z-path third data stream includes a first identifier, which is used to identify the codeword boundary of the FEC codeword; the second processing unit 1302 is also used to: identify the codeword boundary of the FEC codeword based on the first identifier and / or the decoding flag bit, and the decoding flag bit is used to indicate whether the decoding processing is successful.

[0219] In some other possible implementations, the second processing unit 1302 is further configured to generate a first signal based on the first identifier and / or the decoding flag before identifying the codeword boundary of the FEC codeword based on the first identifier and / or the decoding flag, wherein the first signal is used to determine the data clock information. It should be noted that the data clock information can be determined by the first signal, so that the CDR unit accelerates the data and clock recovery process, determines the data clock information in advance, reduces the time required for system locking, and facilitates the early determination of the system transmission frequency. In addition, since the first identifier of the present application is designed in a sequence generation method, it not only takes into account the autocorrelation characteristics of the sequence corresponding to the first identifier, which helps the first identifier to be detected more quickly, but also takes into account the fact that the first identifier contains a fixed 0,1 jump characteristic, which improves the convergence speed of the data clock recovery of the CDR unit. It should be noted that if the CDR unit receives its own feedback signal for normal data and clock recovery before receiving the first signal, the CDR unit can enter a locked state based on the signal for normal data and clock recovery, thereby completing the data and clock recovery operation.

[0220] The decoding device provided in the embodiment of the present application is used to perform Figure 9 The decoding method in the corresponding method embodiment, so the embodiment of this application can refer to Figure 9 Please understand the relevant parts of the corresponding method embodiments.

[0221] In the embodiment of the present application, the encoding device and the decoding device are presented in the form of dividing each functional unit in an integrated manner. The "functional unit" here can refer to an application-specific integrated circuit (ASIC), a processor and memory that executes one or more software or firmware programs, an integrated logic circuit, and / or other devices that can provide the above functions. In a simple embodiment, those skilled in the art can imagine that the encoding device and the decoding device can be used Figure 11 The form shown.

[0222] for example, Figure 11 The processor 1101 can call the computer execution instructions stored in the memory 1102 to make the encoding device execute Figure 3 The encoding method performed by the PMA layer in the corresponding method embodiment. Figure 11 The processor 1101 can call the computer execution instruction stored in the memory 1102 to make the decoding device execute Figure 8 The decoding method performed by the PMA layer in the corresponding method embodiment.

[0223] Specifically, Figure 12 The first processing unit 1202, Figure 13 The function / implementation process of the second processing unit 1302 can be achieved by Figure 11 The processor 1101 in the embodiment mobilizes the computer execution instructions stored in the memory 1102 to achieve the above. Figure 12 The first acquisition unit 1201 in Figure 13 The function / implementation process of the second acquisition unit 1301 can be achieved by Figure 11 This is achieved by the transceiver 1103 in .

[0224] In this application Figure 11The various components in the device are communicatively connected, that is, the processing unit (or processor), the storage unit (or memory) and the transceiver unit (transceiver) communicate with each other through internal connection paths to transmit control and / or data signals. The above-mentioned method embodiments of the present application can be applied to a processor, or the steps of the above-mentioned method embodiments can be implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, the steps of the above-mentioned method embodiments can be completed by hardware integrated logic circuits in the processor or instructions in the form of software. The above-mentioned processor can be a central processing unit (CPU), a network processor (NP) or a combination of CPU and NP, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The various methods, steps and logic block diagrams disclosed in this application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the present application can be directly embodied as being executed by a hardware decoding processor, or can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a mature storage medium in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware. Although only one processor is shown in the figure, the device may include multiple processors or the processor may include multiple processing units. Specifically, the processor may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor.

[0225] The memory is used to store computer instructions executed by the processor. The memory can be a storage circuit or a memory. The memory can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory, a programmable read-only memory, an erasable programmable read-only memory, an electrically erasable programmable read-only memory or a flash memory. The volatile memory can be a random access memory, which is used as an external cache. The memory can be independent of the processor or can be a storage unit in the processor, which is not limited here. Although only one memory is shown in the figure, the device can also include multiple memories or the memory can include multiple storage units.

[0226] The transceiver is used to implement content interaction between the processor and other units or network elements. Specifically, the transceiver can be a communication interface of the device, or a transceiver circuit or a communication unit, or a transceiver. The transceiver can also be a communication interface or transceiver circuit of the processor. Optionally, the transceiver can be a transceiver chip. The transceiver can also include a transmitting unit and / or a receiving unit. In one possible implementation, the transceiver can include at least one communication interface. In another possible implementation, the transceiver can also be a unit implemented in software form. In various embodiments of the present application, the processor can interact with other units or network elements through the transceiver. For example, the processor obtains or receives content from other network elements through the transceiver. If the processor and the transceiver are two physically separate components, the processor can interact with other units of the device without going through the transceiver.

[0227] In one possible implementation, the processor, memory, and transceiver may be interconnected via a bus. The bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. Buses may be categorized as address buses, data buses, and control buses.

[0228] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0229] In the various embodiments of the present application, various examples are provided for ease of understanding. However, these examples are merely examples and are not intended to be the best way to implement the present application.

[0230] The above embodiments may be implemented in whole or in part through software, hardware, firmware, or any combination thereof. When implemented using software, they may be implemented in whole or in part in the form of a computer program product.

[0231] The computer program product includes one or more computer instructions. When the computer is loaded and executed on the computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instruction can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instruction can be transmitted from a website, a computer, a server, or a data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode to another website, a computer, a server, or a data center. The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as a server or a data center that includes one or more available media integrations. Available media can be magnetic media, (such as floppy disk, hard disk, tape), optical media (such as DVD), or semiconductor media (such as solid-state drive Solid State Disk (SSD)), etc.

[0232] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the transmitting optical module, receiving optical module, unit and module described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0233] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A coding method, characterized in that: include: Obtain m first data streams through m input channels, where m is a positive integer; Processing the m first data streams to obtain z second data streams, where z is a positive integer; independently encoding each of the z second data streams to obtain z third data streams; Multiplexing the z third data streams to obtain n fourth data streams, where n is a positive integer; Processing the m first data streams to obtain z second data streams includes: Demultiplexing the m first data streams according to a second ratio to obtain z second data streams, where the second ratio is a ratio of m to z; The demultiplexing of the m first data streams according to the second ratio to obtain z second data streams includes: Demultiplexing the m first data streams according to the second ratio to obtain z fifth data streams; Independently perform Q-level processing on each of the z fifth data streams to obtain z second data streams; wherein Q=1, and each level of processing in the Q-level processing includes: Performing round-robin distribution processing on the fifth data to obtain at least two sub-data streams; performing delay processing on the first sub-data stream to obtain a sixth data stream; Multiplexing the second sub-data stream and the sixth data stream to obtain an output data stream; The first sub-data stream is at least one of the at least two sub-data streams, the second sub-data stream is one of the at least two sub-data streams that has not been delayed, and the output data stream is the second data stream.

2. The encoding method according to claim 1, wherein Each of the z second data streams includes a data block to be encoded; and independently encoding each of the z second data streams includes: Encoding a first data block to obtain a forward error correction (FEC) codeword, wherein the first data block corresponds to at least C / z consecutive data blocks to be encoded in the second data stream, where C is a positive integer and is an integer multiple of z; The encoding method further comprises: A first identifier is inserted into a codeword boundary position of one of the FEC codewords.

3. The encoding method according to claim 1 or 2, characterized in that The first identifier includes a preset identifier sequence.

4. The encoding method according to claim 1 or 2, characterized in that The encoding method further comprises: Obtaining m seventh data streams through the m first input channels; Demultiplexing the m seventh data streams according to the second ratio to obtain z eighth data streams; Processing the m first data streams to obtain z second data streams includes: The z-way second data stream and the z-way eighth data stream are multiplexed to obtain z-way second data stream after multiplexing.

5. The encoding method according to claim 1 or 2, characterized in that The encoding method further comprises: An alignment marker in each of the second data streams is identified, where the alignment marker is used to identify a symbol boundary in the corresponding second data stream.

6. The encoding method according to claim 5, characterized in that The alignment marker is an alignment block including a 120-bit sequence, and the alignment block includes a 48-bit common alignment marker.

7. The encoding method according to claim 1 or 2, characterized in that The m-channel first data streams are obtained by multiplexing the z-channel data streams after Reed-Solomon (RS) encoding at a first ratio.

8. The encoding method according to claim 2, wherein: The throughput rate or baud rate of the data after the first identifier is inserted is an integer multiple of the reference clock.

9. The encoding method according to claim 1 or 2, characterized in that: m=4,z=32,n=4.

10. The encoding method according to claim 1 or 2, before independently encoding each of the z second data streams, the method further comprises: Delay processing is performed on the z-path second data stream.

11. The method according to claim 10, characterized in that The method further comprises: The sub-data streams that have undergone delay processing and the sub-data streams that have not undergone delay processing are multiplexed.

12. A coding device, characterized in that: The encoding device is used to perform the method according to any one of claims 1 to 11.

13. A computer-readable storage medium, characterized in that When the instructions are executed on a computer, the computer is caused to perform the method according to any one of claims 1 to 11.

14. A chip system, which may include a processor, wherein the processor is configured to execute the method according to any one of claims 1 to 11.

Images