Fault detection method and device, equipment, storage medium and program product

Abstract

The embodiment of the invention discloses a fault detection method and device, equipment, a storage medium and a program product, and the method comprises the steps: detecting the states of two to-be-detected ports between the two to-be-detected ports of a physical layer through transmitting a preset bit stream, and enabling the preset bit stream to comprise fault detection information; when it is detected that at least one of the two ports to be detected fails, target traffic transmitted between the two ports to be detected is switched to a target link, and the target link represents a link between a first port and a second port. The first port and the second port represent other ports except the at least one port.

Description

Technical Field

[0001] The present application belongs to the technical field of transmission and Internet Protocol (IP), and in particular, relates to a fault detection method, device, equipment, storage medium and program product. Background Art

[0002] In the related art, for the Transmission Control Protocol (TCP) / IP network reference model, the failure of the forwarding node can be detected based on the link layer protocol, the network layer protocol, the application layer protocol, etc. In addition, the failure detection of the forwarding node can also be achieved through the hardware bidirectional forwarding detection (BFD) mechanism; however, the technical solution of the related art has the problem of long detection time. Summary of the invention

[0003] In order to solve the problem of long detection time existing in the related art, the embodiments of the present application propose a fault detection method, apparatus, device, storage medium and program product.

[0004] The present application provides a fault detection method, the method comprising:

[0005] Detecting the states of the two ports to be detected by transmitting a preset bit stream between the two ports to be detected at the physical layer, wherein the preset bit stream includes fault detection information;

[0006] When a fault is detected in at least one of the two ports to be detected, target traffic transmitted between the two ports to be detected is switched to a target link, where the target link represents a link between a first port and a second port, and the first port and the second port represent other ports except the at least one port.

[0007] In some embodiments, the detecting the states of the two ports to be detected by transmitting a preset bit stream between the two ports to be detected at the physical layer includes: in each fault detection cycle, detecting the states of the two ports to be detected by transmitting the preset bit stream between the two ports to be detected at the physical layer; the fault detection cycle represents a cycle for detecting port faults.

[0008] In some embodiments, each fault detection cycle includes at least a target time period for transmitting the preset bit stream; after detecting the status of the two ports to be detected by transmitting the preset bit stream between the two ports to be detected at the physical layer, the method further includes: in response to the at least one port not receiving the preset bit stream within the target time period, determining that the at least one port has a fault.

[0009] In some embodiments, the method further includes: in response to the at least one port not receiving the preset bit stream within the target time period, determining to enter a next fault detection cycle.

[0010] In some embodiments, the method further includes: in response to a receiving port of the two ports to be detected receiving the preset bit stream within the target time period, in the current fault detection cycle, continuing to detect the status of the two ports to be detected by transmitting the preset bit stream between the two ports to be detected.

[0011] In some embodiments, before detecting the status of the two ports to be detected by transmitting a preset bit stream, the method also includes: constructing a composite bit stream by preset coding at the sending ports of the two ports to be detected; replacing at least one idle code block in the composite bit stream with a fault detection code block for carrying the fault detection information to obtain the preset bit stream.

[0012] In some embodiments, the preset encoding is 64B / 66B encoding.

[0013] In some embodiments, the fault detection information in the fault detection code block includes at least one of the following: a local device identifier, a local device port, a peer device identifier, a peer device port, a data transmission status between the two ports to be detected, and a target time period. The target time period represents a time period used to transmit the preset bit stream in each fault detection cycle, and the fault detection cycle represents a period for detecting port faults.

[0014] The present application also provides a fault detection device, the device comprising:

[0015] A first processing module, configured to detect the states of two ports to be detected at the physical layer by transmitting a preset bit stream between the two ports to be detected, wherein the preset bit stream includes fault detection information;

[0016] The second processing module is used to switch the target traffic transmitted between the two ports to be detected to a target link when a fault is detected in at least one of the two ports to be detected, wherein the target link represents a link between the first port and the second port, and the first port and the second port represent other ports except the at least one port.

[0017] An embodiment of the present application also provides an electronic device, comprising a processor and a memory for storing a computer program that can be run on the processor; wherein the processor is used to run the computer program to execute any one of the above-mentioned fault detection methods.

[0018] An embodiment of the present application further provides a computer storage medium on which a computer program is stored. When the computer program is executed by a processor, any one of the above-mentioned fault detection methods is implemented.

[0019] An embodiment of the present application further provides a computer program product, including a computer program, which implements any of the above-mentioned fault detection methods when executed by a processor.

[0020] It can be seen that the embodiment of the present application constructs a bit stream at the physical layer for fault detection, without the need for additional fault detection through the upper layer protocol, which can reduce the processing delay caused by complex protocol encapsulation and thus reduce the fault detection time of the network node. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A flowchart of a fault detection method according to an embodiment of the present application;

[0022] Figure 2 A schematic diagram of switching links when a port fails in an embodiment of the present application;

[0023] Figure 3 Schematic diagram of four states of a fault detection cycle in an embodiment of the present application;

[0024] Figure 4 This is a flow chart of a data frame processed by a transceiver in an embodiment of the present application;

[0025] Figure 5 A schematic diagram of the encoding format of the original data frame and the 66B code block provided in an embodiment of the present application;

[0026] Figure 6 A schematic diagram of the code block structure of the composite bit stream and the preset bit stream in the embodiment of the present application;

[0027] Figure 7 Schematic diagram of the code block structure of the o code block in the embodiment of the present application;

[0028] Figure 8 This is a schematic diagram of the structure of a fault detection device according to an embodiment of the present application;

[0029] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The rapid development of artificial intelligence generated content (AIGC) technology has led to an explosive growth in the demand for large-scale intelligent computing power. As an infrastructure that carries large-scale computing resources, the importance of intelligent computing centers has become increasingly prominent. The latency, bandwidth, stability, and security of the Internet network in which the intelligent computing center is located are directly related to the performance of the effective computing power of the cluster. At present, Ethernet, with its powerful industrial ecology and continuously enhanced connection bandwidth capabilities, is gradually becoming an important development direction of network interconnection technology for intelligent computing centers.

[0031] The intelligent computing data center network needs to have high reliability to ensure the smooth progress of key tasks. If a failure occurs during the training of an artificial intelligence (AI) cluster, it is necessary to support fault-tolerant replacement or elastic expansion and contraction to handle the faulty node. And it should be able to support job rearrangement and scheduling to improve the overall training efficiency. In addition, in order to recover from faults in a timely manner, it is necessary to enhance the ability to perceive faults and quality degradation, and control the time required for obstacle avoidance and self-healing within seconds by obtaining fine-grained business flow throughput, packet loss and other information.

[0032] In the related art, for the TCP / IP network reference model, there are fault detection mechanisms at multiple levels; illustratively, these fault detection mechanisms include the link layer Ethernet Operation Administration and Maintenance (Eth-OAM) mechanism, the mechanism based on the Spanning Tree Protocol (STP), the mechanism based on the Rapid Spanning Tree Protocol (RSTP), the mechanism based on the Multiple Spanning Tree Protocol (MSTP), the HELLO mechanism of various network layer protocols, and the heartbeat mechanism and retransmission mechanism of various application layer protocols themselves. The Hello detection mechanism of commonly used network protocols such as Open Shortest Path First (OSPF) and Border Gateway Protocol (BGP) can achieve a fault convergence speed of seconds.

[0033] When detecting the failure of the forwarding node through the upper layer protocols such as the link layer protocol, network layer protocol, and application layer protocol, the fault detection time is more than 1 second. The second-level fault recovery time means that a large number of public user services will be interrupted or retransmitted. For high-speed data transmission, such as G-bit rate level, a detection time of more than 1 second will result in a large amount of data loss, and such a fault detection time is unacceptable.

[0034] In related technologies, the hardware bidirectional forwarding detection (Bidirectional Forwarding Detection, BFD) mechanism is a relatively common mechanism for realizing fast fault detection through hardware detection. When fault detection is performed through the BFD mechanism, by linking with the upper-layer routing protocol, the fast convergence of routing node detection can be realized to ensure the sustainability of services. The hardware BFD mechanism can provide millisecond-level detection speed, accelerate network convergence speed, reduce application interruption time, and improve network reliability.

[0035] Although the hardware BFD mechanism can achieve millisecond-level detection, it cannot meet the fault detection requirements of the 800G port transmission scenario of the intelligent computing center's high-speed interconnection. In addition, since the hardware BFD fault detection message needs to encapsulate IP header and other information, it will also occupy the network's valuable bandwidth resources.

[0036] In summary, the technical solutions of related technologies have the problems of long detection time and high bandwidth resource occupancy rate, and need to be improved so that the fault detection solutions can be more easily deployed in the operator network.

[0037] In view of the above-mentioned technical problems, a technical solution of the embodiment of the present application is proposed. The solution of the embodiment of the present application is a fault detection solution based on the Ethernet physical layer, which integrates the fault detection technology with the Ethernet physical layer technology to achieve fault detection with characteristics such as low overhead, low latency and reliable transmission, and meet the reliable transmission requirements of the data link layer and all upper layer protocols.

[0038] The following is a further detailed description of the embodiments of the present application in conjunction with the accompanying drawings and examples. It should be understood that the embodiments provided herein are only used to explain the embodiments of the present application and are not intended to limit the embodiments of the present application. In addition, the embodiments provided below are partial embodiments for implementing the present application, rather than providing all embodiments for implementing the present application. In the absence of conflict, the technical solutions recorded in the embodiments of the present application can be implemented in any combination.

[0039] It should be noted that, in the embodiments of the present application, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a method or device including a series of elements includes not only the elements explicitly recorded, but also includes other elements not explicitly listed, or also includes elements inherent to the implementation of the method or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other related elements (such as steps in a method or units in a device, for example, a unit may be a part of a circuit, a part of a processor, a part of a program or software, etc.) in the method or device including the element.

[0040] The fault detection method provided in the embodiment of the present application includes a series of steps, but the fault detection method provided in the embodiment of the present application is not limited to the recorded steps. Similarly, the fault detection device provided in the embodiment of the present application includes a series of modules, but the device provided in the embodiment of the present application is not limited to including the modules explicitly recorded, and may also include modules that need to be set up to obtain relevant information or perform processing based on information.

[0041] Figure 1 is a flow chart of a fault detection method according to an embodiment of the present application, such as Figure 1 As shown, the process may include:

[0042] Step 101: Detect the states of two ports to be detected by transmitting a preset bit stream between two ports to be detected at the physical layer, wherein the preset bit stream includes fault detection information.

[0043] In the embodiment of the present application, the fault detection information is information used to detect physical layer port faults, and the fault detection information can be pre-set according to actual needs.

[0044] Step 102: When it is detected that at least one of the two ports to be detected fails, target traffic transmitted between the two ports to be detected is switched to a target link, where the target link represents a link between a first port and a second port, and the first port and the second port represent other ports except the at least one port mentioned above.

[0045] In the embodiment of the present application, when it is detected that at least one of the two ports to be detected is faulty, port isolation measures can be taken, and then the target traffic is switched to the target link; Figure 2 , GSF1 represents the sending end device of the physical layer, GSP1, GSP2 and GSP3 represent three receiving end devices of the physical layer, F1P1, F1P2 and F1P3 represent three physical layer ports of GSF1, P1P1 is the physical layer port of GSP1, P2P1 is the physical layer port of GSP2, and P3P1 is the physical layer port of GSP3; when at least one port between F1P1 and P1P1 fails, the target traffic transmitted between F1P1 and P1P1 can be switched to the target link, and the target link can be the link between F1P2 and P2P1, or the link between F1P3 and P3P1.

[0046] In practical applications, steps 101 to 102 can be implemented based on a processor, and the processor can be at least one of an application specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a CPU, a controller, a microcontroller, and a microprocessor.

[0047] It can be seen that the embodiment of the present application constructs a bit stream at the physical layer for fault detection, without the need for additional fault detection through the upper layer protocol, which can reduce the processing delay caused by complex protocol encapsulation and thus reduce the fault detection time of the network node.

[0048] In some embodiments of the present application, a process of detecting the states of two ports to be detected by transmitting a preset bit stream between two ports to be detected at a physical layer may include:

[0049] In each fault detection cycle, the states of the two ports to be detected are detected by transmitting a preset bit stream between the two ports to be detected at the physical layer. The fault detection cycle represents a cycle for detecting port faults.

[0050] Here, the fault detection cycle can be pre-configured according to actual needs. Exemplarily, each fault detection cycle at least includes a target time period for transmitting the preset bit stream.

[0051] Accordingly, after detecting the states of the two ports to be detected by transmitting the preset bit stream between the two ports to be detected at the physical layer, the method further includes: determining that at least one port has a fault in response to at least one port not receiving the preset bit stream within a target time period.

[0052] It can be seen that the embodiments of the present application can simply and easily implement the detection of port faults by determining whether a preset bit stream is received within a target time period.

[0053] In some embodiments of the present application, the method further includes: in response to the at least one port not receiving a preset bit stream within a target time period, determining to enter a next fault detection cycle. In this way, the fault detection of the physical layer port can be continued in the target time period of the next fault detection cycle, thereby achieving continuous fault detection of the physical layer port.

[0054] In some embodiments of the present application, the method further includes: in response to a receiving port of the two ports to be detected receiving a preset bit stream within a target time period, in a current fault detection cycle, continuing to detect the states of the two ports to be detected by transmitting the preset bit stream between the two ports to be detected. It can be seen that when the receiving port of the two ports to be detected receives the preset bit stream within the target time period, it can be considered that the two ports to be detected are not currently faulty. Therefore, by continuing to transmit the preset bit stream between the two ports to be detected to detect the states of the two ports to be detected, normal data transmission between the two ports to be detected can be achieved, and possible future faults of the ports can also be detected.

[0055] Exemplarily, the fault detection cycle can be recorded as PHYT, and the four time periods arranged in chronological order in each fault detection cycle include a time period corresponding to the first state, a time period corresponding to the second state, a time period corresponding to the third state, and a time period corresponding to the fourth state; wherein the first state can be recorded as a port-error (PORT-FAULT) state, the second state can be recorded as a port-start (PORT-START) state, the third state can be recorded as a port-middle (PORT-MID) state, the fourth state can be recorded as a port-normal (PORT-NORMAL) state, and the time period corresponding to the fourth state is the target time period.

[0056] Reference Figure 3 In the time period corresponding to the first state, the two ports to be detected transmit a preset start bit (START bit) stream, and then enter the time period corresponding to the second state. In the time period corresponding to the second state, the two ports to be detected transmit a preset intermediate bit (MID bit) stream, and then enter the time period corresponding to the third state. In the time period corresponding to the third state, the two ports to be detected begin to transmit a preset normal bit (NORMAL bit) stream, and at the same time, start the timer. After transmitting the NORMAL bit stream within the timer's timing duration, enter the target time period, and reset the timer's timing time. Here, by transmitting the NORMAL bit stream in the time period corresponding to the third state, it is beneficial to achieve stable reception of the NORMAL bit stream in the target time period. In the target time period, the NORMAL bit stream continues to be transmitted between the two ports to be detected, and at the same time, start the timer. If the receiving port can receive the NORMAL bit stream within the timer's timing duration, the fourth state is retained, and the NORMAL bit stream continues to be transmitted in the target time period; if the receiving port fails to receive the NORMAL bit stream within the timer's timing duration, the next fault detection cycle is entered.

[0057] In some embodiments, a physical layer detection (PhyDetect) session can be established between two ports to be detected, and a physical layer detection (PhyDetect) bit stream is periodically sent along the path between them. The PhyDetect bit stream is the above-mentioned preset bit stream, and the sending interval of the sending end and the receiving interval of the receiving end in the two ports to be detected can be configured. In the time period corresponding to the first state, the time period corresponding to the second state, the time period corresponding to the third state, and the time period corresponding to the fourth state, the type of the physical layer detection session can be different types. For example, in the time period corresponding to the first state, the type of the physical layer detection session can be represented by the number 0; in the time period corresponding to the second state, the type of the physical layer detection session can be represented by the number 1; in the time period corresponding to the third state, the type of the physical layer detection session can be represented by the number 2; in the time period corresponding to the fourth state, the type of the physical layer detection session can be represented by the number 3.

[0058] In some embodiments of the present application, before detecting the status of the two ports to be detected by transmitting a preset bit stream, the method further includes: constructing a composite bit stream consisting of a start code block, a data code block, an end code block and an idle code block by a preset coding at the sending port of the two ports to be detected; then, replacing at least one idle code block in the composite bit stream with a fault detection code block for carrying fault detection information to obtain a preset bit stream. In some embodiments, the preset coding is 64B / 66B coding.

[0059] In an embodiment of the present application, a composite bit stream is constructed by performing 64B / 66B encoding at the physical layer, and then the idle code blocks in the composite bit stream are replaced with fault detection code blocks, thereby realizing the transmission of fault detection information. Here, the fault detection code block can be recorded as an o code block.

[0060] Reference Figure 4 , the original data frame is converted into a series of 8-bit data bit stream sequences at the sending end media access control (MAC) layer. The converted 8-bit data bit stream sequence passes through the sending end physical layer (PHY) chip. In the PHY chip, the physical layer's physical coding sublayer (PCS) converts the interface data or control characters into 66-bit blocks according to certain rules, that is, 66B code blocks. The encoding format of the original data frame and the 66B code block can be Figure 5 The encoding format shown is shown in Figure 5 The original data frame includes a 7-byte preamble (PREAMBLE), a 1-byte start of frame delimiter (SFD), a 6-byte destination address (Destination MAC, DMAC), a 6-byte source address (Source MAC, SMAC), a 2-byte type field, n bytes of data, and a 4-byte frame check sequence (FCS).

[0061] The 66B code block is processed by physical layer such as scrambling, Reed-Solomon Forward Error Correction (RS-FEC), and segmentation before entering the egress port. After receiving information from the ingress port, the receiver processes it through the Physical Medium Attachment (PMA) sublayer, extracts fault detection information at the PCS layer, and then restores the Ethernet frame.

[0062] A 66B code block contains 66 bits of data. For example, the data at the [0:1] position in a 66B code block represents the synchronization header, and the data at the [2:65] position represents the actual transmitted information. Here, the [0:1] position represents the positions of the 1st bit and the 2nd bit, and the [2:65] position represents the positions of the 3rd bit to the 66th bit.

[0063] Reference Figure 5 and Figure 6, the 66B code blocks in the composite bit stream include the start code block, data code blocks, end code blocks and idle code blocks; among them, the start code block can be recorded as the S code block, the start code block consists of the synchronization header "10" + 8-bit code block type field (block_type_field) and 8 7-bit control information, and the start code block indicates the beginning of a data frame. The data code block can be recorded as the D code block, and the data code block consists of the synchronization header "01" and 8 8-bit data information. The end code block can be recorded as the T code block, and the end control word in the end code block can appear at any position in the 8 bytes. It is distinguished by the control code block type field, and the end code block indicates the end of a frame. The idle code block can be recorded as the I code block, and the idle code block consists of the synchronization header "10", 1E and 8 7-bit control information. The idle code block is a code block that is not in an idle state.

[0064] According to the provisions of Institute of Electrical and Electronics Engineers (IEEE) 802.3, there is an Inter Packet Gap (IPG) between adjacent Ethernet data frames, and after the IPG is encoded by 66B, it will become an end code block and an idle code block.

[0065] In the embodiment of the present application, the o code block can be inserted at a specific position of the IPG by replacing the idle code block. The o code block will not be inserted randomly in the IPG. This is because the insertion position of the randomly inserted o code block may have a certain deviation compared to the expected insertion position. Assuming that the insertion period of the o code block is τ, the first o code block is inserted on time. When the second o code block needs to be inserted, that is, after the time τ, the expected insertion position is the data code block, not the idle code block. Therefore, the second o code block needs to wait for τ' time before being inserted, that is, after encoding, the o code block is inserted after the end code block of the Ethernet message.

[0066] Exemplarily, the o code block carries fault detection information, the control field is 0x4B, the o code (o CODE) field is 0x8, and the control field and the o code field are used to indicate that the code block currently being transmitted is an o code block carrying fault detection information. Figure 7 The available information (fault detection information) of the o code block is D1 to D3, and the available information of the o code block occupies a total of 3 bytes.

[0067] It can be seen that the embodiment of the present application can replace the idle code block with the fault detection code block used to carry the fault detection information, thereby realizing fault detection, that is, the embodiment of the present application can use the inherent code block of the Ethernet physical layer to carry the fault detection parameters, without introducing additional bandwidth overhead, thereby realizing low overhead of bandwidth resources.

[0068] In some embodiments of the present application, the fault detection information in the fault detection code block includes at least one of the following: a local device identifier, a local device port, a peer device identifier, a peer device port, a data transmission state between the two ports to be detected, and a target time period, wherein the target time period indicates a time period for transmitting the preset bit stream in each fault detection cycle, and the fault detection cycle indicates a cycle for detecting port faults. Here, the local device identifier may be an ID or other identifier, the peer device identifier may be an ID or other identifier, the data transmission state between the two ports to be detected may be a first state, a second state, a third state, and a fourth state, and the first state, the second state, the third state, and the fourth state may be represented by the numbers 0, 1, 2, and 3, respectively.

[0069] Exemplarily, the control fields in the fault detection information shown in Table 1 may be transmitted using multiple o code blocks in the order of the numbering of the o code blocks shown in Table 1. For example, the field used to identify the start of the combined frame is transmitted in the first o code block. The combined frame is a data frame carrying a preset bit stream. The code block result of the combined frame is Figure 6 The code block structure shown in FIG. 1 ; the local device identifier is transmitted in the second o code block, and so on, until the transmission of the fault detection information shown in Table 1 is completed.

[0070] Table 1 Control field table in fault detection information

[0071] oCode block number illustrate 1 Used to mark the start of a combined frame 2 Local device identification 3 Local device port 4 Peer device ID 5 Peer device port 6 Type of physical layer detection session 7 Data transmission status between ports to be detected 8 The timer duration 9-N Reserved Fields

[0072] The embodiment of the present application can implement Ethernet physical layer fault detection based on a preset bit stream constructed based on 64B / 66B encoding, and can be applied to scenarios such as intelligent computing center networks and wide area networks. The technical solution of the embodiment of the present application includes physical layer port fault detection, port fault processing, physical layer fault information transmission and other parts. Physical layer fault detection is used to detect the status information of the port at the physical layer, fault processing is the processing method of the faulty port and the corresponding traffic after the fault information is detected, and fault information transmission is used to transmit fault information at the physical layer.

[0073] In the embodiment of the present application, by constructing a bit stream at the physical layer for fault detection, the complex protocol encapsulation overhead and processing delay are reduced, and the advantages of low overhead, low delay and protocol transparency are achieved. The inherent code blocks of the Ethernet physical layer are used to carry fault detection parameters, and no additional bandwidth overhead is introduced, so that low overhead is achieved, and the bandwidth utilization rate is high for bandwidth-sensitive usage scenarios such as data center interconnection and enterprise parks. In addition, the 64B / 66B encoding method is compatible with all types of ports and has universality. At the same time, the o code block insertion adopts in-situ replacement, which has the advantage of short delay.

[0074] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0075] Figure 8 Schematic diagram of the structure of the fault detection device of the embodiment of the present application. Figure 8 As shown, the device comprises:

[0076] A first processing module 801 is configured to detect the states of two ports to be detected at a physical layer by transmitting a preset bit stream between the two ports to be detected, wherein the preset bit stream includes fault detection information;

[0077] The second processing module 802 is used to switch the target traffic transmitted between the two ports to be detected to a target link when a fault is detected in at least one of the two ports to be detected, wherein the target link represents a link between the first port and the second port, and the first port and the second port represent other ports except the at least one port.

[0078] In some embodiments, the first processing module 801 is used to detect the status of the two ports to be detected by transmitting a preset bit stream between the two ports to be detected at the physical layer, including: in each fault detection cycle, the status of the two ports to be detected is detected by transmitting the preset bit stream between the two ports to be detected at the physical layer; the fault detection cycle represents the cycle for detecting port faults.

[0079] In some embodiments, each fault detection cycle includes at least a target time period for transmitting the preset bit stream; the first processing module 801 is also used to detect the states of the two ports to be detected by transmitting the preset bit stream between the two ports to be detected at the physical layer, and in response to at least one port not receiving the preset bit stream within the target time period, determine that at least one port has a fault.

[0080] In some embodiments, the first processing module 801 is further configured to determine to enter a next fault detection cycle when the at least one port does not receive the preset bit stream within the target time period.

[0081] In some embodiments, the first processing module 801 is further used to, when a receiving port among the two ports to be detected receives the preset bit stream within the target time period, continue to detect the status of the two ports to be detected by transmitting the preset bit stream between the two ports to be detected in the current fault detection cycle.

[0082] In some embodiments, the first processing module 801 is also used to construct the composite bit stream through preset coding at the sending ports of the two ports to be detected before detecting the status of the two ports to be detected by transmitting a preset bit stream; and replace at least one idle code block in the composite bit stream with a fault detection code block for carrying the fault detection information to obtain the preset bit stream.

[0083] In some embodiments, the preset encoding is 64B / 66B encoding.

[0084] In some embodiments, the fault detection information in the fault detection code block includes at least one of the following: a local device identifier, a local device port, a peer device identifier, a peer device port, a data transmission status between the two ports to be detected, and a target time period. The target time period represents a time period used to transmit the preset bit stream in each fault detection cycle, and the fault detection cycle represents a period for detecting port faults.

[0085] In practical applications, the first processing module 801 and the second processing module 802 can be implemented based on a processor and a communication device.

[0086] It should be noted that the description of the above device embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the device embodiment of the present application, please refer to the description of the method embodiment of the present application for understanding.

[0087] It should be noted that in the embodiments of the present application, if the above method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium, including a number of instructions to enable a computer device (which can be a terminal, a server, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a disk or an optical disk. In this way, the embodiments of the present application are not limited to any specific combination of hardware and software.

[0088] Correspondingly, an embodiment of the present application further provides a computer program product, which includes computer executable instructions, and the computer executable instructions are used to implement any fault detection method provided in the embodiment of the present application.

[0089] Accordingly, an embodiment of the present application further provides a computer storage medium, on which computer executable instructions are stored, and the computer executable instructions are used to implement any one of the fault detection methods provided in the above embodiments.

[0090] An embodiment of the present application also provides an electronic device. Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown in FIG. Fig. 9 As shown, the electronic device 90 may include:

[0091] Memory 901, used to store executable instructions;

[0092] The processor 902 is configured to implement any one of the above-mentioned fault detection methods when executing the executable instructions stored in the memory 901.

[0093] The processor 902 may be at least one of an ASIC, a DSP, a DSPD, a PLD, a FPGA, a CPU, a controller, a microcontroller, and a microprocessor.

[0094] The above-mentioned computer-readable storage medium and memory 902 can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory (Flash Memory), a magnetic surface memory, an optical disk, or a compact disc read-only memory (CD-ROM) and other memories; it can also be various terminals including one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0095] In some embodiments, the functions or modules included in the device provided in the embodiments of the present application can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0096] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

[0097] The methods disclosed in the various method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0098] The features disclosed in the various product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0099] The features disclosed in the various method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0100] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0101] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A fault detection method, characterized in that: The method comprises: Detecting the states of the two ports to be detected by transmitting a preset bit stream between the two ports to be detected at the physical layer, wherein the preset bit stream includes fault detection information; When a fault is detected in at least one of the two ports to be detected, target traffic transmitted between the two ports to be detected is switched to a target link, where the target link represents a link between a first port and a second port, and the first port and the second port represent other ports except the at least one port.

2. The method according to claim 1, characterized in that The detecting the states of the two ports to be detected by transmitting a preset bit stream between the two ports to be detected at the physical layer includes: In each fault detection cycle, the states of the two ports to be detected are detected by transmitting the preset bit stream between the two ports to be detected at the physical layer; the fault detection cycle represents a cycle for detecting port faults.

3. The method according to claim 2, characterized in that Each fault detection cycle at least includes a target time period for transmitting the preset bit stream; After detecting the states of the two ports to be detected by transmitting the preset bit stream between the two ports to be detected at the physical layer, the method further includes: In response to the at least one port not receiving the preset bit stream within the target time period, it is determined that the at least one port fails.

4. The method according to claim 3, characterized in that The method further includes: in response to the at least one port not receiving the preset bit stream within the target time period, determining to enter a next fault detection cycle.

5. The method according to claim 3, characterized in that: The method further includes: in response to a receiving port of the two ports to be detected receiving the preset bit stream within the target time period, in a current fault detection cycle, continuing to detect the states of the two ports to be detected by transmitting the preset bit stream between the two ports to be detected.

6. The method according to any one of claims 1 to 5, characterized in that: Before detecting the states of the two ports to be detected by transmitting a preset bit stream, the method further includes: Constructing a composite bit stream by using a preset encoding at the sending ports of the two ports to be detected; At least one idle code block in the composite bit stream is replaced with a fault detection code block used to carry the fault detection information to obtain the preset bit stream.

7. The method according to claim 6, characterized in that The preset encoding is 64B / 66B encoding.

8. The method according to claim 6, characterized in that The fault detection information in the fault detection code block includes at least one of the following: a local device identifier, a local device port, a peer device identifier, a peer device port, a data transmission status between the two ports to be detected, and a duration of a target time period. The target time period represents a time period for transmitting the preset bit stream in each fault detection cycle, and the fault detection cycle represents a cycle for detecting port faults.

9. A fault detection device, characterized in that: The device comprises: A first processing module, configured to detect the states of two ports to be detected at the physical layer by transmitting a preset bit stream between the two ports to be detected, wherein the preset bit stream includes fault detection information; The second processing module is used to switch the target traffic transmitted between the two ports to be detected to a target link when a fault is detected in at least one of the two ports to be detected, wherein the target link represents a link between the first port and the second port, and the first port and the second port represent other ports except the at least one port.

10. An electronic device, characterized in that: The electronic device comprises a processor and a memory for storing a computer program that can be run on the processor; wherein, The processor is configured to run the computer program to perform the method according to any one of claims 1 to 8.

11. A computer storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

12. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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