Image sensor, operating method thereof, and electronic device

Abstract

An image sensor, an operating method thereof, and an electronic device are provided. The image sensor includes: a first photoelectric element; a second photoelectric element having a receiving area larger than that of the first photoelectric element; a first floating diffusion region in which charges generated by the first photoelectric element are stored; a second floating diffusion region in which charges generated by the second photoelectric element are stored, and which is connected to a gate of the driving transistor; a capacitor selectively connected to the first floating diffusion region based on a readout mode, and storing charge overflowing from the first photoelectric element; a third floating diffusion region connected to the first floating diffusion region and the second floating diffusion region through the first switching transistor and the second switching transistor, respectively; a first end of the reset transistor is selectively connected to one of the plurality of voltage nodes through a reset node, and a second end of the reset transistor is connected to the third floating diffusion region.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0080034 filed on June 22, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Apparatus, devices, and methods consistent with the present disclosure relate to an image sensor including a split photodiode pixel (or referred to as a split photodiode pixel, or a separated photodiode pixel, split photodiode pixel). Background Art

[0003] The image sensor is a device that converts an optical signal into an electrical signal, and includes a charge coupled device (CCD) image sensor and a complementary metal oxide semiconductor (CMOS) image sensor.

[0004] In a CMOS image sensor, an active pixel sensor (APS) sends charges generated when a light signal is incident on a photodiode (PD) to a floating diffusion region. A driving transistor converts the potential of the floating diffusion region into a voltage and outputs the voltage to a column line.

[0005] Image sensors are developed to reduce the size of pixels to increase resolution, and to improve dynamic range for the purpose of improving image quality in various illumination environments.

[0006] There are various techniques for achieving high dynamic range (HDR) of image sensors. One of the various techniques involves split photodiode pixel technology. Summary of the invention

[0007] One aspect provides an image sensor including a split photodiode pixel with reduced noise.

[0008] According to one aspect of one or more embodiments, an image sensor is provided, comprising: a first photoelectric element having a first receiving area; a second photoelectric element having a second receiving area larger than the first receiving area of ​​the first photoelectric element; a first floating diffusion region, in which charges generated by the first photoelectric element are stored; a second floating diffusion region, in which charges generated by the second photoelectric element are stored, and the second floating diffusion region is connected to a gate of a driving transistor; a capacitor selectively connected to the first floating diffusion region based on a readout mode, and configured to store charges overflowing from the first photoelectric element; a third floating diffusion region, connected to the first floating diffusion region and the second floating diffusion region through a first switching transistor and a second switching transistor, respectively; and a reset transistor, a first end of the reset transistor being selectively connected to one of a plurality of voltage nodes through a reset node, and a second end of the reset transistor being connected to the third floating diffusion region.

[0009] According to another aspect of one or more embodiments, there is provided an operating method of an image sensor, the image sensor comprising a pixel, the pixel comprising a first photoelectric element, a second photoelectric element having a receiving area larger than a receiving area of ​​the first photoelectric element, a plurality of floating diffusion areas, and a plurality of voltage nodes, the method comprising: in a high conversion gain (HCG) mode during a readout period of the first photoelectric element, sampling a first reset level signal of at least one floating diffusion area of ​​the plurality of floating diffusion areas that is reset to a voltage of a first voltage node providing a low voltage among the plurality of voltage nodes; in the HCG mode during a readout period of the first photoelectric element, sampling a first reset level signal of at least one floating diffusion area of ​​the plurality of floating diffusion areas that is reset to a voltage of a first voltage node providing a low voltage among the plurality of voltage nodes; In the embodiment of the present invention, a first image level signal of at least one of the multiple floating diffusion areas is sampled; in a low conversion gain (LCG) mode during a readout period of the first photoelectric element, a second image level signal of at least one of the multiple floating diffusion areas is sampled; and in an LCG mode during a readout period of the first photoelectric element, a second reset level signal of at least one of the multiple floating diffusion areas that is reset to a voltage of a first voltage node is sampled, wherein, during the readout period of the first photoelectric element, the multiple floating diffusion areas are electrically coupled differently in the HCG mode and the LCG mode.

[0010] According to another aspect of one or more embodiments, an electronic device is provided, the electronic device comprising: a pixel array, a plurality of pixels are arranged in the pixel array; and a control circuit configured to send a control signal to a plurality of transistors in a pixel included in the plurality of pixels. The pixel comprises: a first photoelectric element having a first receiving area; a second photoelectric element having a second receiving area larger than the first receiving area of ​​the first photoelectric element; a first floating diffusion area, in which the charge generated by the first photoelectric element is stored; a second floating diffusion area, in which the charge generated by the second photoelectric element is stored, and the second floating diffusion area is connected to the gate of the driving transistor; a capacitor selectively connected to the first floating diffusion area based on a readout mode and configured to store the charge overflowed from the first photoelectric element; a third floating diffusion area, connected to the first floating diffusion area and the second floating diffusion area through a first switching transistor and a second switching transistor, respectively; and a reset transistor, a first end of the reset transistor selectively connected to one of a plurality of voltage nodes through a reset node, and a second end of the reset transistor connected to the third floating diffusion area. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects will become apparent by describing in detail various embodiments of the present invention with reference to the attached drawings.

[0012] Figure 1 is a block diagram illustrating an image sensor according to an embodiment.

[0013] Figure 2 is a circuit diagram for describing a pixel of an image sensor according to an embodiment.

[0014] Figure 3 is a diagram showing the Figure 2 FIG. 1 is a diagram of a reset operation during a readout operation of a large photodiode of a unit pixel.

[0015] Figure 4 is a diagram showing the Figure 2 FIG. 1 is a diagram of a reset operation during a readout operation of a small photodiode of a unit pixel.

[0016] Figure 5 is a circuit diagram for describing a unit pixel of an image sensor of the related art.

[0017] Figure 6 is a diagram showing a method according to an embodiment of the present invention. Figure 2 A timing diagram of a driving method for a readout period of a unit pixel.

[0018] 7A to 7H is a diagram showing a method according to some embodiments Figure 2Graph showing changes in the potential of each photodiode of a unit pixel.

[0019] Figure 8 is a circuit diagram showing an example of voltage node arrangement according to an embodiment.

[0020] Fig. 9 is a block diagram illustrating an image sensor according to an embodiment.

[0021] Fig.10 is a circuit diagram for describing a pixel of an image sensor according to an embodiment.

[0022] Fig.11 is a diagram showing a method according to an embodiment of the present invention. Fig.10 A timing diagram of a unit pixel driving method.

[0023] Fig.12 is a flowchart illustrating an operating method of an image sensor according to an embodiment. DETAILED DESCRIPTION

[0024] Hereinafter, various embodiments of the present disclosure may be described in detail and clearly so that those skilled in the art can easily implement the various embodiments.

[0025] Figure 1 is a block diagram showing an image sensor according to an embodiment. Figure 1 , the image sensor 100 may include a pixel array 110 , a row decoder / driver (Row-DEC.&DRV.) 120 , an analog-to-digital converter (ADC) 130 , an output buffer 140 , and a timing controller 150 .

[0026] The pixel array 110 includes a plurality of unit pixels 112. For example, the plurality of unit pixels 112 may be arranged in a matrix form. The pixel array 110 may receive a plurality of pixel drive signals (CSn) (such as, for example, a selection signal, a reset signal, a transmission control signal, a gain control signal, a switch control signal, and a voltage selection signal) from a row decoder / driver 120. The pixel array 110 may operate under the control of the received pixel drive signal (CSn), and each of the unit pixels 112 may convert an optical signal into an electrical signal. The electrical signal generated by each unit pixel 112 may be provided to an analog-to-digital converter 130 via a plurality of column lines CLm.

[0027] Each unit pixel 112 includes a split photodiode pixel and includes a plurality of photoelectric elements. One photoelectric element included in each unit pixel 112 may have a larger receiving area than another photoelectric element. A photoelectric device having a relatively large receiving area may be referred to as a large photodiode (hereinafter referred to as "LPD"). A photoelectric device having a relatively small receiving area may be referred to as a small photodiode (hereinafter referred to as "SPD").

[0028] In some embodiments, the photoelectric element may be a photodiode (PD). The photodiode PD is a photoelectric element that generates charges in proportion to the light signal incident from each pixel and accumulates the generated charges. The photoelectric element may be a photodiode PD, a photocapacitor, a photogate, a pinned photodiode (PPD), a local pinned photodiode, an organic photodiode (OPD) or a quantum dot (QD) or a combination thereof. The following various embodiments are described on the premise that the photoelectric element is a photodiode PD. However, the above-mentioned other photoelectric elements may be used, and the embodiments are not limited to the photodiode PD.

[0029] In some embodiments, each of the plurality of unit pixels 112 included in the pixel array 110 may support dual conversion gains providing a high conversion gain (HCG) mode and a low conversion gain (LCG) mode. The corresponding photodiode LPD or SPD may support the dual conversion gain mode. Therefore, each of the unit pixels 112 may support a total of four modes by supporting the HCG mode and the LCG mode according to the illumination of the incident light of each photodiode LPD or SPD. In other words, for each unit pixel 112, the large photodiode LPD may support both the HCG mode and the LCG mode, and the small photodiode SPD may support both the HCG mode and the LCG mode. Therefore, the unit pixel 112 may provide a wide dynamic range.

[0030] Specifically, during the readout operation of the unit pixel 112, the reset voltage provided during the readout of the large photodiode LPD may be different from the reset voltage provided during the readout of the small photodiode SPD. The reset voltage provided during the readout of the small photodiode SPD may be provided by a regulator inside the image sensor. Therefore, even when correlated double sampling is not performed during some of the readout operations of the small photodiode SPD, the kTC noise caused by the second voltage node VDD may be reduced. According to an embodiment, the structure and operation of each unit pixel 112 will be described more fully below with reference to the accompanying drawings.

[0031] Under the control of the timing controller 150, the row decoder / driver (Row-DEC.&DRV.) 120 can select a row of the pixel array 110. In order to select a row in the plurality of rows, the row decoder / driver 120 can generate a selection signal. The row decoder / driver 120 can sequentially activate each control signal CSn for the unit pixel corresponding to the selected row. In some embodiments, the sequence can be predetermined. Then, the reset level signal, the image level signal, etc. generated from each unit pixel 112 in the selected row can be transmitted to the analog-to-digital converter 130.

[0032] The analog-to-digital converter (ADC) 130 may convert the reset level signal and the image level signal into digital signals, and may output the digital signals as image data. For example, the analog-to-digital converter 130 may sample the reset level signal and the image level signal in a correlated double sampling manner, and may then convert the sampling result into a digital signal. To this end, in some embodiments, a correlated double sampler (CDS) may be further included before the analog-to-digital converter 130. Double sampling may be performed during some of the readout operations of the small photodiode SPD.

[0033] The output buffer 140 may latch and output the image data provided from the analog-to-digital converter 130 in units of columns. The output buffer 140 may temporarily store the image data output from the analog-to-digital converter 130 under the control of the timing controller 150, and may then sequentially output the latched (or temporarily stored) image data through the column decoder.

[0034] The timing controller 150 may control the pixel array 110, the row decoder / driver 120, the analog-to-digital converter 130, the output buffer 140, etc. In order to perform operations of the pixel array 110, the row decoder / driver 120, the analog-to-digital converter 130, the output buffer 140, etc., the timing controller 150 may supply control signals (such as clock signals and timing control signals). In some embodiments, the timing controller 150 may include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, etc.

[0035] Figure 2 is a circuit diagram showing a unit pixel 112 according to an embodiment. Figure 3 and Figure 4 is a method for describing the method according to some embodiments Figure 2 112 is a diagram of a reset operation in a readout operation of each of the photodiodes LPD and SPD in the unit pixel 112.

[0036] The unit pixel 112 according to the embodiment may support a dual conversion gain mode for providing a high conversion gain and a low conversion gain for each photodiode LPD or SPD. Specifically, the reset voltage provided during the readout operation of the large photodiode LPD may be different from the reset voltage provided during the readout operation of the small photodiode SPD. The reset voltage provided to the small photodiode SPD during readout may be lower than the reset voltage provided to the large photodiode LPD during readout. To this end, the reset node ND connected to the reset transistor RX may be selectively connected to one of the plurality of voltage nodes VRD and VDD based on the readout mode.

[0037] Reference Figure 2 , the unit pixel 112 may include a plurality of photodiodes LPD and SPD, a plurality of transistors LTX, STX, RX, DRX, DX, SX, SW1, SW2, VX1, and VX2, and an overflow capacitor Cof.

[0038] Transfer transistors LTX and STX connected to the plurality of photodiodes LPD and SPD are turned on or off in response to transfer control signals LTG and STG provided from the row decoder / driver 120, respectively. The transfer transistors LTX and STX may transmit charges accumulated in the connected photodiodes LPD and SPD to the floating diffusion areas FD1 and FD2, respectively.

[0039] The plurality of floating diffusion regions FD1 , FD2 , and FD3 are physically separated from one another.

[0040] One end of the overflow capacitor Cof may be connected to the first floating diffusion area FD1, and the other end thereof may be connected to the voltage node VSC. Charges overflowing from the small photodiode SPD may be accumulated in the overflow capacitor Cof through the first floating diffusion area FD1.

[0041] The overflow capacitor Cof may be connected to the first floating diffusion area FD1 through the first switching transistor SW1. In an example embodiment, the overflow capacitor Cof may be selectively connected to the first floating diffusion area FD1 based on a readout mode. In response to a first switch control signal CSW1 provided from the row decoder / driver 120, the first switching transistor SW1 is turned on or off according to a conversion gain mode during a readout operation of the small photodiode SPD. For example, the first switching transistor SW1 is turned on in a low conversion gain (LCG) mode of the small photodiode SPD to electrically couple the capacitance of the overflow capacitor Cof together with the first floating diffusion area FD1 and the third floating diffusion area FD3 to the second floating diffusion area FD2.

[0042] The first floating diffusion area FD1 may be connected to the third floating diffusion area FD3 through the second switching transistor SW2. In response to the second switching control signal CSW2 provided from the row decoder / driver 120, the second switching transistor SW2 is turned on or off according to a conversion gain mode during a readout operation of the small photodiode SPD.

[0043] The second floating diffusion area FD2 may be connected to the third floating diffusion area FD3 through the gain control transistor DRX, and connected to the gate of the drive transistor DX operating as a source follower amplifier.

[0044] In response to the gain control signal DRG provided from the row decoder / driver 120, the gain control transistor DRX is turned on or off according to the readout mode of the large photodiode LPD. For example, the gain control transistor DRX is turned on in the low conversion gain (LCG) mode of the large photodiode LPD to electrically couple the third floating diffusion area FD3 to the second floating diffusion area FD2. The gain control transistor DRX is turned off in the high conversion gain (HCG) mode of the large photodiode LPD to electrically separate the third floating diffusion area FD3 from the second floating diffusion area FD2.

[0045] The gate of the drive transistor DX may be connected to the second floating diffusion region FD2 and may function as a source follower amplifier. For example, in some embodiments, the drive transistor DX may convert the potential of the second floating diffusion region FD2 into a voltage and may output the voltage (Vout) to the column line CLi (see FIG. 1 ) via the select transistor SX (or referred to as a source follower transistor). Figure 1 In some embodiments, the drive transistor DX may convert the potential of the second floating diffusion area FD2 to which the first floating diffusion area FD1 and / or the third floating diffusion area FD3 are electrically coupled into a voltage based on a readout mode, and may output the voltage (Vout) to the column line via the selection transistor SX.

[0046] When a unit pixel to be read in a row unit is selected, the selection transistor SX is turned on. The selection transistor SX can be driven by a selection signal SEL provided in a row unit from the row decoder / driver 120. When the selection transistor SX is turned on, the voltage amplified by the drive transistor DX can be delivered to the drain of the selection transistor SX. The selection transistor SX can output the received voltage (Vout) to the column line CLi.

[0047] The reset transistor RX of the unit pixel 112 according to the embodiment may reset at least one of the first floating diffusion area FD1, the second floating diffusion area FD2, and the third floating diffusion area FD3 in response to the reset signal RG. Figure 2As shown in , the source of the reset transistor RX can be connected to the third floating diffusion area FD3. When the reset signal RG is activated while the gain control signal DRG is activated, the gain control transistor DRX is turned on, and the reset voltage is delivered from the reset node ND to the second floating diffusion area FD2 and the third floating diffusion area FD3. When the reset signal RG is activated while the second switch control signal CSW2 is activated, the second switch transistor SW2 is turned on, and the reset voltage is delivered from the reset node ND to the first floating diffusion area FD1 and the third floating diffusion area FD3. Depending on the readout mode, the gain control transistor DRX and the second switch transistor SW2 can be turned on or off at the same time, or one or the other of the gain control transistor DRX and the second switch transistor SW2 can be turned on.

[0048] The reset transistor RX is selectively connected to one of the plurality of voltage nodes VRD and VDD through the reset node ND. For example, the reset transistor RX may be selectively connected to one of the voltage nodes VRD and VDD through the reset node ND based on the readout mode. In an embodiment, the voltage nodes VRD and VDD may provide different reset voltages. In an embodiment, the voltage provided by the first voltage node VRD may be lower than the voltage provided by the second voltage node VDD. The reset node ND may be connected to the plurality of voltage nodes VRD and VDD through the first voltage selection transistor VX1 or the second voltage selection transistor VX2, respectively. The first voltage selection transistor VX1 and the second voltage selection transistor VX2 are turned on or off in response to the voltage selection signals CVX1 and CVX2 provided from the row decoder / driver 120, respectively. The first voltage selection transistor VX1 and the second voltage selection transistor VX2 are turned on in different readout sections.

[0049] In the embodiments, reference Figure 3 During the readout operation of the large photodiode LPD, the second voltage selection transistor VX2 is turned on, and the second switch transistor SW2 and the first voltage selection transistor VX1 are turned off or maintained in the off state. In this case, the voltage of the second floating diffusion area FD2 and the third floating diffusion area FD3 can be reset to the voltage level provided by the second voltage node VDD.

[0050] In detail, during the readout operation of the large photodiode LPD, in each of the HCG mode and the LCG mode, a reset level signal is sampled from at least one floating diffusion area. The reset level signal is sampled from at least one floating diffusion area that is reset to a voltage level provided by the second voltage node VDD. To this end, the second voltage selection transistor VX2 connected to the reset node ND and the second voltage node VDD is turned on. In addition, the reset transistor RX connecting the reset node ND and the third floating diffusion area FD3 and the gain control transistor DRX connecting the third floating diffusion area FD3 and the second floating diffusion area FD2 are turned on. The second switch transistor SW2 and the first voltage selection transistor VX1 are turned off or maintained in a cut-off state. When the third floating diffusion area FD3 is electrically coupled to the second floating diffusion area FD2, the reset voltage from the second voltage node VDD is provided to the third floating diffusion area FD3 and the second floating diffusion area FD2.

[0051] In the embodiments, reference Figure 4 , in at least part of the section during the readout period of the small photodiode SPD, the first voltage selection transistor VX1 is turned on, the second switch transistor SW2 is turned on, and the second voltage selection transistor VX2 is turned off or maintained in the off state. In this case, based on the conversion gain mode during the readout period of the small photodiode SPD, the voltage of each of the first floating diffusion area FD1, the second floating diffusion area FD2, and the third floating diffusion area FD3 electrically coupled to each other can be reset to the voltage level provided by the first voltage node VRD. In some embodiments, the voltage of the overflow capacitor Cof and the first floating diffusion area FD1, the second floating diffusion area FD2, and the third floating diffusion area FD3 electrically coupled to each other can be reset to the voltage level provided by the first voltage node VRD.

[0052] In detail, during the readout operation of the small photodiode SPD, in each of the HCG mode and the LCG mode, a reset level signal is sampled from at least one floating diffusion area. The reset level signal is sampled from at least one floating diffusion area reset to a voltage level provided by the first voltage node VRD. To this end, the first voltage selection transistor VX1 connected to the reset node ND and the first voltage node VRD is turned on, and the second voltage selection transistor VX2 is turned off or maintained in a cut-off state. The reset transistor RX connecting the reset node ND and the third floating diffusion area FD3, the second switch transistor SW2 connecting the third floating diffusion area FD3 and the first floating diffusion area FD1, and the gain control transistor DRX connecting the third floating diffusion area FD3 and the second floating diffusion area FD2 are turned on. In the case where the first floating diffusion area FD1 and the third floating diffusion area FD3 are electrically connected to the second floating diffusion area FD2, the reset voltage from the first voltage node VRD is provided to the third floating diffusion area FD3, the first floating diffusion area FD1, and the second floating diffusion area FD2. During the readout operation of the small photodiode SPD, in the LCG mode, the first switch transistor SW1 connecting the overflow capacitor Cof and the first floating diffusion area FD1 may be turned on. In this case, the reset voltage from the first voltage node VRD may also be provided to the overflow capacitor Cof.

[0053] In other words, during the readout operation of the large photodiode LPD and the readout operation of the small photodiode SPD, at least one floating diffusion area of ​​the unit pixel 112 according to an embodiment is reset to a different voltage level. That is, in some embodiments, at least one floating diffusion area of ​​the unit pixel 112 is reset during the readout operation of the large photodiode LPD to a voltage level different from the voltage level to which the at least one floating diffusion area of ​​the unit pixel 112 is reset during the readout operation of the small photodiode SPD.

[0054] Specifically, in some embodiments, the reset voltage provided from the first voltage node VRD through the reset node ND during the readout operation of the small photodiode SPD can be lower than the reset voltage provided from the second voltage node VDD during the readout operation of the large photodiode LPD. Therefore, the kTC noise caused by the second voltage node VDD during the readout operation of the small photodiode SPD can be reduced. In addition, the normal operation of the load transistor (Load Tr.) through which a constant current flows for the operation as a source follower amplifier of the drive transistor DX can be guaranteed.

[0055] Figure 5 is a circuit diagram for describing a unit pixel of an image sensor of the related art. Figure 5In the split photodiode pixel of the related art, the reset transistor RX is connected to one second voltage node VDD. Therefore, the reset voltage of the second voltage node VDD is provided to the floating diffusion areas FD1, FD2, and FD3.

[0056] During the sampling operation of the reset level signal, the related art split photodiode pixel turns off the reset transistor RX after the reset voltage is supplied.

[0057] In the HCG mode of the large photodiode LPD of the split photodiode pixel of the related art, the gain control transistor DRX connected to the second floating diffusion area FD2 and the third floating diffusion area FD3 is turned off. In this case, due to the clock feedthrough when the gain control transistor DRX and the reset transistor RX are turned off, the voltage of the second floating diffusion area FD2 drops.

[0058] On the other hand, during the readout operation of the small photodiode SPD of the split photodiode pixel of the related art, the gain control transistor DRX connected to the second floating diffusion area FD2 and the third floating diffusion area FD3 is turned on. In addition, the switch transistor SW connected to the third floating diffusion area FD3 and the first floating diffusion area FD1 is turned on. In this case, when the switch transistor SW is turned on, the voltage of the first floating diffusion area FD1 increases due to clock feedthrough.

[0059] That is, in the split photodiode pixel of the related art, the difference between the reset level signal of the specific conversion gain mode of the large photodiode LPD and the reset level signal of the specific conversion gain mode of the small photodiode SPD can be very large. In addition, the voltage conversion ratio of the source follower transistor SX also has a predetermined change. For the function of the source follower transistor SX, the load transistor (Load Tr.) needs to operate in the saturation region. However, due to the large difference in the reset level signal, the load transistor (Load Tr.) may operate in the triode region. Therefore, there is a possibility that the pixel cannot operate normally.

[0060] In contrast, in the unit pixel 112 according to the embodiment, the reset voltage provided during the readout operation of the small photodiode SPD is lower than the reset voltage provided during the readout operation of the large photodiode LPD. In other words, at least one floating diffusion area is reset to a voltage level different from the voltage level to which at least one floating diffusion area is reset during the readout period of the small photodiode SPD. Therefore, regardless of clock feedthrough, the difference between the reset level signal of the specific conversion gain mode of the large photodiode LPD and the reset level signal of the specific conversion gain mode of the small photodiode SPD is not large, or the levels of the two signals can be similar to each other. As a result, the load transistor (Load Tr.) can operate in the saturation region, and the pixel can operate normally.

[0061] In an embodiment, when the reset voltage provided during the readout operation of the small photodiode SPD is provided by an internal regulator of the image sensor, the kTC noise caused by the second voltage node VDD can be reduced. When it is not possible to perform correlated double sampling (for example, in an LCG mode for sampling the charge on the overflow capacitor of the small photodiode SPD), this reduction in kTC noise is more advantageous than the split photodiode pixel of the related art.

[0062] Figure 6 is a diagram showing the Figure 2 A timing diagram of a driving method during a readout period of a unit pixel. 7A to 7H is a diagram showing a method according to some embodiments Figure 2 Graph showing changes in the potential of each photodiode of a unit pixel.

[0063] Reference Figure 6 , at time T0, the reset signal RG and the gain control signal DRG provided to the unit pixel 112 are at a high level. In addition, the first voltage selection signal CVX1 is at a low level, and the second voltage selection signal CVX2 is at a high level. Therefore, the reset voltage of the second voltage node VDD is provided to the reset node ND. The reset transistor RX is turned on, and the reset node ND is electrically connected to the third floating diffusion area FD3 and the second floating diffusion area FD2. The charges of the third floating diffusion area FD3 and the second floating diffusion area FD2 are drained to the second voltage node VDD through the reset node ND. As a result, the second floating diffusion area FD2 and the third floating diffusion area FD3 are reset to the reset voltage level provided by the second voltage node VDD.

[0064] At time T1, the reset signal RG and the gain control signal DRG are turned to low level. Therefore, the reset transistor RX and the gain control transistor DRX are turned off. As a result, the third floating diffusion area FD3 is electrically isolated from the second floating diffusion area FD2, and each of the second floating diffusion area FD2 and the third floating diffusion area FD3 is in a floating state.

[0065] At time T2, the driving transistor DX samples the voltage level of the second floating diffusion area FD2, and can output the sampling result as a reset level signal (Vout) of the HCG mode of the large photodiode LPD. Fig. 7A As shown in FIG. 1 , the second floating diffusion region FD2 is isolated from the third floating diffusion region FD3 by a potential barrier of the gain control transistor DRX. The voltage level of the second floating diffusion region FD2 can be defined as a first reference voltage (1 st reference voltage), and can be used as a reference voltage for the HCG mode of a large photodiode LPD.

[0066] At time T3, the transfer control signal LTG turns to a high level. Therefore, the transfer transistor LTX connected to the large photodiode LPD is turned on, and the charges accumulated in the large photodiode LPD move to the second floating diffusion area FD2.

[0067] At time T4, the transmission control signal LTG is at a low level. The driving transistor DX samples the voltage level of the second floating diffusion area FD2 and can output the sampling result as an image level signal (Vout) of the HCG mode of the large photodiode LPD. Figure 7B As shown in , the second floating diffusion area FD2 is blocked from the third floating diffusion area FD3 by the potential barrier of the gain control transistor DRX. Therefore, an image level signal having an HCG mode can be output. Correlated double sampling (CDS) can be performed on the image level signal of the HCG mode of the large photodiode LPD based on the first reference voltage.

[0068] At time T5, the gain control signal DRG is turned to a high level. Therefore, the gain control transistor DRX is turned on. As a result, the third floating diffusion area FD3 is electrically coupled to the second floating diffusion area FD2, and the charge of the second floating diffusion area FD2 is shared with the third floating diffusion area FD3. In some embodiments, the transfer control signal LTG can be turned to a high level again, so that the remaining charge in the large photodiode LPD moves to the second floating diffusion area FD2.

[0069] At time T6, the transmission control signal LTG is at a low level. The driving transistor DX samples the voltage level of the second floating diffusion area FD2 electrically coupled to the third floating diffusion area FD3, and outputs the sampling result as an image level signal (Vout) of the LCG mode of the large photodiode LPD. Figure 7C As shown in FIG. 1 , the potential barrier of the gain control transistor DRX disappears, and the second floating diffusion area FD2 shares charges with the third floating diffusion area FD3. Therefore, an image level signal in the LCG mode can be output.

[0070] At time T7, the reset signal RG changes to a high level. The gain control signal DRG is at a high level. In addition, the second voltage selection signal CVX2 is also at a high level. Therefore, the reset voltage of the second voltage node VDD is provided to the third floating diffusion area FD3 and the second floating diffusion area FD2 through the reset node ND. The second floating diffusion area FD2 and the third floating diffusion area FD3 are reset to the reset voltage level provided by the second voltage node VDD.

[0071] At time T8, the driving transistor DX samples the voltage level of the second floating diffusion area FD2 electrically coupled to the third floating diffusion area FD3, and outputs the sampling result as a reset level signal (Vout) in the LCG mode of the large photodiode LPD. Fig.7D As shown in FIG. 1 , the potential barrier of the gain control transistor DRX disappears, and the second floating diffusion area FD2 is electrically coupled to the third floating diffusion area FD3. The voltage level of the second floating diffusion area FD2 electrically coupled to the third floating diffusion area FD3 may be defined as a second reference voltage (2 nd reference voltage) and can be used as a reference voltage for the LCG mode of a large photodiode LPD.

[0072] exist Figure 6 , the second voltage selection signal CVX2 is shown to be maintained at a high level during the readout operation of the large photodiode LPD. However, in some embodiments, the second voltage selection signal CVX2 may selectively maintain a high level only during the same segment as the reset signal RG. For example, the second voltage selection signal CVX2 may be transitioned to a high level together with the reset signal RG.

[0073] At time T9, the reset signal RG, the second switch control signal CSW2 and the first voltage selection signal CVX1 are turned to a high level. The second voltage selection signal CVX2 is turned to a low level. The gain control signal DRG is at a high level. Therefore, the first voltage selection transistor VX1 is turned on, and the reset voltage of the first voltage node VRD is provided to the reset node ND. The reset transistor RX is turned on, and the reset node ND is electrically connected to the first floating diffusion area FD1, the second floating diffusion area FD2 and the third floating diffusion area FD3. The charges of the first floating diffusion area FD1, the second floating diffusion area FD2 and the third floating diffusion area FD3 are discharged to the first voltage node VRD through the reset node ND. As a result, the first floating diffusion area FD1, the second floating diffusion area FD2 and the third floating diffusion area FD3 are reset to the reset voltage level provided by the first voltage node VRD. The first voltage node VRD can receive a voltage from a regulator inside the image sensor.

[0074] At time T10, the driving transistor DX samples the voltage level of the second floating diffusion area FD2 electrically coupled to the first floating diffusion area FD1 and the third floating diffusion area FD3, and outputs the sampling result as a reset level signal (Vout) in the HCG mode of the small photodiode SPD. Fig. 7E As shown in FIG. 1 , the overflow capacitor Cof is blocked from the first floating diffusion area FD1 by the potential barrier of the first switch transistor SW1. Therefore, the charge overflowing from the small photodiode SPD to the overflow capacitor Cof does not move to the first floating diffusion area FD1. The voltage level of the second floating diffusion area FD2 electrically coupled to the first floating diffusion area FD1 and the third floating diffusion area FD3 can be defined as a third reference voltage (3 rd reference voltage) and can be used as a reference voltage for the HCG mode of a small photodiode SPD.

[0075] At time T11, the transfer control signal STG changes to a high level. Therefore, the transfer transistor STX connected to the small photodiode SPD is turned on, and the charge accumulated in the small photodiode SPD moves to the first floating diffusion area FD1. The charge moved to the first floating diffusion area FD1 is shared with the second floating diffusion area FD2 and the third floating diffusion area FD3.

[0076] At time T12, the transmission control signal STG is at a low level. The driving transistor DX samples the voltage level of the second floating diffusion area FD2 electrically coupled to the first floating diffusion area FD1 and the third floating diffusion area FD3, and outputs the sampling result as an image level signal (Vout) in the HCG mode of the small photodiode SPD. Figure 7FAs shown in FIG. 1 , the overflow capacitor Cof is blocked from the first floating diffusion region FD1 by the potential barrier of the first switch transistor SW1. Therefore, an image level signal having an HCG mode can be output.

[0077] At time T13, the first switch control signal CSW1 is turned to a high level. Therefore, the first switch transistor SW1 is turned on. As a result, the overflow capacitor Cof is electrically coupled to the first floating diffusion area FD1, and the charge of the overflow capacitor Cof is shared with the first floating diffusion area FD1, the second floating diffusion area FD2, and the third floating diffusion area FD3. In some embodiments, before time T13, the transfer control signal STG is again turned to a high level, so that the remaining charge in the small photodiode SPD moves to the first floating diffusion area FD1.

[0078] At time T14, the driving transistor DX samples the voltage level of the second floating diffusion area FD2 electrically coupled to the overflow capacitor Cof, the first floating diffusion area FD1, and the third floating diffusion area FD3, and outputs the sampling result as an image level signal (Vout) in the LCG mode of the small photodiode SPD. Figure 7G As shown in , the charge of the overflow capacitor Cof is shared by the first floating diffusion area FD1, the second floating diffusion area FD2, and the third floating diffusion area FD3. Therefore, an image level signal of the LCG mode of the small photodiode SPD can be output.

[0079] At time T15, the reset signal RG is turned to a high level. The gain control signal DRG, the first switch control signal CSW1, the second switch control signal CSW2, and the first voltage selection signal CVX1 are at a high level. Therefore, the overflow capacitor Cof, the first floating diffusion area FD1, the second floating diffusion area FD2, and the third floating diffusion area FD3 are reset to the reset voltage level provided by the first voltage node VRD. In an example embodiment, after the image level signal of the LCG mode is output during the readout period of the first photoelectric element SPD, the reset node ND can provide the voltage of the first voltage node VRD to at least one of the first floating diffusion area FD1, the second floating diffusion area FD2, and the third floating diffusion area FD3.

[0080] At time T16, the driving transistor DX samples the voltage level of the second floating diffusion area FD2 electrically coupled to the overflow capacitor Cof, the first floating diffusion area FD1, and the third floating diffusion area FD3, and outputs the sampling result as a reset level signal (Vout) in the LCG mode of the small photodiode SPD. Figure 7HAs shown in FIG. 1 , the potential barriers of the first switch transistor SW1, the second switch transistor SW2, and the gain control transistor DRX disappear, and the overflow capacitor Cof, the first floating diffusion area FD1, and the third floating diffusion area FD3 are coupled to the second floating diffusion area FD2. The voltage level of the second floating diffusion area FD2 electrically coupled to the overflow capacitor Cof, the first floating diffusion area FD1, and the third floating diffusion area FD3 may be defined as a fourth reference voltage (4 st reference voltage) and can be used as a reference voltage for the LCG mode of small photodiodes SPD.

[0081] exist Figure 6 , the first voltage selection signal CVX1 is shown to be maintained at a high level during the readout operation of the small photodiode SPD. However, the first voltage selection signal CVX1 may selectively maintain a high level only during the same segment as the reset signal RG. For example, the first voltage selection signal CVX1 may be converted to a high level together with the reset signal RG.

[0082] As reference Figure 6 and 7A to 7H As described, during the readout operation of the small photodiode SPD, a reset voltage of the first voltage node VRD lower than a reset voltage provided by the second voltage node VDD is supplied to at least one floating diffusion region through the first voltage selection transistor VX1. Figure 6 In the example, R may represent the time point at which the reset level signal is obtained, and S may represent the time point at which the image level signal is obtained.

[0083] Figure 8 1 is a circuit diagram illustrating an example of a layout of a plurality of voltage nodes provided in a pixel array 110_1 of an image sensor according to an embodiment.

[0084] The multiple voltage nodes VRD and VDD may correspond to Figure 2 Detailed description of components identical or similar to those described above is omitted for the sake of brevity.

[0085] The first voltage node VRD, which is one of the multiple voltage nodes VRD and VDD provided in the pixel array 110_1 according to the embodiment, can provide a lower voltage to the unit pixel 112 than the second voltage node VDD, which is another voltage node. The voltages of the first voltage node VRD and the second voltage node VDD can be provided to at least one floating diffusion region of the unit pixel 112 through the reset node ND of the unit pixel 112. The first voltage node VRD and the second voltage node VDD can be connected to the reset node ND through the third switching transistor SW3 and the fourth switching transistor SW4, respectively. The voltage of the first voltage node VRD can be provided as a reset voltage during the readout operation of the small photodiode SPD of the unit pixel 112. The voltage of the second voltage node VDD can be provided as a reset voltage during the readout operation of the large photodiode LPD of the unit pixel 112. Therefore, the third switching transistor SW3 and the fourth switching transistor SW4 are turned on during different time periods.

[0086] In some embodiments, the first voltage node VRD of the image sensor may have a mesh structure. Therefore, even in the case of pixels of the image sensor operating in a rolling shutter manner, the reset voltage of the first voltage node VRD may be accurately provided for each row of the pixel array during a readout operation of the small photodiode SPD.

[0087] The first voltage node VRD of the mesh structure can reduce the blinking horizontal fixed pattern noise (HFPN) of the image sensor.

[0088] Back to Figure 5 , the split photodiode pixel of the related art may be instantly filled with the charge on the overflow capacitor Cof by very high intensity incident light. In this case, at the time of the reset operation of the small photodiode SPD, a very large overflow current from the voltage node VDD may flow into the small photodiode SPD. Therefore, due to the voltage drop in the floating diffusion area caused by the overflow current, the reset level signals of the pixels in some rows are significantly different from the reset level signals of the pixels in other rows, and thus flicker HFPN occurs.

[0089] In contrast, regardless of the overflow current, the first voltage node VRD according to the embodiment can reduce the voltage drop in the floating diffusion region by lowering the resistance of the reset path through the mesh structure. As a result, the flickering HFPN can be prevented.

[0090] Fig. 9 is a circuit diagram showing an example of an image sensor 100_1 according to an embodiment.

[0091] The image sensor 100_1 includes a pixel array 110 including a plurality of unit pixels, a row decoder / driver (Row-DEC.&DRV.) 120, an analog-to-digital converter (ADC) 130, an output buffer 140, and a timing controller 150. In some embodiments, the image sensor 100_1 may further include a regulator 160. Each pixel in the pixel array 110 is a split photodiode pixel including a large photodiode LPD and a small photodiode SPD, and the large photodiode LPD and the small photodiode SPD have receiving areas of different sizes from each other. The pixel includes an overflow capacitor that stores charges overflowing from the small photodiode SPD. Each of the large photodiode LPD and the small photodiode SPD has an HCG mode and an LCG mode. For the sake of brevity, a detailed description of components that are the same or similar to the above components is omitted.

[0092] During the readout operation of each of the large photodiode LPD and the small photodiode SPD according to the embodiment, voltages having different levels may be supplied as reset voltages.

[0093] The voltage of the first voltage node VRD may be received from the regulator 160 inside the image sensor. The regulator 160 receives the analog power AVDD from the power management integrated circuit (PMIC) 200 located outside the image sensor, may adjust the analog power AVDD, and may provide the adjusted analog power AVDD to the first voltage node VRD. The voltage of the second voltage node VDD may be received from the PMIC 200. That is, the voltage of the second voltage node VDD may be provided by the AVDD from the PMIC 200 without being adjusted by the regulator 160.

[0094] The PMIC 200 may provide the image sensor 100_1 with an analog power supply AVDD, a digital power supply DVDD, and an input / output (IO) power supply IOVDD. The second voltage node VDD may be connected to the analog power supply AVDD provided by the PMIC 200. That is, the second voltage node VDD may be connected to the analog power supply AVDD provided by the PMIC 200 without being regulated by the regulator 160.

[0095] During the readout operation of the small photodiode SPD, the voltage of the first voltage node VRD may be provided as a reset voltage of the pixel circuit. During the readout operation of the large photodiode LPD, the voltage of the second voltage node VDD may be provided as a reset voltage of the pixel circuit. The voltage of the first voltage node VRD may be lower than the voltage of the second voltage node VDD.

[0096] Therefore, the image sensor 100_1 according to the embodiment can reduce kTC noise caused by the analog power supply AVDD while reading out charges stored in the overflow capacitor according to the conversion gain mode of the small photodiode SPD.

[0097] In addition, the difference between the reset level signal of the small photodiode SPD and the reset level signal of the large photodiode LPD caused by clock feedthrough can be reduced. Therefore, the normal operation of the pixel is guaranteed.

[0098] Fig.10 is a circuit diagram showing an example of a unit pixel 112_1 of an image sensor according to an embodiment. Fig.11 is a diagram showing the Fig.10 A timing diagram of a driving method during a readout period of the unit pixel 112_1.

[0099] The unit pixel 112_1 according to the embodiment includes a large photodiode LPD and a small photodiode SPD having receiving areas of different sizes. The unit pixel 112_1 may support a dual conversion gain mode for providing a high conversion gain and a low conversion gain for each photodiode LPD or SPD. The reset voltage provided to the small photodiode SPD during the readout operation may be lower than the reset voltage provided to the large photodiode LPD during the readout operation. To this end, the voltage node ND connected to the reset transistor RX may be selectively connected to one of the plurality of voltage nodes VRD and VDD based on the readout mode.

[0100] Reference Fig.10 , the unit pixel 112_1 may include a plurality of photodiodes LPD and SPD, a plurality of transistors LTX, STX, RX, DRX, DX, SX, SW1, SW2, VX1 and VX2, and an overflow capacitor Cof. For the sake of brevity, detailed descriptions of components identical or similar to those described above are omitted.

[0101] With reference Figure 2 Unlike the described unit pixel 112, the unit pixel 112_1 according to the embodiment includes a fifth switching transistor SW5 connecting the reset node ND and the overflow capacitor Cof. The fifth switching transistor SW5 is controlled in response to a fifth switching control signal CSW5.

[0102] Reference Fig.11 At time T1, the driving transistor DX samples the voltage level of the second floating diffusion area FD2 and may output the sampling result as a reset level signal (Vout) of the HCG mode of the large photodiode LPD.

[0103] At time T2 , the driving transistor DX may sample the voltage level of the second floating diffusion area FD2 , and may output the sampling result as an image level signal (Vout) of the HCG mode of the large photodiode LPD.

[0104] At time T3, the driving transistor DX samples the voltage level of the second floating diffusion area FD2 electrically coupled to the third floating diffusion area FD3 and outputs the sampling result as an image level signal (Vout) of the LCG mode of the large photodiode LPD.

[0105] At time T4, the driving transistor DX samples the voltage level of the second floating diffusion area FD2 electrically coupled to the third floating diffusion area FD3 and outputs the sampling result as a reset level signal (Vout) of the LCG mode of the large photodiode LPD.

[0106] At time T5 , the driving transistor DX samples the voltage level of the second floating diffusion area FD2 electrically coupled to the first and third floating diffusion areas FD1 and FD3 , and outputs the sampling result as a reset level signal (Vout) in the HCG mode of the small photodiode SPD.

[0107] At time T6, the driving transistor DX samples the voltage level of the second floating diffusion area FD2 electrically coupled to the first and third floating diffusion areas FD1 and FD3, and outputs the sampling result as an image level signal (Vout) in the HCG mode of the small photodiode SPD.

[0108] At time T7, the driving transistor DX samples the voltage level of the second floating diffusion area FD2 electrically coupled to the overflow capacitor Cof, the first floating diffusion area FD1 and the third floating diffusion area FD3, and outputs the sampling result as an image level signal (Vout) in the LCG mode of the small photodiode SPD.

[0109] At time T8, when the reset signal RG is at a high level, the fifth switch control signal CSW5 is turned to a high level. The first voltage selection signal CVX1 is at a high level. Therefore, the fifth switch transistor SW5 is turned on, and the voltage of the first voltage node VRD is provided to the overflow capacitor Cof through the reset node ND and the fifth switch transistor SW5. In an example embodiment, in at least one section of the LCG mode during the readout period of the small photodiode SPD, in a state where the overflow capacitor Cof, the first floating diffusion area FD1, the second floating diffusion area FD2, and the third floating diffusion area FD3 are combined together, while the voltage of the first voltage node VRD providing a voltage relatively low or less than the threshold voltage is provided to the third floating diffusion area FD3, the fifth switch transistor is turned on SW5. Therefore, the charge in the overflow capacitor Cof is quickly discharged to the first voltage node VRD. As a result, the reset speed of the overflow capacitor Cof can be improved. Thereafter, at time T9, the driving transistor DX samples the voltage level of the second floating diffusion area FD2 electrically coupled to the overflow capacitor Cof, the first floating diffusion area FD1 and the third floating diffusion area FD3, and outputs the sampling result as a reset level signal (Vout) in the LCG mode of the small photodiode SPD.

[0110] Fig.12 is a flowchart showing an operation method of an image sensor according to an embodiment. The image sensor may include a reference Figure 2 The unit pixel 112 described or referred to Fig.10 The unit pixel 112_1 is described. The unit pixel includes a large photodiode LPD and a small photodiode SPD having receiving areas of different sizes. Some charges of the small photodiode SPD may overflow into the capacitor due to high-intensity incident light.

[0111] The unit pixel includes a plurality of floating diffusion regions. During a readout period of the small photodiode SPD, the plurality of floating diffusion regions are electrically coupled in the HCG mode and the LCG mode (eg, differently). The plurality of floating diffusion regions coupled to each other may be different in each mode.

[0112] Each photodiode LPD or SPD for a unit pixel may support a dual conversion gain mode for providing high conversion gain and low conversion gain.A reset voltage supplied to a small photodiode SPD during a readout operation may be lower than a reset voltage supplied to a large photodiode LPD during a readout operation.

[0113] In operation S110, the operating method includes sampling a first reset level of a voltage of at least one of the floating diffusion areas during an HCG mode of the small photodiode SPD. For example, the operating method may include: in the HCG mode during a readout period of the small photodiode SPD, sampling a first reset level signal of at least one floating diffusion area in the floating diffusion area that is reset to a voltage of a first voltage node providing a low voltage among a plurality of voltage nodes.

[0114] In operation S120, the operating method includes sampling a first image level of a voltage of at least one floating diffusion region during an HCG mode of the small photodiode SPD. For example, the operating method may include sampling a first image level signal based on a voltage of at least one floating diffusion region among a plurality of floating diffusion regions in an HCG mode during a readout period of the small photodiode SPD.

[0115] In operation S130, the operating method includes sampling a second image level of a voltage of at least one floating diffusion area during an LCG mode of the small photodiode SPD. For example, the operating method may include sampling a second image level signal of at least one floating diffusion area among a plurality of floating diffusion areas in an LCG mode during a readout period of the small photodiode SPD.

[0116] In operation S140, the operating method includes sampling a second reset level of a voltage of at least one floating diffusion region during an LCG mode of the small photodiode SPD. For example, the operating method may include sampling a second reset level signal of at least one floating diffusion region reset to a voltage of a first voltage node providing a low voltage in an LCG mode during a readout period of the small photodiode SPD.

[0117] The unit pixel may reset at least one floating diffusion area to a voltage of a first voltage node providing a low voltage before sampling the first reset level signal and sampling the second reset level signal.

[0118] The unit pixel may perform readout of the large photodiode LPD before or after the readout period of the small photodiode SPD. During the readout of the large photodiode LPD, at least one floating diffusion area may be reset to a voltage of a second voltage node higher than a voltage of the first voltage node.

[0119] The first voltage node may be connected to a voltage provided by a regulator inside the image sensor, and the second voltage node may be connected to a voltage provided by the PMIC.

[0120] The above description relates to various detailed embodiments. Embodiments in which the design is simply changed or the design is easily changed are included in the scope of the present disclosure as well as the scope of the above-described embodiments. Technologies that are easily changed and implemented by using the above-described embodiments are included in the scope of the present disclosure.

[0121] According to an embodiment, an image sensor including a split photodiode may reduce noise of an image.

[0122] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. An image sensor, comprising: A first photoelectric element having a first receiving area; a second photoelectric element having a second receiving area larger than the first receiving area of ​​the first photoelectric element; a first floating diffusion region in which the charges generated by the first photoelectric element are stored; a second floating diffusion region in which the charges generated by the second photoelectric element are stored and which is connected to the gate of the driving transistor; a capacitor selectively connected to the first floating diffusion region based on a readout mode and configured to store charges overflowing from the first photoelectric element; a third floating diffusion region connected to the first floating diffusion region and the second floating diffusion region through the first switch transistor and the second switch transistor respectively; as well as A reset transistor, a first terminal of the reset transistor is selectively connected to one of the plurality of voltage nodes through a reset node, and a second terminal of the reset transistor is connected to the third floating diffusion region.

2. The image sensor according to claim 1, wherein: The plurality of voltage nodes provide different voltages.

3. The image sensor according to claim 1, wherein: During the readout period of the first photoelectric element and the readout period of the second photoelectric element, the second floating diffusion area is reset to a different voltage level, and the third floating diffusion area is reset to a different voltage level.

4. The image sensor according to claim 1, wherein: The plurality of voltage nodes include a first voltage node and a second voltage node, and The voltage provided by the first voltage node is lower than the voltage provided by the second voltage node.

5. The image sensor according to claim 4, wherein: During at least one section of a readout period of the first photoelectric element, the reset node is connected to the first voltage node.

6. The image sensor according to claim 4, wherein: After outputting an image level signal of a low conversion gain mode during a readout period of the first photo element, the reset node supplies a voltage of the first voltage node to at least one of the first floating diffusion area, the second floating diffusion area, and the third floating diffusion area.

7. The image sensor according to claim 4, wherein: In at least one section of the low conversion gain mode during the readout period of the first photoelectric element, the reset node provides the voltage of the first voltage node to the third floating diffusion area when the capacitor, the first floating diffusion area, the second floating diffusion area and the third floating diffusion area are combined together.

8. The image sensor according to claim 4, wherein: In at least one section of the high conversion gain mode during the readout period of the first photoelectric element, the reset node provides the voltage of the first voltage node to the third floating diffusion area in a state where the first floating diffusion area, the second floating diffusion area and the third floating diffusion area are combined together.

9. The image sensor according to claim 4, wherein: During a readout period of the second photoelectric element, the reset node is connected to the second voltage node.

10. The image sensor according to claim 4, wherein: The second voltage node receives a voltage from a power management integrated circuit, and the first voltage node receives a voltage from a regulator inside the image sensor.

11. The image sensor according to any one of claims 1 to 10, wherein: The reset node is connected to each of the plurality of voltage nodes through a plurality of reset switches, respectively, and The plurality of reset switches are respectively turned on in different time periods during the readout period.

12. The image sensor according to claim 4, wherein: The first voltage node has a mesh structure.

13. The image sensor according to claim 1, further comprising: The switch element is configured to connect one end of the capacitor to the reset node.

14. The image sensor according to claim 13, wherein: In at least one section of the low conversion gain mode during the readout period of the first photoelectric element, when the capacitor, the first floating diffusion area, the second floating diffusion area and the third floating diffusion area are combined together, the switching element is turned on while the voltage of a voltage node among the multiple voltage nodes that provides a voltage relatively low or less than the threshold voltage is provided to the third floating diffusion area.

15. An operating method of an image sensor, the image sensor comprising a pixel, the pixel comprising a first photoelectric element, a second photoelectric element having a receiving area larger than a receiving area of ​​the first photoelectric element, a plurality of floating diffusion regions, and a plurality of voltage nodes, the operating method comprising: sampling a first reset level signal of at least one floating diffusion area among the plurality of floating diffusion areas reset to a voltage of a first voltage node among the plurality of voltage nodes providing a voltage relatively low or less than a threshold voltage in a high conversion gain HCG mode during a readout period of the first photoelectric element; sampling a first picture level signal of the at least one floating diffusion area among the plurality of floating diffusion areas in an HCG mode during a readout period of the first photoelectric element; sampling a second image level signal of at least one floating diffusion area of ​​the plurality of floating diffusion areas in a low conversion gain LCG mode during a readout period of the first photoelectric element; as well as sampling a second reset level signal of at least one floating diffusion area among the plurality of floating diffusion areas reset to a voltage of a first voltage node in an LCG mode during a readout period of the first photoelectric element, During a readout period of the first photoelectric element, the plurality of floating diffusion regions are electrically coupled differently in the HCG mode and the LCG mode.

16. The operating method according to claim 15, further comprising: before sampling the first reset level signal, resetting at least one floating diffusion area among the plurality of floating diffusion areas to a voltage of a first voltage node; as well as Before sampling the second reset level signal, at least one floating diffusion area among the plurality of floating diffusion areas is reset to a voltage of a first voltage node.

17. The operating method according to claim 15, further comprising: At least one of the plurality of floating diffusion regions is reset to a voltage of a second voltage node that provides a voltage higher than that of the first voltage node during at least a portion of a readout period of the second photoelectric element.

18. The operating method according to claim 17, wherein: The first voltage node is connected to a voltage provided by a regulator inside the image sensor, and the second voltage node is connected to a voltage provided by a power management integrated circuit.

19. The operating method according to any one of claims 15 to 18, wherein: The reset voltage provided by the multiple voltage nodes to at least one of the multiple floating diffusion areas during the readout period of the first photoelectric element is different from the reset voltage provided by the multiple voltage nodes to at least one of the multiple floating diffusion areas during the readout period of the second photoelectric element.

20. An electronic device, comprising: a pixel array, wherein a plurality of pixels are arranged in the pixel array; as well as a control circuit configured to send control signals to a plurality of transistors included in pixels of the plurality of pixels, Among them, pixels include: A first photoelectric element having a first receiving area; a second photoelectric element having a second receiving area larger than the first receiving area of ​​the first photoelectric element; a first floating diffusion region in which the charges generated by the first photoelectric element are stored; a second floating diffusion region in which the charges generated by the second photoelectric element are stored and which is connected to the gate of the driving transistor; a capacitor selectively connected to the first floating diffusion region based on a readout mode and configured to store charges overflowing from the first photoelectric element; a third floating diffusion region connected to the first floating diffusion region and the second floating diffusion region through the first switching transistor and the second switching transistor, respectively; and A reset transistor, a first terminal of the reset transistor is selectively connected to one of the plurality of voltage nodes through a reset node, and a second terminal of the reset transistor is connected to the third floating diffusion region.

Images