Method for improving flatness of bottom oxide layer of floating gate type memory

Abstract

The invention provides a method for improving the flatness of a bottom oxide layer of a floating gate type memory. In the traditional process, a large number of dangling bonds are generated in a SiO2 / Si interface, defects are generated, the durability and data retention of a device are reduced, and interface traps and body traps are more easily generated in the cycle operation of a flash memory due to poor uniformity of a bottom oxide layer. According to the method, under the condition that the thickness of the oxide is not increased, higher film quality is achieved, by introducing the means that the sacrificial oxide layer grows first and then is removed and combining chlorine-doped oxidation growth, the problem of interface damage is effectively avoided, and meanwhile the uniformity of the film thickness can be improved. In addition, the surface roughness is measured through an atomic force microscope, and a TCAD spurt tool is used for evaluating the leakage condition of electrons passing through the oxide. In combination with final device durability and data retention simulation and experimental results, the method provided by the invention is finally verified to improve the reliability of the flash device.

Description

Technical Field

[0001] The invention relates to the field of semiconductor integrated circuit memory devices, in particular to a method for improving the flatness of a bottom oxide layer of a floating gate type memory. Background Art

[0002] As the demand for embedded flash memory grows in the automotive electronics field, higher and higher requirements are placed on the cycle endurance and data retention performance of flash memory. Flash memory uses electrically programmable erase operations to write and erase data. After long-term continuous operation, the oxide layer damage caused by electrons passing through the oxide layer will cause the device to fail. On the one hand, in order to obtain greater electronic programming and erasing efficiency, the oxide needs to be thin enough. But on the other hand, for the data retention requirements of the device, each flash memory cell only allows a small amount of electron leakage to maintain data for more than 10 years. To this end, the oxide needs to show better electron leakage performance without increasing the oxide thickness.

[0003] Since the programming operation of the memory device is realized by the hot carrier injection mechanism, the quality of the bottom oxide layer related to the programming operation will affect the threshold voltage in the programming operation, and further affect the device reliability under cyclic operation. The mainstream process of advanced flash memory is often to grow the bottom oxide layer by high-temperature dry oxidation or ISSG process. The oxide layer grown by the above method has high density and is suitable for growing thin oxide layers, but the above process will produce a large number of dangling bonds in the SiO2 / Si interface, which is easy to produce interface traps. Such defects in the oxide layer will reduce the device durability and data retention. In addition, since the process is prone to local oxidation thinning at the corners of shallow trench isolation (STI) and uneven thickness of the central oxidation area, the bottom oxide layer with poor uniformity will cause the flash memory device to be more prone to interface traps and body traps in cyclic operation. Therefore, the above factors will lead to reduced performance of advanced flash memory cells and poor device reliability. Summary of the invention

[0004] The purpose of the present invention is at least to solve the problem of oxide layer quality and film thickness uniformity during the growth process of the bottom oxide layer, and to propose a method for improving the flatness of the bottom oxide layer of a floating gate memory.

[0005] A method for improving the flatness of a bottom oxide layer of a floating gate memory, specifically comprising: depositing a tunneling layer on a substrate and then growing an oxide layer by dry oxygen oxidation; forming shallow trench isolation trenches in the substrate, followed by well implantation, and then annealing; Removing the oxide layer on the surface of the substrate, and then growing a sacrificial oxide layer by dry oxygen oxidation; The sacrificial oxide layer is stripped off, and then the bottom oxide layer is grown by chlorine-doped oxidation.

[0006] Preferably, in the process of growing the oxide layer by dry oxygen oxidation, the temperature is 1000-1200° C., the oxygen flow rate is 1-5 L / min, and the protective gas is an inert gas.

[0007] Preferably, the annealing temperature is 1100-1300°C.

[0008] Preferably, in the process of growing the sacrificial oxide layer by dry oxygen oxidation, the temperature is 800-1000° C., the oxygen flow rate is 1-5 L / min, and the protective gas is an inert gas.

[0009] Preferably, the sacrificial oxide layer is wet-stripped using dilute hydrofluoric acid; Preferably, in the process of growing the bottom oxide layer by chlorine-doped oxidation, the temperature is 800-1000° C., the oxygen flow rate is 1-5 L / min, and the chlorine source is a chlorine-containing solvent.

[0010] Preferably, the chlorine-containing solvent is C2HCl3.

[0011] Preferably, the inert gas is nitrogen or argon.

[0012] Preferably, the bottom oxide layer has a thickness of 9-11 nm.

[0013] Preferably, the substrate is a silicon wafer.

[0014] The beneficial effects of the present invention are: The present invention introduces a method of first growing and then removing the sacrificial oxide layer, and combines it with chlorine-doped oxidation growth to effectively avoid the generation of interface damage problems and improve the uniformity of film thickness. Compared with dry oxygen oxidation and ISSG processes, the flash device oxide layer thickness uniformity simulated by the method of the present invention is better, which has a significant effect on improving the reliability of flash devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 A schematic diagram of a process for preparing a bottom oxide layer of a memory device according to the present invention; Figure 2 The present invention shows a module process for achieving a high flatness of the bottom oxide layer of a 1.5T floating gate memory. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0018] Figure 2 The module process of the present invention for improving the flatness of the bottom oxide layer of a 1.5T floating gate memory is as follows: Step S1: Before the oxide layer grows, the silicon wafer needs to be wet cleaned and dried for standby use, then a tunneling layer is deposited on the substrate, and then an 11nm oxide layer is grown by dry oxygen oxidation. The oxidation furnace temperature is set to 1180°C, the oxygen flow rate is 1L / min, and the silicon wafer is heated in an open circuit after being loaded into the furnace. In addition, inert gas nitrogen or argon is introduced into the oxidation furnace for protection.

[0019] Step S2: After the STI is formed, well implantation is performed, followed by annealing at 1100° C. to repair the damage to the crystal lattice.

[0020] STI is a technology used for device isolation. Its purpose is to form shallow grooves in the silicon substrate to isolate different devices or circuit parts and prevent electrical interference. The desired groove shape is formed on the surface of the silicon wafer by exposure and development. A groove with a depth of several hundred nanometers to 1 micron is etched on the silicon substrate using dry etching. A layer of silicon oxide is grown in the etched groove by thermal oxidation. This oxide layer will play an insulating and isolating role. The groove is filled with a filling material (such as silicon oxide or silicon nitride grown by CVD). Chemical mechanical polishing (CMP) is performed to flatten the surface to ensure that the top surface of the STI is flush with the surrounding silicon plane.

[0021] The well implantation process is mainly used to introduce dopant ions into the silicon substrate to form n-type or p-type wells to realize different types of transistors. The dopant ions are selected according to the type of well to be formed. Boron (B) is usually used as a p-type dopant, and phosphorus (P) or arsenic (As) is used as an n-type dopant. The dopant ions are implanted into the silicon substrate by ion implantation technology. The implantation energy and dose need to be precisely controlled to ensure that the depth and concentration of the doping meet the design requirements. Annealing is performed after implantation to repair the lattice defects caused by ion implantation and promote the diffusion of dopant ions to form a uniform well area. After annealing, the dopant ions form an n-type or p-type well in the substrate. The depth and doping concentration of the well usually affect the threshold voltage and current characteristics of the device.

[0022] Step S3: After ion implantation, the oxide layer on the surface is removed.

[0023] Step S4: Grow a 5 nm sacrificial oxide layer in a dry O2 atmosphere at 900°C, still with inert gas protection.

[0024] Step S5: stripping the sacrificial oxide of 5 nm by wet dilute hydrofluoric acid.

[0025] Step S6: Add C2HCL3 (TCE) to dry O2 at 900°C to grow a 10nm bottom oxide layer.

[0026] The oxidation rate is sensitive to impurities present in the oxidant. This method allows chlorine to enter silicon oxide, which can increase the oxidation rate and improve the properties of the oxide layer and SiO2 / Si interface. For example, it reduces the fixed positive charge density and interface state density, passivates mobile ions, and thus reduces oxidation defects introduced by ion contamination of equipment and process raw materials, reduces defects in SiO2, thereby improving the oxide layer's ability to resist electrical breakdown, reduces stacking faults in silicon oxide, and increases the life of minority carriers in the silicon substrate.

[0027] After step S6 is completed, conventional preparation of source and drain, floating gate, control gate, erase gate and select gate is performed, which will not be described in detail. Figure 1 .

[0028] The surface roughness of the oxide in the present invention is measured by an atomic force microscope (AFM), and the surface roughness can be used to evaluate the leakage of electrons through the oxide. The oxide surface obtained by the sacrificial oxide layer method is smoother, and the smoother the oxide layer surface, the better the data retention performance. The present invention compares the uniformity of the oxide layer thickness of the flash device simulated by dry oxygen oxidation, ISSG process and the sacrificial oxide layer method proposed by the present invention through the TCAD sprocess tool, as well as the distribution of defects along the SiO2 gate oxide layer and the Si / SiO2 interface during the programming process. Combined with the final device durability and data retention simulation and experimental results, the method of the present invention finally verifies the effect of improving the reliability of the flash device.

[0029] The memory structure experiment and simulation based on this process are completed through actual tape-out and TCAD sprocess tools. Combined with actual electrical performance testing and device electrical modeling, actual reliability testing and device reliability simulation, the improvement of this process on oxide layer flatness and device reliability is evaluated. The memory simulation mainly involves the distribution of Si / SiO2 interface states, bulk oxide traps and near-interface oxide traps.

[0030] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for improving the flatness of the bottom oxide layer of a floating gate memory, characterized in that: The method is specifically: depositing a tunneling layer on a substrate and then growing an oxide layer by dry oxygen oxidation; forming shallow trench isolation trenches in the substrate, followed by well implantation, and then annealing; Removing the oxide layer on the surface of the substrate, and then growing a sacrificial oxide layer by dry oxygen oxidation; The sacrificial oxide layer is stripped off, and then the bottom oxide layer is grown by chlorine-doped oxidation.

2. The method according to claim 1, characterized in that In the process of growing the oxide layer by dry oxygen oxidation, the temperature is 1000-1200° C., the oxygen flow rate is 1-5 L / min, and the protective gas is an inert gas.

3. The method according to claim 1, characterized in that The annealing temperature is 1100-1300°C.

4. The method according to claim 1, characterized in that In the process of growing the sacrificial oxide layer by dry oxygen oxidation, the temperature is 800-1000° C., the oxygen flow rate is 1-5 L / min, and the protective gas is an inert gas.

5. The method according to claim 1, characterized in that The sacrificial oxide layer is wet stripped using dilute hydrofluoric acid; The method according to claim 1 is characterized in that the temperature during the growth of the bottom oxide layer by chlorine-doped oxidation is 800-1000° C., the oxygen flow rate is 1-5 L / min, and the chlorine source is a chlorine-containing solvent.

6. The method according to claim 6, characterized in that The chlorine-containing solvent is C2HCl3.

7. The method according to claim 2 or 4, characterized in that The inert gas used is nitrogen or argon.

8. The method according to claim 1, characterized in that The thickness of the bottom oxide layer is 9-11 nm.

9. The method according to claim 1, characterized in that The substrate is a silicon wafer.

Images