Semiconductor memory device and forming method thereof

Abstract

The invention provides a semiconductor memory device and a method of forming the same. The semiconductor memory device includes a plurality of nanowires vertically stacked over a substrate, and a plurality of memory films respectively surrounding the nanowires. Each memory film includes at least two dielectric layers formed on respective nanowires. The semiconductor memory device also includes a gate electrode layer surrounding the memory film, and an isolation structure sealing the gate electrode layer. The isolation structure directly contacts the gate electrode layer and the at least two dielectric layers of the memory film.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device, and more particularly to a flash memory having a three-dimensional structure. Background Art

[0002] The industry needs a flash memory with a three-dimensional structure, in which a memory cell array is stacked along a direction perpendicular to a main surface of a substrate to improve the integration of the memory cells. Summary of the invention

[0003] The semiconductor memory device includes a plurality of nanowires vertically stacked on a substrate, and a plurality of storage films respectively surrounding the nanowires. Each storage film includes at least two dielectric layers formed on the corresponding nanowire. The semiconductor memory device also includes a gate electrode layer surrounding the storage film, and an isolation structure sealing the gate electrode layer. The isolation structure directly contacts the gate electrode layer and at least two dielectric layers of the storage film.

[0004] The semiconductor memory device includes a first column of memory transistors stacked in a vertical direction. Each memory transistor in the first column includes at least two nanowires, and these nanowires of the memory transistors are stacked in respective stages. The semiconductor memory device also includes a second column of drain lines, which are stacked in respective stages in the vertical direction. The second column of drain lines is divided into a plurality of groups, each group of drain lines includes at least two drain lines, which are electrically connected to at least two nanowires of the corresponding memory transistor. The semiconductor memory device also includes a plurality of conductive vias respectively landing on the plurality of groups of drain lines, and at least two drain lines in each group are electrically connected to each other through the corresponding conductive vias.

[0005] A method for forming a semiconductor memory device includes forming a stack of a plurality of channel layers and a plurality of sacrificial layers arranged alternately. The stack includes a first strip region, a second strip region, and a connection region connecting the first strip region and the second strip region. The method also includes removing a portion of the sacrificial layer in the connection region, forming a storage film to surround a portion of the channel layer in the connection region, forming a gate electrode layer to surround the storage film, and removing a portion of the sacrificial layer in the first strip region and the second strip region to form a plurality of gaps exposing the storage film. The method also includes partially removing the storage film from the gaps, and replacing a portion of the channel layer in the first strip region and the second strip region with a plurality of conductive lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to make the features and advantages of the present invention more clearly understood, different embodiments are described in detail below with reference to the accompanying drawings:

[0007] Figure 1 is a circuit diagram showing a semiconductor memory device 100 having a three-dimensional structure according to some embodiments.

[0008] Figure 2 is a perspective schematic diagram showing a semiconductor memory device having a three-dimensional structure according to some embodiments.

[0009] FIG. 3A to FIG. 3O is a schematic diagram showing various intermediate stages of forming a semiconductor memory device having a three-dimensional structure according to some embodiments.

[0010] Figure 4A-1 to Figure 4C-3 is a schematic diagram showing various intermediate stages of forming a semiconductor memory device having a three-dimensional structure according to some embodiments.

[0011]

Explanation of symbols

[0012] 100,200:Semiconductor memory device

[0013] 102: Substrate

[0014] 104: Stack

[0015] 104C: Connection area

[0016] 104E1: First stripe

[0017] 104E2: Second stripe

[0018] 106,106E1,106E2: Sacrificial layer

[0019] 108,108E1,108E2: Channel layer

[0020] 108N:Nanowire

[0021] 110,144,150,156: Patterned mask layer

[0022] 111: Slot

[0023] 112: Space

[0024] 114: Gap

[0025] 116: Storage film

[0026] 118: First oxide layer

[0027] 120: Nitride layer

[0028] 122: Second oxide layer

[0029] 124: Gate electrode layer

[0030] 126: Gate structure

[0031] 127: Groove

[0032] 128: Dielectric layer

[0033] 130: Gap

[0034] 132: Isolation Structure

[0035] 134: Gap

[0036] 136: Gap

[0037] 140: Source / drain region

[0038] 142_1,142_2,142_3,142_4,142E1,142E2,160: Conductive wire

[0039] 146: Depression

[0040] 148: Dielectric layer

[0041] 152A, 152B: Through hole

[0042] 154,154A,154B: Conductive vias

[0043] 202:Metal layer

[0044] 204: Third oxide layer

[0045] C1,C2,C3,C4,C5,C6: columns

[0046] DL,DL_11,DL_12,DL_13,DL_14,DL_15,DL_16,DL_n1,DL_n2,DL_n3,DL_n4,D L_n5,DL_n6: drain line

[0047] L1, L2, L3, L4, L5: Level

[0048] MC,MC_11,MC_12,MC_13,MC_14: storage unit

[0049] MT: Transistor

[0050] SL,SL_11,SL_12,SL_13,SL_14,SL_15,SL_16,SL_n1,SL_n2,SL_n3,SL_n4,SL_n5,SL_n6: source line

[0051] T1, T2: thickness

[0052] WL, WL_1, WL_2: word lines DETAILED DESCRIPTION

[0053] refer to Figure 1The semiconductor memory device 100 may be a nonvolatile memory device, such as a flash memory device having a three-dimensional structure, or a NOR flash memory device having a three-dimensional structure. The semiconductor memory device 100 includes a memory cell array, word lines WL (e.g., WL_1 and WL_2), source lines SL (e.g., SL_11 to SL_16, and SL_n1 to SL_n6), and drain lines DL (e.g., DL_11 to DL_16, and DL_n1 to DL_n6).

[0054] To make it easier to understand the semiconductor memory device 100, an XYZ reference coordinate is provided in the figure. The X-axis and the Y-axis are generally oriented in a lateral (or horizontal) direction, that is, parallel to the main surface of the substrate. The Y-axis is lateral (e.g., approximately perpendicular) to the X-axis. The Z-axis is generally oriented in a vertical direction, that is, perpendicular to the main surface (or XY plane) of the substrate.

[0055] The memory cell array includes a plurality of memory cells MC (e.g., MC_11, MC_12, MC_13, and MC_14). Each memory cell MC includes a memory transistor. The memory transistors of the memory cells are gate all-around transistors (GAA transistors). In some embodiments, the memory transistor of each memory cell MC includes at least two nanowires, for example, 2-6 nanowires. For example, Figure 1 As shown, each memory cell MC contains three nanowires. Figure 1 Nanowires are shown in FIG. 1 , but the memory transistor may include any suitable nanostructure, such as nanosheets, nanotubes, etc.

[0056] The semiconductor memory device 100 includes a multi-level structure (or a multi-layer structure). The nanowires, source lines SL, and drain lines DL of the memory cells MC are arranged in each level (in the XY plane) of the multi-level structure. The levels are arranged in the Z direction.

[0057] For example, the source line SL_11, the drain line DL_11, and the nanowires between the source line SL_11 and the drain line DL_11, the source line SL_n1, the drain line DL_n1, and the nanowires between the source line SL_n1 and the drain line DL_n1 are located at the first level (i.e., the lowest level). The source line SL_12, the drain line DL_12, and the nanowires between the source line SL_12 and the drain line DL_12, the source line SL_n2, the drain line DL_n2, and the nanowires between the source line SL_n2 and the drain line DL_n2 are located at the second level (i.e., the second lowest level).

[0058] Each memory cell MC may be located in at least two stages (e.g., in three stages). On the other hand, the memory cells MC of the semiconductor memory device 100 are arranged in a plurality of columns (in the XZ plane). For example, the memory cells MC_11, MC_12, MC_13, and MC_14 are arranged in the same column.

[0059] The source lines SL and the drain lines DL extend in the X direction. The source lines SL are arranged in a plurality of columns, and the drain lines DL are arranged in a plurality of columns. For example, source lines SL_11 to SL_16 are arranged in one column, and drain lines DL_11 to DL_16 are arranged in another column. The columns of source lines SL and the columns of drain lines DL are alternately arranged in the Y direction, and a column of memory cells MC is interposed between a corresponding column of source lines SL and a corresponding column of drain lines DL.

[0060] For each memory cell MC, the source terminals of the memory transistor are electrically coupled to the vertically grouped source lines SL, and the drain terminals of the memory transistor are electrically connected to the vertically grouped drain lines DL. The source lines SL in each group are electrically connected to each other, and the drain lines DL in each group are electrically connected to each other. The number of source lines SL in each group or the number of drain lines DL in each group is the same as the number of nanowires of the corresponding memory cells electrically connected to them.

[0061] For example, the source port of the storage transistor of the memory cell MC_11 is electrically connected to a group of source lines SL_11, SL_12 and SL_13, and the source lines SL_11, SL_12 and SL_13 can be electrically connected together through conductive vias. Similarly, the drain port of the storage transistor of the memory cell MC_11 is electrically connected to a group of drain lines DL_11, DL_12 and DL_13, and the drain lines DL_11, DL_12 and DL_13 can be electrically connected together through conductive vias.

[0062] Memory cells MC located in the same column and the same level share the same set of source lines SL and the same set of drain lines DL. For example, memory cells MC_11 and MC_12 share a set of source lines SL_11, SL_12 and SL_13, and a set of drain lines DL_11, DL_12 and DL_13.

[0063] The word line WL extends along the Y direction. In some embodiments, the word line WL is located above the memory cell array, the source line SL, and the drain line DL. The word line WL is arranged at the topmost layer of the multi-level structure. In other embodiments, the word line WL may be located at the bottommost layer of the multi-level structure and below the memory cell array, the source line SL, and the drain line DL. The gate port of the memory transistor of the memory cell is electrically connected to the corresponding word line WL.

[0064] As semiconductor memory devices continue to shrink, gate lengths are limited by hot carrier injection. Specifically, smaller gate lengths tend to have electron velocity overshoots, and thus encounter fewer lattice collisions to heat the electrons. As a result, there is less opportunity for carrier scattering injection into the memory film and / or floating gate of the memory cell.

[0065] Since nanowires can provide more boundaries, the collision chances of carrier scattering and injection into the memory film and / or floating gate are increased. Therefore, the gate-all-around architecture can contribute to the continued scaling of semiconductor memory devices.

[0066] However, as the size (eg, diameter) of the nanowire decreases, the on-state current decreases dramatically. According to some embodiments of the present invention, a memory cell may include at least two nanowires, thereby increasing the on-state current and thus improving the operating speed.

[0067] refer to Figure 2 , Figure 2 The semiconductor memory device 100 shown in FIG. 1 may be the semiconductor memory device 100 of FIG. 1 . Figure 1 The semiconductor memory device 100 is formed on a substrate (not shown). The semiconductor memory device 100 includes a multi-level structure, in which levels L1-L5 are vertically stacked in the Z direction. The semiconductor memory device 100 may include more than five levels, for example, 6-100 levels.

[0068] The semiconductor memory device 100 includes a memory transistor MT, conductive lines 142E1 and 142E2, a conductive line 160, and a conductive via 154. The memory transistor MT functions as Figure 2 The memory cell MC discussed. The memory transistor MT includes a nanowire 108N, a gate structure 126 and a source / drain region 140. The nanowires 108N are arranged in levels L1-L4. Each memory transistor MT includes at least two nanowires 108N in adjacent levels. For example, the memory transistors MT each include two nanowires 108N in levels L1 and L2, or two nanowires 108N in levels L3 and L4. The nanowires 108N are also arranged in multiple columns (e.g., C2 and C5).

[0069] The gate structure 126 includes a storage film surrounding each nanowire 108N and a gate electrode layer surrounding the storage film. Each storage film includes an oxide-nitride-oxide (ONO) structure that can capture carriers to provide access to data in the storage cell. In some other embodiments, the storage film may include an additional metal layer that acts as a floating gate. The source / drain region 140 is sandwiched between the nanowire 108N and the conductive wires 142E1 and 142E2, and they are in direct contact. The source / drain region 140 can be made of a doped semiconductor material (such as silicon), for example, with n-type or p-type impurities.

[0070] Conductive lines 142E1 and 142E2 extend in the X direction. Conductive lines 142E1 and 142E2 are arranged in steps L1-L4. Conductive line 142E1 may be Figure 1 The source line SL, and the conductive line 142E2 can be Figure 1 The drain line DL is described. Each storage transistor MT is electrically coupled to a corresponding set of conductive lines 142E1 and a corresponding set of conductive lines 142E2. The conductive lines 142E1 are also arranged in multiple columns (e.g., C1 and C4), and the conductive lines 142E2 are also arranged in multiple columns (e.g., C3 and C6). In some embodiments, the conductive lines 142E1 and 142E2 are metal layers.

[0071] The conductive wires 142E1 may be divided into arrays, and the conductive wires 142E1 in each group are electrically connected together through the conductive vias 154. Similarly, the conductive wires 142E2 may be divided into arrays, and the conductive wires 142E2 in each group are electrically connected together through the conductive vias 154.

[0072] For example, the conductive lines 142E1 in the columns C1 of the stages L1 and L2 are in the same group and are electrically connected to each other; the conductive lines 142E1 in the columns C1 of the stages L3 and L4 are in the same group and are electrically connected to each other. The conductive lines 142E2 in the columns C3 of the stages L1 and L2 are in the same group and are electrically connected to each other, and the conductive lines 142E2 in the columns C3 of the stages L3 and L4 are in the same group and are electrically connected to each other. The number of source lines SL or drain lines DL in one group is the same as the number of nanowires 108N of the corresponding memory transistors MT electrically connected to them.

[0073] The conductive vias 154 are each landed on a corresponding group of conductive lines 142E1 and a corresponding group of conductive lines 142E2. Each conductive via 154 may penetrate all conductive lines in a group (142E1 or 142E2). In some embodiments, the conductive vias 154 are formed of a conductive material (e.g., metal).

[0074] The conductive line 160 is formed in the level L5 and is located above the memory transistor MT. The conductive line 160 extends along the Y direction. The conductive line 160 is electrically connected to the gate structure 126 of the memory transistor MT. The conductive line 160 is as shown in FIG. Figure 1 In some embodiments, the conductive line 160 is a metal line.

[0075] The semiconductor memory device 100 further includes an isolation structure (not shown) to seal the memory transistor MT, the conductive lines 142E1 and 142E2, the conductive line 160 and the conductive via 154, and fill the remaining space of the semiconductor memory device 100. The isolation structure may include a plurality of insulating layers.

[0076] A method of forming the semiconductor memory device 100 is discussed below.

[0077] Figure 3A and Figure 3B A perspective schematic diagram showing a three-dimensional semiconductor memory device 100 is shown. Figures ending with "-1" (e.g., Figure 3C-1 ) is the same as Figure 3B FIG. 1 is a plan view of the semiconductor memory device 100 corresponding to the XY plane in FIG. 1. FIG. 1 ends with “-2” (e.g., Figure 3C-2 ) is the same as Figure 3B 1 is a cross-sectional view of the semiconductor memory device 100 corresponding to the YY cross section in FIG. Figure 3C-3 ) is the same as Figure 3B Schematic cross-sectional view of the semiconductor memory device 100 corresponding to the X1-X1 cross section in FIG.

[0078] refer to Figure 3A , the semiconductor memory device 100 includes a substrate 102 and a stack 104 formed on the substrate 102. The substrate 102 may be or include a semiconductor substrate (e.g., a silicon substrate). The stack 104 is a multi-layer structure and includes a plurality of alternating sacrificial layers 106 and a plurality of channel layers 108. The sacrificial layers 106 may be made of an insulating material, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a combination thereof. The channel layer 108 may be made of a semiconductor material, such as silicon.

[0079] A patterned mask layer 110 is formed on the stack 104. The patterned mask layer 110 may be a patterned photoresist layer or a patterned hard mask layer. The patterned mask layer 110 has a rail-shaped profile in a top view. Specifically, the patterned mask layer 110 has two strip-shaped portions extending along the X direction, and a plurality of connecting portions between the strip-shaped portions and extending along the Y direction.

[0080] The stack 104 is etched using the patterned mask layer 110, such as Figure 3B As shown. The patterned mask layer 110 can be removed during the etching process or by an additional process. After the etching process, the stack 104 is formed into one or more patterned stacks 104, each of which has a rail-shaped profile in a top view. Each patterned stack 104 includes a first strip region 104E1, a second strip region 104E2, and a plurality of connection regions 104C. The first strip region 104E1 and the second strip region 104E2 extend along the X direction. The connection region 104C extends along the Y direction and connects the first strip region 104E1 to the second strip region 104E2. The space defined between the first strip region 104E1, the connection region 104C, and the second strip region 104E2 is marked as 112.

[0081] A patterning process is performed to remove the portion of the sacrificial layer 106 in the connection region 104C, thereby forming a gap 114, such as Figure 3C-2 and Figure 3C-3 The patterning process includes forming a patterned mask layer (eg, a patterned photoresist layer or a patterned hard mask layer) to cover the strip regions 104E1 and 104E2, and then performing an etching process (eg, an isotropic etching process) to selectively remove the sacrificial layer 106 in the connection region 104C.

[0082] After the patterning process, the portion of the channel layer 108 in the connection region 104C, referred to as the nanowire 108N, has its four major surfaces exposed from the space 112 and the gap 114. An additional trimming process may be used to shape the nanowire 108N to have a cylindrical profile.

[0083] Portions of the sacrificial layer 106 and the channel layer 108 in the strip region 104E1 are labeled 106E1 and 108E1 , respectively, and portions of the sacrificial layer 106 and the channel layer 108 in the strip region 104E2 are labeled 106E2 and 108E2 , respectively.

[0084] The storage film 116 and the gate electrode layer 124 are sequentially formed on the semiconductor memory device 100. Figure 3D-1 , Figure 3D-2 and Figure 3D-3 As shown. The storage film 116 surrounds the nanowire 108N and partially fills the space 112 and the gap 114. The storage film 116 includes a first oxide layer 118, a nitride layer 120 formed on the first oxide layer 118, and a second oxide layer 122 formed on the nitride layer 120. The first oxide layer 118 is formed along the nanowire 108N, the channel layers 108E1 and 108E2, and the sacrificial layers 106E1 and 106E2. The first oxide layer 118 and the second oxide layer 122 are made of silicon oxide, and the nitride layer 120 is made of silicon nitride.

[0085] Gate electrode layer 124 surrounds storage film 116 and overfills remaining portions of space 112 and gap 114. Gate electrode layer 124 is made of a conductive material (e.g., metal or metal nitride such as Ru, W, Co, Mo, Al, Cu, TiN, TaN, etc.).

[0086] The gate electrode layer 124 and the storage film 116 are patterned to form a trench 127. Figure 3E-1 to Figure 3E-3 As shown. The patterning process may include photolithography and etching processes. The grooves 127 and the nanostructures 108N are arranged alternately in the X direction. Alternatively, the grooves 127 may be arranged in a manner of skipping two or more nanostructures 108N. The grooves 127 expose the channel layers 108E1 and 108E2 and the sacrificial layers 106E1 and 106E2 in the strip regions. The gate electrode layer 124 and the storage film 116 are cut into a plurality of sections electrically isolated from each other by the grooves 127. The gate electrode layer 124 and the storage film 116 of each section are combined to form a gate structure 126.

[0087] A dielectric layer 128 is formed to fill the trench 127, such as Figure 3F-1 to Figure 3F-3 The dielectric layer 128 may be made of a dielectric material, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a combination thereof.

[0088] Then, a patterning process (using photolithography and etching processes) is performed on a portion (not shown) of the semiconductor memory device 100 between two adjacent patterned stacks 104 to open the trench 111. The trench 111 is located beside the channel layers 108E1 and 108E2 and the sacrificial layers 106E1 and 106E2, on the side where the gate electrode layer 124 is not defined, and does not overlap with the dielectric layer 128. A lateral etching process (e.g., using diluted hydrofluoric acid) is then performed to remove the sacrificial layers 106E1 and 106E2 in the strip region, thereby forming a gap 130, as shown in FIG. Figure 3G-2 As shown in the figure, the gap 130 exposes the storage film 116. During this process, care should be taken to ensure that the dielectric layer 128 is etched to a minimum extent in the lateral direction.

[0089] Then, a lateral etching process is performed to etch away the first oxide layer 118 (for example, using diluted hydrofluoric acid) and the nitride layer 120 (for example, using hot phosphoric acid) next to the channel layers 108E1 and 108E2 from the gap 130 until the second oxide layer 122 of the storage film 116 is exposed. Figure 3G-1 and Figure 3G-2 Likewise, care should be taken during this process to ensure that the dielectric layer 128 is etched to a minimal extent in the lateral direction.

[0090] The nitride layer 120 is initially a continuous extended layer surrounding the vertical stack of these nanowires 108N. Now it is cut into a plurality of nitride layers 120, each of which surrounds the corresponding nanowire 108N and is not connected to each other. In this way, the carriers injected into the storage film 116 will be confined around the corresponding nanowire 108N and cannot move to other adjacent nanowires 108N. Therefore, the risk of charge leakage can be reduced, thereby improving the ability of data retention.

[0091] In addition, each memory cell includes multiple channels, and each channel is surrounded by a charge storage region (e.g., a storage film). In this way, each memory cell can have multiple charge storage locations for data access, so the memory cell can be less negatively affected by defects in the storage film. Therefore, the reliability of the resulting semiconductor memory device can be improved.

[0092] The storage film 116 has a horizontal portion between the nanowire 108N and the gate electrode layer 124, which has a thickness T1 in the Z direction. Figure 3G-2 The storage film 116 has a vertical portion on the side wall of the gate electrode layer 124, which has a thickness T2 in the Y direction, as shown in FIG. Figure 3G-2 As shown, the thickness T1 is greater than the thickness T2. In other words, the number of layers of the horizontal portion of the storage film 116 is greater than that of the vertical portion of the storage film 116, for example, two more layers.

[0093] A dielectric layer is formed to fill the gap 130. The dielectric layer and the dielectric layer 128 are collectively referred to as an isolation structure 132. Figure 3H-1 and Figure 3H-2 The dielectric layer filled in the gap 130 can be the same material as the dielectric layer 128, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a combination thereof. The isolation structure 132 is in direct contact with the first oxide layer 118, the nitride layer 120, and the second oxide layer 122 of the storage film 116.

[0094] A lateral etching process (eg, isotropic etching) is performed to remove the channel layers 108E1 and 108E2 in the strip region, thereby forming a gap 134. Figure 3I-1 and Figure 3I-2 Then, a lateral etching process (eg, isotropic etching) is performed to recess the nanowire 108N, thereby forming a notch 136 .

[0095] Form source / drain regions 140 in the gaps 136, such as Figure 3J-1 and Figure 3J-2As shown. In some embodiments, the source / drain region 140 can be made of a doped semiconductor material (e.g., silicon), for example, doped with n-type or p-type impurities, and can be formed using an in-situ doped epitaxial growth process. The doped semiconductor material can be first deposited to fill the gap 134 and the gap 136, and then the doped semiconductor material can be removed from the gap 134 using an etching process. The remaining portion of the doped semiconductor material in the gap 136 serves as the source / drain region 140. The nanowire 108N, the gate structure 126 (including the storage film 116 and the gate electrode layer 124), and the source / drain region 140 are combined to form a gate-all-around transistor.

[0096] Conductive lines 142 (including 142E1 and 142E2) are formed in gaps 134, such as Figure 3K-1 to Figure 3K-3 As shown. The conductive line 142 is electrically connected to the source / drain region 140. In some embodiments, a silicide layer (e.g., CoSi) may be formed between the conductive line 142 and the source / drain region 140. In some embodiments, the conductive lines 142E1 and 142E2 may be made of a metal material (e.g., W, Al, Cu, Co, or Ru), a metal nitride (e.g., TiN or TaN), or a combination thereof.

[0097] In some embodiments, at the same level, the upper surfaces of the conductive wires 142E1 and 142E2, the upper surface of the source / drain region 140, and the upper surface of the nanowire 108N are substantially flush. In some embodiments, at the same level, the bottom surfaces of the conductive wires 142E1 and 142E2, the bottom surface of the source / drain region 140, and the bottom surface of the nanowire 108N are substantially flush. Figure 3K-2 shown.

[0098] Figure 3L to Figure 3O is a schematic cross-sectional view of the semiconductor memory device 100 , showing the formation of the conductive via 154 . Figure 3L to Figure 3O Corresponds to Figure 3B The X2-X2 section in the figure.

[0099] refer to Figure 3L , a patterned mask layer 144 (eg, a patterned photoresist layer or a patterned hard mask layer) is formed on the semiconductor memory device 100 . Figure 3L Conductive lines 142_1 to 142_4 shown in FIG. 1 may be conductive lines 142E1 or conductive lines 142E2 described above. Semiconductor memory device 100 is subjected to an etching process using patterned mask layer 144 to form recess 146. Patterned mask layer 144 may be removed during the etching process or by an additional process. Recess 146 cuts through two conductive lines 142_3 and 142_4.

[0100] refer to Figure 3M, a dielectric layer 148 is formed to fill the recess 146. In some embodiments, the dielectric layer 124 may be formed of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a combination thereof. A patterned mask layer 150 (e.g., a patterned photoresist layer or a patterned hard mask layer) is formed on the semiconductor memory device 100. The semiconductor memory device 100 is etched using the patterned mask layer 150 to form a through hole 152A. The through hole 152A passes through the conductive lines 142_3 and 142_4. The patterned mask layer 150 may be removed during the etching process or by an additional process.

[0101] refer to Figure 3N , forming a conductive via 154A in the via hole 152A. In some embodiments, the conductive via 154A can be formed of a metal material (e.g., W, Al, Cu, Co, or Ru), or a metal nitride (e.g., TiN or TaN), or a combination thereof. A patterned mask layer 156 (e.g., a patterned photoresist layer or a patterned hard mask layer) is formed on the semiconductor memory device 100. The semiconductor memory device 100 is etched using the patterned mask layer 156 to form a via hole 152B. The via hole 152B penetrates the dielectric layer 148 and the two conductive lines 142_1 and 142_2 located therebelow. The patterned mask layer 156 can be removed during the etching process, or removed by an additional process.

[0102] refer to Fig.3O , forming a conductive via 154B in the through hole 152B. In some embodiments, the conductive via 154B can be made of the same metal material as the conductive via 154A. The conductive lines 142_3 and 142_4 are electrically connected to each other through the conductive via 154A, thereby forming a vertical group of conductive lines. The conductive lines 142_1 and 142_2 are electrically connected to each other through the conductive via 154B, thereby forming another group of vertical group of conductive lines.

[0103] It should be understood that the semiconductor structure 100 may be further subjected to conventional processes to form various components on the semiconductor structure. For example, a conductive line (eg, a word line) may be formed on the gate-all-around transistor and electrically connected to the gate structure 126 .

[0104] refer to Figure 4A-1 to Figure 4C-3 The semiconductor memory device 200 and Figure 2 and FIG. 3A to FIG. 3O The semiconductor memory device 100 is similar to the semiconductor memory device 100, except that the storage film 116 further includes a metal layer.

[0105] Continued from Figure 3C-1 to Figure 3C-3 , a storage film 116 and a gate electrode layer 124 are sequentially formed on the semiconductor memory device 200, such as Figure 4A-1 to Figure 4A-3As shown. The storage film 116 further includes a metal layer 202 formed on the first oxide layer 118, and a third oxide layer 204 formed on the metal layer 202. The nitride layer 120 is formed on the third oxide layer 204. The metal layer 202 is made of Ru, W, Co, Mo, Al or Cu. In some embodiments, the metal layer 202 serves as a floating gate of a semiconductor memory device. The third oxide layer 204 is made of silicon oxide.

[0106] The semiconductor memory device 200 is performed in front Figure 3E-1 to Figure 3G-2 The steps described in , thereby forming a gate structure 126, a dielectric layer 128 and a gap 130, as shown in Figure 4B-1 and Figure 4B-2 The first oxide layer 118 and the metal layer 202 are etched away until the third oxide layer 204 of the storage film 116 is exposed, as shown in FIG. Figure 4B-2 shown.

[0107] The metal layer 202 is originally a continuous extended layer surrounding the vertical stack of these nanowires 108N. Now it is cut into a plurality of metal layers 202, each of which surrounds the corresponding nanowire 108N and is not connected to each other. Therefore, the carriers injected into the storage film 116 will be confined around the corresponding nanowire 108N and cannot move to other adjacent nanowires 108N. Therefore, the risk of charge leakage can be reduced, thereby improving the ability of data retention.

[0108] The semiconductor memory device 200 is Figure 3H-1 to Figure 3K-3 The isolation structure 132, the source / drain region 140 and the conductive line 142 (including 142E1 and 142E2) are formed. Figure 4C-1 to Figure 4C-3 As shown. The isolation structure 132 is in direct contact with the first oxide layer 118, the metal layer 202 and the third oxide layer 204 of the storage film 116. Afterwards, the semiconductor memory device 200 is subjected to the above Figure 3L to Figure 3O The above steps are followed to form a conductive through hole (not shown).

[0109] As described above, an embodiment of the present invention provides an architecture of a three-dimensional semiconductor memory device (e.g., a NOR flash memory). The memory cell of this semiconductor memory device includes a gate-all-around transistor, each of which includes at least two nanowires, which can increase the on-current and reduce the negative impact caused by defects in the memory film. In addition, the silicon nitride layer or floating gate of the memory film is cut laterally. Therefore, the risk of charge leakage can be reduced, thereby improving the ability to retain data.

[0110] Although the present invention is disclosed in the above embodiments, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the claims.

Claims

1. A semiconductor memory device, characterized in that: include: A plurality of nanowires are vertically stacked on a substrate; A plurality of storage films respectively surrounding the nanowires, wherein each of the storage films comprises at least two dielectric layers; a gate electrode layer surrounding the storage film; as well as An isolation structure seals the gate electrode layer, wherein the isolation structure directly contacts the gate electrode layer and the at least two dielectric layers of the storage film.

2. The semiconductor memory device according to claim 1, wherein: The at least two dielectric layers are a silicon oxide layer and a silicon nitride layer.

3. The semiconductor memory device according to claim 1, wherein: Also includes: A plurality of first conductive wires, vertically stacked on the substrate and electrically coupled to a plurality of first ends of the nanowires; as well as A plurality of second conductive wires are vertically stacked on the substrate and electrically coupled to a plurality of second ends of the nanowires.

4. The semiconductor memory device according to claim 3, wherein: The first conductive line is divided into a plurality of source line groups, and each source line group includes at least two source lines electrically connected to each other through a conductive through hole.

5. The semiconductor memory device according to claim 3, wherein: The second conductive lines are divided into a plurality of drain lines, and each drain line group includes at least two drain lines electrically connected to each other through a conductive through hole.

6. The semiconductor memory device according to claim 3, wherein: Also includes: A plurality of first source / drain regions, sandwiched between the first conductive wire and the first end of the nanowire; as well as A plurality of second source / drain regions are sandwiched between the second conductive wire and the second end of the nanowire.

7. The semiconductor memory device according to claim 6, wherein: A top surface of each of the first source / drain regions is flush with a top surface of the corresponding first conductive line, and a bottom surface of each of the first source / drain regions is flush with a bottom surface of the corresponding first conductive line.

8. The semiconductor memory device according to claim 1, wherein: Each of the memory films further includes a metal layer, which is sandwiched between the at least two dielectric layers of the memory film and directly contacts the isolation structure.

9. A semiconductor memory device, characterized in that: include: A first column of a plurality of memory transistors stacked in a vertical direction, wherein each memory transistor in the first column comprises at least two nanowires, and the nanowires of the memory transistors are stacked in respective stages; a plurality of drain lines in a second column, the drain lines being stacked in the respective steps in the vertical direction, wherein the drain lines in the second column are divided into a plurality of groups, each group of drain lines comprising at least two drain lines electrically connected to the at least two nanowires of the corresponding storage transistor; as well as A plurality of conductive vias are respectively landed on a plurality of groups of drain lines, wherein the at least two drain lines in each group are electrically connected to each other through the corresponding conductive vias.

10. The semiconductor memory device according to claim 9, wherein: Also includes: A third column of multiple source lines are stacked in the respective stages in the vertical direction, wherein the memory transistors of the first column are sandwiched between the drain lines of the second column and the source lines of the third column.

11. The semiconductor memory device according to claim 10, wherein: The source lines in the third column are divided into a plurality of groups, each group of source lines includes at least two source lines electrically connected to the at least two storage nanowires of the corresponding storage transistors, and the at least two source lines in each group are electrically connected to each other.

12. The semiconductor memory device according to claim 9, wherein: The storage transistors in the first column include: a plurality of storage films surrounding the nanowires respectively, and a gate electrode layer covering the storage films. Each of the memory films comprises at least three layers and has a vertical portion along a side wall of the gate electrode layer and a horizontal portion between the gate electrode layer and the corresponding nanowire, and The horizontal portion of the storage film has a greater number of layers than the vertical portion of the storage film.

13. The semiconductor memory device according to claim 9, wherein: The nanowires extend in a first horizontal direction, and the drain lines extend in a second horizontal direction, wherein the second horizontal direction is perpendicular to the first horizontal direction.

14. The semiconductor memory device according to claim 13, wherein: Also includes: A word line is located above the storage transistors in the first column, the word line extends in the first horizontal direction and is electrically coupled to the storage transistors in the first column.

15. The semiconductor memory device according to claim 9, wherein: One of the conductive vias penetrates the at least two drain lines in a corresponding group.

16. A method for forming a semiconductor memory device, characterized in that: include: Forming a stack of a plurality of channel layers and a plurality of sacrificial layers arranged alternately, wherein the stack comprises a first strip region, a second strip region, and a connecting region connecting the first strip region and the second strip region; removing portions of the sacrificial layer in the connection region; forming a storage film to surround portions of the channel layer in the connection region; forming a gate electrode layer to surround the storage film; removing a plurality of portions of the sacrificial layer in the first strip-shaped region and the second strip-shaped region to form a plurality of gaps exposing the storage film; partially removing the storage film from the gap; as well as Portions of the channel layer in the first strip region and the second strip region are replaced with a plurality of conductive lines.

17. The method for forming a semiconductor memory device according to claim 16, wherein: The steps of forming the storage film include: depositing a first oxide layer; depositing a nitride layer on the first oxide layer; and A second oxide layer is deposited on the nitride layer.

18. The method for forming a semiconductor memory device according to claim 17, wherein: The step of partially removing the storage film from the gap includes: The first oxide layer and the nitride layer are etched until the second oxide layer is exposed.

19. The method for forming a semiconductor memory device according to claim 16, wherein: The first strip region and the second strip region extend in a first horizontal direction, and the connection region extends in a second horizontal direction perpendicular to the first horizontal direction.

20. The method for forming a semiconductor memory device according to claim 16, wherein: Also includes: A first conductive via is formed passing through a first conductive line and a second conductive line among the conductive lines.

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