Quantum-bit device, method for manufacturing quantum-bit device, and contact layer for use in such method

Abstract

A qubit device, a method for manufacturing a qubit device, and a contact layer for use in the method. A qubit device includes a first superconductor layer, a second superconductor layer, a capacitor, a first interconnect, and a second interconnect. The first superconductor layer includes a first superconductor material. The first superconductor material is a first anisotropic layered material having a covalently bound atomic layer and a first c-axis perpendicular to the covalently bound atomic layer of the first superconductor material. The second superconductor layer includes a second superconductor material. The second superconductor material is a second anisotropic layered material having a covalently bound atomic layer and a second c-axis perpendicular to the covalently bound atomic layer of the second superconductor material. A second superconductor layer disposed over the first superconductor layer to form a Josephson junction between the first superconductor material and the second superconductor material, where the first c-axis and the second c-axis are aligned with each other at the Josephson junction; and wherein the aligned first and second c-axes at the Josephson junction intersect both the first and second superconductor layers. The capacitor includes a first electrode and a second electrode. A first interconnect electrically connects the first electrode and the first superconductor layer. A second interconnect electrically connects the second electrode and the second superconductor layer. The capacitor is arranged at a vertical position that exceeds the vertical position of both the first and second superconductor layers.

Description

Technical Field

[0001] The present disclosure relates to a qubit device using a high-Tc superconductor, such as a d-wave superconductor, and in particular to a qubit device similar to a transmon type. Background Art

[0002] The modern microelectronics industry is experiencing rapid growth, with a trend toward widespread use of qubits, which provide the basis for quantum computing. Quantum computing has received much attention over the past few years, in part because it promises ultrafast factorization and the potential to efficiently simulate quantum dynamics. There are many different architectures for quantum computers based on the different physical systems used to implement the qubits. These include atomic trap and ion trap quantum computing, superconducting charge and flux qubits, nuclear magnetic resonance, spin- and charge-based quantum dots, nuclear spin quantum computing, and optical quantum computing. All of these systems have their own advantages in quantum information processing. However, even though there may be some leaders now (such as ion trap and superconducting quantum computing), it seems that no physical implementation has a clear advantage over other implementations at this time.

[0003] Conventional superconducting qubit devices include Josephson junctions between low-temperature superconductor materials (such as Al or Nb). The qubit device can be flexibly designed to match the necessary parameters. Its macroscopic size allows strong coupling, thereby achieving fast gates and measurements. The transmission sub-superconducting qubit is the most common hardware implementation of quantum technology, and it is used in conventional superconducting quantum processors (such as those developed by Google or IBM). The main weakness of the transmission sub-is that it is coupled to the electric field in the capacitor, resulting in a shortened coherence time and crosstalk between qubits, and thus causing errors in the calculation.

[0004] Such conventional superconductor-based qubits, including Josephson junctions between low-temperature superconductor materials, have coherence times approaching one millisecond. However, despite their high quality, qubits based on low-temperature superconductors have intrinsic limitations. For example, due to the inherent superconducting properties of low-temperature superconductors, such as their small superconducting gap and their extremely low critical temperature (about 1K), those qubits are strongly affected by magnetic fields.

[0005] Superconducting qubits using high temperature superconductors have the potential to overcome some of those limitations. However, the actual physical implementation of qubits using high temperature superconductor Josephson junctions is technically challenging because, for those materials, unlike low temperature superconductors (such as Al or niobium Nb), photolithographic structuring or deposition techniques are not available so far. When photolithographic structuring or deposition techniques used to make conventional qubit devices are applied to high temperature superconductors, they cause significant defect densities therein and decomposition of the high temperature superconductor material occurs.

[0006] WO 2022 / 197482 A1 describes a transport subtype quantum bit in which the conductive layer of the capacitor consists of a van der Waals material. Summary of the invention

[0007] In view of the technical problem explained above, an improved qubit is needed. This problem is solved by a qubit device according to claim 1, a method for manufacturing a qubit device according to claim 9, and a contact layer for manufacturing a qubit device according to claim 15. The dependent claims relate to preferred embodiments.

[0008] In a first aspect, a quantum bit device includes a first superconductor layer, a second superconductor layer, a capacitor, a first interconnect, and a second interconnect. The first superconductor layer includes a first superconductor material. The first superconductor material is a first anisotropic layered material having a covalently bonded atomic layer and a first c-axis perpendicular to the covalently bonded atomic layer of the first superconductor material. The second superconductor layer includes a second superconductor material. The second superconductor material is a second anisotropic layered material having a covalently bonded atomic layer and a second c-axis perpendicular to the covalently bonded atomic layer of the second superconductor material. The second superconductor layer is arranged on the first superconductor layer to form a Josephson junction between the first superconductor material and the second superconductor material. The first c-axis and the second c-axis are aligned with each other at the Josephson junction. The aligned first c-axis and the second c-axis at the Josephson junction intersect both the first superconductor layer and the second superconductor layer. The capacitor includes a first electrode and a second electrode. The first interconnect electrically connects the first electrode and the first superconductor layer. The second interconnect electrically connects the second electrode and the second superconductor layer. The capacitor is arranged at a vertical position that exceeds vertical positions of both the first superconductor layer and the second superconductor layer.

[0009] This structure permits the Josephson junction to be designed and provided independently of the capacitor, and vice versa. Thus, a fully optimized qubit device is provided. Compared to low temperature superconductor materials, superconductor layers including anisotropic layered materials may be subject to variations (e.g., in terms of their size or shape) during manufacture. An advantage of the described qubit device is that manufacturing variations of (multiple) superconductor layers (and / or, respectively, Josephson junctions) do not translate into variations in the capacitor; instead, they can be compensated by a custom design of the capacitor. The capacitor can be manufactured using conventional photolithographic structuring or deposition techniques, thereby providing high structural accuracy.

[0010] The structures are a direct consequence of the implementation of the manufacturing techniques or the provision of contact layers, respectively, which will be described in detail below. The defect density of the resulting structure (i.e., the (first and second) superconductor materials) is significantly lower than that of a structure manufactured using photolithographic structuring or deposition techniques, respectively, or significantly lower than that of the (high critical temperature) superconductor material(s) therein.

[0011] The Josephson junction may be referred to as a van der Waals Josephson junction, particularly in embodiments where the first superconductor material and / or the second superconductor material is a van der Waals material.

[0012] The first anisotropic layered material and / or the second anisotropic layered material may be a cleavable material, such as a material cleavable using an adhesive tape.

[0013] The first superconductor layer may be composed of a first superconductor material.

[0014] The second superconductor layer may be composed of a second superconductor material.

[0015] The first c-axis may refer to a unique crystallographic axis of the first superconductor material.

[0016] The second c-axis may refer to a unique crystallographic axis of the second superconductor material.

[0017] The first superconductor material and / or the second superconductor material may include a layered atomic structure and / or a crystalline structure. The first (and / or second) c-axis may be perpendicular to the covalently bonded layers and / or perpendicular to the van der Waals gap of the layered atomic structure and / or the crystalline structure of the first (and / or second) superconductor material.

[0018] The first superconductor material and / or the second superconductor material may be a van der Waals material.Any of the anisotropic layered materials may be isotropic on an atomic scale and / or in terms of their electronic, optical and / or mechanical properties, for example when in single crystal form.

[0019] A capacitor may be arranged above the Josephson junction.

[0020] The vertical line may intersect both the first superconductor layer and the first electrode.

[0021] The vertical line may intersect both the second superconductor layer and the second electrode.

[0022] The qubit device may further include an electrically insulating element.

[0023] The electrical insulation element may be arranged at a vertical position between the vertical position of the capacitor and the vertical position of the first superconductor layer and / or the second superconductor layer.

[0024] The respective electrically insulating element ensures that the second superconductor layer and the first electrode are electrically insulated from each other and / or that the first superconductor layer and the second electrode are electrically insulated from each other. Furthermore, the electrically insulating element provides a matrix for the first interconnect and / or the second interconnect.

[0025] An electrically insulating element may be arranged between the first superconductor layer and the second electrode.

[0026] An electrically insulating element may be arranged between the second superconductor layer and the first electrode.

[0027] An electrically insulating element may be arranged between the first superconductor layer and the first electrode.

[0028] An electrically insulating element may be arranged between the second superconductor layer and the second electrode.

[0029] At least one section of the first interconnect may be arranged in the electrically insulating element.

[0030] The first interconnect may be arranged in the electrically insulating element.

[0031] At least one section of the second interconnect may be arranged in the electrically insulating element.

[0032] The second interconnect may be arranged in the electrically insulating element.

[0033] The first interconnect and / or the second interconnect may extend through the electrically insulating element and optionally from a bottom surface thereof to a top surface thereof.

[0034] The electrically insulating element may include or consist of silicon carbide, silicon nitride or amorphous silicon.

[0035] The corresponding materials provide sufficient electrical insulation. In addition, these materials are mechanically flexible when provided as sufficiently thin layers (e.g., not more than 600 nm), which is beneficial for the manufacture of corresponding quantum bit devices.

[0036] The lateral extension of the electrically insulating element may completely cover the lateral extension of the first superconductor layer and the lateral extension of the second superconductor layer.

[0037] In corresponding embodiments, the electrically insulating element also provides mechanical protection for the first superconductor layer and / or the second superconductor layer, and in some embodiments provides sealing, for example against moisture or reactive gases such as oxygen.

[0038] The electrically insulating element may have a thickness in the range from 300 nm to 600 nm along the vertical direction.

[0039] The qubit device may further comprise a packaging of the Josephson junction, such as a water-tight, moisture-proof, oxygen-tight and / or hermetic packaging, wherein the packaging comprises an electrically insulating element and optionally a substrate on which the Josephson junction is arranged.

[0040] The first superconductor material may include a first orientation parallel to its covalently bound atomic layers. The second superconductor material may include a second orientation parallel to its covalently bound atomic layers. The first superconductor material and the second superconductor material at the Josephson junction may be arranged at an angle between the first orientation and the second orientation, the angle corresponding to the predefined angle.

[0041] The angle between the orientations of the superconductor material can be used to tailor the device parameters of a qubit device according to the requirements of a particular device application. For example, a qubit device with a particularly long coherence time can be provided by adjusting the corresponding angles.

[0042] The first superconductor material and the second superconductor material at the Josephson junction may be arranged at an angle between the first orientation and the second orientation, the angle being in a range from 38° to 44.9°.

[0043] The corresponding angle maximizes the coherence time of the qubit device, especially for superconductor materials with an angle of about 90° between their horizontal basis lattice vectors, such as BSCCO (i.e., Bi2Sr2Ca n-1 Cu n O 2n+4+x ).

[0044] The first c-axis may correspond to a fundamental lattice vector of the first superconductor material.

[0045] The second c-axis may correspond to a fundamental lattice vector of the second superconductor material.

[0046] The first orientation may correspond to a first fundamental lattice vector perpendicular to the first c-axis, and in particular to a direction of the first fundamental lattice vector perpendicular to the first c-axis.

[0047] The second orientation may correspond to a second basis lattice vector perpendicular to the second c-axis, and in particular to a direction of the second basis lattice vector perpendicular to the first c-axis.

[0048] The covalently bonded atomic layers of the first superconductor material and / or the second superconductor material may be separated by a van der Waals gap.

[0049] The first orientation may correspond to a lattice vector of the first superconductor material parallel to the covalently bonded atomic layers of the first superconductor material, and the second orientation may correspond to a corresponding lattice vector of the second superconductor material parallel to the covalently bonded atomic layers of the second superconductor material.

[0050] The first orientation may refer to a node direction in a d-wave electronic spectrum of the corresponding superconductor material.

[0051] The first superconductor material and the second superconductor material may have the same crystal structure and / or the same crystal unit cell and / or be the same superconductor material.

[0052] The first superconductor material and / or the second superconductor material may be a high temperature superconductor material, in particular having a critical temperature of at least 4K or at least 8K or at least 15K or at least 30K or at least 50K or at least 70K or at least 78K.

[0053] The first superconductor material and / or the second superconductor material may be a type II superconductor material.

[0054] The first superconductor material and / or the second superconductor material may be a d-wave superconductor material.

[0055] The first superconductor material and / or the second superconductor material may comprise oxygen or chalcogenide, in particular to at least 20 atomic percent or at least 30 atomic percent.

[0056] The first superconductor material and / or the second superconductor material may include a chemical composition Bi2Sr2Ca n-1 Cu n O 2n+4+x , in particular, wherein n=1 or 2 or 3 or 4.

[0057] The distance between the first superconductor material and the second superconductor material at the Josephson junction may be at least 0.2 nm, particularly at least 0.25 nm, particularly at least 0.3 nm, particularly at least 0.35 nm, particularly at least 0.4 nm, particularly at least 0.45 nm, or at least 0.5 nm.

[0058] The distance between the first superconductor material and the second superconductor material at the Josephson junction may be at most 10 nm, in particular at most 8 nm, in particular at most 6 nm, in particular at most 4 nm, in particular at most 3 nm, in particular at most 2 nm, in particular at most 1 nm.

[0059] A spacer material may be arranged between the first superconductor material and the second superconductor material at the Josephson junction, wherein, optionally, the spacer material comprises or consists of an anisotropic layered material.

[0060] The spacer material can help ensure the correct distance between the superconductor materials at the Josephson junction.

[0061] The area of ​​the overlap region between the first superconductor material and the second superconductor material at the Josephson junction may be at least 0.1 μm 2 , in particular at least 0.3 μm 2 , in particular at least 0.5 μm 2 , or at least 1μm 2 .

[0062] The area of ​​the overlap region between the first superconductor material and the second superconductor material at the Josephson junction may be at most 50 μm 2 or up to 1μm 2 .

[0063] The qubit device may further include a microwave resonator.

[0064] Corresponding microwave resonators facilitate the readout of qubit devices, for example in the form of decentralized readout.

[0065] The microwave resonator may be capacitively coupled to the capacitor, optionally in a horizontal direction.

[0066] The microwave resonator may be arranged at a vertical position that exceeds vertical positions of both the first superconductor layer and the second superconductor layer.

[0067] The corresponding microwave resonator can advantageously be produced together with the capacitor in the same process step, so that the corresponding qubit device can be produced in few steps and thus efficiently and economically.

[0068] The microwave resonator may comprise or consist of a superconductor material, such as a low temperature superconductor material or an elemental or nitride superconductor material, such as Al, Nb, NbN or TiN.

[0069] A corresponding choice of materials facilitates the use of conventional photolithographic structuring or deposition techniques to produce the corresponding component(s) and thus improves the structural accuracy during production.

[0070] The resonant frequency of the microwave resonator may be in the range from 1 GHz to 10 GHz, or in the range from 1 GHz to 10 GHz.

[0071] The capacitance of the capacitor may be in the range from 4 femtofarads to 500 femtofarads, or in the range from 4 femtofarads to 400 femtofarads, or in the range from 70 femtofarads to 400 femtofarads.

[0072] The first electrode and / or the second electrode and / or the first interconnect and / or the second interconnect may include or consist of a superconductor material, such as a low temperature superconductor material or an elemental or nitride superconductor material, such as Al, Nb, NbN or TiN.

[0073] In a second aspect, a method for making a qubit device includes: providing a Josephson junction between a first superconductor material and a second superconductor material; and providing a contact layer spaced apart from the Josephson junction. The contact layer includes an electrically insulating element, a first interconnect, and a second interconnect. The first interconnect extends through the electrically insulating element. The second interconnect extends through the electrically insulating element. The method further includes: arranging the contact layer over the Josephson junction to form an electrical contact between the first interconnect and the first superconductor material and to form an electrical contact between the second interconnect and the second superconductor material.

[0074] This method of manufacturing (by providing the contact layer spaced apart from the Josephson junction and arranging the contact layer over the Josephson junction at a later step) ensures that damage to the Josephson junction or to the first and second superconductor materials, respectively, is minimized during manufacturing.

[0075] The contact layer provided to be spaced apart from the Josephson junction may include a capacitor arranged on the electrically insulating element. The capacitor may include a first electrode and a second electrode. In corresponding embodiments, the first interconnect may be electrically connected to the first electrode, and / or the second interconnect may be electrically connected to the second electrode.

[0076] The contact layer provided to be spaced apart from the Josephson junction may comprise a microwave resonator arranged on top of the electrically insulating element, wherein, optionally, the microwave resonator is capacitively coupled to a capacitor.

[0077] The method may further include cooling the Josephson junction to a temperature below a first temperature when the contact layer is arranged on the Josephson junction, wherein the first temperature is 0°C, or 250K, or 230K, or 210K, or 190K, or 170K, or 150K, or 130K.

[0078] Cooling further reduces any damage to the Josephson junction or to the first superconductor material and the second superconductor material, respectively, during manufacturing.

[0079] Arranging the contact layer over the Josephson junction may include: attaching a transfer device to the contact layer; and cooling the transfer device to a temperature below a second temperature used to attach the transfer device to the contact layer. The transfer device may be adapted to provide strong adhesion when the temperature of the transfer device is below the second temperature and to provide weak adhesion when the temperature of the transfer device is above the second temperature or above a third temperature that exceeds the second temperature.

[0080] The corresponding transfer device permits reliable pick-up and placement of the contact layer at reduced (ie below the first temperature) manufacturing temperatures.

[0081] The transfer means may comprise or consist of an elastomer.

[0082] The second temperature and / or the third temperature may exceed the glass transition temperature of the elastomer.

[0083] The third temperature may correspond to a glass transition temperature of the elastomer.

[0084] The elastomer may be PTFE or PDMS.

[0085] The second temperature may be no greater than the first temperature.

[0086] Arranging the contact layer over the Josephson junction may include releasing the transfer device from the contact layer, wherein releasing the transfer device from the contact layer includes heating the transfer device to a temperature between the second temperature and the first temperature. The corresponding temperature may exceed a third temperature, the third temperature exceeding both the first temperature and the second temperature.

[0087] The first superconductor material may be a first anisotropic layered material having covalently bonded atomic layers and a first c-axis perpendicular to the covalently bonded atomic layers of the first superconductor material. The second superconductor material may be a second anisotropic layered material having covalently bonded atomic layers and a second c-axis perpendicular to the covalently bonded atomic layers of the second superconductor material.

[0088] In corresponding embodiments, the Josephson junction may be provided such that the first c-axis and the second c-axis are aligned with each other at the Josephson junction, and / or may be provided such that both the first c-axis and the second c-axis intersect both the first superconductor material and the second superconductor material at the Josephson junction.

[0089] Providing a Josephson junction between the first superconductor material and the second superconductor material may include: disposing a first superconductor layer of a first anisotropic layered material over a substrate; and disposing a second superconductor layer of a second anisotropic layered material over the first superconductor layer to create a Josephson junction.

[0090] Providing a Josephson junction between the first superconductor material and the second superconductor material may include, before arranging the first superconductor layer and the second superconductor layer, cleaving the first anisotropic layered material to generate the first superconductor layer and / or cleaving the second anisotropic layered material to generate the second superconductor layer, and optionally, maintaining the first anisotropic layered material at a temperature lower than the first temperature when cleaving it, and / or maintaining the second anisotropic layered material at a temperature lower than the first temperature when cleaving it.

[0091] Cleaving the first anisotropic layered material and / or cleaving the second anisotropic layered material and / or arranging the first superconductor layer over the substrate and / or arranging the second superconductor layer over the first superconductor layer may be performed using a transfer device comprising or consisting of an elastomer.

[0092] The electrically insulating element may be provided with a thickness small enough to be mechanically flexible, such as having a thickness of 300 nm to 600 nm.

[0093] According to a third aspect, a contact layer for manufacturing a quantum bit device includes an electrically insulating element, a capacitor, a first interconnect and a second interconnect. The capacitor includes a first electrode and a second electrode arranged on the electrically insulating element. The first interconnect is electrically connected to the first electrode and extends from the bottom surface of the electrically insulating element through the electrically insulating element to its top surface. The second interconnect is electrically connected to the second electrode and extends from the bottom surface of the electrically insulating element through the electrically insulating element to its top surface. Each of the first electrode, the second electrode, the first interconnect and the second interconnect includes a corresponding superconductor material.

[0094] The electrically insulating element may comprise a thickness small enough to be mechanically flexible, such as a thickness of 300 nm to 600 nm.

[0095] The contact layer may comprise a microwave resonator arranged on the electrically insulating element, wherein, optionally, the microwave resonator is capacitively coupled to the capacitor.

[0096] According to a further aspect, a method for changing the state of a quantum bit device includes: coupling a first microwave having a first microwave frequency to the quantum bit device, wherein the first microwave frequency is associated with an energy difference between a third excited state and a ground state of the quantum bit device; coupling a second microwave having a second microwave frequency to the quantum bit device, wherein the second microwave frequency is associated with an energy difference between a third excited state and a second excited state of the quantum bit device; and coupling a third microwave having a third microwave frequency to the quantum bit device, wherein the third microwave frequency is associated with an energy difference between the second excited state and the first excited state of the quantum bit device.

[0097] This method allows to reliably change the state of a qubit device even if the transition between the ground state and the first excited state of the qubit device has a very low transition probability, or even if the ground state and the first excited state are (almost) degenerate.

[0098] According to an embodiment, the first microwave frequency does not match the energy difference between the third excited state and the ground state of the qubit device, for example, the difference is at least 0.01% and at most 5%. Alternatively, or in addition, the second microwave frequency may not match the energy difference between the third excited state and the second excited state of the qubit device, for example, the difference is at least 0.01% and at most 5%. Alternatively, or in addition, the third microwave frequency may not match the energy difference between the second excited state and the first excited state of the qubit device, for example, the difference is at least 0.01% and at most 5%. In a corresponding embodiment, the first microwave, the second microwave, and the third microwave may be coupled to the qubit device at the same time.

[0099] According to another embodiment, the method includes: first coupling the first microwave and the third microwave to the qubit device (wherein, optionally, the first microwave and the third microwave can be coupled to the qubit device as pi-pulses), then coupling the second microwave to the qubit device (wherein, optionally, the second microwave can be coupled to the qubit device according to a predefined phase difference between the ground state and the first excited state), and then coupling the first microwave and the third microwave to the qubit device (wherein, optionally, the first microwave and the third microwave can be coupled to the qubit device as pi-pulses). In a corresponding embodiment, the first microwave frequency can match the energy difference between the third excited state and the ground state of the qubit device, for example, within 0.01%. Alternatively, or in addition, the second microwave frequency can match the energy difference between the third excited state and the second excited state of the qubit device, for example, within 0.01%. Alternatively, or in addition, the third microwave frequency can match the energy difference between the second excited state and the first excited state of the qubit device, for example, within 0.01%.

[0100] The qubit device may be a qubit device according to any of the embodiments described above.

[0101] The first microwave frequency may be in the range from 7 GHz to 15 GHz.

[0102] The second microwave frequency may be in the range from 1 GHz to 2 GHz.

[0103] The third microwave frequency may be in the range from 6 GHz to 13 GHz.

[0104] The method may further include analyzing the changed state of the quantum bit using decentralized readout.

[0105] Coupling the first microwave, the second microwave, and / or the third microwave to the qubit device and / or decentralized readout may use the microwave resonator described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0106] The techniques of the present disclosure and advantages associated therewith will be best apparent from the description of exemplary embodiments according to the accompanying drawings, in which:

[0107] Figure 1 A cross-sectional view of a quantum bit device according to an embodiment is provided;

[0108] Figure 2a A cross-sectional view of a quantum bit device according to another embodiment is provided;

[0109] Figure 2b A cross-sectional view of a quantum bit device according to another embodiment is provided;

[0110] Figure 2c A cross-sectional view of a quantum bit device according to another embodiment is provided;

[0111] Figure 3 A top view of a quantum bit device according to another embodiment is provided;

[0112] Figure 4a A perspective view of a quantum bit device according to another embodiment is provided; Figure 4b Given Figure 4a A cross-sectional view of a quantum bit device; Figure 5a A second superconductor layer is illustrated according to a perspective view, the second superconductor layer being arranged on the first superconductor layer to form a Josephson junction;

[0113] Figure 5b The top view shows the Figure 5a a second superconductor layer disposed on the first superconductor layer;

[0114] Figure 6 A method for forming a qubit device is illustrated;

[0115] Figure 7 The process steps for providing a contact layer are illustrated;

[0116] Figure 8 A cross-sectional view of a contact layer according to an embodiment is given;

[0117] Fig. 9 illustrates the process steps for disposing a second superconductor layer over a first superconductor layer to form a Josephson junction;

[0118] Fig.10A method for changing the state of a qubit device according to an embodiment is illustrated; and

[0119] Fig.11 A method for changing the state of a qubit device according to another embodiment is illustrated. DETAILED DESCRIPTION

[0120] Figure 1 A cross-sectional view of a qubit device 100 according to a first embodiment is given.

[0121] The qubit device 100 includes a first superconductor layer 102 a . The qubit device further includes a second superconductor layer 102 b disposed on the first superconductor layer 102 a to form a Josephson junction 120 .

[0122] The first superconductor layer 102a and the second superconductor layer 102b include respective superconductor materials. Those superconductor materials are anisotropic layered materials, which are typical cases of high critical temperature superconductor materials or d-wave superconductor materials, respectively.

[0123] The thickness of the superconductor layers 102a, 102b is typically in the range of 30 nm to 90 nm.

[0124] Close-up 124' illustrates an anisotropic layered material. It gives a close-up of the structure of the second superconductor layer 102b in region 124. The distance between the covalently bonded atomic layers 126 in close-up 124' corresponds to 1 to 5 nm, depending on the specific superconductor material. The covalently bonded atomic layers 126 of the second superconductor material are separated from each other by van der Waals gaps 128. Axis c is perpendicular to the covalently bonded atomic layers 126 or the van der Waals gaps 128, respectively.

[0125] In close-up 124 ′, the structure of the second superconductor material of the second superconductor layer 102 b is illustrated. However, the first superconductor material of the first superconductor layer 102 a has a similar structure with a layer of covalently bonded atoms 128 and van der Waals gaps 126 .

[0126] Examples of anisotropic layered superconductor materials are cuprates such as BSCCO (i.e., Bi2Sr2Ca n-1 Cu n O 2n+4+x , where n = 2, 3, 4)) or iron-based high temperature superconductors (e.g., FeSe, K-doped FeSe, FeSe x Te 1-x ).

[0127] Further, capacitor 132 is arranged above first superconductor layer 102a and second superconductor layer 102b, that is, arranged at a position exceeding respective positions of first superconductor layer 102a and second superconductor layer 102b along vertical direction z.

[0128] The capacitor 132 includes two electrodes 130a, 130b arranged adjacent to each other.

[0129] In the depicted embodiment, the electrodes 130a, 130b are coupled horizontally (i.e., with a minimum spacing between the electrodes 130a, 130b), and the surface normal of at least one or each of the electrodes 130a, 130b is horizontal and points toward the other of the electrodes 130a, 130b. Figure 2a ), electrodes 130a, 130b are vertically coupled.

[0130] The first interconnect 108a electrically connects the first superconductor layer 102a and the first electrode 130a.

[0131] The second interconnect 108b electrically connects the second superconductor layer 102b and the second electrode 130b.

[0132] Preferably, the electrodes 130a, 130b and the interconnects 108a, 108b are composed of corresponding superconductor materials, which are either low critical temperature superconductor materials (e.g., elemental superconductors or their nitrides, such as Al, Nb, TiN) or high critical temperature superconductor materials (e.g., anisotropic layered superconductor materials as described above). The electrodes 130a, 130b and the interconnects 108a, 108b made of low critical temperature superconductor materials facilitate high precision manufacturing.

[0133] Figure 2a A cross-sectional view of a quantum bit device 100 according to an embodiment is given, which is similar to Figure 1 quantum bit device.

[0134] However, in Figure 2a In an embodiment, the electrodes 130a, 130b are vertically coupled (i.e., wherein the electrodes 130a, 130b exhibit their minimum separation), a surface normal of at least one or each of the electrodes 130a, 130b is vertical and points toward the other of the electrodes 130a, 130b.

[0135] Figure 2b A cross-sectional view of a quantum bit device 100 according to an embodiment is given, which is similar to Figure 1 quantum bit device.

[0136] However, Figure 2bThe interconnecting members 108a, 108b extend in the vertical and horizontal directions, and Figure 1 The interconnecting members 108a, 108b in the embodiment extend only in the vertical direction.

[0137] therefore, Figure 1 The interconnects 108a, 108b are shorter, which is beneficial in some applications. Figure 2a The electrodes 130a, 130b may be placed in the device layout independently of the superconductor layers 102a, 102b, thereby improving design flexibility, which may be beneficial in some applications.

[0138] Figure 2c A cross-sectional view of a quantum bit device 100 according to an embodiment is given, which is similar to Figure 1 quantum bit device.

[0139] exist Figure 2c In the embodiment of FIG. 5 , the electrically insulating element 114 is arranged between the superconductor layers 102 a , 102 b and the electrodes 130 a , 130 b .

[0140] In particular, the electrically insulating element 114 ensures that the electrode 130a is electrically insulated from the superconductor layer 102b and that the electrode 130b is electrically insulated from the superconductor layer 102a.

[0141] The electrical insulating element 114 is composed of silicon or nitride, carbide or oxide material. More specifically, the electrical insulating element can be made of silicon carbide, silicon nitride or amorphous silicon.

[0142] In some embodiments, the electrical insulating element 114 is used to terminate or seal the superconductor layers 102a, 102b, particularly in conjunction with the following ( Figure 6 ) will be described in conjunction with the substrate 140. In such embodiments, the electrically insulating element 114 and the substrate 140 together enclose the superconductor layers 102a, 102b (arranged between the electrically insulating element 114 and the substrate 140) in a watertight or moisture-proof or airtight manner.

[0143] In addition, Figure 2c In an embodiment of the present invention, the spacer material 116 is disposed between the first superconductor layer 102a and the second superconductor layer 102b. The spacer material 116 ensures that the distance between the superconductor layers 102a, 102b is appropriate to form the Josephson junction 120. In some embodiments, the spacer material 116 is composed of an anisotropic layered material such as hexagonal boron nitride. According to any of the other embodiments, the spacer material may also be provided with the qubit device 100.

[0144] Figure 3 A top view of a qubit device 100 is presented according to some embodiments.

[0145] In a vertical (xz) cross section along line 134, Figure 3 The quantum bit device 100 is similar to Figure 1 or Figure 2c In other words, according to some embodiments, Figure 3 Depicted Figure 1 or Figure 2c A top view on the quantum bit device 100.

[0146] Figure 3 A particular shape of capacitor 132 in the horizontal x, y plane is depicted. Alternative shapes are possible. However, a capacitance of capacitor 132 in the range of from 70 to 400 femtofarads has proven beneficial.

[0147] The resulting capacitance energy EC = e 2 / 2C (where e is the electron charge) is greater than the typical Josephson energy E of the Josephson junction 120 J 100 times smaller or more.

[0148] Figure 3 Region 136 is indicated in FIG.

[0149] Figure 4a , Figure 4b A qubit device 100 is depicted according to another embodiment. Figure 4a A perspective view is given. In which area 136 corresponds to Figure 3 of area 136. Figure 4b A cross-sectional view is given, more specifically, according to Figure 3 The line 134 indicated in Figure 3 , Figure 4a A vertical (xz) cross-section of region 136 of FIG.

[0150] Figure 4a , Figure 4b The qubit device 100 in includes a microwave resonator 138 capacitively coupled to a capacitor 132 (ie, one of the electrodes 130a, 130b).

[0151] The resonant frequency of the microwave resonator 138 is in the range of 1 to 15 GHz.

[0152] Microwave resonator 138 is suitable for decentralized readout of qubit device 100 .

[0153] The capacitor 132 and the microwave resonator 138 have a thickness in the range from 40 nm to 80 nm.

[0154] The overall dimensions (length and / or width along the horizontal direction) of the qubit device 100 or the electrically insulating element 114 , respectively, are in the range from 0.5 to 1 mm.

[0155] Figure 5a , Figure 5b The second superconductor layer 102b, which is arranged on the first superconductor layer 102a to form a Josephson junction 120, is illustrated in detail. Figure 5a A perspective view of the superconductor layers 102a, 102b and the Josephson junction 120 is given, and Figure 5b A top view is given. Figure 5a , Figure 5b The detailed description of the superconductor layers 102a, 102b and the Josephson junction 120 in FIG. 1 is also applicable to the superconductor layers 102a, 102b and the Josephson junction 120 of the qubit device 100 according to any of the various embodiments described above.

[0156] The first superconductor layer 102a and the second superconductor layer 102b overlap in a region 110. In other words, the region 110 forms an overlapping region 110 (i.e., an overlapping region of the superconductor layers 102a, 102b). More specifically, in the overlapping region 110, a first section 112a of the first surface 106a of the first superconductor layer 102a faces a second section 112b of the second surface 106b of the second superconductor layer 102b, and vice versa.

[0157] Specifically, in the overlapping region 110 , the superconductor layers 102 a and 102 b are spaced apart by a distance d.

[0158] The first superconductor material (i.e., the superconductor material of the first superconductor layer 102a) has a first orientation 118a. Figure 5a , Figure 5b , the first orientation 118a is represented by the arrow 118a in the horizontal plane. In other words, the first orientation 118a is parallel to the first section 112a of the first surface 106a.

[0159] The second superconductor material (ie, the superconductor material of the second superconductor layer 102b) has a corresponding second orientation 118b.

[0160] The orientation 118a, 118b may be defined by any one or any combination of the following criteria:

[0161] According to the first definition, orientations 118a, 118b correspond to the primary lattice vectors of the first / second superconductor material, respectively (such as, the corresponding in-plane primary lattice vectors), or to the projections of the corresponding (first / second) superconductor material's primary lattice vectors onto a horizontal plane or onto the first surface 106a or onto the second surface 106b.

[0162] Alternatively, the orientations 118a and 118b are defined by crystal planes of the first / second superconductor material.

[0163] The orientation 118a, 118b is alternatively defined by the reciprocal lattice vectors of the first / second superconductor material, ie by the in-plane reciprocal lattice vectors or by the projection of the reciprocal lattice vectors onto a horizontal plane or onto the first surface 106a or onto the second surface 106b, respectively.

[0164] Alternatively, the orientations 118a and 118b are defined by the electron orbitals 114a and 114b or by the crystal momentum of the Bloch states of the first / second superconductor material. According to some embodiments, the first / second superconductor material is a d-wave superconductor or a superconductor with a d-wave superconducting gap, respectively. In this case, the orientations 118a, 118b may be associated with a d-wave electronic spectrum, in particular with a d-wave node electronic spectrum 114a.

[0165] The first orientation 118a and the second orientation 118b are arranged at an angle θ according to a predefined angle.

[0166] In particular, when the angle θ is in the range of 38° to 44.9°, the single-Cooper pair tunneling E J or Josephson energy E J The inventors have used the method for BSCCO and more specifically for Bi2Sr2CaCu2O 8+x The simulation verifies the Josephson energy E J Similarly, other d-wave superconductors (either high critical temperature superconductors, or superconductors including anisotropic layered superconductor materials, respectively) are expected to have angles of about 90° between their fundamental lattice vectors perpendicular to the axis c.

[0167] Josephson Energy and Critical Current I of Josephson Junction c Directly related, such as E J =I c Φ0 / 2π, where Φ0=h / 2e flux quantum.

[0168] In this case, double Cooper pair tunneling is still possible, and the double Cooper pair tunneling energy E k Similar to the Josephson energy E J The double Cooper pair tunneling term can be written as E κcos(2φ), thereby forming a double barrier. In a preferred embodiment, the corresponding two lowest energy eigenstates are used to provide a two-level system for the qubit device. The energy difference between the corresponding eigenstates of the two levels is small, i.e. within an energy / frequency difference of up to 2 GHz and in some embodiments up to 1 GHz. Therefore, the corresponding eigenstates are called quasi-degenerate.

[0169] The degeneracy is closely related to, and therefore indicative of, a situation in which dielectric losses and crosstalk between qubit devices (i.e., between the quantum mechanical states of their corresponding two-level systems) are greatly reduced. Those dielectric losses and crosstalk are the main limitations of conventional transporter qubits. Thus, the relaxation time of the described qubit device is significantly improved compared to the relaxation time of conventional qubit devices (e.g., transporter type). According to simulations performed by the inventors, this improvement amounts to a factor of 10.000, resulting in coherence times of up to 1 s.

[0170] Figure 6 A method 400 for fabricating a qubit device 100 is depicted.

[0171] At step 402, a Josephson junction 120 between a first superconductor material and a second superconductor material is provided.

[0172] At step 404 , a contact layer 104 spaced apart from the Josephson junction 120 is provided.

[0173] The contact layer 104 includes an electrically insulating element 114, a first interconnect 108a, and a second interconnect 108b. The first interconnect 108a extends through the electrically insulating element 114. The second interconnect 108b extends through the electrically insulating element 114.

[0174] In some embodiments (not shown), the contact layer 104 is provided with additional, optional electrical elements disposed thereon, such as a capacitor 132 including a first electrode 130a and a second electrode 130b disposed on the electrically insulating element 114, or a microwave resonator 138 disposed on the electrically insulating element 114. In some embodiments with the capacitor 132, the first interconnect 108a is connected to the first electrode 130a, and the second interconnect 108b is electrically connected to the second electrode 130b.

[0175] At step 406, a contact layer 104 is disposed over the Josephson junction 120 to form an electrical contact between the first interconnect 108a and the first superconductor material and to form an electrical contact between the second interconnect 108b and the second superconductor material.

[0176] In some embodiments, at step 402 , a substrate 140 is provided.

[0177] In some embodiments, at step 402, the first superconductor material (and / or the second superconductor material) is arranged on the substrate in the form of a first (and / or second) superconductor layer 102a (102b). To this end, the pre-prepared first (and / or second) superconductor layer 102a (102b) is transferred to the substrate 140, for example, as in Fig. 9 Alternatively, the first (or second) superconductor material may be deposited onto the substrate 140 (eg, reactively) from a gas phase or using a vacuum deposition technique such as chemical vapor deposition or molecular beam epitaxy.

[0178] In some embodiments, at step 406, the contact layer 104 is cooled to a temperature of <-85°C (in other words, a second temperature below -85°C) with liquid nitrogen and arranged on the Josephson junction 120 while at the low temperature. To this end, the contact layer 104 is arranged on a PDMS stamp 412 serving as a transfer device 412. The contact layer 104 and the transfer device 412 are cooled 406 to below the second temperature. Below the second temperature, the PDMS stamp 412 provides strong adhesion to the contact layer 104.

[0179] Then, the PDMS stamp 412 and the contact layer 104 disposed thereon are positioned over and in physical contact with the substrate 140 and the Josephson junction 120 on the substrate 140. Thus, the contact layer 104 is disposed 406 over the Josephson junction 120.

[0180] In an optional additional step, the PDMS stamp 412 is removed from the contact layer 104. To this end, the PDMS stamp 412 is heated to a temperature higher than the second temperature, and preferably to a temperature > -30°C. In other words, the PDMS stamp 412 is heated to a third temperature higher than the second temperature, and preferably higher than -30°C. This reduces the adhesion of the PDMS stamp 412. Therefore, the PDMS stamp can be removed, leaving the contact layer 104 arranged above the Josephson junction 120.

[0181] To avoid thermal damage to the first layer 102a, the temperature of the first layer is kept below 0°C (first temperature) when the contact layer 104 is arranged on the first layer 102a. This is achieved by keeping the temperature of the PDMS stamp 412 below the first temperature when the PDMS stamp 412 is in contact with the substrate 140 and / or the Josephson junction 120.

[0182] The reduced adhesion of the PDMS stamp 412 at high temperatures (compared to the second temperature of -85°C) is related to the amorphous molecular structure of PDMS, which has a glass transition temperature of about -100°C. Therefore, the third temperature is above the glass transition temperature of PDMS. The second temperature is at least equivalent to the glass transition temperature of PDMS. For temperatures above the glass transition temperature, the adhesion of elastic polymers decreases with increasing temperature. In other words, alternative materials can be used for transfer device 412 instead of PDMS, especially elastic polymers, as long as their glass transition temperature is lower than the second temperature (and the third temperature).

[0183] Figure 7 Details are given of the process steps of providing 404 the contact layer 104 spaced apart from the Josephson junction 120 according to an embodiment.

[0184] According to the depicted embodiment, the electrically insulating element 114 is provided by depositing a layer 114 of insulating material onto a second substrate 500 remote from the substrate 140 .

[0185] An opening 508 is etched through electrically insulating element 114 .

[0186] A metallization layer 510 is deposited over and in the opening 508. Thus, interconnects 108a, 108b are formed that pass through the opening 508 down to the bottom surface of the electrically insulating element 114.

[0187] According to some embodiments (not shown), the metallization layer 510 is also used to form additional electrical components above the electrically insulating element 114 , such as a capacitor 132 or the first and second electrodes 130 a and 130 b , respectively, and / or a microwave resonator 138 .

[0188] Then, grooves 514 are formed in the electrically insulating element 114. The grooves 514 reach down to the bottom surface of the electrically insulating element 114 or cut through the electrically insulating element 114, respectively. The grooves 514 are interrupted laterally by sections of the insulating material of the electrically insulating element 114, which serve as anchoring points (tie points).

[0189] Then, a deeper trench 518 (than trench 514) is formed, reaching into the second substrate 500 and / or into an optional sacrificial layer (not shown) between the second substrate 500 and the electrically insulating element 114. In other words, the (top) sacrificial portion of the second substrate 500 serves as the sacrificial layer if a different sacrificial layer is absent.

[0190] Then, an isotropic etch is performed in the lateral regions within the deeper trench 518 to remove the sacrificial layer and / or sacrificial portion of the second substrate 500 below the electrically insulating element 114. Thus, the resulting contact layer 104 is independent with respect to the second substrate 500. The resulting contact layer 104 is mechanically flexible, provided that the electrically insulating element 114 is thin enough. For this purpose, a thickness of the electrically insulating element 114 in the range of 300 to 600 nm has proven to be beneficial.

[0191] Before or after isotropic etching, the PDMS stamp 412 is attached to (transferred to) the electrically insulating element 114 with openings 508 (these openings may now be completely filled with the metallization layer 510). The PDMS stamp 412 is cooled to a temperature below the second temperature; the cooling may be performed before or after the PDMS stamp 412 is transferred to the electrically insulating element 114 with openings 508.

[0192] While cooling, the cooled PDMS stamp 412 is removed from the second substrate 500. The PDMS cooled to below the second temperature has strong adhesion. Therefore, removing the PDMS stamp 412 from the second substrate 500 lifts the contact layer 104 off the second substrate 500 because the contact layer 104 strongly adheres to the PDMS stamp 412.

[0193] Therefore, the contact layer 104 is still arranged on the PDMS stamp 412 and is spaced apart from the substrate 500, as shown in FIG. Figure 7 as shown in the last panel of .

[0194] Optionally, the contact layer 104 is cleaned at its bottom surface (facing away from the PDMS stamp 412) using, for example, a wet and / or dry cleaning step (such as etching, ion milling). If applied, the cleaning step is preferably performed just before the contact layer 104 is arranged on the substrate 140.

[0195] Figure 8 Describes as Figure 6 Method 400 is used and passed Figure 7 The contact layer 104 is obtained by the method 404 .

[0196] Figure 8 The contact layer 104 is formed with an optional capacitor 132 and an optional microwave resonator 138. The top view of the contact layer 104 corresponds to Figure 3 4 (but without the Josephson junction 120 and the first and second superconductor layers 102a, 102b), and the perspective view of the contact layer 104 corresponds to the perspective view of FIG.

[0197] In an alternative embodiment (not shown, see Figure 7), the contact layer 104 is formed without the capacitor 132 and / or without the microwave resonator 138.

[0198] Fig. 9 Process steps for providing 402 a Josephson junction 120 between a first superconductor material and a second superconductor material are illustrated according to an embodiment.

[0199] This method can optionally be applied to Figure 6 In the method, the process step 402 is expanded or replaced.

[0200] At step 602, a superconductor material is provided in the form of a superconductor layer 102a over a substrate 140. The superconductor material is an anisotropic layered material.

[0201] The anisotropic layered material of superconductor layer 102a has a crystallographic orientation 620. Crystallographic orientation 620 corresponds to a direction parallel to covalently bonded atomic layers 126 or van der Waals gaps 128, respectively, such as Figure 1 For example, the crystallographic orientation 620 corresponds to a primary lattice vector parallel to the covalently bonded atomic layer 126 or parallel to the van der Waals interstices 128, respectively, or corresponds to a projection of the primary lattice vector of the anisotropic layered material onto the covalently bonded atomic layer 126 or onto the van der Waals interstices 128, respectively.

[0202] At step 604, a transfer device 412 in the form of a PDMS stamp 412 is attached to (transferred onto) the superconductor layer 102a and the substrate 140, as similarly described for Figure 7 The PDMS stamp 412 is attached to the electrically insulating element 114 as described.

[0203] The PDMS stamp 412 is cooled to a temperature lower than the second temperature described above; the cooling may be performed before or after the PDMS stamp 412 is transferred onto the superconductor layer 102 a and the substrate 140 .

[0204] At step 606, while cooling, the cooled PDMS stamp 412 is removed from the substrate 140. The PDMS cooled to below the second temperature has strong adhesion. Therefore, when the PDMS stamp 412 is removed from the substrate 140, a portion of the superconductor layer 102a adheres to the PDMS stamp 412. Another portion of the superconductor layer 102a remains on the substrate 140. In other words, the superconductor layer 102a is cleaved.

[0205] Cleavage of the anisotropic layered material and thus the superconductor layer 102a generally proceeds along the van der Waals gaps 128 between the covalently bonded atomic layers 126 of the anisotropic layered material. Thus, the surfaces of the superconductor layers 102a, 102b freshly prepared by cleavage are parallel to the covalently bonded atomic layers 126, and / or parallel to the crystallographic planes of the layered material, respectively.

[0206] At step 608, the portion of the superconductor layer 102a remaining on the substrate 140 forms the first superconductor layer 102a. Hereinafter, only the remaining superconductor layer 102a will be referred to as the first superconductor layer 102a.

[0207] The portion of the superconductor layer 102a that adheres to the PDMS stamp 412 forms a second superconductor layer 102b. According to the depicted embodiment, the second superconductor layer 102b is composed of the same material as the first superconductor layer 102a. However, by applying the processes described above in steps 602, 604, 606 to different superconductor materials, a second superconductor layer 102b composed of a different superconductor material can be provided. Thereafter, the portion of the different superconductor material that adheres to the corresponding PDMS stamp will then be used as the second superconductor layer 102b.

[0208] Still referring to step 608, the PDMS stamp 412 with the second superconductor layer 102b adhered thereto is then oriented and positioned relative to the substrate 104 and the first superconductor layer 102a.

[0209] According to the depicted embodiment, positioning and orienting involves rotating 610 about an axis 612 perpendicular to the second superconductor layer 102b to rotate (twist) a crystallographic orientation 622 of the second superconductor layer 102b relative to a crystallographic orientation 620 of the first superconductor layer 102a.

[0210] Referring to step 614 , the PDMS stamp 412 with the second superconductor layer 102 b adhered thereto is transferred onto the first superconductor layer 102 a and the substrate 140 according to the position and orientation described in the context of step 608 .

[0211] In particular, the PDMS stamp 412 is transferred onto the substrate 140 such that the first superconductor layer 102a and the second superconductor layer 102b overlap to form the overlap region 110 and / or the Josephson junction 120 described above.

[0212] Referring to step 616 , the PDMS stamp 412 is heated to a temperature exceeding the second temperature and preferably exceeding the third temperature described above to reduce adhesion of the PDMS stamp 412 .

[0213] The PDMS stamp 412 is then removed from the substrate 140 .

[0214] Since the adhesion of PDMS decreases at high temperatures exceeding the second temperature and preferably exceeding the third temperature, PDMS stamp 412 releases first superconductor layer 102a and second superconductor layer 102b. First superconductor layer 102a and second superconductor layer 102b are left on substrate 140.

[0215] At step 618, providing 402 of the Josephson junction 120 is completed.

[0216] Fig.10 , Fig.11 Two different embodiments of methods for changing the state of qubit device 100 are illustrated.

[0217] Before delving into the details of each embodiment, features common to both embodiments are described.

[0218] In general, a qubit implements a quantum mechanical two-level system. Ideally, a quantum mechanical two-level system would provide exactly two distinguishable quantum states. In practice, quantum mechanical two-level systems typically have a much higher number of distinguishable quantum states.

[0219] The qubit device 100 implements a corresponding quantum mechanical two-level system.

[0220] exist Fig.10 , Fig.11 , four quantum states of a quantum mechanical two-level system or a quantum bit device 100 are depicted: a ground state |0>, a first excited state |1>, a second excited state |2>, and a third excited state |3>.

[0221] The target state of the qubit device 100 refers to a superposition of the ground state |0> and the first excited state |1>.

[0222] In order to change the state of the qubit device, microwaves 702 , 704 , 706 having three different frequencies are coupled to the qubit device 100 .

[0223] The first microwave frequency of the first microwave 702 is associated with the energy difference between the third excited state |3> and the ground state |0>. The first microwave frequency is in the range of 7 GHz to 15 GHz.

[0224] The second microwave frequency of the second microwave 704 is associated with the energy difference between the third excited state |3> and the second excited state |2>. The second microwave frequency is in the range of 1 GHz to 2 GHz.

[0225] The third microwave frequency of the third microwave 706 is associated with the energy difference between the second excited state |2> and the first excited state |1>. The third microwave frequency is in the range of 6 GHz to 13 GHz.

[0226] Microwaves 702, 704, 706 drive a quantum mechanical two-level system, for example, from a ground state |0> to a superposition of the ground state |0> and a first excited state |1>. The transition is resonantly coupled to the second excited state |2> and the third excited state |3> ( Fig.10 ) or non-resonantly (11).

[0227] After changing the state of the quantum mechanical two-level system or qubit device 100, respectively, the changed state is analyzed using decentralized readout (eg, using the microwave resonator 138 described above).

[0228] Fig.10 A resonant transition is shown. In this case, at least one, at least two or all of the first, second and third microwave frequencies are matched to the corresponding energy difference, for example within 0.01% of the corresponding energy difference.

[0229] exist Fig.10 In the embodiment of, the first microwave 702 and the third microwave 706 are first coupled to the qubit device as π pulses, thereby migrating the occupancy and phase of the ground state |0> and the first excited state |1> to the second excited state |2> and the third excited state |3>. Thereafter, the second microwave 704 is coupled to the qubit device as a control pulse to define the superposition of the second excited state |2> and the third excited state |3> according to the application requirements of the qubit device. Thereafter, the first microwave 702 and the third microwave 706 are coupled to the qubit device as π pulses, thereby migrating the superposition of the second excited state |2> and the third excited state |3> to the ground state |0> and the first excited state |1>.

[0230] Fig.11 A non-resonant transition 708 is shown. In this case, at least one, at least two or all of the first, second and third microwave frequencies do not match the corresponding energy difference, for example, differ by at least 0.01% and / or at most 5% of the corresponding energy difference. In a corresponding embodiment, microwaves 702, 704, 706 are coupled synchronously to the qubit device 100. The induced transition generally corresponds to a transition in a resonant situation, but is a single non-resonant Raman type multiphoton transition. In Fig.11 In the non-resonant case, the intensity of microwaves 702, 704, 706 is usually higher than in Fig.10 The strength of the resonance condition.

[0231] Reference numerals list

[0232] 100-qubit device

[0233] 102a, 102b first superconductor layer, second superconductor layer

[0234] 126 Covalently bonded atomic layers

[0235] 128 Van der Waals gap

[0236] C c-axis

[0237] 120 Josephson knot

[0238] 132 Capacitor

[0239] 130a, 130b first electrode, second electrode

[0240] 124 Area

[0241] 124' Close-up of area 124

[0242] 108a, 108b first interconnection member, second interconnection member

[0243] 2B First fixing element

[0244] 114 Electrical insulation components

[0245] 140 Substrate

[0246] 118a, 118b are parallel to the first orientation and the second orientation of the covalently bonded atomic layer.

[0247] 114a, 114b electron d orbital

[0248] 106a, 116b: Surfaces of the first superconductor material and the second superconductor material

[0249] 110 Overlapping Area

[0250] 112a, 112b are surfaces of the first superconductor material and the second superconductor material facing each other in the Josephson junction / overlapping region.

[0251] d is the distance between the first superconductor material and the second superconductor material at the Josephson junction

[0252] 134 lines / plane

[0253] 136 Area

[0254] 138 Microwave Resonator

[0255] 412 transfer device, PDMS stamp

[0256] 602 Provide a first superconductor material on a substrate

[0257] 604 Attach the PDMS stamp to the substrate having the first superconductor material

[0258] 606: cracking the first superconductor material to generate a first superconductor layer and a second superconductor layer

[0259] 608 Align and position the second superconductor layer arranged on the PDMS stamp

[0260] 610 Rotation

[0261] 612 Axis

[0262] 614 Attach the PDMS stamp and the second superconductor layer disposed thereon to the substrate having the first superconductor layer

[0263] 616 Removal of PDMS Stamp

[0264] 618 substrate having a first superconductor layer and a second superconductor layer

[0265] 620, 622 Crystal orientation of the first superconductor material and the second superconductor material

[0266] 702, 704, 706 first microwave, second microwave, third microwave

[0267] 708 Non-resonant / Raman transition

Claims

1. A quantum bit device (100), comprising: a first superconductor layer (102a), the first superconductor layer comprising a first superconductor material, wherein the first superconductor material is a first anisotropic layered material having a covalently bonded atomic layer (126) and a first c-axis perpendicular to the covalently bonded atomic layer (126) of the first superconductor material; a second superconductor layer (102b), the second superconductor layer comprising a second superconductor material, wherein the second superconductor material is a second anisotropic layered material having a covalently bonded atomic layer (126) and a second c-axis perpendicular to the covalently bonded atomic layer (126) of the second superconductor material; wherein the second superconductor layer (102b) is arranged on the first superconductor layer (102a) to form a Josephson junction (120) between the first superconductor material and the second superconductor material; wherein the first c-axis and the second c-axis are aligned with each other at the Josephson junction (120); and wherein the first c-axis and the second c-axis aligned at the Josephson junction (120) intersect both the first superconductor layer (102a) and the second superconductor layer (102b); Wherein, the quantum bit device (100) further comprises: A capacitor (132) comprising a first electrode (130a) and a second electrode (130b); a first interconnect (108a) electrically connecting the first electrode (130a) and the first superconductor layer (102a); and a second interconnect (108b) electrically connecting the second electrode (130b) and the second superconductor layer (102b); and The capacitor (132) is arranged at a vertical position that exceeds the vertical positions of both the first superconductor layer (102a) and the second superconductor layer (102b).

2. The qubit device (100) according to claim 1, further comprising an electrically insulating element (114), in, The electrical insulation element (114) is arranged at a vertical position between the vertical position of the capacitor (132) and the vertical position of the first superconductor layer (102a) and / or the second superconductor layer (102b); and / or wherein the electrical insulation element (114) is arranged between the first superconductor layer (102a) and the first electrode (130a); and / or wherein the electrical insulation element (114) is arranged between the second superconductor layer (102b) and the second electrode (130b); and / or wherein at least one section of the first interconnect (108a) is arranged in the electrically insulating element (114); and / or The first interconnect (108a) is arranged in the electrically insulating element (114); and / or wherein at least one section of the second interconnect (108b) is arranged in the electrically insulating element (114); and / or The second interconnect (108b) is arranged in the electrically insulating element (114); and / or wherein the first interconnect (108a) and / or the second interconnect (108b) extend through the electrically insulating element (114) and optionally extend from a bottom surface of the electrically insulating element to a top surface of the electrically insulating element; and / or Wherein, the electrical insulating element (114) comprises silicon carbide, silicon nitride or amorphous silicon, or consists of silicon carbide, silicon nitride or amorphous silicon; and / or wherein the lateral extension of the electrical insulating element (114) completely covers the lateral extension of the first superconductor layer (102a) and the lateral extension of the second superconductor layer (102b); and / or The electrical insulating element (114) has a thickness in the range of 300 nm to 600 nm along the vertical direction.

3. The qubit device (100) of claim 2, further comprising packaging of the Josephson junction (120), such as a water-tight, moisture-proof, oxygen-tight and / or airtight packaging, wherein: The package comprises the electrically insulating element (114) and optionally a substrate (140) on which the Josephson junction (120) is arranged.

4. The qubit device (100) according to any one of the preceding claims, wherein: The first superconductor material comprises a first orientation (118a, 620) parallel to its covalently bonded atomic layer (126), and the second superconductor material comprises a second orientation (118b, 622) parallel to its covalently bonded atomic layer (126), and wherein the first superconductor material and the second superconductor material at the Josephson junction (120) are arranged at an angle (θ) between the first orientation (118a, 620) and the second orientation (118b, 622), the angle corresponding to a predefined angle.

5. The quantum bit device (100) according to claim 4, in, The first superconductor material and the second superconductor material at the Josephson junction (120) are arranged at an angle (θ) between the first orientation (118a, 620) and the second orientation (118b, 622), the angle being in the range of 38° to 44.9°; and / or wherein the first c-axis corresponds to a primary lattice vector of the first superconductor material, and the second c-axis corresponds to a primary lattice vector of the second superconductor material; and / or wherein the first orientation (118a, 620) corresponds to a first primary lattice vector perpendicular to the first c-axis, and in particular corresponds to a direction of the first primary lattice vector perpendicular to the first c-axis; and / or wherein the second orientation (118b, 622) corresponds to a second primary lattice vector perpendicular to the second c-axis, and in particular corresponds to a direction of the second primary lattice vector perpendicular to the first c-axis; and / or wherein the covalently bonded atomic layers (126) of the first superconductor material and / or the second superconductor material are separated by a van der Waals gap (128); and / or Wherein, the first orientation (118a, 620) corresponds to a lattice vector of the first superconductor material parallel to the covalently bonded atomic layer (126) of the first superconductor material, and the second orientation (118b, 622) corresponds to a corresponding lattice vector of the second superconductor material parallel to the covalently bonded atomic layer (126) of the second superconductor material; wherein optionally, the first superconductor material and the second superconductor material have the same crystal structure and / or the same crystal unit cell and / or are the same superconductor material.

6. The qubit device (100) according to any one of the preceding claims, in, The first superconductor material and / or the second superconductor material is a high temperature superconductor material, in particular, having a critical temperature of at least 4K or at least 8K or at least 15K or at least 30K or at least 50K or at least 70K or at least 78K; and / or Wherein, the first superconductor material and / or the second superconductor material is a type II superconductor material; and / or wherein the first superconductor material and / or the second superconductor material is a d-wave superconductor material; and / or wherein the first superconductor material and / or the second superconductor material comprises oxygen or chalcogenide, in particular up to at least 20 atomic percent or at least 30 atomic percent; and / or Wherein, the first superconductor material and / or the second superconductor material comprises a chemical composition Bi2Sr2Ca n- 1Cu n O 2n+4+x , in particular, wherein n=1 or 2 or 3 or 4.

7. The qubit device (100) of any preceding claim, further comprising a microwave resonator (138); wherein optionally, the microwave resonator (138) is capacitively coupled to the capacitor (132), optionally along a horizontal direction; and / or Optionally, the microwave resonator (138) is arranged at a vertical position, which exceeds the vertical positions of both the first superconductor layer (102a) and the second superconductor layer (102b); and / or Optionally, the microwave resonator (138) comprises or consists of a superconductor material, such as a low temperature superconductor material or an element or nitride superconductor material, such as Al, Nb, NbN or TiN; and / or Optionally, the resonance frequency of the microwave resonator (138) is in the range of 1 GHz to 15 GHz.

8. The qubit device (100) according to any one of the preceding claims, wherein: The first electrode (130a) and / or the second electrode (130b) and / or the first interconnect (108a) and / or the second interconnect (108b) include or consist of a superconductor material, such as a low-temperature superconductor material or an element or nitride superconductor material, such as Al, Nb, NbN or TiN.

9. A method (400) for manufacturing a quantum bit device (100), the method comprising: providing (402) a Josephson junction (120) between the first superconductor material and the second superconductor material; Providing (404) a contact layer (104) spaced apart from the Josephson junction (120), wherein the contact layer (104) comprises: An electrical insulating element (114); a first interconnect (108a) extending through the electrically insulating element (114); and a second interconnect (108b) extending through the electrically insulating element (114); and The contact layer (104) is disposed (406) over the Josephson junction (120) to form an electrical contact between the first interconnect (108a) and the first superconductor material and to form an electrical contact between the second interconnect (108b) and the second superconductor material.

10. The method according to claim 9, further comprising: When the contact layer (104) is arranged on the Josephson junction (120), the Josephson junction (120) is cooled to a temperature lower than a first temperature, wherein the first temperature is 0°C, or 250K, or 230K, or 210K, or 190K, or 170K, or 150K, or 130K.

11. The method according to any one of claims 9 or 10, wherein: Arranging the contact layer (104) above the Josephson junction (120) comprises: attaching a transfer device (412) to the contact layer (104); and cooling the transfer device (412) to a temperature below a second temperature for attaching the transfer device (412) to the contact layer (104); wherein the transfer device (412) is adapted to provide strong adhesion when the temperature of the transfer device (412) is lower than the second temperature and to provide weak adhesion when the temperature of the transfer device (412) is higher than the second temperature; and / or wherein the transfer device (412) comprises or consists of an elastomer, wherein optionally, the second temperature corresponds to the glass transition temperature of the elastomer and / or the elastomer is PTFE or PDMS; and / or Wherein, the second temperature is not greater than the first temperature.

12. The method according to claim 11, wherein: Arranging the contact layer (104) over the Josephson junction (120) includes releasing the transfer device (412) from the contact layer (104), wherein releasing the transfer device (412) from the contact layer (104) includes heating the transfer device (412) to a temperature between the second temperature and the first temperature.

13. The method according to any one of claims 9 to 12, in, The first superconductor material is a first anisotropic layered material having a covalently bonded atomic layer (126) and a first c-axis perpendicular to the covalently bonded atomic layer (126) of the first superconductor material; wherein the second superconductor material is a second anisotropic layered material having a covalently bonded atomic layer (126) and a second c-axis perpendicular to the covalently bonded atomic layer (126) of the second superconductor material; and The Josephson junction (120) is provided such that the first c-axis and the second c-axis are aligned with each other at the Josephson junction (120), and / or such that both the first c-axis and the second c-axis intersect both the first superconductor material and the second superconductor material at the Josephson junction (120).

14. The method according to claim 13, wherein: Providing the Josephson junction (120) between the first superconductor material and the second superconductor material comprises: disposing a first superconductor layer (102a) of the first anisotropic layered material on a substrate (140); and Arranging a second superconductor layer (102b) of the second anisotropic layered material on the first superconductor layer (102a) to generate the Josephson junction (120); Optionally, before arranging the first superconductor layer (102a) and the second superconductor layer (102b): cleaving the first anisotropic layered material to generate the first superconductor layer (102a), and optionally maintaining the first anisotropic layered material at a temperature lower than the first temperature while cleaving the first anisotropic layered material; and / or cleaving the second anisotropic layered material to generate the second superconductor layer (102b), and optionally maintaining the second anisotropic layered material at a temperature lower than the first temperature while cleaving the second anisotropic layered material; Optionally, cracking the first anisotropic layered material and / or cracking the second anisotropic layered material and / or arranging the first superconductor layer (102a) on the substrate (140) and / or arranging the second superconductor layer (102b) on the first superconductor layer (102a) is performed using a transfer device (412) including or consisting of an elastomer.

15. A contact layer (104) for manufacturing a quantum bit device (100), the contact layer (104) comprising: An electrical insulating element (114); A capacitor (132) comprising a first electrode (130a) and a second electrode (130b) disposed on the electrically insulating element (114); a first interconnect (108a) electrically connected to the first electrode (130a) and extending from a bottom surface of the electrically insulating element (114) through the electrically insulating element to a top surface thereof; as well as a second interconnect (108b) electrically connected to the second electrode (130b) and extending from a bottom surface of the electrically insulating element (114) through the electrically insulating element to a top surface thereof; Wherein, each of the first electrode (130a), the second electrode (130b), the first interconnect (108a) and the second interconnect (108b) comprises a corresponding superconductor material.

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