Signal processing device and method for responder performance detection

Abstract

The invention discloses a signal processing device and method for transponder performance detection, and mainly solves the problems that the existing signal processing device is various in variety, complex in structure and incomplete in test index. The device comprises a signal processing unit and a data processing and control unit which are bidirectionally connected through a serial port. The signal processing unit is used for transmitting an inquiry signal to the responder, receiving and processing a response signal replied by the responder, carrying out sampling, digital down-conversion, Doppler compensation, pulse compression, target detection, constant false alarm detection and Doppler agglomeration processing on the response signal, and calculating the performance measurement of the responder; the data processing and control unit is used for reading pre-stored working parameters, sending the pre-stored working parameters to the signal processing unit through a serial port, receiving and displaying a performance measurement result of the responder from the signal processing unit in the upper computer, and finally generating a PDF result document. The device is simple in structure, low in cost and comprehensive in test index, and can be used for performance detection of multiple types of responders before daily use.

Description

Technical Field

[0001] The present invention belongs to the field of radar measurement technology, and in particular relates to a signal processing device and method, which can be used to perform function and performance index tests on transponder products that generate different pulse signals. Background Art

[0002] At present, with the increase in the number of missions in the air and sea areas of my country, the guidance mission for aircraft is particularly important. There are various types of guidance transponders and different application scenarios, which are generally divided into guiding aircraft landing or landing. The guidance transponder is one of the important components of the secondary radar system. In order to distinguish different types of transponders, the interrogation-response signal between the transponder and the test equipment is designed as a different pulse signal type. Each guidance transponder has a different local address code number and the content of the transmitted information protocol is also different. Therefore, the signal processing system needs to be able to identify the pulse signal and use different processing methods to obtain effective information of the guided target.

[0003] In view of the characteristics of different transponder response signals, the signal processing system often adopts different hardware processing modules, and the used boards are of various types and complex in structure. In practical applications, it is necessary to verify their reliability through multiple tests. Therefore, it is necessary to design a highly versatile signal processing system to detect transponders with different pulse response signals, which is very necessary to verify the stability of their functions and reduce development costs.

[0004] In 2020, Wei Jiawei from the University of Electronic Science and Technology of China proposed a portable transponder test device in his paper, which consists of two parts: hardware and software. The hardware part includes RF transceiver circuit, frequency measurement circuit, power measurement circuit, FPGA and its peripheral circuits, power supply circuit, PXI bus interface circuit and clock circuit. The software part includes device initialization module, device self-test module, device function test module, device transmission characteristic test module and device reception characteristic test module. The device only tests the transceiver power, code number, altitude and other information of the transponder, and cannot test the operating frequency, receiving sensitivity and response delay of the transponder. Incomplete index testing will make it impossible to obtain the performance deviation of the transponder itself. If the deviation is large, it cannot be used as a qualified device in practice; if the deviation is small, the error needs to be corrected to meet the flight parameters provided by the transponder during normal use and ensure the safety of the flight mission.

[0005] In 2023, Yang Haoxi of the University of Electronic Science and Technology of China proposed transponder test equipment and software in his paper. Its hardware includes RF transceiver network and RF front-end network, FPGA and its peripheral circuits, PCI bus interface module, data cache unit circuit, and the software includes signal simulation control and received information decoding and display. Compared with the former, although this device optimizes the software interaction interface and adds test indicators of transponder sensitivity and response probability, the transponder operating frequency and response delay test functions are still not realized.

[0006] In summary, the existing transponder performance testing equipment has incomplete testing functions and cannot meet the testing requirements for all different modes of transponders in the aviation field. Summary of the invention

[0007] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and to propose a signal processing device and method for transponder performance detection, so as to increase the testing function of the transponder performance detection equipment and realize the testing of different performance indicators of multiple types of transponders using a universal signal processing system.

[0008] To achieve the above object, the technical solution of the present invention includes the following:

[0009] 1. A signal processing device for transponder performance testing, comprising: a signal processing unit 1 and a data processing and control unit 2, which are bidirectionally connected to complete the sending of pre-installed parameters and control instructions and the uploading of test results, characterized in that:

[0010] The signal processing unit 1 includes a motherboard 11 and a signal processing board 12. The motherboard 11 is connected to the signal processing board 12 and serves as a power supply end and a serial port information input end of the signal processing board 12. The signal processing board 12 is used to complete the sending, receiving and processing of the inquiry signal to obtain the performance result of the answering device;

[0011] The data processing and control unit 2 includes an initialization module 21, a serial communication module 22, a control and display module 23 and a document generation module 24;

[0012] The initialization module 21 is used to read the working parameters pre-stored when the device is started and output them to the serial communication module 22;

[0013] The serial communication module 22 receives control instructions from the control and display module 23, and outputs signal processing measurement results to the control and display module 23;

[0014] The control and display module 23 is used to display the performance test results, including: answering status, tested transponder code number, operating frequency, receiving sensitivity, transmitting power and transponder self-test results;

[0015] The document generation module 24 stores the measurement results of the transponder under test in a document in PDF format for easy recording.

[0016] Further, the signal processing board 12 includes: a power module 121, an A / D module 122, an FPGA module 123, a DDS module 124, a DSP module 125, a D / A module 126 and a status display module 127;

[0017] The power module 121 is used to convert the external 12V and 5V voltages into the voltages required by each module;

[0018] The A / D sampling module 122 is used to sample the response signal received by the signal processing board 12 at equal intervals according to the sampling clock, quantize the signal in amplitude and finally output it to the FPGA module 123;

[0019] The FPGA module 123 includes an FPGA chip and its peripheral DDR3 memory, a configuration startup Flash, an SPI Flash, a serial port interface and a clock source, and is used to control the serial port, and respectively control the working modes of the A / D sampling module 122, the DDS module 124 and the D / A module 126, and then perform signal preprocessing on the response signal;

[0020] The DDS module 124 is used to generate an intermediate frequency signal in a working state;

[0021] The DSP module 125 includes a DSP chip and its peripheral DDR3 memory, a configuration startup Flash, an SPI Flash, a serial port interface and a clock source, and is used to complete the reception of work instructions and pre-processed signals, the transmission of measurement results, and further process the pre-processed signals and solve them to obtain the target distance and speed;

[0022] The D / A module 126 is used to convert the signal from a digital signal to an analog signal;

[0023] The status display module 127 is used to indicate whether the FPGA module 123 and the DSP module 124 are working normally.

[0024] 2. A signal processing method for testing transponder performance using the above signal processing device, characterized in that it comprises the following steps:

[0025] 1) sampling the response signal received by the signal processing device at equal intervals in time, quantizing the amplitude, and converting it into a digital signal;

[0026] 2) Down-convert and extract and filter the digital signal to convert it into two orthogonal zero intermediate frequency signals;

[0027] 3) Convert the zero intermediate frequency signal to the frequency domain and eliminate the Doppler offset of the signal in the frequency domain;

[0028] 4) multiplying the offset-eliminated frequency domain signal by its corresponding pulse compression coefficient, and performing inverse Fourier transform on the product to obtain the pulse compression result;

[0029] 5) Performing Doppler Fourier transform on the signal after pulse compression to complete coherent accumulation, forming a range-Doppler matrix, and taking the modulus thereof;

[0030] 6) Perform threshold determination on the matrix after modulo extraction by means of a sliding window to obtain a sparse matrix with most values ​​being 0;

[0031] 7) Perform point resolution and merging processing on the sparse matrix to obtain a condensed sparse matrix;

[0032] 8) According to the maximum values ​​of the velocity dimension and the distance dimension of the condensed sparse matrix and the Doppler channel number corresponding to the maximum value, the target distance and speed are calculated, and the operating frequency, transmission power and operating delay of the transponder are obtained according to the target distance and speed.

[0033] Further, the step 8) is implemented as follows:

[0034] 8a) Select the maximum value in the Doppler dimension for the condensed sparse matrix, perform amplitude weighted average on all points belonging to the same target to obtain the distance unit corresponding to the target distance value, and then multiply the distance unit by the sampling point distance interval to obtain the target distance;

[0035] 8b) searching for two values ​​of adjacent channels in the same distance unit as the maximum value in the condensed sparse matrix, bringing these three values ​​into the front and back filtering algorithms to obtain the accurate Doppler channel number, and using the calculation formula of the relationship between the channel number and the Doppler frequency to obtain the Doppler frequency deviation of the target;

[0036] 8c) Combine the target's Doppler frequency deviation with the transmission signal frame period and the tracking speed gate, and use the Chinese remainder theorem to obtain the precise Doppler frequency deviation; sum the frequency deviation with the current transponder operating frequency to obtain the transponder operating frequency;

[0037] 8d) Obtain the signal amplitude of the maximum value of the Doppler dimension in the condensed sparse matrix, and calculate the transmission power of the transponder according to the target signal amplitude A: P = (A / 100) - 100;

[0038] 8e) According to the speed of light c is 3×10 8 m / s and the target distance S, calculate the response delay: t=2S / c.

[0039] Compared with the prior art, the present invention has the following advantages:

[0040] First, the signal processing device of the present invention can visualize the performance indicators of the transponder under test due to the addition of a data processing and control unit.

[0041] Second, the present invention adopts a signal processing system combining FPGA and DSP, which has high processing capability and strong versatility. It can complete the distance and speed calculation of response signals of different pulse types and obtain the operating frequency, transmission power and working delay indicators of the transponder. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a structural block diagram of a signal processing device of the present invention;

[0043] Figure 2 yes Figure 1 The structural block diagram of the data processing and control unit in;

[0044] Figure 3 yes Figure 1 The structure diagram of the signal processing unit in FIG.

[0045] Figure 4 yes Figure 3 Functional block diagram of the FPGA module;

[0046] Figure 5 yes Figure 3 Functional block diagram of DSP module in;

[0047] Figure 6 It is a flow chart of the implementation of transponder performance detection of the present invention; DETAILED DESCRIPTION

[0048] The present invention is described in detail below with reference to the accompanying drawings and embodiments:

[0049] Reference Figure 1 The signal processing device of the present invention includes two parts: a signal processing unit 1 and a data processing and control unit 2, which are bidirectionally connected via a serial port and are used to send work control instructions and display transponder performance measurement results. Among them, the signal processing unit 1 is used to send an inquiry signal to the transponder and receive and process the response signal replied by the transponder to complete the initial measurement of the transponder performance; the data processing and control unit 2 receives the initial performance measurement value of the transponder through the serial port, performs secondary processing on the result, displays the final result on the host computer and generates a result document PDF.

[0050] Reference Figure 2The signal processing unit 1 includes a motherboard 11 and a signal processing board 12. The motherboard 11 is the transmission medium for information between the signal processing board 12 and the data processing and control unit 2; the signal processing board 12 is the core of the device, which is used to complete the sending of the inquiry signal and the receiving and processing of the response signal and obtain the performance results of the response device. It includes: a power module 121, an AD module 122, an FPGA module 123, a DDS module 124, a DSP module 125, a DA module 126 and a status display module 127, wherein:

[0051] The power module 121 is unidirectionally connected to the FPGA module, the DSP module, the A / D module, the D / A module and the DDS module through a cable. The module is used to convert the external 12V voltage into the 1V, 1.2V, 1.5V, 1.8V and 3.3V voltages required by the FPGA module and the 0.9V, 1.5V and 1.8V voltages required by the DSP module through the power chip; convert the external 5V voltage into the 1.8V voltage required by the A / D module, the 3.3V and 1.8V voltages required by the D / A module and the 3.3V and 1.8V voltages required by the DDS module through the power chip;

[0052] The A / D sampling module 122 is unidirectionally connected to the FPGA module through a cable. The module is controlled by the FPGA module through an SPI interface, receives commands from the FPGA module, samples the response signals at equal time intervals according to the sampling clock, quantizes the amplitude of the sampled signals, and finally obtains a digital signal and outputs it to the FPGA module through a cable for subsequent processing;

[0053] The FPGA module 123 includes an FPGA chip and its peripheral DDR3 memory, configuration startup Flash, SPIFlash, serial port interface and clock source. This module is bidirectionally linked with the DSP module through the SPI interface, and is used to control the power-on of the DSP, the working mode of the A / D module 122, the DDS module 124 and the D / A module 126. When the equipment is in working state, the FPGA module performs digital down-conversion, Doppler frequency shift compensation and pulse compression processing on the signal transmitted from the A / D module; finally, the processed signal and the doorbell interrupt are sent to the DSP, and after receiving the doorbell information, the DSP performs subsequent signal processing and solution;

[0054] The DDS module 124 is unidirectionally connected to the FPGA module 123 via a cable and is used to generate an inquiry signal when the device is in working state;

[0055] The DSP module 125 includes a DSP chip and its peripheral DDR3 memory, a configuration startup Flash, an SPI Flash, a serial port interface and a clock source. The module receives the host computer work instruction data sent by the FPGA module 123 through the SRIO interface and parses and sends it to the FPGA module 123 to make it work in the corresponding working state; after receiving the response signal processed by the FPGA module 123, it further performs signal processing and solves the target and distance information.

[0056] The D / A module 126 is unidirectionally connected to the FPGA module 123 via a cable, and converts digital signals into analog signals for output under the control of the FPGA module 123;

[0057] The status display module 127 is unidirectionally connected to the FPGA module 123, the DSP module and the power module via cables, and is used to indicate whether the power module, the FPGA module 123 and the DSP module 124 are in a normal working state.

[0058] Reference Figure 3 The data processing and control unit 2 includes: an initialization module 21, a serial communication module 22, a control and display module 23 and a document generation module 24, wherein:

[0059] The initialization module 21 is used to read the pre-stored working parameters when the test device is started, and output these parameters to the serial communication module 22;

[0060] The serial communication module 22 mainly completes the interaction with the signal processing unit 1, that is, outputs the signal processing measurement results from the signal processing unit 1 to the display module 23, and outputs the pre-stored working parameters from the initialization module 21 and the working instructions from the display module 23 to the signal processing unit 1;

[0061] The display module 23 is used to display the current target transponder measurement data results sent by the signal processing unit 1 through the serial communication module 21, including: signal processing working state, transponder code number, working frequency, transmission power and response delay.

[0062] The generated result document 24 is used to save the measurement result of the tested transponder as a PDF file for easy storage and recording.

[0063] Reference Figure 4 The FPGA module 123 in the signal processing unit 1 includes four functional submodules: system initialization, DSP communication, FPGA control and signal processing, wherein:

[0064] The system initialization submodule is used to initialize the FPGA module 123, that is, first provide the necessary clocks for some chips and interfaces: the clock configured for power-on of the DSP chip is 25M, the clock provided for the SRIO high-speed link is 125M, and the sampling clock provided for the AD chip is 160M; then generate the power-on control timing that enables the DSP chip to work normally; finally, establish a connection with the SRIO link to realize the control of the A / D module 122 and the DDS module 124, and complete the initialization of the two modules.

[0065] The DSP communication submodule is used to receive and send instructions and result information between the DSP module, that is, through the SRIO interface, the DSP module receives the information transmitted by the DSP communication submodule in a timed query manner, performs signal processing operations when the device is in normal working state, and sends the processed data to the DSP module through the SRIO interface.

[0066] The FPGA control submodule is used to confirm the register parameters of the DDS module according to the code number and working mode, signal frequency, phase and amplitude sent by the host computer, and to program the control register inside the DDS module 124 through the serial I / O port to achieve control. To control the serial port, when sending, send the start bit, then send the data bit, check bit, stop bit, and control the length of the sent data according to the data counter; when receiving, first check the start bit by detecting the falling edge of the input data, then generate the receiving clock, and then use the receiving clock to sample the serial input data, perform shift operations in the buffer, and generate the check bit at the same time; compare the generated check bit with the check bit of the received data: if the check bits are consistent, then determine whether the stop bit of the received data is high. If the stop bit is high, the received data is valid, otherwise the received data is invalid;

[0067] The signal processing submodule is used to complete the preprocessing of the response signal, including signal sampling, digital down-conversion, Doppler compensation and pulse compression processing. The specific processing is as follows:

[0068] When the device is in working state, the response signal is input into the A / D module 122 after passing through the front-end processing circuit to complete the collection of digital signals, and the signal processing submodule intercepts the collected digital signals;

[0069] Next, the intercepted digital signal is subjected to digital down-conversion processing, that is, the intercepted digital signal is multiplied with the local sine / cosine carrier signal generated by the NCO to obtain I and Q signals, and then the two signals are respectively subjected to low-pass filtering and extraction processing through anti-aliasing low-pass filters to obtain the signal after digital down-conversion processing;

[0070] Next, the digital down-converted signal is subjected to Doppler compensation processing to improve the pulse compression performance, that is, to eliminate the frequency shift of the signal caused by Doppler in the frequency domain;

[0071] Finally, the Doppler compensated signal is pulse compressed, that is, the signal is Fourier transformed to transform it from a time domain signal to a frequency domain signal, and then different pulse compression coefficients are selected according to different pulse signal types to multiply the frequency domain signal, and the multiplied signal is inverse Fourier transformed into a time domain signal to complete the pulse compression.

[0072] Reference Figure 5 The DSP module 125 in the signal processing unit 2 includes three functional sub-modules: system initialization, external communication and signal processing, among which:

[0073] The system initialization submodule is used to complete the initialization of the DSP module, including the configuration of the main frequency of the DSP chip and the setting of the global interrupt; the power-on control and operating frequency configuration of the DDR3 module; the power-on control and operating mode configuration of the flash; the power-on control and transmission rate setting of the SRIO, and the completion of its link connection with the FPGA module 123.

[0074] The external communication submodule is used to complete the communication with the FPGA module 123: when the DSP module 125 completes the initialization, it waits for the in-band interrupt sent by the FPGA module 123, and the external communication submodule receives the interrupt information and informs the DSP chip, determines the information carried by the interrupt and parses it.

[0075] The signal processing submodule is used to complete the subsequent processing of the response signal, including moving target detection, constant false alarm detection, and Doppler condensation processing. The specific processing is as follows:

[0076] The signal processing submodule obtains a set of response signals preprocessed by the FPGA module 123, performs Doppler dimension FFT on the signals to complete coherent accumulation, forms a complete range-Doppler matrix, and completes moving target detection;

[0077] Next, the range-Doppler matrix is ​​modulo-calculated, and the range-dimensional GO-CFAR operation is performed after modulo-calculation. The operation uses a sliding window to sum and average the numbers in the window. The processed value is compared with the threshold and a sparse matrix is ​​obtained according to the principle of "setting values ​​below the threshold to 0", thus completing the constant false alarm detection.

[0078] Next, after constant false alarm detection, most of the values ​​of the sparse matrix are processed as 0, and these sparse matrices with most of the values ​​​​as 0 are converted into a one-dimensional vector with a length of the number of distance units. The continuous non-zero values ​​on the one-dimensional vector are identified as the same target occupying several distance units. The distance unit number, channel number and amplitude value of the maximum value point in the amplitude value belonging to the same target are recorded to complete Doppler condensation.

[0079] Reference Figure 6 The present invention uses the above-mentioned signal processing device to implement the performance test of the transponder as follows:

[0080] Step 1, A / D sampling.

[0081] When the signal processing device receives the reply signal, whether it is the binary code pulse reply signal f1(t) of the carrier transponder or the linear frequency modulation pulse signal f2(t) of the landing transponder, it is first subjected to A / D processing to obtain finite discrete digital signals f1(n) and f2(n), where n = 1, 2,…, n.

[0082] In this example, since the signal bandwidth B0 transmitted by the device is 5MHz and the center frequency f0 is 120MHz, the final A / D sampling frequency is selected as f S The sampling bit number is 14 bits, so that the input intermediate frequency signal is sampled at equal intervals and the signal is converted into a digital signal quantized in amplitude to reduce the amount of calculation.

[0083] Step 2: digital orthogonal transformation.

[0084] Generate sine and cosine local oscillator signals using numerically controlled oscillator NCO and Finally, the mixer is used to realize the function of multiplying the sampled signal with the sine and cosine signals, and then the anti-aliasing low-pass filter is used to complete the low-pass filtering and extraction processing to obtain the I-channel signal with the same phase as the sampled signal and the Q-channel signal orthogonal to the sampled signal.

[0085] In this example, the data after A / D sampling is quadrupled under a working clock of 160M, and the two sine and cosine local oscillator signals required for digital down-conversion are regarded as a periodic sequence composed of ±1, 0. The sampled signals are cyclically held, inverted, and zeroed, and then filtered to obtain two orthogonal zero intermediate frequency signals.

[0086] Step 3, Doppler compensation.

[0087] Since the linear frequency modulation signal is not sensitive to the Doppler frequency, even if there is a large Doppler frequency in the signal, it will not affect the effect of pulse compression. However, the binary code signal is more sensitive to the Doppler frequency. If Doppler compensation is not performed on the signal, the Doppler frequency will affect the pulse compression processing of each channel and reduce the gain of pulse compression. Therefore, Doppler compensation is only performed on the binary code signal, and the intermediate frequency signal after the digital orthogonal transformation needs to be spectrally shifted to eliminate the offset signal generated by the Doppler in the frequency domain and reduce the influence of the Doppler frequency shift on the pulse compression.

[0088] In this example, the frequency offset that needs to be eliminated is calculated using known speed gate parameters, and then a group of registers is defined to store a cosine signal. The calculated frequency offset is used to determine how many registers are needed to take a group of numbers in this register group, and finally the zero intermediate frequency signal is multiplied by the numbers in the registers in sequence to achieve Doppler compensation.

[0089] Step 4, pulse compression.

[0090] Pulse compression can be achieved in two ways: time domain or frequency domain. The frequency domain pulse compression method performs Fourier transform on the large time width signal to achieve pulse compression processing, which can not only greatly reduce the amount of calculation, but also achieve a large compression ratio and the best cost performance. Since the binary code signal and the linear frequency modulation signal are of different types, the pulse compression coefficient is different.

[0091] In this example, a frequency domain pulse compression method is used to store the zero intermediate frequency linear frequency modulation signal output after down-conversion or the two-phase code signal after Doppler compensation in the BUFFER cache, and then transform the signal in the BUFFER cache from the time domain to the frequency domain. According to the type of pulse signal, the corresponding pulse compression coefficient is selected and multiplied with the frequency domain signal, and finally an inverse Fourier transform is performed to obtain the pulse compression result.

[0092] Step 5: Moving target detection.

[0093] In this example, the signals after 16 pulse compression are used to form a pulse group matrix, and the matrix is ​​subjected to transposition operation, FFT operation and re-transposition operation in sequence to obtain the result matrix of moving target detection.

[0094] Step 6: CFAR detection.

[0095] In order to keep the false alarm probability constant during signal detection and avoid overload due to too many false alarms, it is necessary to perform constant false alarm processing on the signal to filter out noise and clutter.

[0096] In this example, the distance dimension GO-CFAR operation is performed on the matrix after moving target detection, that is, the matrix after moving target detection is modulo, and the values ​​in the window are summed and averaged in a sliding window manner. The average value is multiplied by the false alarm coefficient and compared with the signal peak value. If the signal is large, it is retained, and if the signal is small, it is set to zero, so as to obtain a sparse matrix.

[0097] Step 7, Doppler condensation.

[0098] After the reply signal passes through moving target detection and constant false alarm detection, the target will be split on the Doppler channel, so Doppler condensation is required to leave only one target point.

[0099] In this example, the sparse matrix after constant false alarm detection is used as the input matrix of this step to perform point resolution and merging processing, that is, first filter out false points, then distinguish the point data of different targets, and merge the point data belonging to the same target together, and find the maximum value and its corresponding Doppler channel number in the distance dimension.

[0100] Step 8: Calculate the target distance.

[0101] In this example, after Doppler condensation, a result matrix is ​​obtained for the two-phase code signal. The result matrix is ​​traversed, and continuous non-zero values ​​can be considered as the approximate range of the target distance. A quadratic polynomial is fitted for the continuous non-zero values. The resolution of the quadratic polynomial fitting ranging result is 0.1m, and the precise distance unit value of the target is obtained, which is then multiplied by the sampling point distance interval to obtain the distance value.

[0102] For linear frequency modulation signals, the positive and negative frequency modulation signals in a pulse signal need to be calculated separately during ranging. After the above processing steps, a pulse signal can obtain the distance unit value of a single pulse. A group of pulse signals will obtain multiple distance unit values. The distance unit values ​​with large differences are filtered out by comparison and then multiplied by the distance interval of the sampling points to obtain the distance value.

[0103] Step 9, calculation of target speed.

[0104] In this example, due to the speed ambiguity of the two-phase code signal, the transmission is carried out in a staggered repetition frequency manner between pulse groups, which has 3 staggered periods. A group of pulses contains 16 pulse signals. After each group of pulse trains is sent, a period adjustment is performed. After receiving the matrix after Doppler condensation, each point of the matrix is ​​traversed to obtain the maximum value of continuous non-zero values ​​and the corresponding number of distance units and channel numbers. Then, the matrix after constant false alarm processing is returned to find the two values ​​of adjacent channels in the same distance unit as the maximum value. The speed is calculated through different repetition frequencies, and then all possible speeds are obtained through fuzzification. Finally, the square of the minimum difference is calculated, which is the current target speed.

[0105] For linear frequency modulation signals, since the signal consists of two segments, positive and negative frequency modulation signals, two levels of speed resolution are required: the first level of resolution is to use the same speed measurement method as the two-phase code signal to obtain two speed values ​​of the positive and negative frequency modulation signals respectively, and the average value is used as the result of the first level speed resolution. However, since this value is unstable and has a large error, this value is taken as the reference speed; the second level of resolution is to defuzzify the eight frequency modulation signals of a pulse group to obtain the speed remainder of the current target speed, and use the speed remainder to obtain multiple possible speed values ​​of the target; then compare the reference speed obtained by the first level resolution with the multiple speed values ​​of the second level resolution, and select the value with the smallest difference from the reference speed as the result of the second level resolution, and finally use the result of the second level resolution as the current speed of the target.

[0106] Step 10: Calculation of transponder operating frequency, transmission power and operating delay indicators.

[0107] Working frequency: Combine the target's Doppler frequency deviation with the transmission signal frame period and the tracking speed gate, and use the Chinese remainder theorem to obtain the precise Doppler frequency deviation. Sum the deviation with the current transponder operating frequency to obtain the transponder's operating frequency.

[0108] Transmit power: The signal amplitude A of the maximum value of the Doppler dimension is obtained in the condensed sparse matrix, and the transmit power of the transponder is calculated based on the target signal amplitude: P = (A / 100)-100;

[0109] Response delay: Calculate the response delay based on the speed of light c and the target distance S: t = 2S / c, where c = 3×10 8 m / s.

[0110] The above description is only a specific example of the present invention and does not constitute any limitation to the present invention. It is obvious that for professionals in this field, after understanding the content and principles of the present invention, it is possible to make various modifications and changes in form and details without departing from the principles and structures of the present invention. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A signal processing device for transponder performance detection, comprising: The signal processing unit (1) and the data processing and control unit (2) are bidirectionally connected to complete the sending of pre-installed parameters and control instructions and the uploading of test results, and are characterized by: The signal processing unit (1) comprises a motherboard (11) and a signal processing board (12). The motherboard (11) is connected to the signal processing board (12) and serves as a power supply end and a serial port information input end of the signal processing board (12). The signal processing board (12) is used to complete the sending, receiving and processing of the inquiry signal to obtain the performance result of the answering device; The data processing and control unit (2) comprises an initialization module (21), a serial communication module (22), a control and display module (23) and a document generation module (24); The initialization module (21) is used to read the working parameters pre-stored when the device is started and output them to the serial communication module (22); The serial communication module (22) receives control instructions from the control and display module (23), and outputs signal processing measurement results to the control and display module (23); The control and display module (23) is used to display the performance test results, including: answering status, the code number of the tested answering machine, the operating frequency, the receiving sensitivity, the transmitting power and the answering machine self-test result; The document generation module (24) stores the measurement results of the transponder under test in a document in PDF format for easy recording.

2. The device according to claim 1, characterized in that The signal processing board (12) comprises: a power module (121), an A / D module (122), an FPGA module (123), a DDS module (124), a DSP module (125), a D / A module (126) and a status display module (127); The power supply module (121) is used to convert external 12V and 5V voltages into voltages required by each module; The A / D sampling module (122) is used to sample the response signal received by the signal processing board (12) at equal intervals according to the sampling clock, quantize the signal in terms of amplitude, and finally output it to the FPGA module (123); The FPGA module (123) comprises an FPGA chip and its peripheral DDR3 memory, a configuration startup Flash, an SPI Flash, a serial port interface and a clock source, and is used to control the serial port, and respectively control the working modes of the A / D sampling module (122), the DDS module (124) and the D / A module (126), and then perform signal preprocessing on the response signal; The DDS module (124) is used to generate an intermediate frequency signal in a working state; The DSP module (125) comprises a DSP chip and its peripheral DDR3 memory, a configuration startup Flash, an SPI Flash, a serial port interface and a clock source, and is used to complete the reception of work instructions and pre-processed signals, the transmission of measurement results, and further process the pre-processed signals and solve them to obtain the target distance and speed; The D / A module (126) is used to convert the signal from a digital signal to an analog signal; The status display module (127) is used to indicate whether the FPGA module (123) and the DSP module (124) are working normally.

3. The testing device according to claim 2, characterized in that The FPGA module (123) controls the serial port, which is implemented as follows: According to the clock of the FPGA module, the required baud rate is generated through counter control; When sending, a data sending clock is generated, the start bit is sent first, then the data bit, check bit, stop bit are sent, and the length of the sent data is controlled according to the data counter; When receiving, the start bit is checked by detecting the falling edge of the input data, and then the receiving clock is generated. The serial input data is sampled using the receiving clock, and the shift operation is performed in the buffer, and the check bit is generated at the same time; Compare the generated check digit with the check digit of the received data: If the check bits are consistent, then determine whether the stop bit of the received data is high. If the stop bit is high, the received data is valid, otherwise the received data is invalid; If the check digits are inconsistent, the received data is invalid.

4. The testing device according to claim 2, characterized in that The FPGA module (123) controls the working modes of the A / D sampling module (122), the DDS module (124) and the D / A module (126) respectively, which is implemented as follows: The FPGA module (123) first provides working clocks to the A / D sampling module (122), the DDS module (124) and the D / A module (126), and then establishes connections between the FPGA module (123) and other modules according to the SPI protocol and the SPI interface; After the connection is established, the working registers of each module are configured. The configuration content includes the sampling frequency of the A / D sampling module (122), the frequency and phase control code of the DDS module (124), and the D / A module (126) selects which signal to convert into an analog signal output.

5. The testing device according to claim 2, characterized in that The FPGA module (123) pre-processes the response signal, which is implemented as follows: The signal processed by the A / D sampling module (122) is filtered using a filter to extract the high-frequency signal, thereby generating an in-phase signal and an orthogonal signal with a low data rate, and completing signal down-conversion; Perform spectrum shifting on the down-converted intermediate frequency signal, that is, eliminating the offset signal generated by Doppler in the frequency domain to complete Doppler compensation; The Doppler compensated signal is transformed by Fourier transform, which transforms it from time domain signal to frequency domain. Different pulse compression coefficients are selected according to different pulse signal types to multiply the frequency domain signal. Finally, an inverse Fourier transform is performed to complete the pulse compression of the signal.

6. The testing device according to claim 2, characterized in that: The DSP module (125) completes the reception of the working instructions and the pre-processed signals by waiting for the interrupt information transmitted by the SRIO interface after the DSP module (125) is initialized. The FPGA module (123) integrates and packages the working instructions and the pre-processed response signals transmitted from the serial port and puts them into the pre-allocated address in the DSP module (125) through SRIO, sends a doorbell interrupt to inform the DSP, and the DSP can read the information at the corresponding address after parsing the doorbell message.

7. The testing device according to claim 2, characterized in that The DSP module (125) completes the transmission of the measurement result by firstly sending it to the register of the FPGA module (123) through the SRIO interface, so as to generate a corresponding data update signal; then the FPGA module (123) performs data recognition on the update signal, and when the signal is set high, it indicates that the data is updated, and finally the latest measurement result is read from the register.

8. The testing device according to claim 2, characterized in that The DSP module (125) processes and solves the signal as follows: Moving target detection: Doppler Fourier transform is performed on the preprocessed signal and coherent accumulation is performed to form a range-Doppler matrix; Constant false alarm detection: Perform range-dimensional GO-CFAR operation on the range-Doppler matrix to obtain a sparse matrix with most values ​​being 0; Doppler condensation: select the maximum value of the Doppler dimension value in the same distance unit on the sparse matrix, and use the Doppler channel corresponding to the maximum value as the rough estimated Doppler channel corresponding to the target speed; Calculate the target distance: perform amplitude weighted average on all points belonging to the same target after selecting the maximum value of the Doppler dimension to obtain the distance unit corresponding to the target distance value, and then multiply the distance unit by the sampling point distance interval to obtain the target distance; Target speed calculation: Find two values ​​of adjacent channels in the same distance unit as the above maximum value in the sparse matrix, bring these three values ​​into the front and back filtering algorithms to obtain the accurate number of Doppler channels, and use the calculation formula of the relationship between the number of channels and the Doppler frequency to obtain the target's Doppler frequency deviation; calculate the target speed based on whether there is speed ambiguity: If there is speed ambiguity, it is necessary to solve the Doppler frequency deviation of the three different periodic response signals and bring them into the staggered algorithm to solve the target speed; If there is no velocity ambiguity, the target velocity can be directly solved based on the conversion formula between Doppler frequency deviation and velocity.

9. A signal processing method for testing transponder performance using the signal processing device of claim 1, characterized in that: The steps include: 1) sampling the response signal received by the signal processing device at equal intervals in time, quantizing the amplitude, and converting it into a digital signal; 2) Down-convert and extract and filter the digital signal to convert it into two orthogonal zero intermediate frequency signals; 3) Convert the zero intermediate frequency signal to the frequency domain and eliminate the Doppler offset of the signal in the frequency domain; 4) multiplying the offset-eliminated frequency domain signal by its corresponding pulse compression coefficient, and performing inverse Fourier transform on the product to obtain the pulse compression result; 5) Performing Doppler Fourier transform on the signal after pulse compression to complete coherent accumulation, forming a range-Doppler matrix, and taking the modulus thereof; 6) Perform threshold determination on the matrix after modulo extraction by means of a sliding window to obtain a sparse matrix with most values ​​being 0; 7) Perform point resolution and merging processing on the sparse matrix to obtain a condensed sparse matrix; 8) According to the maximum values ​​of the velocity dimension and the distance dimension of the condensed sparse matrix and the Doppler channel number corresponding to the maximum value, the target distance and speed are calculated, and the operating frequency, transmission power and operating delay of the transponder are obtained according to the target distance and speed.

10. The method according to claim 9, characterized in that The step 8) is implemented as follows: 8a) Select the maximum value in the Doppler dimension for the condensed sparse matrix, perform amplitude weighted average on all points belonging to the same target to obtain the distance unit corresponding to the target distance value, and then multiply the distance unit by the sampling point distance interval to obtain the target distance; 8b) searching for two values ​​of adjacent channels in the same distance unit as the maximum value in the condensed sparse matrix, bringing these three values ​​into the front and back filtering algorithms to obtain the accurate Doppler channel number, and using the calculation formula of the relationship between the channel number and the Doppler frequency to obtain the Doppler frequency deviation of the target; 8c) Combine the target's Doppler frequency deviation with the transmission signal frame period and the tracking speed gate, and use the Chinese remainder theorem to obtain the precise Doppler frequency deviation; sum the frequency deviation with the current transponder operating frequency to obtain the transponder operating frequency; 8d) Obtain the signal amplitude of the maximum value of the Doppler dimension in the condensed sparse matrix, and calculate the transmission power of the transponder according to the target signal amplitude A: P = (A / 100) - 100; 8e) According to the speed of light c is 3×10 8 m / s and the target distance S, calculate the response delay: t=2S / c.

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