Layout pattern optimization method and semiconductor wafer

Abstract

The invention provides a method for adjusting a layout pattern and a semiconductor wafer. The method comprises the following steps: detecting photoetching hot spots in a first layout pattern; generating a fine tuning pattern for the photoetching hot spots; generating a layout pattern optimization test group according to the photoetching hot spot and the fine tuning pattern; forming a first layout pattern in a crystal grain area of the wafer through a photoetching process, and forming a layout pattern optimization test group in a cutting channel area of the wafer; performing electrical detection on a verification pattern group of the optimization test group, and determining an optimal manufacturing scheme from the photoetching hot spot and the fine tuning pattern according to a result of the electrical detection; and determining a second layout pattern according to the optimal manufacturing scheme.

Description

Technical Field

[0001] The present invention relates to a design method for mass production layout patterns of semiconductor chips, and in particular to a layout pattern optimization method and a semiconductor chip. Background Art

[0002] With the development of the semiconductor industry, electronic products are gradually miniaturized and the density of integrated circuits is increased. In order to achieve the above miniaturization and higher integration, the feature size of integrated circuits (such as the shortest line width or pitch) is continuously reduced. As the feature size is reduced, the problem of inconsistency between the pattern formed by the photolithography process and the designed pattern arises, which is also called the optical proximity effect (OPE). This may cause the manufactured integrated circuit to have short circuits, open circuits or other electrical anomalies.

[0003] In order to determine whether the design pattern is acceptable, a test pattern is usually formed in the chip area of ​​the wafer, and the test pattern is tested through a bare crystal needle test (chip probe testing) process (hereinafter referred to as CP test) to infer whether the pattern formed according to the design pattern is likely to cause electrical abnormalities. However, it takes a long time from the generation of the design pattern to the completion of the CP test. If the design pattern needs to be adjusted only after the inferred result of the CP test, it will be detrimental to the development efficiency of the semiconductor device. Moreover, if the production of the front layer of the test pattern is abnormal, it is easy to interfere with the result of the CP test, resulting in inaccurate inference results. In addition, forming a test pattern in the chip area of ​​the wafer will occupy the space of the chip area, which is not conducive to the miniaturization of the chip.

[0004] On the other hand, in order to check whether the process causes structural defects, a test key or a test element group (TEG) is usually set on the cutting path of the chip. In detail, while each process step is performed to make the components in the chip area, the test key or TEG is synchronously made in the cutting path of the chip, and then the various parameters of the test key or TEG are measured by a test device as a pointer to check whether the process and components are normal, thereby effectively controlling the product quality. However, the existing test key or TEG is formed by a single test pattern (such as a comb pattern), which cannot reflect whether the design pattern in the chip area needs to be adjusted.

[0005] In addition, according to the existing technology, even if the developer finds that the design pattern located in the chip area needs to be adjusted, the developer adjusts the design pattern based on his development experience and uses the trial and error method to repeatedly produce new chips based on the adjusted design pattern, resulting in a very lengthy development process for semiconductor devices. Summary of the invention

[0006] Therefore, a layout pattern optimization method is needed that can accurately find solutions corresponding to each lithography hotspot without affecting mass production.

[0007] In one embodiment of the present disclosure, a method for optimizing a layout pattern includes: detecting a lithography hotspot in a first layout pattern; generating a fine-tuning pattern for the lithography hotspot; generating a layout pattern optimization test group based on the lithography hotspot and the fine-tuning pattern, the layout pattern optimization test group including a first array pattern test group and a second array pattern test group, the first array pattern test group including a plurality of verification pattern groups of different capacities generated based on the lithography hotspot, and the second array pattern test group including a plurality of verification pattern groups of different capacities generated based on the fine-tuning pattern; forming the first layout pattern in a die region of a chip through a lithography process, and forming the layout pattern optimization test group in a cutting path region of the chip; performing electrical detection on the verification pattern groups formed on the chip, and determining an optimal manufacturing solution from the lithography hotspot and the fine-tuning pattern based on the results of the electrical detection; and determining a second layout pattern based on the optimal manufacturing solution.

[0008] In another embodiment of the present disclosure, a semiconductor chip includes: an integrated circuit formed in a die area; and a layout pattern optimization test group formed in a cutting path area, wherein the layout pattern optimization test group includes a first array pattern test group and a second array pattern test group, the first array pattern test group includes a plurality of verification pattern groups of different capacities generated according to the photolithography hotspots, and the second array pattern test group includes a plurality of verification pattern groups of different capacities generated according to the fine-tuning pattern.

[0009] Compared to the prior art that adjusts the design pattern based on its development experience and uses trial and error to repeatedly produce new chips based on the adjusted design pattern, the layout pattern optimization method of one embodiment of the present invention can shorten the development time of the second layout pattern and improve the yield. In addition, when the process conditions change, the layout pattern optimization test group can be set in the cutting road area of ​​the mass production chip to verify whether the layout pattern needs to be adjusted in response to the changed process conditions, which can shorten the verification time of the new process. Furthermore, in some embodiments, electrical testing is performed immediately after the layout pattern optimization test group is formed on the chip, without waiting until the entire chip manufacturing process is completed, thereby saving the time required for the layout pattern optimization method. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a flow chart illustrating a method for adjusting a layout pattern according to some embodiments of the present disclosure;

[0011] Figure 2The figure is a schematic plan view showing, by way of example, a die region and a saw street region in a wafer;

[0012] Figure 3A A schematic plan view showing a characteristic array pattern that may cause difficulty in photolithography;

[0013] Figure 3B A schematic plan view showing another feature array pattern that may cause difficulty in photolithography;

[0014] FIG. 4A to FIG. 4C To illustrate some embodiments according to the present disclosure Figure 3A Schematic plan views of various adjustment schemes of the characteristic array pattern shown;

[0015] Figure 5 A schematic plan view exemplarily showing a group of test patterns corresponding to an adjustment scheme;

[0016] Figure 6 is a schematic plan view exemplarily showing a wafer on which a first layout pattern is formed;

[0017] FIG. 7A to FIG. 7D Plotting the magnitude of the test population versus yield for multiple layout patterns;

[0018] Figure 8 The diagram is a plan view of a semiconductor die separated from a wafer according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0019] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0020] The layout pattern optimization method of one embodiment of the present invention involves setting at least one layout pattern optimization test group in the cutting path area of ​​the chip. And the layout pattern is set in the die area of ​​the chip. The layout pattern optimization test group includes a plurality of array pattern test groups with different patterns, and each array pattern test group includes a plurality of verification pattern groups generated by OPC simulation with the same pattern but different capacities. Based on the results of electrical testing performed on these verification pattern groups, an optimal manufacturing scheme can be determined from these verification pattern groups, and the above-mentioned layout pattern is formed according to this optimal manufacturing scheme. In this embodiment, the layout pattern optimization test group is not set in the die area of ​​the chip, so that it will not affect the production capacity and can shorten the design schedule of the layout pattern.

[0021] Please refer to Figure 1, firstly, step S100 is performed to provide a layout pattern to be adjusted (hereinafter referred to as the first layout pattern). The first layout pattern can be used to form a certain pattern layer in an integrated circuit on a chip. The first layout pattern can be a part of a memory array. The first layout pattern has not been optimized, and some parts thereof may cause difficulties in mask design due to special graphics, high complexity, or being at the boundary between high density and low density, or cause defects in the pattern layer formed on the chip. In the subsequent steps, it will be determined how to optimize the adjustment scheme of the first layout pattern. The chip can be a semiconductor chip (for example, a silicon chip) or a semiconductor-on-insulator (SOI) chip (for example, a silicon-on-insulator chip). In some embodiments, the integrated circuit includes a memory integrated circuit. For example, the memory integrated circuit can be a flash memory integrated circuit, a dynamic random access memory (DRAM) integrated circuit, or the like. In these embodiments, the first layout pattern may include a pattern of a word line, a bit line, a source line, or other pattern layers in a cell region for forming a memory integrated circuit. Furthermore, in some embodiments, the first layout pattern is provided by a computer system such as an Electronic Computer-Aided Design (ECAD) system.

[0022] Please refer to Figure 2 , the wafer 200 can be defined as having a plurality of die regions 202 and a scribe line region 204 between the die regions 202. The plurality of die regions 202 can be arranged in an array. Integrated circuits can be formed in the die regions 202. After the integrated circuit is manufactured, the plurality of die regions 202 can be singulated along the scribe line region 204 during a packaging process to form a plurality of semiconductor dies.

[0023] like Figure 1 As shown, step S102 is then performed to detect lithography hot spots in the first layout pattern. The lithography hot spots include feature portions in the first layout pattern that may cause lithography difficulties due to special patterns, high complexity, or being at the boundary between high density and low density. In some embodiments, the lithography hot spots can be detected by optical proximity correction (OPC) simulation software. In these embodiments, the feature portions may include array patterns composed of repeated graphic units (referred to herein as feature array patterns).

[0024] Please refer to Figure 3A, a characteristic array pattern 300a of an embodiment of the present invention includes a plurality of line segments 302. Each line segment 302 extends along a direction Y, and these line segments 302 are arranged separately from each other along a direction X. In addition, these line segments 302 may have extension portions 302e (which may be understood as a portion of a repeating pattern unit in this article) at intervals. The extension portion 302e further extends from the main portion 302b of the line segment 302 to which it belongs in the direction Y, and has a rectangular (or hammer-shaped) appearance. The extension portion 302e has an initial aspect ratio. Generally speaking, when the characteristic array pattern 300a is transferred to a chip through a photolithography process, errors may be caused by factors such as OPE. For example, after the line segment 302 is transferred to the chip, the main portion 302b connected to the extension portion 302e may gradually widen toward the extension portion 302e at the connection to a degree greater than expected. As a result, the distance between the line segment 302 and the adjacent line segment 302 may be disadvantageously shortened, resulting in an increase in resistance-capacitance delay (RC delay) or even a short circuit problem.

[0025] Please refer to Figure 3B , the characteristic array pattern 300b of another embodiment of the present invention includes a plurality of turning line segments 304 and a plurality of straight line segments 306. Each turning line segment 304 has a U-shaped turning point T 304 , and the end of each straight line segment 306 may be located at the turning point T of a turning line segment 304 304 , and is surrounded on three sides by the turning line segment 304. In addition, each pair of the turning line segment 304 and the straight line segment 306 may be spaced apart from each other, and multiple pairs of the turning line segment 304 and the straight line segment 306 may be periodically arranged along the direction X. When the feature array pattern 300b is transferred onto a wafer through a photolithography process, there may be a problem that, for example, the end of the straight line segment 306 bridges with the adjacent turning line segment 304.

[0026] It should be noted that only two representative feature array patterns 300a and 300b are used for illustration, and the first layout pattern may also include other feature portions that cause difficulties in photolithography. The present disclosure is not limited to the type, position and shape of the feature portions.

[0027] Please refer to Figure 1 , proceed to step S104 to generate a suggested adjustment scheme for each lithography hotspot (hereinafter referred to as a fine-tuning pattern). In some embodiments, in addition to detecting lithography hotspots, the OPC simulation software is also used to generate suggested adjustment schemes corresponding to these lithography hotspots. In this embodiment, for a lithography hotspot, the OPC simulation software can generate multiple suggested adjustment schemes.

[0028] Please refer to FIG. 4A to FIG. 4C In this embodiment, for Figure 3AThe characteristic array pattern 300a shown can generate three fine-tuning patterns, namely, the fine-tuning pattern 400a, the fine-tuning pattern 400b and the fine-tuning pattern 400c. However, the present invention does not limit the number of the generated suggested adjustment schemes. In detail, at least one fine-tuning pattern can be generated according to the modification of the initial aspect ratio of the extended portion 302e of the line segment 302 in the characteristic array pattern 300a. Each fine-tuning pattern corresponds to a modified aspect ratio of the extended portion 302e of the line segment 302, and the aspect ratios of the fine-tuning patterns 400b to 400c are different from each other. For example, in this embodiment, the length of the extended portion 302e of the fine-tuning pattern 400a is the same as the initial length, and the width is greater than the initial width. The length of the extended portion 302e of the fine-tuning pattern 400b is greater than the initial length, and the width is equal to the initial width. The length of the extended portion 302e of the fine-tuning pattern 400c is greater than the initial length, and the width is greater than the initial width.

[0029] Please refer to Figure 1 , proceed to step S106, generating a layout pattern optimization test group according to the lithography hotspot and the fine-tuning pattern. Figure 6 As shown, the layout pattern optimization test group includes a first array pattern test group 606a composed of a plurality of lithography hot spots (e.g., feature array pattern 300a), a second array pattern test group 606b composed of a plurality of fine-tuning patterns 400a replacing a portion of the repeating pattern units in the lithography hot spots in the first array pattern test group 606a, a third array pattern test group 606c composed of a plurality of fine-tuning patterns 400b replacing a portion of the repeating pattern units in the lithography hot spots in the first array pattern test group 606a, and a fourth array pattern test group 606d composed of a plurality of fine-tuning patterns 400c replacing a portion of the repeating pattern units in the lithography hot spots in the first array pattern test group 606a. Figure 6 As shown, the first array pattern test group 606a, the second array pattern test group 606b, the third array pattern test group 606c and the fourth array pattern test group 606d each include 5 verification pattern groups of different capacities, but the present invention is not limited thereto. Figure 5As shown, each array pattern test group includes a verification pattern group 500a of a first capacity, a verification pattern group 500b of a second capacity, and a verification pattern group 500c of a third capacity. In the present embodiment, in the first array pattern test group 606a, these lithography hot spots are arranged at a reference pitch. In the second array pattern test group 606b, these fine-tuning patterns 400b are arranged at a reference pitch. In the third array pattern test group 606c, these fine-tuning patterns 400c are arranged at a reference pitch. The so-called capacity may be, for example, the number of line segments 302. In the present embodiment, the first capacity may be 1MB, the second capacity may be 2MB, and the third capacity may be 4MB. However, the present invention does not limit the size of the capacity and the number of verification pattern groups, as long as each array pattern test group includes verification pattern groups with the same pattern but different capacities. In a preferred embodiment, in each array pattern test group, the smallest capacity may be 1MB, and the largest capacity is less than the total storage capacity of the corresponding cell area (for example, 1GB). In another preferred embodiment, the ratio of the capacity of the verification pattern group to the total storage capacity of the memory array is between 0.05% and 2%.

[0030] Figure 5 Schematic diagrams of the plan view of each array pattern test group 500 are shown as examples. According to different capacities, the total width W of the verification pattern groups 500a, 500b, 500c along the arrangement direction of the line segment 302 (eg, direction X) is 500a , W 500b , W 500c On the other hand, the verification pattern groups 500a, 500b, and 500c may have substantially the same length (dimension in the extension direction of the line segment 302) L 500 .

[0031] Please refer to Figure 1 and Figure 6 , proceed to step S108 , forming a first layout pattern 602 in the die region 202 of the wafer 200 by a photolithography process or a combination of a photolithography process and an etching process, and forming a layout pattern optimization test group 604 in the scribe line region 204 of the wafer 200 .

[0032] Subsequently, step S110 is performed to perform electrical detection on the verification pattern groups formed on the chip 200, and determine an optimal manufacturing solution from the lithography hotspots and at least one fine-tuning pattern according to the results of the electrical detection. In an embodiment in which multiple layout pattern optimization test groups for multiple lithography hotspots are formed on the chip, the optimal manufacturing solutions corresponding to each lithography hotspot can be selected according to the results of the electrical detection of each layout pattern optimization test group. In one embodiment, before completing the entire chip manufacturing process (for example, before completing other film layers other than the first layout pattern), electrical detection is performed on the verification pattern groups formed on the chip 200. The electrical detection is, for example, a wafer acceptance test (WAT). After the electrical detection, the test machine can generate an electrical response trend line for each array pattern test group, and determine which of these electrical response trend lines meets the expected target, and determine the lithography hotspot or fine-tuning pattern in the array pattern test group corresponding to the electrical response trend line that meets the expected target as the optimal manufacturing solution.

[0033] In one embodiment, each electrical property response trend line is a relationship between the WAT result of an array pattern test group and different capacities of the verification pattern group. Among these electrical property response trend lines, the array pattern test group whose WAT result decreases the least with increasing capacity, or the array pattern test group whose WAT result can still be maintained at or above the expected target with increasing capacity, and the corresponding lithography hotspot or fine-tuning pattern can be selected as the best manufacturing solution.

[0034] Please refer to FIG. 7A to FIG. 7D , which are the electrical response trend lines of the first array pattern test group 606a, the second array pattern test group 606b, the third array pattern test group 606c and the fourth array pattern test group 606d. The vertical axis is the WAT result (%), and the horizontal axis is different capacities (MB). Electrical response trend line 700a represents the electrical detection results of all verification pattern groups of the first array pattern test group 606a; electrical response trend line 700b represents the electrical detection results of all verification pattern groups of the second array pattern test group 606b; electrical response trend line 700c represents the electrical detection results of all verification pattern groups of the third array pattern test group 606c; and electrical response trend line 700d represents the electrical detection results of all verification pattern groups of the fourth array pattern test group 606d. Through the judgment of the test machine, the WAT result of the second array pattern test group 606b corresponding to the electrical response trend line 700b decreases the least with the increase of capacity, and can be maintained at or above the expected target regardless of the size of the capacity. Therefore, the fine-tuning pattern 400a used to constitute the second array pattern test group 606b can be determined to be the best manufacturing solution.

[0035] Please refer to Figure 1, and step S112 is performed to determine the second layout pattern with the best manufacturing solution. The second layout pattern may be a layout pattern for mass production, which is formed in the die area 202 of the mass production chip 200'. In detail, in an embodiment where the first layout pattern has two photolithography hot spots (e.g., feature array pattern 300a and feature array pattern 300b), a first layout pattern optimization test group corresponding to feature array pattern 300a and a second layout pattern optimization test group corresponding to feature array pattern 300b may be generated in step S106. In this embodiment, when step S110 determines that the best manufacturing solution for feature array pattern 300a is one of the fine-tuning patterns (e.g., fine-tuning pattern 400a), and the best manufacturing solution for feature array pattern 300b is feature array pattern 300b, it is determined that feature array pattern 300a in the first layout pattern needs to be adjusted, and feature array pattern 300b does not need to be adjusted, and the feature array pattern formed by fine-tuning pattern 400a replaces feature array pattern 300a in the first layout pattern, thereby generating a second layout pattern to optimize the first layout pattern. For example, the extended portion 302e of the line segment 302 of the fine-tuning pattern 400a may be used to replace the Figure 3A The extended portion 302e of the line segment 302 in the feature array pattern 300a is shown. In this way, the feature portion in the first layout pattern that is prone to cause photolithography difficulties can be replaced by a pattern that has passed the inspection. That is, the above-mentioned replacement step can be performed on one or more photolithography hotspots of the first layout pattern to obtain a second layout pattern.

[0036] The above optimization method can be used to design a layout pattern corresponding to any pattern layer of an integrated circuit. After these optimized layout patterns (i.e., the second layout patterns) are transferred to a wafer, each pattern layer of the integrated circuit can be formed on the wafer. Since the characteristic parts of each pattern layer that are prone to photolithography difficulties have been replaced in advance before the manufacture of the integrated circuit is completed, the yield of the integrated circuit can be improved.

[0037] In summary, the layout pattern optimization method of one embodiment of the present invention includes detecting the photolithography hotspots in the first layout pattern, generating a fine-tuning pattern for each photolithography hotspot, generating a layout pattern optimization test group based on the photolithography hotspots and the fine-tuning pattern, and performing electrical detection on each verification pattern group formed on the chip, and determining the best manufacturing solution from the photolithography hotspots and the fine-tuning pattern based on the results of the electrical detection. In this way, the second layout pattern (i.e., the layout pattern formed in the die area and used for mass production) is determined by the best manufacturing solution. Compared with the prior art that adjusts the design pattern based on its development experience and uses the trial and error method to repeatedly produce new chips based on the adjusted design pattern, the layout pattern optimization method of one embodiment of the present invention can shorten the development time of the second layout pattern and improve the yield. In addition, when the process conditions change, the layout pattern optimization test group can be set in the cutting road area of ​​the mass production chip to verify whether the layout pattern needs to be adjusted in response to the changed process conditions, thereby shortening the verification time of the new process. Furthermore, in some embodiments, electrical testing is performed immediately after the layout pattern optimization test group is formed on the chip, without having to wait until the entire chip manufacturing process is completed, thereby saving the time required for the layout pattern optimization method.

[0038] Figure 8 FIG. 8 is a schematic plan view of a semiconductor die 800 separated from a wafer 200 according to some embodiments of the present disclosure.

[0039] Please refer to Figure 8 , the semiconductor die 800 includes a second layout pattern 802, and may further include a sealing ring 804. The sealing ring 804 may surround the second layout pattern 802, and may protect the second layout pattern 802 during the singulation process. In some embodiments, the sealing ring 804 may be made of a metal material. In some embodiments, a portion of the scribe line region 204 from the wafer 200 is retained in the semiconductor die 800, for example, on one side of the sealing ring 804. In these embodiments, at least one layout pattern optimization test group (for example, the layout pattern optimization test group 604) formed in the scribe line region 204 may be partially retained in the remaining portion of the scribe line region 204. For example, the upper portion of the layout pattern optimization test group 604 is retained in the semiconductor die 800. The retained portion of the layout pattern optimization test group 604 may include the upper portions of the first array pattern test group 606a, the second array pattern test group 606b, the third array pattern test group 606c, and the fourth array pattern test group 606d. The plurality of verification pattern groups in each array pattern test group may be separately arranged side by side according to the capacity. In addition, each verification pattern group may have the same length but different widths based on the different capacities.

[0040] According to the layout pattern optimization method and semiconductor chip of the present invention, the development time of mass production patterns can be effectively shortened and the yield rate can be improved, thereby reducing the experimental semiconductor chips wasted in the semiconductor chip development process and reducing the waste of resources caused by the semiconductor chip development process, so as to achieve the goal of green semiconductor technology development.

[0041] However, in alternative embodiments, the layout pattern optimization test group 604 may not remain in the portion where the scribe line region 204 remains in the semiconductor die 800. In other embodiments, the scribe line region 204 may not even remain in the semiconductor die 800.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for optimizing a layout pattern, characterized in that: include: detecting lithography hot spots in a first layout pattern; generating a fine-tuned pattern for the lithographic hotspot; Generating a layout pattern optimization test group according to the lithography hotspot and the fine-tuning pattern, the layout pattern optimization test group comprising a first array pattern test group and a second array pattern test group, the first array pattern test group comprising a plurality of verification pattern groups of different capacities generated according to the lithography hotspot, and the second array pattern test group comprising a plurality of verification pattern groups of different capacities generated according to the fine-tuning pattern; Forming the first layout pattern in a die region of a wafer by a photolithography process, and forming the layout pattern optimization test group in a scribe line region of the wafer; Performing electrical inspection on the verification pattern groups formed on the wafer, and determining the best manufacturing solution from the photolithography hot spots and the fine-tuning patterns according to the results of the electrical inspection; and A second layout pattern is determined according to the optimal manufacturing solution.

2. The method for optimizing a layout pattern according to claim 1, characterized in that: The photolithography hotspot in the first layout pattern is detected by optical proximity calibration. The photolithography hotspot is a portion of a plurality of repeated pattern units of a feature array pattern in the first layout pattern. The fine-tuning pattern is used to replace the portion of the plurality of repeated pattern units.

3. The method for optimizing a layout pattern according to claim 2, characterized in that: The portions of the plurality of repeating pattern units are respectively extension portions of a line segment, the width of the extension portions is greater than the width of the main portion of the line segment, and the fine-tuning pattern and the extension portions of the line segment are identical except for the different aspect ratios.

4. The method for optimizing a layout pattern according to claim 3, characterized in that: The fine-tuning pattern includes a first fine-tuning pattern and a second fine-tuning pattern, wherein the aspect ratio of the first fine-tuning pattern is different from the aspect ratio of the second fine-tuning pattern. The layout pattern optimization test group further includes a third array pattern test group, the second array pattern test group includes a plurality of verification pattern groups of different capacities generated according to the first fine-tuning pattern, and the third array pattern test group includes a plurality of verification pattern groups of different capacities generated according to the second fine-tuning pattern, The optimal manufacturing solution is determined from the photolithography hotspot, the first fine-tuning pattern and the second fine-tuning pattern according to the result of the electrical property detection.

5. The method for optimizing a layout pattern according to claim 3, characterized in that: The line segment pitch of the test pattern in the layout pattern optimization test group is the same as the line segment pitch of the feature array pattern, but the line segment length of the test pattern is different from the line segment length of the feature array pattern.

6. The method for optimizing a layout pattern according to claim 1, characterized in that: A ratio of the multiple capacities of the multiple verification pattern groups to the total storage capacity of the die area is between 0.05% and 2%.

7. The method for optimizing a layout pattern according to claim 4, characterized in that: The first fine-tuning pattern and the second fine-tuning pattern have the same length and different widths from each other.

8. The method for optimizing a layout pattern according to claim 6, characterized in that: The plurality of verification pattern groups in the first array pattern test group are arranged side by side and separated from each other, and the plurality of verification pattern groups in the second array pattern test group are arranged side by side and separated from each other.

9. The method for optimizing a layout pattern according to claim 1, characterized in that: Also includes: generating a plurality of electrical response trend lines for the plurality of array pattern test groups; and Determine which of the plurality of electrical response trend lines meets the expected target, Determining the best manufacturing solution from the photolithography hotspots and the fine-tuning patterns according to the results of the electrical detection includes determining the photolithography hotspots or the fine-tuning patterns in the array pattern test group corresponding to the electrical response trend line that meets the expected target as the best manufacturing solution.

10. The method for optimizing a layout pattern according to claim 9, characterized in that: The electrical property inspection is for the wafer to be tested.

11. The method for optimizing a layout pattern according to claim 10, characterized in that: Each of the electrical response trend lines is a relationship between the wafer acceptance test result and capacity of one of the plurality of array pattern test groups.

12. The method for optimizing a layout pattern according to claim 9, characterized in that: Among these electrical response trend lines, the array pattern test group in which the electrical test results decrease the least as the multiple capacities increase, or the electrical test results remain at or above the expected target as the multiple capacities increase, and the corresponding photolithography hotspot or the fine-tuning pattern is judged to be the optimal manufacturing solution.

13. A semiconductor wafer, characterized in that: include: Integrated circuits, formed in the die region; as well as A layout pattern optimization test group is formed in a cutting path area, wherein the layout pattern optimization test group includes a first array pattern test group and a second array pattern test group, the first array pattern test group includes a plurality of verification pattern groups of different capacities generated according to photolithography hotspots, and the second array pattern test group includes a plurality of verification pattern groups of different capacities generated according to the fine-tuning pattern.

14. The semiconductor wafer according to claim 13, characterized in that The plurality of verification pattern groups of the first array pattern test group have the same length and different widths, and the plurality of verification pattern groups of the second array pattern test group have the same length and different widths.

15. The semiconductor wafer according to claim 13, characterized in that The plurality of verification pattern groups in the first array pattern test group are arranged side by side and separated from each other, and the plurality of verification pattern groups in the second array pattern test group are arranged side by side and separated from each other.

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