A method for detecting and compensating lithography stitching deviation

Abstract

The present invention discloses a detection method and a compensation method for lithography stitching deviation, belonging to the field of lithography technology. The detection method includes fabricating a zero layer containing registration marks with zero relative position deviation in the stitching seam area; aligning the stitching layer with the zero layer and measuring the registration deviation using the registration marks. The compensation method includes calculating the registration deviation through the registration marks and performing compensation. The present invention can reduce the lithography stitching deviation to the required range.

Description

Technical Field

[0001] The present invention belongs to the field of lithography technology, and particularly relates to a method for detecting and compensating lithography stitching deviation. Background Art

[0002] At present, the mainstream lithography machine manufacturer ASML has a maximum single-exposure size of 26mm * 33mm for its lithography machine equipment. With the development of semiconductor technology, processors, memories, image sensors, FPGAs, and silicon photonics chips are increasingly widely used, and more and more optical chips will exceed the size of 26mm * 33mm. Therefore, lithography stitching technology is required in production.

[0003] Perfect stitching means that the two lithography patterns are completely aligned, which is an ideal state that cannot be achieved. The parameter that measures the alignment accuracy between two chips in lithography is the stitching deviation. There are many sources of deviation, such as uneven movement of the wafer stage and the mask stage during lithography; the alignment accuracy between the wafer and the mask; the thermal deformation of the mask during operation; the stress generated by the wafer during processing; and the distortion of the projection optical path of the lithography machine, etc., all of which will cause stitching deviation.

[0004] Although there are many sources of deviation, the resulting impact is generally very small, about dozens to hundreds of nanometers. When the product size is within 26mm * 33mm, stitching is not required. Since there are scribe lanes between the chips, the redundancy of the deviation is large and can be ignored. However, when stitching is required, the impact of the stitching deviation caused by the above factors needs to be considered.

[0005] As the process becomes more and more advanced, the requirements for stitching are also getting higher. Taking optical chips as an example, the carrier for transmitting information in optical chips is light. When performing stitching lithography, it is necessary to align the optical waveguides as much as possible to reduce the loss of optical signals. The waveguide width is generally in the range of several hundred nanometers, and the deviation of dozens to hundreds of nanometers mentioned above has a greater impact on the transmission loss. Summary of the Invention

[0006] The purpose of the present invention is to provide a method for detecting and compensating lithography stitching deviation to overcome the defects of the prior art. By adding zero-layer lithography to fabricate the stitching seam position, forming alignment marks and zero-deviation overlay marks, and then performing subsequent waveguide layer fabrication. Since the mask fabrication accuracy is relatively high, it can be considered that there is no deviation in the relative position between the zero-layer overlay marks. At this time, the overlay deviation of the waveguide layer relative to the zero layer can be used to characterize the stitching deviation size. By calculating the overlay deviation through the overlay marks and performing compensation, the lithography stitching deviation can be reduced.

[0007] The purpose of the present invention is achieved by the following technical solutions:

[0008] A method for detecting lithography stitching deviation, the method comprising:

[0009] Making a zero layer including an overlay mark with a relative position zero deviation in the joint seam area;

[0010] The zero layer is aligned with the splicing layer to measure the overlay deviation.

[0011] Furthermore, the step of making a zero layer of an overlay mark including a relative position zero deviation in the joint seam area specifically includes:

[0012] By photolithography across the stitching seam, a zero layer is added before the stitching layer, the range of the zero layer includes the stitching position of two photolithography areas, and the zero layer includes the overlay mark and alignment mark of the stitching seam position.

[0013] Furthermore, the overlay marks include at least two groups, which are respectively placed at two ends of the joint seam, and each group includes two marks, which are respectively placed on two sides of the joint seam.

[0014] Furthermore, the step of aligning the zero layer with the splicing layer and measuring the overlay deviation specifically includes:

[0015] Using the alignment mark to make a stitching layer lithography on the stitching layer;

[0016] The size of the stitching deviation is characterized by the size of the overlay deviation of the stitching layer lithography to the zero layer, and the overlay deviation is calculated through the overlay mark.

[0017] On the other hand, the present invention further provides a method for compensating for photolithography stitching deviation, wherein the method measures the photolithography stitching deviation by any of the aforementioned methods, and the compensation method comprises:

[0018] The overlay deviation is compensated to reduce the photolithography stitching deviation to within a preset deviation range threshold.

[0019] Furthermore, the method further comprises:

[0020] At least one group of overlay marks is added between the two groups of overlay marks on each splicing layer, and then deviation detection and compensation are performed.

[0021] The beneficial effects of the present invention are:

[0022] The present invention utilizes cross-joint seam lithography to produce an overlay mark with zero relative position deviation as a reference, and then uses the joint layer lithography to align the zero layer. The overlay deviation can be measured to characterize the joint deviation, and the joint deviation can be compensated by compensating the overlay deviation. The method is simple and easy. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of zero layer lithography and waveguide layer lithography according to an embodiment of the present invention;

[0024] Figure 2 is a schematic diagram of photolithography splicing according to an embodiment of the present invention;

[0025] Figure 3 It is a schematic diagram of the overlay mark pattern in the embodiment of the present invention.

[0026] Reference numerals: 001 - zero layer, 011 - first zero - layer overlay mark, 012 - second zero - layer overlay mark, 013 - third zero - layer overlay mark, 014 - fourth zero - layer overlay mark, 021 - first alignment mark, 022 - second alignment mark, 101 - first waveguide, 102 - second waveguide, 111 - first waveguide to the first overlay mark of the zero layer, 112 - second waveguide to the first overlay mark of the zero layer, 113 - first waveguide to the second overlay mark of the zero layer, 114 - second waveguide to the second overlay mark of the zero layer, 201 - splicing seam, 211 - first alignment overlay mark, 212 - second alignment overlay mark, 213 - third alignment overlay mark, 214 - fourth alignment overlay mark. Detailed implementation manners

[0027] The following uses specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0028] Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the protection scope of the present invention.

[0029] For the splicing exposure of electrical chips, the requirement for splicing deviation is relatively low. In most cases, as long as the wires overlap each other to form a path, the chip can work normally. Different from the splicing of electrical chips, the carrier for transmitting information in optical chips is light. When performing splicing lithography, it is necessary to make the optical waveguides as aligned as possible to reduce the loss of optical signals. The waveguide width is generally in the range of several hundred nanometers, and the splicing deviation has a greater impact on the transmission loss.

[0030] In order to solve the above - mentioned technical problems, the following various embodiments of a method for detecting and compensating the splicing deviation in lithography of the present invention are proposed.

[0031] This embodiment provides a method for measuring and correcting the splicing deviation in lithography. Taking the splicing of optical waveguides as an example, specifically, the method includes the following steps:

[0032] Step 1: Add a zero layer in front of the waveguide layer, and the range of the zero layer needs to cover the splicing position of two lithography regions.

[0033] Specifically, the zero layer must contain the alignment marks at the position of the splicing seam. For each waveguide layer to be spliced, at least two sets of alignment marks are required, which are respectively placed at the upper and lower ends of the splicing seam, and each set contains two marks, which are placed on the left and right sides of the splicing seam. Refer to Figure 1 , such as Figure 1 shown in the schematic diagrams of the zero-layer photolithography and waveguide-layer photolithography of this embodiment. In the figure, there are two sets of alignment marks on the zero layer 001, and each set of alignment marks contains two zero-layer alignment marks. In the upper part of the zero layer 001, it includes the first zero-layer alignment mark 011 located on the left side and the second zero-layer alignment mark 012 located on the right side. In the lower part of the zero layer 001, it includes the third zero-layer alignment mark 013 located on the left side and the fourth zero-layer alignment mark 014 located on the right side. In addition, the first alignment mark 021 and the second alignment mark 022 are respectively engraved on the left and right layers of the zero layer 001. Since the accuracy of the mask is much greater than the lithography splicing accuracy, it can be considered that there is no deviation in the relative positions among the first zero-layer alignment mark 011, the second zero-layer alignment mark 012, the third zero-layer alignment mark 013, and the fourth zero-layer alignment mark 014.

[0034] It should be noted that if there is more than one waveguide layer, each waveguide layer should have two sets of alignment marks, and the requirements are the same as above.

[0035] Step 2: Align using the zero-layer alignment marks and fabricate the waveguide-layer photolithography. Refer to Figure 1 , Figure 1 which contains two waveguides to be spliced on the left and right. Two waveguide-layer photolithographies are fabricated on the first waveguide 101 located on the left side using the first alignment mark 021. The first waveguide 101 includes the first waveguide's first alignment mark with respect to the zero layer 111 and the first waveguide's second alignment mark with respect to the zero layer 113. Two waveguide-layer photolithographies are fabricated on the second waveguide 102 located on the right side using the second alignment mark 022. The second waveguide 102 includes the second waveguide's first alignment mark with respect to the zero layer 112 and the second waveguide's second alignment mark with respect to the zero layer 114.

[0036] Measure the lithography deviation between the waveguide layer and the zero layer using the alignment marks of the zero layer and the alignment marks of the waveguide layer. The calculation method is a commonly used technical means in the art and will not be elaborated here. As mentioned above, since there is no deviation in the relative positions among the first zero-layer alignment mark 011, the second zero-layer alignment mark 012, the third zero-layer alignment mark 013, and the fourth zero-layer alignment mark 014, therefore, the lithography deviations of the first waveguide's first alignment mark with respect to the zero layer 111, the first waveguide's second alignment mark with respect to the zero layer 113, the second waveguide's first alignment mark with respect to the zero layer 112, and the second waveguide's second alignment mark with respect to the zero layer 114 relative to the first zero-layer alignment mark 011, the second zero-layer alignment mark 012, the third zero-layer alignment mark 013, and the fourth zero-layer alignment mark 014 can characterize the splicing deviation.

[0037] It should be noted that the method for compensating overlay error is a conventional technical means in the art, and the detailed steps will not be elaborated here.

[0038] Step 3: Compensate the overlay error until the stitching error reaches an acceptable range. Refer to Figure 2 , such as Figure 2 shown is the schematic diagram of lithographic stitching in this embodiment. Figure 2 In [reference], the first waveguide 101 and the second waveguide 102 are stitched together by using the zero layer to form a waveguide layer. The zero layer 001 includes a stitching seam 201. The first waveguide's first overlay mark 111 on the zero layer, the first waveguide's second overlay mark 113 on the zero layer, the second waveguide's first overlay mark 112 on the zero layer, and the second waveguide's second overlay mark 114 on the zero layer respectively correspond to the first zero-layer overlay mark 011, the second zero-layer overlay mark 012, the third zero-layer overlay mark 013, and the fourth zero-layer overlay mark 014, jointly forming the first alignment overlay mark 211, the second alignment overlay mark 212, the third alignment overlay mark 213, and the fourth alignment overlay mark 214.

[0039] It should be noted that after the specific deviation value has been determined, the method for compensating overlay error is a conventional technical means in the art, and the detailed steps will not be elaborated here.

[0040] Refer to Figure 3 , such as Figure 3 shown is the schematic diagram of the overlay mark pattern, Figure 3 which shows a pattern of the alignment overlay mark. In addition to the overlay mark patterns exemplified in this embodiment, other patterns can also be used as overlay marks.

[0041] After completing the compensation for the stitching error, subsequent processes such as etching are carried out to form the waveguide layer.

[0042] This embodiment uses the method of cross-stitching-seam lithography to fabricate overlay marks with zero relative position deviation as a reference, then aligns the waveguide layer lithography with the zero layer, measures the overlay error to characterize the stitching error, and compensates the stitching error by compensating the overlay error. The testing method is simple and feasible.

[0043] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for detecting photolithography splicing deviation, characterized in that: The method comprises: Making a zero layer including an overlay mark with a relative position zero deviation in the joint seam area; The step of making a zero layer of an overlay mark including a relative position zero deviation in the splicing seam area specifically includes: In a manner of photolithography across the splicing seam, a zero layer is added before the splicing layer, wherein the range of the zero layer includes the splicing position of the two photolithography areas, and the zero layer includes the overlay mark and the alignment mark of the splicing seam position; The overlay marks include at least two groups, which are placed at both ends of the joint seam, and each group includes two marks, which are placed on both sides of the joint seam; The zero layer is aligned with the splicing layer to measure the overlay deviation.

2. The method for detecting photolithography splicing deviation according to claim 1, characterized in that: The method of aligning the zero layer with the splicing layer and measuring the overlay deviation specifically includes: Using the alignment mark to make a stitching layer lithography on the stitching layer; The size of the stitching deviation is characterized by the size of the overlay deviation of the stitching layer lithography to the zero layer, and the overlay deviation is calculated through the overlay mark.

3. A method for compensating photolithography splicing deviation, characterized in that: The method measures the photolithography stitching deviation by the method described in any one of claims 1 or 2, and the compensation method comprises: The overlay deviation is compensated to reduce the photolithography stitching deviation to within a preset deviation range threshold.

4. The method for compensating photolithography stitching deviation according to claim 3, characterized in that: The method further comprises: At least one group of overlay marks is added between the two groups of overlay marks on each splicing layer, and then deviation detection and compensation are performed.

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