Configurable distributed interlock system

Abstract

Various embodiments include methods and apparatus for providing personal safety and machine safety and operation. In an example, a distributed interlock system includes at least one master device coupled to a number of slave devices. The slave devices receive signals from one or more tools and provide the signals to the master device. The master device evaluates the signals and prevents the unsafe condition from being transmitted to the one or more slave devices prior to execution of one or more instructions related to the unsafe condition. Other methods and systems are also disclosed.

Description

This application is a divisional application of the invention patent application with application number 201980044489.3, application date May 6, 2019, and invention name “Configurable Distributed Interlocking System”. Priority claim

[0001] This application claims priority to U.S. Patent Application No. 62 / 667,865, filed on May 7, 2018, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The subject matter disclosed herein relates to control systems that provide operating signals and safety interlocks. More specifically, the subject matter disclosed herein relates to machine safety and personal safety around machine tools and tool-to-tool safety. Background Art

[0003] The current status of control systems is to use relay-based safety interlocks. The fastest commercially available interlock mechanism is the "EtherCAT Safety Protocol (Ethernet Control Automation Technology)" system. However, even with the "EtherCAT Safety Protocol" implementation, interlock evaluation will increase the delay of the input / output (I / O) cycle time, which makes the simultaneous implementation unusable for advanced machine tool applications.

[0004] Currently, the EtherCAT standard is an Ethernet-based fieldbus system. One type of system is available from Beckhoff Automation (Beckhoff Automation GmbH & Co. KG; Huelshorstweg 2033415 Verl Germany). The protocol of this system is standardized in the International Electrotechnical Commission (IEC) standard 61158 and is used for hard and soft real-time computing requirements in automation technology. Therefore, currently, tools in semiconductor manufacturing environments often have EtherCAT or other Ethernet-based control architecture connections built-in or added to the tool. However, the contemporaneous implementation of the EtherCAT standard and related technologies has not met all requirements for personal safety and proper tool operation.

[0005] The information described in this section is intended to provide those skilled in the art with the subject matter disclosed below and should not be considered as admitted prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A An example of a high-level overview of a control automation technology (CAT) control system with distributed interlocking (ITLK) system components according to various exemplary embodiments is shown;

[0007] Figure 1BAn example of another high-level overview of a CAT control system with distributed interlocking (ITLK) system components according to various exemplary embodiments is shown;

[0008] Figure 2 shows an example of a node package overview according to various exemplary embodiments;

[0009] Figure 3 An example of a high-level overview of a distributed interlocking system according to various exemplary embodiments is shown;

[0010] Figure 4A shows examples of system interlocks according to various exemplary embodiments;

[0011] Figure 4B shows an example of a system interlock according to various exemplary embodiments that references output actual value feedback compared to output desired values;

[0012] Figure 4C shows another example of a system interlock according to various exemplary embodiments;

[0013] Figure 5 shows examples of deterministic latency and synchronous input and output according to various exemplary embodiments;

[0014] Fig. 6A shows examples of inhibitory interlocks according to various exemplary embodiments;

[0015] Figure 6B shows examples of preventive interlocks according to various exemplary embodiments;

[0016] Figure 7 shows an example of dual redundancy of a distributed interlocking system according to various exemplary embodiments;

[0017] Figure 8 An example of a distributed interlocking system with firmware separated from interlocking equations is shown according to various exemplary embodiments;

[0018] Fig. 9 shows an example of a system architecture for daisy-chaining communications between multiple master devices according to various exemplary embodiments;

[0019] Fig.10 shows a three-dimensional view of an exemplary embodiment of a gas delivery cartridge having several gas delivery channels mounted therein and utilizing various embodiments of the disclosed subject matter;

[0020] Fig.11Ashows a three-dimensional view of an exemplary embodiment of a gas delivery box having external EtherCAT node connections to various gas delivery components within the gas delivery box;

[0021] Fig. 11B Shows Fig.11A Another three-dimensional view of an exemplary embodiment of a gas delivery box having another view of various gas delivery components within the gas delivery box;

[0022] Fig. 11C Shows the Fig.11A An exemplary embodiment of a portion of an EtherCAT connector for system communication;

[0023] Fig.11D Shows the Fig.11A an exemplary embodiment of another portion of an EtherCAT connector for system communications; and

[0024] Fig.12 A simplified block diagram of a machine in the example form of a computer system is shown within which a set of instructions may be executed to cause the machine to perform any one or more of the methods and operations set forth herein. DETAILED DESCRIPTION

[0025] Reference will now be made to some generalized and specific embodiments shown in the various drawings to describe the disclosed subject matter in detail. In the following description, many specific details are set forth to provide a thorough understanding of the disclosed subject matter. However, it will be apparent to those skilled in the art that the disclosed subject matter may be implemented without some or all of these specific details. In other cases, well-known process steps or structures are no longer described in detail to avoid obscuring the disclosed subject matter. Specific terms of abbreviations and acronyms used in this article include:

[0026] ASIC: Application-Specific Integrated Circuit;

[0027] CAT: Control Automation Technology:

[0028] DI: digital input;

[0029] DO: expected digital output for driving;

[0030] EtherCAT: Ethernet control automation technology;

[0031] FPGA: Field Programmable Gate Array;

[0032] ITLK: Interlock:

[0033] EtherCAT: a specific exemplary embodiment of a hardware platform that can operate EtherCAT protocol software and / or firmware and complies with the EtherCAT standard developed under the IEEE 802 standard;

[0034] RS-485: The well-known serial communication protocol (also known as the Telecommunications Industry Association standard TIA-485 and the Electronic Industries Alliance standard EIA-485) is a standard that defines the electrical characteristics of drivers and receivers for serial communication systems, which are shown here primarily for ease of understanding. After reading and understanding the disclosure provided herein, those skilled in the art will recognize that other types of communication protocols may also be used;

[0035] SBC: Single Board Computer;

[0036] SO: Expected output:

[0037] SI: actual value of the output (readback of SO); and

[0038] Type 5: An example of an interface converter card type. However, those skilled in the art will recognize that other types of adapter cards may be easily substituted upon reading and understanding the disclosure provided herein.

[0039] The disclosed subject matter supports distributed interlocks that are safety certified according to the TEC 61508 standard. The distributed interlock system disclosed herein enables any DI and any DO in the entire system to be used for interlock calculations. For example, an overtemperature OK DI from the bottom of the module can be used to enable heater power on the top of the module for different nodes. This is done without sending DIOs between nodes. In addition, preventive interlocks can evaluate interlock conditions and prevent unsafe conditions before instructions are executed. Interlocks are, for example, firmware configurable, which enables any or all equations to be updated without redesigning, for example, printed circuit boards (PCBs) and / or cables, and without hardware recertification.

[0040] In various exemplary embodiments, the distributed interlocking system disclosed herein evaluates the interlocking equations substantially in real time through a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) or other controller or processor type or other components known in the art, the system is configured as a master-slave configuration (or multiple interconnected hosts, at least some of the multiple hosts have their own set of slave devices) and is performed in a cycle time as short as an EtherCAT trunk. Therefore, the distributed interlocking system is active, not passive, and the system operates without adding delays to the I / O execution cycle.

[0041] Therefore, the distributed interlocking system disclosed herein allows for system-wide distributed interlocking, which is actively and substantially evaluated in real time. In various embodiments, the interlocking equations can be firmware configurable, thereby eliminating traditional hardware changes and associated safety recertification. Therefore, the disclosed distributed interlocking system can significantly shorten development cycle time and reduce costs.

[0042] The disclosed subject matter contained herein is generally related to the operation of "tools" in a semiconductor manufacturing environment (a wafer fab). These tools may include various types of deposition (including plasma-based tools such as ALD (atomic layer deposition), CVD (chemical vapor deposition), PECVD (plasma enhanced CVD), etc.) and etching tools (e.g., reactive ion etching (RIE) tools), as well as various types of thermal furnaces (e.g., rapid thermal annealing and oxidation), ion implantation, and various other process and metrology tools found in various wafer fabs and known to those skilled in the art. In addition, various embodiments disclosed herein are beneficial to certain tool components, such as gas delivery boxes that supply various gases (including toxic and / or corrosive gases) to the tools. However, the disclosed subject matter is not limited to semiconductor environments and can be used in many machine tool environments, such as robotic components, manufacturing and processing environments.

[0043] Therefore, all tools in a wafer fab have one or more safety features and / or requirements due to the potential threat to personal safety or machine safety and operability. For example, interlock systems and various types of sensors are built into the tools or can be added to various tools. In one example, a person skilled in the art knows that the RF generator on a plasma tool should be locked when maintenance is performed on the RF generator. In other examples, a technician recognizes that if two or more gases of certain types are combined, they may burn or have other types of hazardous interactions. As described above, the simultaneous implementation of the EtherCAT standard and related technologies cannot meet all requirements for personal safety and proper tool operation.

[0044] For example, a distributed interlock system may reference a query table to determine whether there are any specific sequence combinations in a single tool or tool-to-tool that may be particularly hazardous to personal safety or machine safety and operation. In a specific example, those skilled in the art know that silane (SiH4) is an inorganic, colorless, gaseous compound of silicon and hydrogen that has strong reducing properties and is self-igniting in air. Therefore, if oxygen and silane are mixed, they may ignite or explode. By placing such chemical reactions into a query table, the disclosed subject matter can prevent valves that control the flow of these gases from combining with these gases. Therefore, such chemical reactions can be prevented from occurring, rather than just reacting to a potentially catastrophic situation that has already occurred. This "preventive" interlock operation will be described in more detail below.

[0045] As disclosed herein, the disclosed subject matter can be configured to provide interlocks on all input / output (I / O) ports on a tool. Additionally, as described above, the disclosed subject matter can be preventative - to prevent certain interactions and operations from occurring, rather than shutting down a tool or I / O port only after an operation has occurred. Thus, the disclosed subject matter can interlock software signals with hardware signals.

[0046] In order to facilitate understanding of the disclosed subject matter, various examples will be provided with reference to a semiconductor manufacturing environment. However, after reading and understanding the disclosure provided herein, those skilled in the art will recognize that the distributed interlock system of the present disclosure can be used in various environments using various types of tools or other machines.

[0047] Reference now Figure 1A , which shows a high-level overview example of a control automation technology (CAT) control system 100 with distributed interlocking (ITLK) system components according to various exemplary embodiments. Figure 1A Shown are a master device 101 , a number of slave nodes 105A to 105C (which may comprise, for example, a tool or a portion of a tool, such as a gas delivery box, or individual components within a tool), and an interlock host 111 . Figure 1A Three slave nodes are shown for illustration purposes. However, the number of slave nodes may be less (eg, as little as one) or more.

[0048] In an exemplary embodiment, the master device 101 may be a single board computer (SBC). The master device 101 may directly receive input from and provide output to one or more slave nodes 105A to 105C. In various embodiments, one or more slave nodes 105A to 105C may provide input to or receive output from the sequencer 103. The sequencer 103 is shown as being included as part of the master device 101, but in other embodiments, the sequencer 103 may be a stand-alone device (not shown). In an embodiment, one or more of the slave nodes 105A to 105C may provide input directly to the master device and / or sequencer 103, or receive output from it.

[0049] In various embodiments, the sequencer 103 may be a firmware or software component. The sequencer may "run" on a host device or in a standalone device. In an embodiment, the sequencer may be a hardware device implemented, for example, in one or more field programmable gate arrays (FPGAs) or in one or more application specific integrated circuits (ASICs), or other controller or processor type components known in the art.

[0050] Sequencer 103 may be used to analyze sequences of events, for example, within a tool or across various tools (e.g., in tool-to-tool interactions). For example, these interactions may include tracking inputs and when they were initiated (e.g., with reference to time or with reference to another event), and tracking when output responses occurred (e.g., with reference to time or with reference to another event).

[0051] Each of the slave nodes 105A to 105C is shown to include an interface conversion card 107 and an interlock (ITLK) slave device 109. Figure 1A As shown, the interface conversion card 107 is shown as a type 5 device known in the art. However, those skilled in the art will recognize that other types of interface cards can be easily substituted after reading and understanding the disclosure provided herein. The ITLK slave device 109 receives the input signal DI and provides an actual output signal SI. The actual output signal SI is the actual value of the output signal, which is a readback of the output signal SO.

[0052] As shown, each slave node 105A to 105C is coupled to an interlocking master 111. In various embodiments, the interlocking master 111 can be configured according to RS-485 or related standards. However, the interlocking master 111 is not required to operate RS-485 or related standards.

[0053] In general, the CAT control system 100 with distributed interlocking (ITLK) system components provides a full system interface with DI / DO interlocking, as described in more detail below.

[0054] Figure 1B An example of another high-level overview of a CAT control system 130 having distributed interlocking (ITLK) system components according to various exemplary embodiments is shown. In this embodiment, the sequencer is arranged to intercept all input signals from slave nodes 105A to 105C and all output signals to slave nodes 105A to 105C. In addition, Figure 1B Two ITLK slaves are shown in slave node 105A: output ITLK slave 113A and input ITLK slave 113B. Figure 1B As shown, the output ITLK slave device 113A provides the actual output signal SI. As described above with reference to the ITLK slave device 109, the actual output signal SI is the actual value of the output signal, which is the readback of the output signal SO. In addition, as shown, the ITLK slave device 113B receives the input signal DI.

[0055] In various embodiments, Figure 1A and 1B The system provides an interlock master module and an interlock equation solver for centralized interlock calculations. All interlock equations may be contained in, for example, the master device 101, the interlock host 111, or a combination of the two, but the present invention is not limited to these devices. In one embodiment, each ITLK slave device 109, 113A, 113B is a remote I / O device. In a specific exemplary embodiment, the ITLK slave device 109, 113A, 113B can manage 64 DIs and 64 DOs or more / device, can be daisy-chained with one or more other devices in the ITLK slave devices 109, 113A, 113B (each with expandable I / O), and can include the same hardware and firmware to achieve interchangeability, and each output can maintain a current of 500mA or more.

[0056] Available Figure 1A CAT control system 100 with distributed interlocking (ITLK) system components and Figure 1B Various combinations of CAT control systems 130. The high-level overview only provides an overview of two possible system architectures. More details of the CAT control system are described below.

[0057] Figure 2 An example of a node package overview 200 (eg, a node module) is shown according to various exemplary embodiments. Figure 2 The figure shows a connector board 201, which has an interface conversion card 203, a first DIO ITLK board 205 and a second DIO ITLK board 207. The interface conversion card 203 can be connected to Figure 1A and 1BEach of the first DIO ITLK board 205 and the second DIO ITLK board 207 may be similar to Figure 1A and 1B The ITLK slave device 109.

[0058] like Figure 2 In the specific exemplary embodiment depicted, the interface conversion card 203 can be a Type 5 device known in the art. However, those skilled in the art will know after reading and understanding the disclosure provided herein that other types of interface cards can also be easily substituted. The interface conversion card 203 is coupled to the first DIO ITLK board 205, which is in turn coupled to the second DIO ITLK board 207, through, for example, a serial peripheral interface (SPI) communication channel. In this embodiment, the interface conversion card 203 is also coupled to an EtherCAT connection and is presented as receiving up to 32 analog inputs (AI) and sending up to 32 analog outputs (AO). However, the number of AI and AO channels is illustrative only and is not limited to 32 AI and 32 AO.

[0059] like Figure 2 In the specific exemplary embodiment depicted, each of the first DIO ITLK board 205 and the second DIO ITLK board 207 can have up to 64 digital inputs (DI) and 64 digital outputs (DO) per board, which can be further expanded through daisy chaining. However, the number of DI and DO channels is only illustrative and is not limited to 64 DI and 64 DO.

[0060] In addition, as shown, each of the first DIO ITLK board 205 and the second DIO ITLK board 207 is coupled to, for example, an RS-485 interface. Figure 1A or 1B interlock host. Although not explicitly shown, additional DIOITLK boards may also be included. Each of the first DIO ITLK board and the second DIO ITLK board 207 can sustain 500mA or more per output. In a specific exemplary embodiment, each of the first DIO ITLK board 205 and the second DIO ITLK board 207 can sustain a load of 7A or more and can be configured to prevent input protection and output protection from short circuits to ground, and further protect to -15V and to +24V. These voltage and current ratings are for illustration only and are not limited to the values ​​shown.

[0061] Based on the description provided herein, and as described in more detail below, the distributed interlocking system of the disclosed subject matter provides at least the following interactions and safety features: (1) Preventive system interlocks that: Not limited by the node’s local DI / DO; and Ability to interlock drive output intent; (2) Flexibility - any DO in the system can be interlocked with any DI or DO; (3) Configurability - interlocking equations can be easily and conveniently changed: (4) Predictability - the system has a deterministic interlock response time: (5) Safety - the system's safety integrity level is 3 (compliant with SIL3), as defined by the IEC 61508 standard and is a dual-redundant system; and (6) Visibility - The system can be easily integrated with a graphical user interface (GUI), for example, with a diagnostic utility for startup operation and troubleshooting. A representative GUI is described in more detail below.

[0062] In a specific exemplary embodiment, the GUI can display various items, such as the operating status of each node in the system; the DI and DO status of each component in the system; the relationship between the expected interlock output and the actual interlock output; and the AI ​​and AO status of various components in the system. The exemplary GUI can be used to switch DO and set AO; plot and analyze, for example, AIO, DIO, and SIO waveforms; and upload and download all or selected portions of the object status on EtherCAT.

[0063] The exemplary GUI may also provide an "EtherCAT view" that shows, for example, the SIO and the SIO user interface. The EtherCAT view may be configured to provide, for example, diagnostics and troubleshooting during a startup event ("bringup") or when an error occurs. The EtherCAT view may also be configured to report the status of each DIO and SIO in the system, DOs may be commanded "on" or "off", and SO SI mismatches may be highlighted and / or color coded to indicate which type of mismatch has occurred.

[0064] In addition, the EtherCAT view can be configured to provide a drawing tool that can track, draw and save any signal waveform in the system. The drawing tool is used to analyze the sequence to, for example, track the input and when the input began, and track when the related output response occurred. The various types of GUIs and EtherCAT views each use tools known and understood by those skilled in the art.

[0065] The distributed interlocking system of the disclosed subject matter also provides certain features and functions, as described above and in more detail below, which in certain specific exemplary embodiments include at least the following: (1) Dual redundant system that can utilize pre-certified hardware; (2) Serial communication systems, such as RS-485, between a host (or multiple hosts) and one or more slaves in a communication protocol; (3) preventive interlocking, which can also achieve the purpose of interlocking to drive output; (4) Deterministic interlock delay time less than, for example, 1 msec, which is independent of several interlock equations; (5) Synchronous input sampling and output driving; and (6) Interlock instruction capacity up to 5,000 or more.

[0066] Reference Figure 3 , according to various exemplary embodiments, an example of a high-level overview of a distributed interlocking system 300 is shown. The high-level overview of the distributed interlocking system 300 is merely an illustrative example to provide a generalized theory of operation, and is shown as including a motherboard 301 and a plurality of daughterboards 303A to 303C, which are arranged in a master / slave architecture. Although only three daughterboards are shown, the distributed interlocking system 300 is not limited to three. More or fewer daughterboards may be used.

[0067] The master device (here, motherboard 301) includes a centralized interlocking equation solver. All interlocking equations may be stored, for example, on a non-volatile memory device (e.g., a flash memory device) within motherboard 301. The motherboard 301 may be connected to Figure 1A and 1B The main device 101 is the same or similar.

[0068] Each slave device (here, daughter boards 303A to 303C) may be similar or identical to each other. Figure 1A and 1B The ITLK slave devices 109 of the motherboard 301 are the same or similar. In an embodiment, each of the daughter boards 303A to 303C can be identified by a unique identification (ID) provided by, for example, a connector board to uniquely address a specific one of the daughter boards 303A to 303C. Each daughter board 303A to 303C as a slave device can synchronously sample the received input and send the received input to the motherboard 301 as a master device. In addition, each daughter board 303A to 303C can synchronously drive the output based on the result or direction received from the motherboard 301.

[0069] Figure 4A An example of a system interlock 400 is shown in accordance with various exemplary embodiments. Figure 4A The diagram shows a master device 401 and several slave devices 403A to 403C. Each of the master device 401 and the slave devices 403A to 403C may be the same or similar to other master devices and slave devices identified herein, such as Figure 1A and 1BThe master device 101 and ITLK slave nodes 105A to 105C. In the example of system interlock 400, any DO in the system can be interlocked via any combination of DO and DI.

[0070] For example, continue to refer to Figure 4A , a logic example (E0 SO 32 = (E0 DI0) & (E1 DI14) & (E2 DI 66)) is provided by the master device 401, which sends and receives data from three slave devices 403A to 403C (in Figure 4A In various embodiments, all three slave devices 403A to 403C are linked (eg, via one or more field connection panels on each tool) and controlled by the distributed interlocking system disclosed herein.

[0071] Figure 4B An example of a system interlock 430 is shown according to various exemplary embodiments, which references output actual value feedback compared to output desired value. Figure 4B In , the expected digital output from the master device is transmitted to the board on the tool to drive a specific operation (e.g., DO is an input transmitted to the tool). The safety output (the expected value at the output) is monitored and fed back as the actual value of the output (i.e., the readback of SO). If the two values ​​are not the same or are not within a certain predetermined tolerance for a given operation or tool, for example, the distributed interlock system disclosed herein can revert to a safe mode based on the requirements of the given operation and / or tool. The distributed interlock system can consider and act on multiple inputs (e.g., thousands or more), such as DO signals from other software and / or hardware, to ensure that all software and hardware provide safe operation.

[0072] Figure 4C Another example of a system interlock 450 is shown in accordance with various exemplary embodiments. Figure 4C Shown as including a master device 401 and three slave devices 403A to 403B. In this logic example, (E0 SO 32 = (E0 DI 0) & (E1 DI 14) & (E2 DI 66)) is provided by the master device 401, which sends and receives signals from the three slave devices 403A to 403C. In another logic example, E1 SO 44 = (E0 SO 32) as understood by those skilled in the art.

[0073] Figure 5Shown are examples of deterministic latency and synchronous input and output according to various exemplary embodiments for master-slave architecture 500, and related graphics showing the SIOP measurement start and end points of each of E0, E1 and E2. In a specific exemplary embodiment, regardless of the number of interlocking equations and / or commands and / or operations involved, the deterministic response time can be updated every 1 millisecond (msec) or less. Therefore, in this embodiment, the response time (e.g., the time required for something to the time acting on something) is less than 1 millisecond. In the case of a semiconductor wafer plant, the synchronous output can drive all nodes in the wafer plant and / or in a sub-manufacturing (or production line) to issue instructions at the same time. The synchronous output driving all nodes (e.g., box to box) can have, for example, a maximum output-output jitter of about 100 nanoseconds (nsec).

[0074] According to various exemplary embodiments, Fig. 6A shows an example of inhibitory interlocking, while Figure 6B An example of a preventive interlock is shown. As described herein, the disclosed distributed interlock system has both inhibitory interlocks and preventive interlocks, whereas the prior art systems do not have preventive interlocks. For example, Fig. 6A As shown, the inhibiting system allows both valves to open almost simultaneously for 520 μsec before closing. Figure 6B The preventive system (which is part of the distributed interlock system disclosed herein) prevents either gas valve from opening even if the two valves are commanded to open by DO1 and DO2, respectively. The preventive interlock portion of the distributed interlock system may incorporate, for example, various types of lookup tables, as described above, to prevent the valve from opening even if a command-to-open signal is sent.

[0075] Therefore, if Fig. 6A and 6B As shown, the interlock system has the ability to interlock the intention to actuate an output, where the output is based on the state of the input and the intention to actuate the output. The system can therefore prevent the system from actuating outputs that cannot be activated simultaneously (e.g., as in the example provided above in conjunction with oxygen and silane, which may ignite or explode) based on equipment safety and / or personal safety considerations.

[0076] continue Fig. 6A For example, assume that D01 and D02 are the expected input signals. Further assume that S01 and S02 are the output signals after the relay is interlocked. When the D01 and D02 signals are set to "1" at the same time, the interlock output signals S01 and S02 present a glitch of 520 μsec due to the relay time when the relay is closed.

[0077] Figure 7An example of dual redundancy 700 of a distributed interlocking system according to various exemplary embodiments is shown. The distributed interlocking system can be configured to have at least dual redundancy, for example, two FPGAs on each board (on the master device and all slave devices) to perform the same task. The FPGA is illustrative only and can be replaced or supplemented by one or more other devices discussed herein (e.g., one or more ΔSICs).

[0078] like Figure 7 As shown, the interlocking host 701 has a first redundant module A; and a second redundant module B. The first LTLK slave device 703A and the second ITLK slave device 703B are each shown to include a first redundant module A; and a second redundant module B (respectively, element symbols 705A, 705B, 705C and 705D). As described above, each module may include various hardware devices (e.g., FPGA, ASIC, processor, etc.), firmware devices (e.g., electronic devices that can be programmed to execute certain codes), or software devices that control certain physical devices and related input signals and output signals. Programmability considerations are discussed in more detail below.

[0079] In one embodiment, each redundant device on each board can be programmed to perform the same task. For example, if the first redundant module A fails, the second redundant module B automatically takes over the task of the first redundant module.

[0080] In another embodiment, the first redundant module A drives the output signal and the output device. Another redundant module reads back the output signal and compares it with its own result, and turns off the output signal if there is a mismatch within a predetermined limit. In some examples, the predetermined limit can be zero.

[0081] In this embodiment, all management and control equations (plus any lookup tables) can be performed on the interlock master 701. In this example, the first ITLK slave 703A (part "A") performs the actual "actuation", such as switching a valve, while the first ITLK slave 703B (part "B") performs the signal readback and clearly marks any differences (within predetermined limits) to enable the slave and associated tool to be placed back into a safe state as described above. Therefore, in this embodiment, the distributed interlock system includes "communication" between "A" and "B" to verify instructions and other I / O signals.

[0082] With respect to programmability of, for example, an FPGA, some considerations in specific exemplary embodiments include: (1) Separating interlocking equations from FPGA firmware (FW) a.FPGA FW i.FPGA FW can be configured into various functions of the operating system: and ii.FPGA FW can be pre-certified and does not necessarily need to be changed when changing equations. Therefore, re-certification is not required. b. Interlocking equations: i. The interlocking equations are specific to the use case of the system; ii. The interlock equations can be changed without redoing the FPGA FW certification: and iii. Still use the tool for safe re-certification. (2) Programmability can be designed for IEC 61508 certification.

[0083] Figure 8 An example of a distributed interlocking system with firmware and interlocking equations separated is shown according to various exemplary embodiments. Figure 8 The interlock master unit 801 is shown as including an interlock master unit. The interlock master unit 801 may be the same or similar to other master devices in the master devices described herein. The interlock master unit 801 includes a first FPGA 803A and a second FPGA 803B. The first FPGA 803A and the second FPGA 803B are each coupled to a non-volatile memory device 807A, 807B and a firmware device 805A, 805B, respectively.

[0084] The non-volatile memory devices 807A, 807B may be any non-volatile memory device described herein and known in the art, such as flash memory devices, conductive bridge random access memory (CBRAM), programmable metallization cells (PMC), phase change memory (PCM), and other non-volatile memory device types known in the art. Devices configured to be programmed as firmware devices are known in the art (e.g., devices configured to receive firmware and firmware updates are semiconductor chips or integrated circuits).

[0085] In a specific exemplary embodiment, the FW component is stored in firmware devices 805A and 805B and can be programmed by its own header. For FPGA 803A and 803B respectively, firmware devices 805A and 805B may include a single firmware device with two files or two separate firmware devices with one file each. The FW files on each of firmware devices 805A and 805B may be the same, but stored in different addresses. Interlock equations are stored in non-volatile memory devices 807A and 807B. Interfaces such as SPI communication channels can couple non-volatile memory devices 807A and 807B to corresponding FPGA 803A and 803B. Regardless of the specific configuration mode, the content of non-volatile memory devices 807A and 807B does not affect the function FW stored in corresponding firmware devices 805A and 805B.

[0086] In such Figure 8 In the example shown where the interlock equations are separate from the firmware, the application specific code (e.g., multi-purpose code) of the controlled or controllable tool (e.g., semiconductor processing tool such as ALD, CVD, PECVD, PVD, etc., or components located thereon or therein) can be changed by the end user. Thus, this variability is a programmable aspect. However, the functional code (e.g., A drive and B readback as described above) is generally not configurable by the end user to prevent unexpected results; unexpected results could potentially eliminate some or all of the safety functions of the distributed interlock system as described herein.

[0087] Fig. 9 An example of a system architecture 900 for daisy-chain communication between multiple master devices is shown according to various exemplary embodiments. The system architecture 900 can be used with any other system described herein.

[0088] Fig. 9 Shown include several master devices 903A, 903B, 903C (master device is also indicated as M0, M1 and M2 on the figure). Three master devices are presented based on illustrative purposes, and more or less master devices can also be used. Each master device 903A, 903B, 903C includes master-slave communication part 901A, 901B, 901C and master-master communication part 905A, 905B, 905C respectively. Each communication part can be based on RS-485 communication protocol or other wired or wireless protocols and technologies known in the art. For example, Ethernet communication can be used between master devices. In specific exemplary embodiments, master device can be in online topology (linetopology) with 100Mbps (or higher) full-duplex communication. In addition, there may be intermediate network device or network configuration to be located between one or more master devices 903A, 903B, 903C. As with any host device or system described herein, the system can be configured to calculate any ITLK devices and potential delays, such as delays due to process tolerances or noise and / or jitter signals. Such delays can avoid false trips or false alarms in the system.

[0089] For purposes of illustration, a master device 903A is shown in electrical communication with a plurality of slave devices 907A (the slave devices are also labeled E0, E1, E2, and E3 in the figure). Each slave device 907A may be an ITLK slave device located on, for example, a single tool, or may be a slave device physically distributed across a number of tools (including all tools located in one or more production lines). Four slave devices are shown for purposes of illustration, but more or fewer slave devices may be used. In addition, each of the master devices 903A, 903B, 903C may be coupled to a plurality of slave devices (not shown) so as not to obscure the disclosed subject matter.

[0090] For shared IO operations between different ones of the master devices 903A, 903B, 903C in the exemplary embodiment: (1) Any DI, DO on any node can be shared with any master device (for example, any DIO on any master device can be interlocked with any other DIO on any other master device); (2) Shared IO (XIO) transfers in excess of 1 Gbps Ethernet over various types of communications, such as through Reduced Media Independent Interface (RMII), Gigabit Media Independent Interface (GMII), Reduced Gigabit Media Independent Interface (RGMII), Serial Gigabit Media Independent Interface (SGMII), Quad Serial Gigabit Media Independent Interface (QSGMII), XGMII, and others; all in full duplex; (3) The firmware can have a shared reflective memory space on each host device; a. Each master device allocates memory space for XIO; b. Update XIO memory data for each interlocked calculation cycle; and c. After all master data are exchanged, all XIO memories may contain the same content; (4) Each master device "knows" its position in the chain and can read the link status of the physical layer (PHY); (5) Each master device may have a unique ITLK table that describes, for example, which and how many slave devices will be coupled to the master device, and describes the SO logic local to each master device (e.g., DIO from any slave device may be used); and (6) Each master device knows when to add or remove based on the TTLK table - there is no set connection order.

[0091] In various exemplary embodiments, detailed reflective memory transfers may include: (1) Reflective memory update, which is initiated once per interlock calculation cycle; (2) updates can be initiated by, for example, the first and final master in a chain after receiving the latest slave data; and (3) The data is forwarded down the chain until all data has been received.

[0092] As with other system embodiments described herein, each interlock host may run functional firmware (or its hardware equivalent). Each interlock host also runs application firmware (interlock logic firmware). Functional firmware refers to the code that runs the system, such as, for example, serial communications, system monitoring, and other functions. Application firmware refers to the interlock logic programmed into the unit written by the end user. Examples of firmware are also described herein in other parts of the present invention.

[0093] In an embodiment, the application firmware may be automatically generated by a software parser. The software parser translates a human-readable interlock logic table (e.g., from a spreadsheet) into multiple hexadecimal files; one hexadecimal file for each host used in the system as declared in the spreadsheet. These generated files are unique to each other and assign a media access control (MAC) address to the master device, which is programmed on the master device. The generated files also declare which other MACs are in the system.

[0094] Using the MAC, each master knows exactly which other masters it should receive information from. In a specific exemplary embodiment, any communication with a master that is not declared in the interlock table may be considered unsafe. Thus, if master "A" detects that it is connected to master "B" which is not allowed on the system, master "A" will consider input from master "B" to be unsafe. This type of arrangement can also be applied to connecting two identical masters together.

[0095] In various embodiments, any conflict caused between master devices can be considered an unsafe condition, and all communications between these master devices can then be considered unsafe. The master devices can then react by discarding unsafe data to always ensure that the system fails safely. Interlock system for use with gas delivery boxes

[0096] In this exemplary embodiment, a component of an interlock system is described that can be used with various types of gas delivery boxes. Gas delivery boxes (or gas panels) are used in semiconductor manufacturing equipment to deliver multiple gases to, for example, a vacuum processing chamber to deposit or etch films on a substrate. These gas delivery boxes include multiple gas mass flow controllers (MFCs), with one or more MFCs for each gas type. The MFCs and related components of the MFCs, such as valves, regulators, filters, and similar types of gas delivery components, are typically mounted on a "gas stick" and coupled together. Typically, many gas sticks (e.g., three to thirty or more) are used to provide gas to, for example, a processing chamber of a semiconductor processing tool. Different gases, flows, and pressures can be used for each operation on the processing tool.

[0097] Since most, if not all, gas delivery boxes deliver hazardous or toxic gases, the interlock system used with the gas delivery box must prevent or minimize possible threats to personal safety or machine safety and operability. In various embodiments, the interlock system can be connected to various types of safety systems, such as the EtherCAT controller discussed above.

[0098] In contemporary systems currently used in the semiconductor and related industries, the prior art is a gas delivery box with multiple analog line connections on a multi-pin connector, such as one or more "D-type" connectors. The D-type connector has a number of cables connected to a central input / output controller (IOC) to send, for example, analog signals to or from gas components such as an MFC device, and to provide power to the MFC. In addition, additional analog signals are sent to and received from additional gas flow components, such as pressure sensors and switches, digital control signals are sent to and received from pneumatic solenoids, and IOC signals communicate with the system controller. Power is currently also provided to these and other components through the D-type connector.

[0099] As mentioned above, interlocks are required to ensure that combinations of valve openings that could create hazardous conditions for machinery and / or personnel safety are minimized or prevented. These interlocks are typically hardware based, such as using jumper wires or specially designed interlocking printed circuit board assemblies.

[0100] In one example, vacuum semiconductor manufacturing equipment uses multiple gases delivered to a process chamber to coat a film onto a substrate and / or remove a film from a substrate. The gas flow is controlled by an MFC. Solenoid-type pneumatic valves are used to open or close various gas paths to the chamber to control the gas mixture within the process chamber. The subject matter disclosed in this section is a gas delivery box or gas delivery panel having an integrated controller that communicates with a system controller via, for example, an EtherCAT interface.

[0101] For interlocking, the gas delivery box integrated EtherCAT controller can be a slave to the interlock master that must be connected to make the gas box operate. The interlock master can perform interlock functions when connected to a module or system or 1:1 test interlock master.

[0102] The test interlock host allows the gas delivery box to be tested. When the gas delivery box is first set up, it must be tested. The 1:1 test interlock host always triggers the SO corresponding to the DO without any interlock. For example, on the tool, valve "A" can be silane and valve "B" can be O2. The interlock host on the tool prevents "A" from being opened at the same time as "B". Therefore, the test interlock host allows all functions of the gas delivery box to be verified. In order to verify the function, the use of the test interlock host enables each valve to be cycled to ensure the operation of each valve. The slave machine requires the host input to operate, therefore, for testing purposes, the 1:1 test interlock host allows the freedom to operate any valve at any time, because there will be no safety issues during the test phase. Therefore, any or all combinations of valve actuation can be tested and verified.

[0103] The gas delivery box or gas panel can be controlled via a single EtherCAT interface. The single EtherCAT interface greatly simplifies the setup and testing of the gas delivery box. In various embodiments, the gas delivery box can be configured and tested via an EtherCAT connection, thereby reducing the required test equipment and the cable arrangement and separation of the interface box that is problematic in the prior art. Therefore, the disclosed subject matter enables easy integration into any gas delivery box, such as typically coupled to a semiconductor processing tool, and can be pre-configured and tested, making the disclosed subject matter "plug and play". The plug-and-play configuration enables simple integration at the end user site, thereby improving the in-transit merger (MIT) process. As is well known in the art, MIT is a process in which each subsystem is shipped separately to the end user's site and then integrated to form a complete system at the end user site. The disclosed subject matter also further improves the integration-to-order (ITO) process.

[0104] As described in detail herein, the EtherCAT (or similar) controller is part of the "hard structure" (various gas flow components, such as MFCs, valves, etc. of the gas delivery box), which means that once the gas flow path and gas flow components are configured, the EtherCAT controller can be quickly configured and the entire gas delivery box can be tested through the EtherCAT interface. The EtherCAT controller and other gas delivery box components can be pre-stored in the integration location without knowing which gas delivery box will need to be integrated. Having the gas delivery box pre-set at the integration location can shorten the lead time of the gas delivery box from, for example, about 8 to 10 weeks to about 1 to 2 weeks. The significantly shortened lead time saves costs accordingly, while providing a quick solution for end users of semiconductor manufacturing and related equipment.

[0105] Reference now Fig.10, a three-dimensional view 1000 of an exemplary embodiment of a gas delivery box 1005 is shown, which has several gas delivery channels installed therein and uses various embodiments of the disclosed subject matter. The gas delivery box 1005 can be configured to accommodate several gas delivery channels to supply gas to one or more equipment gas inlet supply pipelines, such as various types of plasma etching and deposition equipment used in semiconductor and related industries. For example, in various embodiments, the gas delivery box 1005 can be configured with less than 10 channels, 10 to 20 channels, or more than 20 channels, each of which can be coupled to various gas supply sources, such as various precursor gases. The gas delivery box 1005 includes a backing plate 1001, as is known in the art, and various components of the disclosed subject matter can be fixed to the backing plate 1001 (e.g., threaded or otherwise physically or chemically connected or bonded). The gas delivery box 1005 is shown as including a plurality of gas component channels 1003 (e.g., "gas sticks"), which are provided with gas delivery components (e.g., valves, mass flow controllers, pressure sensors, pressure regulators, etc.).

[0106] The back plate 1001 of the gas delivery box 1005 is also shown as including many other components. The back plate 1001, housing, printed circuit board, wires, pneumatic bank and other components discussed herein (not necessarily all components are shown) are all known in the art.

[0107] Fig.11A A three-dimensional view 1100 of an exemplary embodiment of a gas delivery box 1005 is shown, which has an external EtherCAT node connection 1150 connected to various gas delivery components within the gas delivery box 1005. The three-dimensional view 1100 is also shown to include a number of MFCs 1111 and a number of gas delivery components 1113 (e.g., lockout / tagout (LOTO) valves, pressure regulators, gas filters, two-port valves, three-port valves, etc.). Each of the several MFCs is electrically coupled via an MFC communication line 1109.

[0108] The external EtherCAT node connection 1150 is shown to include an EtherCAT connector area 1103 for communication between components within the gas delivery box 1005 and a remote controller (not shown), allowing access to several communication components within the gas delivery box (hereinafter referred to as Fig. 11B The access port 1101 and the interlocking main connector area 1170 are shown and described in more detail.

[0109] The interlock main connector area 1170 is also shown as including, for example, a connector port 1105 for coupling to an interlock host, and an additional connector port 1107 for coupling to, for example, an external exhaust sensor (in a specific exemplary embodiment, the additional connector port 1107 can be a DB-9 port for digital and / or analog communications).

[0110] Fig. 11B Shows Fig.11A 1005, which has another view of various gas delivery components within the gas delivery box 1005. The three-dimensional view 1130 shows the internal communication components 1131 within the gas delivery box 1005, which can be viewed from the Fig.11A The internal communication component 1131 provides digital and / or analog communication between a remote controller (not shown) and various gas delivery components (eg, MFC 1111 and several gas delivery components 1113) within the gas delivery box 1005.

[0111] Fig. 11C Shows the Fig.11A 1104 is an exemplary embodiment of a portion of an external EtherCAT node connection 1150 for system communication, which includes an EtherCAT connector area 1103. The EtherCAT connector area 1103 is shown to include, for example, several indicator lights 1151 (e.g., for confirming power delivery, EtherCAT diagnostics, fan operation, etc.), and a system controller (not shown) and a plurality of control panels 1152. Fig.10 , 11A One or more EtherCAT connectors 1153 for communicating with the gas delivery box 1005 of 11B. In a specific exemplary embodiment, the one or more EtherCAT connectors 1153 may include RJ-45 connectors known in the art.

[0112] Fig.11D Another section showing the external EtherCAT node connection 1150 (see Fig.11A and 11B ) of an exemplary embodiment, which includes an interlocking main connector area 1170 for use according to Fig.11A system communication. A machine with instructions for performing various operations

[0113] Fig.12 A block diagram of components of a machine 1200 capable of reading instructions from a machine-readable medium (e.g., a non-transitory machine-readable medium, a machine-readable storage medium, a computer-readable storage medium, or any suitable combination thereof) and performing any one or more of the methods discussed herein is shown according to some embodiments. Specifically, Fig.12 A representative diagram of a machine 1200 in the example form of a computer system is shown, within which instructions 1224 (e.g., software, programs, applications, applet, mobile application (APP), or other executable code) for causing the computer 1200 to perform any one or more of the methodologies discussed herein may be executed.

[0114] In another embodiment, the machine 1200 operates as a stand-alone device or can be connected (e.g., networked) to other machines. In a networked deployment, the machine 1200 can operate as a server machine or client machine in a server-client network environment or as a peer machine in a peer (or distributed) network environment. The machine 1200 can be a server computer, a client computer, a personal computer (PC), a tablet computer, a laptop computer, a notebook computer, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a smart phone, a network device, a network router, a network switch, a network bridge, or any machine capable of sequentially or otherwise executing instructions 1224 (which specifies the action to be taken by the machine). In addition, although only a single machine is shown, the term "machine" should also be considered to include a machine set that executes instructions 1224 individually or in combination to perform any one or more methods discussed herein.

[0115] The machine 1200 includes a processor 1202 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (D3P), an application specific integrated circuit (ASTC), a radio frequency integrated circuit (RFIC), or any suitable combination thereof), a main memory 1204, and a static memory 1206, which are configured to communicate with each other via a bus 1208. The processor 1202 may include a microcircuit, which may be temporarily or permanently configured by some or all of the instructions 1224, so that the processor 1202 may be configured to perform all or part of any one or more methods described herein. For example, a group of one or more microcircuits of the processor 1202 may be configured to execute one or more modules (e.g., software modules) described herein.

[0116] The machine 1200 may further include a graphics display 1210 (e.g., a plasma display panel (PDP), a light emitting diode (LED) display, a liquid crystal display (LCD), a projector, or a cathode ray tube (CRT)). The machine 1200 may also include an alphanumeric input device 1212 (e.g., a keyboard), a cursor control device 1214 (e.g., a mouse, a touch pad, a trackball, a joystick, a motion sensor, or other pointing instrument), a storage unit 1216, a signal generating device 1218 (e.g., a speaker), and a network interface device 1220.

[0117] The storage unit 1216 includes a machine-readable medium 1222 (e.g., a tangible and / or non-transitory machine-readable storage medium) on which are stored instructions 1224 that implement any one or more of the methods or functions described herein. The instructions 1224 may also be retained, in whole or in part, within the main memory 1204, within the processor 1202 (e.g., within a cache of the processor), or both during execution by the machine 1200. Thus, the main memory 1204 and the processor 1202 may be considered machine-readable media (e.g., a tangible and / or non-transitory machine-readable medium). The instructions 1224 may be sent or received over the network 1226 via the network interface device 1220. For example, the network interface device 1220 may transmit the instructions 1224 using any one or more transmission protocols (e.g., Hypertext Transfer Protocol (HTTP)).

[0118] In some embodiments, the machine 1200 may be a portable computer device, such as a smartphone or tablet computer, and have one or more additional input components (e.g., sensors or meters). Examples of these additional input components include image input components (e.g., one or more cameras), audio input components (e.g., microphones), direction input components (e.g., compasses), position input components (e.g., global positioning system (GPS) receivers), orientation components (e.g., gyroscopes), motion detection components (e.g., one or more accelerometers), height detection components (e.g., altimeters), and gas detection components (e.g., gas sensors). Input collected by any one or more of these input components may be accessed and used by any of the modules described herein.

[0119] As used herein, the term "memory" refers to a machine-readable medium capable of temporarily or permanently storing data, and may be considered to include, but not limited to, random access memory (RAM), read-only memory (ROM), buffer memory, flash memory, and cache. Although the machine-readable medium 1222 is shown as a single medium in one embodiment, the term "machine-readable medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database or associated cache and server) capable of storing instructions. The term "machine-readable medium" should also be considered to include any medium or combination of multiple media capable of storing instructions executed by a machine (e.g., machine 1200), so that the instructions can enable the machine to perform any one or more methods described herein when executed by one or more processors of the machine (e.g., processor 1202). Therefore, "machine-readable medium" refers to a single storage device or device, as well as a "cloud-based" storage system or storage network including multiple storage devices or devices. Therefore, the term "machine-readable medium" should be considered to include, but not limited to, one or more tangible (e.g., non-temporary) data storage repositories in solid-state memory, optical media, magnetic media, or any suitable combination thereof.

[0120] Furthermore, machine-readable media are non-transitory and do not include propagating signals. However, labeling a tangible machine-readable medium as "non-transitory" should not be interpreted to mean that the medium cannot be moved - the medium should be considered to be movable from one physical location to another. Furthermore, because the machine-readable medium is tangible, the medium can be considered a machine-readable device.

[0121] The instructions 1224 may further be sent or received over a network 1226 (e.g., a communication network) through the network interface device 1220 using a transmission medium and utilizing any of several known transmission protocols (e.g., HTTP). Examples of communication networks include a local area network (LAN), a wide area network (WAN), the Internet, a mobile telephone network, a plain old telephone service network (POTS network), and wireless data networks (e.g., WiFi and WiMAX networks). The term "transmission medium" shall be construed to include any intangible medium that is capable of storing, encoding, or carrying instructions to be executed by a machine, and includes digital or analog communication signals or other intangible media to facilitate communication of such software.

[0122] As described above, any gas delivery box or gas panel can be controlled via a single EtherCAT interface as described above. The single EtherCAT interface greatly simplifies the setup and testing of the gas delivery box or gas panel. In various embodiments, the gas delivery box can be configured and tested via an EtherCAT connection, thereby reducing the required test equipment and the problematic cabling and separation of the interface box in the prior art. Thus, the disclosed subject matter can be easily integrated into any gas delivery box, such as is commonly coupled to a semiconductor processing tool, and can be pre-configured and tested, such that the disclosed subject matter comprises a plug-and-play configuration, allowing for simple integration at an end-user site.

[0123] Throughout the specification, multiple examples may be implemented as components, operations or structures described as a single entity. Although the individual operations of one or more methods are illustrated and described as separate operations, one or more separate operations may be performed simultaneously, and it is not necessary to perform the operations in the order shown. The structures and functions presented as separate components in the exemplary configuration may be implemented in combination with the structures or components. Similarly, the structures and functions presented as individual components may be implemented as separate components. These and other variations, modifications, additions and improvements all fall within the scope of the subject matter of this article.

[0124] Certain embodiments are described herein as including logic or several components, modules or mechanisms. A module may constitute a software module (e.g., a code contained on a machine-readable medium or in a transmission signal) or a hardware module. A "hardware module" is a tangible unit capable of performing certain operations and may be configured or arranged in a certain physical manner. In various embodiments, one or more computer systems (e.g., a stand-alone computer system, a client computer system, or a server computer system) or one or more hardware modules of a computer system (e.g., a processor or a group of processors) may be configured by software (e.g., an application or an application portion) as a hardware module for performing certain operations as described herein.

[0125] In some embodiments, the hardware module can be implemented mechanically, electronically, or any suitable combination thereof. For example, the hardware module may include dedicated circuits or logic that are permanently configured to perform certain operations. For example, the hardware module may be a dedicated processor, such as a field programmable gate array (FPGA) or an ASIC. In various embodiments described herein, an FPGA pre-certified to SIL3 standard may be used.

[0126] A hardware module may also include programmable logic or circuitry that is temporarily configured by software to perform certain operations. For example, a hardware module may include software contained within a general purpose processor or other programmable processor. It should be understood that the decision to mechanically implement a hardware module in a dedicated and permanently configured circuit or in a temporarily configured circuit (e.g., configured by software) may be driven by cost and time considerations.

[0127] Therefore, the term "hardware module" should be understood to include a tangible entity, which is a physical structure, permanently configured (e.g., hardwired) or temporarily configured (e.g., programmed) to operate in a certain manner or perform certain operations described herein. As used herein, a "hardware implementation module" refers to a hardware module. Considering an embodiment in which the hardware module is temporarily configured (e.g., programmed), it is not necessary to configure or instantiate each hardware module at all times. For example, in the case where the hardware module includes a general-purpose processor configured by software to become a special-purpose processor, the general-purpose processor can be configured into different special-purpose processors (e.g., including different hardware modules) at different times. The software can thus configure the processor, for example, to constitute a specific hardware module at one moment and to constitute different hardware modules at different moments.

[0128] A hardware module can provide information to and receive information from other hardware modules. Therefore, the hardware modules can be considered as communicatively coupled. In the case of multiple hardware modules being present at the same time, communication can be achieved by signal transmission between two or more hardware modules (e.g., through appropriate circuits and buses). In embodiments where multiple hardware modules are configured or instantiated at different times, communication between these hardware modules can be achieved, for example, by the storage and retrieval of information in a memory structure, wherein multiple hardware modules can access the memory structure. For example, a hardware module can perform an operation and store the output of the operation in a memory device that is communicatively coupled to it. Then, another hardware module can subsequently access the memory device to obtain and process the stored output. A hardware module can also initiate communication with an input or output device and can operate on a resource (e.g., a collection of information).

[0129] The various operations of the exemplary methods described herein may be performed, at least in part, by one or more processors that are temporarily configured (e.g., by software) or permanently configured to perform the associated operations. Such processors, whether temporarily or permanently configured, may constitute processor-implemented modules that operate to perform one or more operations or functions described herein. As used herein, a "processor-implemented module" refers to a hardware module that is executed using one or more processors.

[0130] Similarly, the methods described herein may be implemented at least in part by a processor, which is an example of hardware. For example, at least some of the operations of the method may be performed by one or more processors or processor-implemented modules. In addition, one or more processors may also be operable to support related operational performance in a "cloud computing" environment or "software as a service (SaaS)". For example, at least some of the operations may be performed by a group of computers (as an example of a machine including a processor), which may be accessed via a network (e.g., the Internet) and via one or more appropriate interfaces (e.g., application programming interface (API)).

[0131] The execution of certain operations may be dispersed among one or more processors, not only within a single machine, but also deployed across several machines. In some embodiments, one or more processors or processor-implemented modules may be located in a single geographic location (e.g., in a home environment, an office environment, or a server farm). In other embodiments, one or more processors or processor-implemented modules may be distributed across several geographic locations.

[0132] As used herein, the word "or" may be understood to mean inclusive or exclusive. In addition, those skilled in the art will be able to understand other embodiments after reading and understanding the disclosure provided. In addition, those skilled in the art will readily understand after reading and understanding the disclosure provided herein that various combinations of the techniques and examples provided herein may all be applied in various combinations.

[0133] Although various embodiments are discussed separately, it is not intended that these separate embodiments be considered independent techniques or designs. As described above, each of the various parts may be interrelated, and each may be used alone or in combination with other particulate matter sensor calibration system embodiments discussed herein. For example, although various embodiments of methods, operations, and processes have been described, these methods, operations, and processes may be used alone or in various combinations.

[0134] Therefore, for those skilled in the art, many modifications and changes will be easily made after reading and understanding the disclosure provided herein. In addition to what is listed herein, those skilled in the art can easily know from the foregoing description that the methods and devices with equivalent functions within the scope of the present invention. Parts and features of some embodiments may be included in other embodiments, or replace parts and features of other embodiments. These modifications and changes are intended to fall within the scope of the appended claims. Therefore, the present invention is limited only by the terms of the appended claims and the full scope of equivalent schemes granted by these claims. It should also be understood that the terms used herein are only for the purpose of describing specific embodiments and are not used for limitation.

[0135] The abstract of the present invention is provided to enable the reader to quickly determine the nature of the technical disclosure. The abstract is submitted with the understanding that it cannot be used to interpret or limit the claims. In addition, in the aforementioned embodiments, it can be seen that various features can be combined together in a single embodiment for the purpose of simplifying the present invention. The method of the present invention should not be interpreted as limiting the claims. Therefore, the following claims are incorporated into the embodiments here, and each claim is each as a separate embodiment.

Claims

1. A distributed interlocking system, comprising: a plurality of slave nodes, each having an interface conversion card and an interlock (ITLK) slave device; as well as At least one master device electrically communicates with the plurality of slave nodes and is programmable to prevent sequence combinations that endanger personal safety, the at least one master device being configured to evaluate signals received from at least selected slave nodes among the plurality of slave nodes substantially in real time, the at least one master device having at least one preventive interlock section configured to evaluate interlock conditions and prevent the sequence combinations that endanger personal safety from being transmitted to one or more of the plurality of slave nodes before one or more instructions are executed.

2. A distributed interlocking system according to claim 1, wherein the sequence combination that endangers personal safety is based on a lookup table readable by the at least one master device.

3. The distributed interlocking system according to claim 1, wherein the at least one master device is further configured to provide instructions and operation signals to selected slave nodes among the plurality of slave nodes.

4. The distributed interlocking system according to claim 1, wherein: At least one of the master devices is configured as a dual redundant device, wherein components of the at least one master device are configured to perform the same tasks such that if a first redundant module fails, a second redundant module automatically takes over the tasks of the first redundant module.

5. The distributed interlocking system according to claim 1, wherein: The plurality of slave nodes are configured to synchronously sample input signals received from the tool and transmit the sampled signals to the at least one master device; and The plurality of slave nodes are further configured to synchronously drive output signals after receiving a result from the at least one master device, the received result being based on the input signal sent to the at least one master device.

6. The distributed interlocking system of claim 1, further comprising a sequencer to analyze a sequence of events based on the one or more signals received from at least one of the plurality of slave nodes after receiving the one or more signals from the tool.

7. The distributed interlocking system of claim 1, further comprising an interlocking equation solver to evaluate interlocking equations in substantially real time, wherein the interlocking equations are based on values ​​stored in a lookup table.

8. The distributed interlocking system according to claim 1, wherein: The interlock delay time based on the evaluated interlock condition is less than 1 millisecond and is independent of several interlock equations.

9. The distributed interlocking system according to claim 1, wherein: All interlocking calculations are centralized in the at least one master device.

10. The distributed interlocking system according to claim 1, wherein: At least a portion of the plurality of slave nodes of the distributed interlock system are coupled to components within a gas delivery box.

11. The distributed interlocking system according to claim 10, wherein: Each of the components within the gas delivery box is configured to be tested via a communication interface.

12. The distributed interlocking system according to claim 10, wherein: The integrated controller of the gas delivery box is one of the plurality of slave nodes in electronic communication with the at least one master device.

13. The distributed interlocking system according to claim 12, wherein: The integrated controller communicates with the at least one host device to operate the gas delivery box.

14. A distributed interlocking system, comprising: a lookup table configured to determine whether any combination of sequences is a hazard to human safety in a single tool operation or tool-to-tool operation; a plurality of slave nodes, each having an interface conversion card and an interlock (ITLK) slave device; At least one master device is coupled to the query table and is in electrical communication with the plurality of slave nodes, the at least one master device being configured to evaluate signals received from at least selected slave nodes among the plurality of slave nodes substantially in real time, the at least one master device having at least one preventive interlocking unit configured to evaluate interlock conditions based on the query table and prevent the sequence combination that endangers personal safety from being transmitted to one or more of the plurality of slave nodes before one or more instructions are executed.

15. The distributed interlocking system according to claim 14, wherein the at least one master device is further configured to provide instructions and operation signals to selected slave nodes among the plurality of slave nodes.

16. The distributed interlocking system according to claim 14, further comprising: a non-volatile memory device coupled to each of the master devices to store all interlocking equations; as well as A firmware device is coupled to each of the host devices to perform operations.

17. The distributed interlocking system of claim 14, further comprising a centralized interlocking equation solver located within the at least one master device.

18. A dual redundant distributed interlocking system, comprising: multiple interlocking slave devices; as well as At least one master device electrically communicates with the plurality of interlock slave devices and is programmable to prevent sequence combinations that endanger personal safety, the at least one master device being configured to evaluate signals received from selected interlock slave devices among the plurality of interlock slave devices in substantially real time, the at least one master device having at least one preventive interlock portion configured to evaluate interlock conditions and prevent the unsafe condition from being transmitted to one or more of the plurality of interlock slave devices before one or more instructions associated with the unsafe condition are executed.

19. The dual redundant distributed interlocking system of claim 18, further comprising a lookup table readable by the at least one master device, the lookup table being at least partially configured for use by the at least one master device to determine whether any combination of chemical sequences poses a hazard to personal safety.

20. The dual redundant distributed interlocking system according to claim 18, wherein: The components of the dual redundant distributed interlocking system are configured to perform the same tasks such that if a first redundant module fails, a second redundant module automatically takes over the tasks of the first redundant module.

21. The dual redundant distributed interlocking system according to claim 18, wherein: The first redundant module drives the output signals and the output device, while the second redundant module reads back the output signals, compares the output signals with its own results, and turns off the output signal if at least one of the output signals has a mismatch within predetermined limits with a corresponding one of its own results.

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