Current-limiting distributed static synchronous series compensator simulation model construction method

Abstract

The invention provides a current-limiting distributed static synchronous series compensator simulation model construction method, which constructs a simulation test system model and a current-limiting distributed static synchronous series compensator simulation model in electromagnetic transient simulation software, and comprises the following steps: constructing a power transmission line simulation test system model; constructing a main circuit simulation model of the current-limiting distributed static synchronous series compensator; constructing a distributed static synchronous compensator control circuit simulation model; and constructing a current limiting module control circuit simulation model. According to the current-limiting distributed static synchronous series compensator simulation model construction method provided by the invention, simulation research can be carried out on electric fields and magnetic fields of all elements of a power system and corresponding voltage and current change processes at a microsecond-second level, and simulation verification can be carried out on response performance and control characteristics of power electronic devices; and simulation data support is provided for equipment design and engineering application of the current-limiting distributed static synchronous series compensator.

Description

Technical Field

[0001] The present invention relates to the technical field of electrical equipment fault analysis, and in particular to a method for constructing a simulation model of a current-limiting distributed static synchronous series compensator. Background Art

[0002] With the continuous development of power electronic devices, FACTS (flexible AC transmission) technology has been widely valued and studied in power systems. The installed capacity of new energy power generation is gradually increasing in the power system, and the resulting power system stability and safety issues need to be solved urgently. The introduction of FACTS devices in the AC transmission system can effectively improve the safety and economy of the AC transmission system, making the power system more digital and intelligent. However, FACTS devices operating in actual power systems may be impacted by high current and high voltage in various short-circuit faults in the system. As a series-type FACTS device, whether DSSC (distributed static synchronous series compensator) has a reliable fault protection function is related to the actual promotion and application of FACTS devices.

[0003] Short circuit fault is one of the common serious faults in power system. If a short circuit fault occurs on the line equipped with DSSC, the fully controlled power electronic devices in DSSC device, such as IGBT, may be damaged due to high current and high voltage under the existing technology level. Therefore, it is necessary to simulate the electric field and magnetic field of each component of the power system and the corresponding voltage and current change process at the microsecond-second level, and simulate and verify the response performance and control characteristics of power electronic devices. However, there is little research in this aspect in the existing technology, and a scientific and effective simulation model construction method is urgently needed to provide simulation data support for the design and engineering application of current-limiting distributed static synchronous series compensator equipment. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art.

[0005] To this end, the present invention provides a method for constructing a simulation model of a current-limiting distributed static synchronous series compensator.

[0006] The present invention provides a method for constructing a simulation model of a current-limiting distributed static synchronous series compensator, which uses electromagnetic transient simulation software to construct a simulation test system model and a current-limiting distributed static synchronous series compensator simulation model, including:

[0007] Constructing a transmission line simulation test system model; the transmission line simulation test system model includes a transmission end, a transmission line and a receiving end, the transmission end is connected to the receiving end through the transmission line, and the transmission line simulation test system model is used for simulating the transmission line and simulating the transmission line with a short circuit fault;

[0008] Construct a current-limited distributed static synchronous series compensator main circuit simulation model; the current-limited distributed static synchronous series compensator main circuit simulation model includes a distributed static synchronous compensator subcircuit and a current limiting module subcircuit; wherein, the distributed static synchronous compensator subcircuit adopts a single-phase full-bridge converter; the current limiting module subcircuit adopts a single-phase half-controlled bridge converter; the single-phase full-bridge converter and the single-phase half-controlled bridge converter are connected in series and then connected to the transmission line simulation test system model;

[0009] Constructing a distributed static synchronous compensator control circuit simulation model, the distributed static synchronous compensator control circuit simulation model receives each first target signal, the first target signal includes an output voltage actual value signal, an output current actual value signal, a DC capacitor actual voltage signal and an active power signal generated by the distributed static synchronous compensator subcircuit, and performs sinusoidal pulse width modulation on each received first target signal after logical judgment to generate a distributed trigger pulse signal for controlling the distributed static synchronous compensator subcircuit;

[0010] A current limiting module control circuit simulation model is constructed, wherein the current limiting module control circuit simulation model receives each second target signal, wherein each second target signal includes an input voltage signal and a line fault signal in the current limiting module subcircuit, and generates a current limiting trigger pulse signal for controlling the current limiting module subcircuit according to each received second target signal.

[0011] The method for constructing a simulation model of a current-limiting distributed static synchronous series compensator according to the above technical solution of the present invention may also have the following additional technical features:

[0012] In the above technical solution, the transmission line simulation test system model also includes a power supply substation arranged at the transmission end, a receiving end substation arranged at the receiving end, and an AC system fault simulation test module; the power supply substation is connected to the receiving end substation through a transmission line; the AC system fault simulation test module is connected in parallel to the transmission line to simulate a short circuit fault in the transmission line and generate a line fault signal.

[0013] In the above technical solution, the single-phase full-bridge converter includes:

[0014] A first electronic switch having a first end, a second end and a control end, wherein the second end of the first electronic switch is coupled to the power transmission line, and the control end of the first electronic switch receives a first distributed trigger pulse signal;

[0015] A first diode having a first end and a second end, wherein the first end of the first diode is coupled to the first end of the first electronic switch, and the second end of the first diode is coupled to the second end of the first electronic switch;

[0016] A second electronic switch having a first end, a second end and a control end, the first end of the second electronic switch being coupled to the first end of the first electronic switch, and the control end of the second electronic switch receiving a second distributed trigger pulse signal;

[0017] A second diode having a first end and a second end, wherein the first end of the second diode is coupled to the first end of the second electronic switch, and the second end of the second diode is coupled to the second end of the second electronic switch;

[0018] A third electronic switch has a first end, a second end and a control end, the first end of the third electronic switch is coupled to the first end of the first electronic switch, the second end of the third electronic switch is connected to the single-phase half-controlled bridge converter, and the control end of the third electronic switch receives a third distributed trigger pulse signal;

[0019] A third diode having a first end and a second end, wherein the first end of the third diode is coupled to the first end of the third electronic switch, and the second end of the third diode is coupled to the second end of the third electronic switch;

[0020] a fourth electronic switch, having a first end, a second end and a control end, wherein the first end of the fourth electronic switch is coupled to the second end of the third electronic switch, the second end of the fourth electronic switch is coupled to the second end of the second electronic switch, and the control end of the fourth electronic switch receives a fourth distributed trigger pulse signal;

[0021] a fourth diode having a first end and a second end, wherein the first end of the fourth diode is coupled to the first end of the fourth electronic switch, and the second end of the fourth diode is coupled to the second end of the fourth electronic switch;

[0022] The DC link capacitor has a first end and a second end, wherein the first end of the DC link capacitor is coupled to the first end of the third electronic switch, and the second end of the DC link capacitor is coupled to the second end of the fourth electronic switch.

[0023] In the above technical solution, the distributed static synchronous compensator subcircuit is connected to the transmission line through an LC filter; the LC filter includes:

[0024] A first inductor having a first end and a second end, wherein the first end of the first inductor is coupled to the second end of the first electronic switch;

[0025] A first resistor having a first end and a second end, wherein the first end of the first resistor is coupled to the second end of the first inductor and the transmission line respectively;

[0026] The first capacitor has a first end and a second end, the first end of the first capacitor is coupled to the second end of the first resistor, and the second end of the first capacitor is coupled to the first end of the fourth electronic switch and the transmission line respectively.

[0027] In the above technical solution, the current signal generated at the first end of the first resistor is defined as an output current actual value signal generated by the distributed static synchronous compensator sub-circuit;

[0028] defining a voltage signal between a first end of the first resistor and a second end of the first capacitor as an output voltage actual value signal generated by a distributed static synchronous compensator sub-circuit;

[0029] The voltage signal between the two ends of the DC link capacitor is defined as the actual voltage signal of the DC capacitor generated by the distributed static synchronous compensator sub-circuit.

[0030] In the above technical solution, the current limiting module subcircuit includes:

[0031] A first thyristor having a first end, a second end and a control end, wherein the second end of the first thyristor is coupled to the power transmission line, and the control end of the first thyristor receives a first current limiting trigger pulse signal;

[0032] A second thyristor, having a first end, a second end and a control end, the first end of the second thyristor is coupled to the first end of the first thyristor, and the control end of the second thyristor receives a second current limiting trigger pulse signal;

[0033] A third thyristor has a first end, a second end and a control end, the first end of the third thyristor is respectively coupled to the second end of the second thyristor, the power transmission line and the first end of the fourth electronic switch, and the control end of the third thyristor receives a third current limiting trigger pulse signal;

[0034] a fourth thyristor, having a first end, a second end and a control end, wherein the first end of the fourth thyristor is coupled to the second end of the first thyristor, the second end of the fourth thyristor is coupled to the second end of the third thyristor, and the control end of the fourth thyristor receives a fourth current limiting trigger pulse signal;

[0035] A second inductor having a first end and a second end, wherein the first end of the second inductor is coupled to the first end of the second thyristor, and the second end of the second inductor is coupled to the second end of the third thyristor;

[0036] Wherein, a voltage signal between the second end of the first thyristor and the second end of the second thyristor is defined as an input voltage signal in the current limiting module sub-circuit.

[0037] In the above technical solution, the distributed static synchronous compensator control circuit simulation model includes a command value calculation module and an SPWM module;

[0038] Constructing the distributed static synchronous compensator control circuit simulation model includes:

[0039] The output voltage actual value signal, the output current actual value signal, the DC capacitor actual voltage signal and the active power signal generated by the distributed static synchronous compensator subcircuit are obtained; the command value calculation module uses the phase angle in the transmission line current as the phase angle reference value, that is, the phase angle of the output current actual value signal is obtained by using the component phase-locked loop PLL in the electromagnetic transient simulation software; the d-axis component and q-axis component of the output current actual value signal and the d-axis component and q-axis component of the output voltage actual value signal are calculated according to the phase angle of the output current actual value signal;

[0040] Taking the control of single-phase line power flow as the control target, a double closed-loop controller of a single-phase full-bridge converter is constructed, wherein the double closed-loop controller of the single-phase full-bridge converter includes a system-level controller and a device-level controller; a PI controller is used to calculate a d-axis component command value output by the system-level controller and a q-axis component command value output by the system-level controller;

[0041] Inputting the d-axis component command value output by the system-level controller and the q-axis component command value output by the system-level controller to the device-level controller, and calculating the d-axis component output by the device-level controller and the q-axis component output by the device-level controller by using a PI controller;

[0042] The d-axis component output by the device-level controller, the q-axis component output by the device-level controller, and the phase angle of the output current actual value signal are input into the single-phase inverse Pike transformation unit to obtain a reference voltage signal; the reference voltage signal is used as the modulation voltage of the single-phase SPWM module and is compared with the triangular carrier to generate the first distributed trigger pulse signal, the second distributed trigger pulse signal, the third distributed trigger pulse signal, and the fourth distributed trigger pulse signal.

[0043] In the above technical solution, the method of using a PI controller to calculate the d-axis component instruction value output by the system level controller and the q-axis component instruction value output by the system level controller includes:

[0044] The d-axis component of the actual value signal of the output voltage is used as the DC side capacitor voltage command value, and the DC side capacitor voltage command value is subtracted from the DC capacitor actual voltage signal. The difference is calculated by the PI controller to obtain the d-axis component command value output by the system level controller; the q-axis component of the actual value signal of the output voltage is used as the line flow command value, and the line flow command value is subtracted from the active power signal. The difference is calculated by the PI controller to obtain the q-axis component command value output by the system level controller.

[0045] In the above technical solution, the method of calculating the d-axis component output by the device-level controller and the q-axis component output by the device-level controller by using the PI controller includes:

[0046] The d-axis component command value output by the system-level controller is subtracted from the d-axis component of the output voltage actual value signal, and the difference is calculated by the PI controller to obtain the output current d-axis component command value of the single-phase full-bridge converter; the output current d-axis component command value of the single-phase full-bridge converter is subtracted from the d-axis component of the output current actual value signal, and the difference is calculated by the PI controller and then the d-axis component output by the device-level controller is obtained through the decoupling calculation link;

[0047] The q-axis component command value output by the system-level controller is subtracted from the q-axis component of the output voltage actual value signal, and the difference is calculated by the PI controller to obtain the output current q-axis component command value of the single-phase full-bridge converter; the output current q-axis component command value of the single-phase full-bridge converter is subtracted from the q-axis component of the output current actual value signal, and the difference is calculated by the PI controller and then the q-axis component output by the device-level controller is obtained through the decoupling calculation link.

[0048] In the above technical solution, the construction of the current limiting module control circuit simulation model includes:

[0049] Under normal operating conditions, that is, when the line fault signal is logically invalid, the zero crossing point of the input voltage signal is detected by the Zero Detector module in the electromagnetic transient simulation software. When the input voltage signal has a positive first-order derivative at the zero crossing point, the first current limiting trigger pulse signal and the third current limiting trigger pulse signal are logically valid, and the second current limiting trigger pulse signal and the fourth current limiting trigger pulse signal are logically invalid; when the input voltage signal has a negative first-order derivative at the zero crossing point, the first current limiting trigger pulse signal and the third current limiting trigger pulse signal are logically invalid, and the second current limiting trigger pulse signal and the fourth current limiting trigger pulse signal are logically valid;

[0050] Under a short-circuit fault condition, that is, when the line fault signal is logically valid, the first current limiting trigger pulse signal, the second current limiting trigger pulse signal, the third current limiting trigger pulse signal and the fourth current limiting trigger pulse signal are all logically invalid.

[0051] In summary, due to the adoption of the above technical features, the beneficial effects of the present invention are:

[0052] The present invention provides a method for constructing a simulation model of a current-limiting distributed static synchronous series compensator based on electromagnetic transient simulation software (PSCAD / EMTDC). PSCAD / EMTDC can be used to simulate and verify the electromagnetic transient process of the current-limiting distributed static synchronous series compensator, and provide simulation data support for the equipment design and engineering application of the current-limiting distributed static synchronous series compensator. Among them, the current-limiting distributed static synchronous series compensator adds a current limiting module compared to the conventional distributed static synchronous series compensator, which can effectively protect the power electronic devices in the distributed static synchronous series compensator and reduce the risk of damage to the device due to failure. Through simulation analysis, the current-limiting distributed static synchronous series compensator can have a good power flow control effect, and can also effectively protect the power electronic devices in the device in the event of a short circuit fault in the line.

[0053] Additional aspects and advantages of the present invention will become apparent from the following description or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0055] Figure 1 is a flow chart of a method for constructing a simulation model of a current-limiting distributed static synchronous series compensator according to an embodiment of the present invention;

[0056] Figure 2 It is a schematic diagram of a 500kV transmission line simulation test system model in a method for constructing a current-limiting distributed static synchronous series compensator simulation model according to an embodiment of the present invention;

[0057] Figure 3 It is a schematic diagram of a simulation model of a main circuit of a current-limiting distributed static synchronous series compensator in a method for constructing a simulation model of a current-limiting distributed static synchronous series compensator according to an embodiment of the present invention;

[0058] Figure 4 It is a schematic diagram of a simulation model of a distributed static synchronous compensator control circuit in a method for constructing a simulation model of a current-limiting distributed static synchronous series compensator according to an embodiment of the present invention;

[0059] Figure 5 It is a schematic diagram of a simulation model of a current limiting module control circuit in a method for constructing a simulation model of a current limiting distributed static synchronous series compensator according to an embodiment of the present invention;

[0060] Figure 6It is a schematic diagram of a line active power variation curve in a method for constructing a current-limiting distributed static synchronous series compensator simulation model according to an embodiment of the present invention;

[0061] Figure 7 It is a line current waveform diagram during a short-circuit fault in a current-limiting distributed static synchronous series compensator simulation model construction method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0062] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0063] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0064] Refer to the following Figures 1 to 7 The following describes a method for constructing a simulation model of a current-limiting distributed static synchronous series compensator according to some embodiments of the present invention.

[0065] Some embodiments of the present application provide a method for constructing a simulation model of a current-limiting distributed static synchronous series compensator.

[0066] like Figure 1 As shown, the first embodiment of the present invention proposes a method for constructing a simulation model of a current-limiting distributed static synchronous series compensator, and uses electromagnetic transient simulation software (PSCAD / EMTDC) to construct a simulation test system model and a current-limiting distributed static synchronous series compensator simulation model, which specifically includes the following steps S1-S4.

[0067] S1. Construct a transmission line simulation test system model; the transmission line simulation test system model includes a transmission end, a transmission line and a receiving end, the transmission end is connected to the receiving end through a transmission line, and the transmission line simulation test system model is used for simulating transmission lines and simulating transmission lines with short circuit faults.

[0068] In a specific embodiment, a 500 kV transmission line simulation test system model is used as an example for explanation. Figure 2As shown, the transmission line simulation test system model includes a power supply end substation, a transmission line, a receiving end substation and an AC system fault simulation test module; the power supply end substation is connected to the receiving end substation through the transmission line; the AC system fault simulation test module is connected in parallel to the transmission line, and is used to simulate a short circuit fault in the transmission line after receiving a fault enable signal Fault_EN, and generate a line fault signal Fault. Among them, the power supply end substation and the receiving end substation are both illustrated as three-phase AC voltage sources, and the transmission line is illustrated as two power line modules PI SECTION; the AC system fault simulation test module is arranged between the two power line modules PI SECTION, one end of which is connected to the transmission line, and the other end is connected to the ground.

[0069] S2, build the simulation model of the main circuit of the current-limited distributed static synchronous series compensator; Figure 2 In the illustrated embodiment, the current-limiting distributed static synchronous series compensator main circuit simulation model is illustrated as a DSSC module, which is connected in series between the power line module PI SECTION and the power supply end substation. The current-limiting distributed static synchronous series compensator main circuit simulation model includes a distributed static synchronous compensator subcircuit and a current limiting module subcircuit; wherein the distributed static synchronous compensator subcircuit adopts a single-phase full-bridge converter; the current limiting module subcircuit adopts a single-phase half-controlled bridge converter; the single-phase full-bridge converter and the single-phase half-controlled bridge converter are connected in series and then connected to the transmission line simulation test system model.

[0070] Specifically, the simulation model of the main circuit of the current-limiting distributed static synchronous series compensator is composed of three single-phase full-bridge converters connected to a single-phase half-controlled bridge current limiter respectively. The current-limiting distributed static synchronous series compensator of each phase has the same structure, and in this disclosure, phase A is taken as an example for explanation.

[0071] like Figure 3 As shown, the current-limited distributed static synchronous series compensator main circuit simulation model (DSSC) is connected in series between nodes S1 and S2 of the transmission line. The power electronic switch IGBT in PSCAD / EMTDC is connected in anti-parallel with the diode to construct a single-phase full-bridge converter, i.e., a distributed static synchronous compensator subcircuit. It can be understood that the above-mentioned electronic switch can adopt any suitable semiconductor controllable switch device. Figure 3 In the illustrated embodiment, the electronic switches are illustrated as insulated gate bipolar transistors (IGBTs), the first end of each electronic switch is the collector of the IGBT, the second end is the emitter of the IGBT, and the control end is the gate of the IGBT.

[0072] Specifically, the distributed static synchronous compensator sub-circuit includes: a first electronic switch V1, a first diode D1, a second electronic switch V2, a second diode D2, a third electronic switch V3, a third diode D3, a fourth electronic switch V4, a fourth diode D4 and a DC link capacitor Cs. The first electronic switch V1 has a first end, a second end and a control end, and the control end of the first electronic switch V1 receives the first distribution trigger pulse signal G1; the first diode D1 has a first end and a second end, and the first end of the first diode D1 is coupled to the first end of the first electronic switch V1, and the second end of the first diode D1 is coupled to the second end of the first electronic switch V1; the second electronic switch V2 has a first end, a second end and a control end, and the first end of the second electronic switch V2 is coupled to the first end of the first electronic switch V1, and the control end of the second electronic switch V2 receives the second distribution trigger pulse signal G2; the second diode D2 has a first end and a second end, and the first end of the second diode D2 is coupled to the first end of the second electronic switch V2, and the second end of the second diode D2 is coupled to the second end of the second electronic switch V2; the third electronic switch V3 has a first end, a second end and a control end, and the first end of the third electronic switch V3 is coupled to the first end of the first electronic switch V1, and the control end of the third electronic switch V3 is coupled to the first end of the first electronic switch V1. The third distributed trigger pulse signal G3 is received; the third diode D3 has a first end and a second end, the first end of the third diode D3 is coupled to the first end of the third electronic switch V3, and the second end of the third diode D3 is coupled to the second end of the third electronic switch V3; the fourth electronic switch V4 has a first end, a second end and a control end, the first end of the fourth electronic switch V4 is coupled to the second end of the third electronic switch V3, the second end of the fourth electronic switch V4 is coupled to the second end of the second electronic switch V2, and the control end of the fourth electronic switch V4 receives the fourth distributed trigger pulse signal G4; the fourth diode D4 has a first end and a second end, the first end of the fourth diode D4 is coupled to the first end of the fourth electronic switch V4, and the second end of the fourth diode D4 is coupled to the second end of the fourth electronic switch V4; the DC link capacitor Cs has a first end and a second end, the first end of the DC link capacitor Cs is coupled to the first end of the third electronic switch V3, and the second end of the DC link capacitor Cs is coupled to the second end of the fourth electronic switch V4.

[0073] In some embodiments, the distributed static synchronous compensator sub-circuit is connected to the transmission line through an LC filter; the LC filter includes: a first inductor L1 having a first end and a second end, the first end of the first inductor L1 is coupled to the second end of the first electronic switch V1; a first resistor R1 having a first end and a second end, the first end of the first resistor R1 is respectively coupled to the second end of the first inductor L1 and a node S1 of the transmission line; a first capacitor C1 having a first end and a second end, the first end of the first capacitor C1 is coupled to the second end of the first resistor R1, and the second end of the first capacitor C1 is respectively coupled to the first end of the fourth electronic switch V4 and the transmission line.

[0074] The current signal generated by the first end of the first resistor R1 is defined as the output current actual value signal IgA generated by the distributed static synchronous compensator sub-circuit; the voltage signal between the first end of the first resistor R1 and the second end of the first capacitor C1 is defined as the output voltage actual value signal VseA generated by the distributed static synchronous compensator sub-circuit; the voltage signal between the two ends of the DC link capacitor Cs is defined as the DC capacitor actual voltage signal VdcA generated by the distributed static synchronous compensator sub-circuit.

[0075] Continue reading Figure 3 The current limiting module sub-circuit includes: a first thyristor M1, a second thyristor M2, a third thyristor M3, a fourth thyristor M4 and a second inductor L2.

[0076] The first thyristor M1 has a first end, a second end and a control end, the second end of the first thyristor M1 is coupled to the node S2 of the transmission line, and the control end of the first thyristor M1 receives the first current limiting trigger pulse signal XG1; the second thyristor M2 has a first end, a second end and a control end, the first end of the second thyristor M2 is coupled to the first end of the first thyristor M1, and the control end of the second thyristor M2 receives the second current limiting trigger pulse signal XG2; the third thyristor M3 has a first end, a second end and a control end, the first end of the third thyristor M3 is respectively coupled to the second end of the second thyristor M2, the node S2 of the transmission line and the second end of the first capacitor C1, and the control end of the third thyristor M3 receives the third current limiting trigger pulse signal XG2. trigger pulse signal XG3; a fourth thyristor M4, having a first end, a second end and a control end, the first end of the fourth thyristor M4 is coupled to the second end of the first thyristor M1, the second end of the fourth thyristor M4 is coupled to the second end of the third thyristor M3, and the control end of the fourth thyristor M4 receives a fourth current limiting trigger pulse signal XG4; a second inductor L2, having a first end and a second end, the first end of the second inductor L2 is coupled to the first end of the second thyristor M2, and the second end of the second inductor L2 is coupled to the second end of the third thyristor M3; wherein the voltage signal between the second end of the first thyristor M1 and the second end of the second thyristor M2 is defined as the input voltage signal V_XA in the current limiting module sub-circuit.

[0077] The first end of the thyristor is the cathode of the thyristor, and the second end of the thyristor is the anode of the thyristor. The current-limiting distributed static synchronous series compensator simulation model provided in this embodiment shows zero impedance when the system is operating normally; when a short-circuit fault occurs in the system, the current-limiting module will immediately access the line to limit the rising rate of the short-circuit current, and cut off the short-circuit current after a short current-limiting process, thereby completing the protection of the DSSC. Compared with the traditional DSSC, the present disclosure can effectively reduce the rising value of the capacitor voltage on the DC side of the DSSC during a short-circuit fault, and reduce the short-circuit current flowing through the DSSC.

[0078] S3. Construct a distributed static synchronous compensator control circuit simulation model, which receives the output voltage actual value signal VseA, the output current actual value signal IgA, the DC capacitor actual voltage signal VdcA and the active power signal Pline generated by the distributed static synchronous compensator sub-circuit, and performs sinusoidal pulse width modulation on the received signal after logical judgment to generate a distributed trigger pulse signal for controlling the distributed static synchronous compensator sub-circuit.

[0079] In some embodiments, Figure 4As shown, the distributed static synchronous compensator control circuit simulation model includes an instruction value calculation module and an SPWM module; constructing the distributed static synchronous compensator control circuit simulation model includes:

[0080] S31. Obtain the output voltage actual value signal VseA, the output current actual value signal IgA, the DC capacitor actual voltage signal VdcA and the active power signal Pline generated by the distributed static synchronous compensator sub-circuit; the command value calculation module uses the phase angle in the transmission line current as the phase angle reference value, that is, uses the component phase-locked loop PLL in the electromagnetic transient simulation software to obtain the phase angle thetaA of the output current actual value signal IgA; transmit the output current actual value signal IgA and the phase angle thetaA of the output current actual value signal IgA to the single-phase Parker transformation module to calculate the d-axis component IgAd and q-axis component IgAq of the output current actual value signal IgA, and transmit the output voltage actual value signal VseA and the phase angle thetaA to the single-phase Parker transformation module to calculate the d-axis component VseAd and q-axis component VseAq of the output voltage actual value signal VseA.

[0081] Specifically, since the input of the phase-locked loop PLL needs to be a three-phase electrical quantity, the output current actual value signal IgA is passed into the Delay module to obtain two new variables that lag behind the original variables by 120° and 240°, and then the three current signals are transmitted to the input end of the phase-locked loop PLL to obtain the phase angle thetaA.

[0082] S32. Taking the control of single-phase line power flow as the control target, construct a single-phase full-bridge converter system-level and device-level dual closed-loop controller; use the PI controller to calculate the d-axis component command value VdARef output by the system-level controller and the q-axis component command value VqARef output by the system-level controller.

[0083] Specifically, the d-axis component VseAd of the output voltage actual value signal VseA is used to control the DC side capacitor voltage, and the d-axis component VseAd of the output voltage actual value signal VseA is used as the DC side capacitor voltage command value, and the DC side capacitor voltage command value is subtracted from the DC capacitor actual voltage signal VdcA. The difference is calculated by the PI controller to obtain the d-axis component command value VdARef output by the system level controller, which is transmitted to the single-phase full-bridge converter device level control circuit as an input quantity. The q-axis component VseAq of the output voltage actual value signal VseA is used to control the line flow size, and the q-axis component VseAq of the output voltage actual value signal VseA is used as the line flow command value, and the line flow command value is subtracted from the active power signal Pline. The difference is calculated by the PI controller to obtain the q-axis component command value VqARef output by the system level controller, which is transmitted to the single-phase full-bridge converter device level control circuit as an input quantity. Among them, the active power signal can be calculated based on the line voltage ULine and the line current ILine.

[0084] S33. The d-axis component command value VdARef output by the system-level controller and the q-axis component command value VqARef output by the system-level controller are input to the device-level controller, and the d-axis component VrAd output by the device-level controller (i.e., the d-axis component of the output voltage reference value of the single-phase full-bridge converter) and the q-axis component VrAq output by the device-level controller (i.e., the q-axis component of the output voltage reference value of the single-phase full-bridge converter) are calculated using a PI controller.

[0085] Specifically, the d-axis component command value VdARef output by the system-level controller is subtracted from the d-axis component VseAd of the output voltage actual value signal VseA, and the difference is calculated by the PI controller to obtain the output current d-axis component command value IgdARef of the single-phase full-bridge converter; the output current d-axis component command value IgdARef of the single-phase full-bridge converter is subtracted from the d-axis component IgAd of the output current actual value signal IgA, and the difference is calculated by the PI controller and then the d-axis component VrAd output by the device-level controller is obtained through the decoupling calculation link.

[0086] The q-axis component command value VqARef output by the system-level controller is subtracted from the q-axis component VseAq of the output voltage actual value signal VseA, and the difference is calculated by the PI controller to obtain the output current q-axis component command value IgqARef of the single-phase full-bridge converter; the output current q-axis component command value IgqARef of the single-phase full-bridge converter is subtracted from the q-axis component IgAq of the output current actual value signal IgA, and the difference is calculated by the PI controller and then the q-axis component VrAq output by the device-level controller is obtained through the decoupling calculation link.

[0087] S34. The d-axis component VrAd output by the device-level controller, the q-axis component VrAq output by the device-level controller and the phase angle thetaA of the output current actual value signal IgA are input into the single-phase phase-to-phase conversion unit to obtain a reference voltage signal VRef; the reference voltage signal VRef is used as the modulation voltage of the single-phase SPWM module and compared with the triangular carrier PWMEN to generate a distributed trigger pulse signal GA, including the first distributed trigger pulse signal G1, the second distributed trigger pulse signal G2, the third distributed trigger pulse signal G3 and the fourth distributed trigger pulse signal G4.

[0088] Referring to steps S31-S34, a method for constructing a simulation model of a control circuit of a B-phase and a C-phase single-phase full-bridge converter can also be obtained.

[0089] S4. Construct a simulation model of the current limiting module control circuit, such as Figure 5 As shown, the current limiting module control circuit simulation model receives the input voltage signal V_XA and the line fault signal Fault in the current limiting module subcircuit, and generates a current limiting trigger pulse signal XG for controlling the current limiting module subcircuit according to the received signal, including a first current limiting trigger pulse signal XG1, a second current limiting trigger pulse signal XG2, a third current limiting trigger pulse signal XG3 and a fourth current limiting trigger pulse signal XG4.

[0090] The control mode of the single-phase half-controlled bridge converter is switched by the line fault signal Fault. When the Fault signal is 0, the single-phase half-controlled bridge converter works in normal operation; when the Fault signal is 1, the single-phase half-controlled bridge converter works in a short-circuit fault condition.

[0091] Under normal operating conditions, that is, when the line fault signal Fault is logically invalid, the zero crossing point of the input voltage signal is detected by the Zero Detector module in the electromagnetic transient simulation software. When the zero crossing point of the input voltage signal has a positive first-order derivative, the first current limiting trigger pulse signal XG1 and the third current limiting trigger pulse signal XG3 are logically valid, and the second current limiting trigger pulse signal XG2 and the fourth current limiting trigger pulse signal XG4 are logically invalid; when the zero crossing point of the input voltage signal has a negative first-order derivative, the first current limiting trigger pulse signal XG1 and the third current limiting trigger pulse signal XG3 are logically invalid, and the second current limiting trigger pulse signal XG2 and the fourth current limiting trigger pulse signal XG4 are logically valid.

[0092] In the case of a short circuit fault, that is, when the line fault signal Fault is logically valid, the first current limiting trigger pulse signal XG1, the second current limiting trigger pulse signal XG2, the third current limiting trigger pulse signal XG3 and the fourth current limiting trigger pulse signal XG4 are all logically invalid.

[0093] In this embodiment, logic validity and logic failure correspond to a high level (1) and a low level (0), respectively, and can be flexibly set according to needs.

[0094] In order to verify the effectiveness of the method for constructing a simulation model of a current-limiting distributed static synchronous series compensator according to the present invention, the following simulation example analysis is performed on the constructed current-limiting distributed static synchronous series compensator simulation model. The main simulation parameters are shown in Table 1.

[0095] Table 1 Main parameter settings of the current-limited distributed static synchronous series compensator simulation model

[0096]

[0097] 1. Simulation analysis of power flow control effect of current-limiting distributed static synchronous series compensator simulation model.

[0098] The simulation settings are as follows: at 0.1s, the current limiting module trigger signal is enabled to charge the inductor of the current limiting module; at 0.3s, the distributed static synchronous series compensator is put into operation to charge the DC side capacitor voltage to 10kV; and at 1.5s, the power flow is regulated.

[0099] The simulation waveform of the power flow control effect of the current-limiting distributed static synchronous series compensator is as follows Figure 6 As shown in the figure, it can be seen from the simulation waveform that the current-limiting distributed static synchronous series compensator did not adjust and control the line power flow 1.5s ago, and the line power flow was basically stable at 830MW. At 1.5s, the current-limiting distributed static synchronous series compensator began to adjust the line power flow. After a transient process of about 0.4s, the device stabilized the active power of the line at around 800MW.

[0100] 2. Simulation analysis of the current limiting effect of short-circuit fault in the simulation model of the current-limiting distributed static synchronous series compensator.

[0101] The simulation settings are as follows: a three-phase short circuit fault occurs in the line at 2.0s, and the fault is cleared after 0.1s.

[0102] The simulation waveform of the current limiting effect of the short-circuit fault of the current limiting distributed static synchronous series compensator is as follows Figure 7 As shown in the figure, it can be seen from the simulation waveform that the maximum short-circuit current of the line is 13.9kA; 0.03s after the short-circuit fault occurs, the current-limiting distributed static synchronous series compensator disconnects the short-circuit current.

[0103] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0104] Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for constructing a simulation model of a current-limiting distributed static synchronous series compensator, characterized in that: Construct a simulation test system model and a current-limiting distributed static synchronous series compensator simulation model in the electromagnetic transient simulation software, including: Constructing a transmission line simulation test system model; the transmission line simulation test system model includes a transmission end, a transmission line and a receiving end, the transmission end is connected to the receiving end through the transmission line, and the transmission line simulation test system model is used for simulating the transmission line and simulating the transmission line with a short circuit fault; Construct a current-limited distributed static synchronous series compensator main circuit simulation model; the current-limited distributed static synchronous series compensator main circuit simulation model includes a distributed static synchronous compensator subcircuit and a current limiting module subcircuit; wherein, the distributed static synchronous compensator subcircuit adopts a single-phase full-bridge converter; the current limiting module subcircuit adopts a single-phase half-controlled bridge converter; the single-phase full-bridge converter and the single-phase half-controlled bridge converter are connected in series and then connected to the transmission line simulation test system model; Constructing a distributed static synchronous compensator control circuit simulation model, the distributed static synchronous compensator control circuit simulation model receives each first target signal, the first target signal includes an output voltage actual value signal, an output current actual value signal, a DC capacitor actual voltage signal and an active power signal generated by the distributed static synchronous compensator subcircuit, and performs sinusoidal pulse width modulation on each received first target signal after logical judgment to generate a distributed trigger pulse signal for controlling the distributed static synchronous compensator subcircuit; A current limiting module control circuit simulation model is constructed, wherein the current limiting module control circuit simulation model receives each second target signal, wherein each second target signal includes an input voltage signal and a line fault signal in the current limiting module subcircuit, and generates a current limiting trigger pulse signal for controlling the current limiting module subcircuit according to each received second target signal.

2. The method for constructing a simulation model of a current-limiting distributed static synchronous series compensator according to claim 1, characterized in that: The transmission line simulation test system model also includes a power supply substation arranged at the transmission end, a receiving end substation arranged at the receiving end, and an AC system fault simulation test module; the power supply substation is connected to the receiving end substation through a transmission line; the AC system fault simulation test module is connected in parallel to the transmission line to simulate a short circuit fault in the transmission line and generate a line fault signal.

3. The method for constructing a simulation model of a current-limiting distributed static synchronous series compensator according to claim 2, characterized in that: The single-phase full-bridge converter comprises: A first electronic switch having a first end, a second end and a control end, wherein the second end of the first electronic switch is coupled to the power transmission line, and the control end of the first electronic switch receives a first distributed trigger pulse signal; A first diode having a first end and a second end, wherein the first end of the first diode is coupled to the first end of the first electronic switch, and the second end of the first diode is coupled to the second end of the first electronic switch; A second electronic switch having a first end, a second end and a control end, the first end of the second electronic switch being coupled to the first end of the first electronic switch, and the control end of the second electronic switch receiving a second distributed trigger pulse signal; A second diode having a first end and a second end, wherein the first end of the second diode is coupled to the first end of the second electronic switch, and the second end of the second diode is coupled to the second end of the second electronic switch; A third electronic switch, having a first end, a second end and a control end, wherein the first end of the third electronic switch is coupled to the first end of the first electronic switch, the second end of the third electronic switch is connected to the single-phase half-controlled bridge converter, and the control end of the third electronic switch receives a third distributed trigger pulse signal; A third diode having a first end and a second end, wherein the first end of the third diode is coupled to the first end of the third electronic switch, and the second end of the third diode is coupled to the second end of the third electronic switch; a fourth electronic switch, having a first end, a second end and a control end, wherein the first end of the fourth electronic switch is coupled to the second end of the third electronic switch, the second end of the fourth electronic switch is coupled to the second end of the second electronic switch, and the control end of the fourth electronic switch receives a fourth distributed trigger pulse signal; a fourth diode having a first end and a second end, wherein the first end of the fourth diode is coupled to the first end of the fourth electronic switch, and the second end of the fourth diode is coupled to the second end of the fourth electronic switch; The DC link capacitor has a first end and a second end, wherein the first end of the DC link capacitor is coupled to the first end of the third electronic switch, and the second end of the DC link capacitor is coupled to the second end of the fourth electronic switch.

4. The method for constructing a simulation model of a current-limiting distributed static synchronous series compensator according to claim 3, characterized in that: The distributed static synchronous compensator subcircuit is connected to the transmission line through an LC filter; the LC filter comprises: A first inductor having a first end and a second end, wherein the first end of the first inductor is coupled to the second end of the first electronic switch; A first resistor having a first end and a second end, wherein the first end of the first resistor is coupled to the second end of the first inductor and the transmission line respectively; The first capacitor has a first end and a second end, the first end of the first capacitor is coupled to the second end of the first resistor, and the second end of the first capacitor is coupled to the first end of the fourth electronic switch and the transmission line respectively.

5. The method for constructing a simulation model of a current-limiting distributed static synchronous series compensator according to claim 4, characterized in that: The current signal generated at the first end of the first resistor is defined as an output current actual value signal generated by the distributed static synchronous compensator sub-circuit; defining a voltage signal between a first end of the first resistor and a second end of the first capacitor as an output voltage actual value signal generated by a distributed static synchronous compensator sub-circuit; The voltage signal between the two ends of the DC link capacitor is defined as the actual voltage signal of the DC capacitor generated by the distributed static synchronous compensator sub-circuit.

6. The method for constructing a simulation model of a current-limiting distributed static synchronous series compensator according to claim 4, characterized in that: The current limiting module subcircuit comprises: A first thyristor having a first end, a second end and a control end, wherein the second end of the first thyristor is coupled to the power transmission line, and the control end of the first thyristor receives a first current limiting trigger pulse signal; A second thyristor, having a first end, a second end and a control end, the first end of the second thyristor is coupled to the first end of the first thyristor, and the control end of the second thyristor receives a second current limiting trigger pulse signal; A third thyristor has a first end, a second end and a control end, the first end of the third thyristor is respectively coupled to the second end of the second thyristor, the power transmission line and the first end of the fourth electronic switch, and the control end of the third thyristor receives a third current limiting trigger pulse signal; a fourth thyristor, having a first end, a second end and a control end, wherein the first end of the fourth thyristor is coupled to the second end of the first thyristor, the second end of the fourth thyristor is coupled to the second end of the third thyristor, and the control end of the fourth thyristor receives a fourth current limiting trigger pulse signal; A second inductor having a first end and a second end, wherein the first end of the second inductor is coupled to the first end of the second thyristor, and the second end of the second inductor is coupled to the second end of the third thyristor; Wherein, a voltage signal between the second end of the first thyristor and the second end of the second thyristor is defined as an input voltage signal in the current limiting module sub-circuit.

7. The method for constructing a simulation model of a current-limiting distributed static synchronous series compensator according to claim 6, characterized in that: The distributed static synchronous compensator control circuit simulation model includes a command value calculation module and an SPWM module; Constructing the distributed static synchronous compensator control circuit simulation model includes: Obtaining an output voltage actual value signal, an output current actual value signal, a DC capacitor actual voltage signal, and an active power signal generated by the distributed static synchronous compensator subcircuit; The command value calculation module uses the phase angle in the transmission line current as the phase angle reference value, that is, uses the component phase-locked loop PLL in the electromagnetic transient simulation software to obtain the phase angle of the output current actual value signal; calculates the d-axis component and q-axis component of the output current actual value signal and the d-axis component and q-axis component of the output voltage actual value signal according to the phase angle of the output current actual value signal; Taking the control of single-phase line power flow as the control target, a double closed-loop controller of a single-phase full-bridge converter is constructed, wherein the double closed-loop controller of the single-phase full-bridge converter includes a system-level controller and a device-level controller; a PI controller is used to calculate a d-axis component command value output by the system-level controller and a q-axis component command value output by the system-level controller; Inputting the d-axis component command value output by the system-level controller and the q-axis component command value output by the system-level controller to the device-level controller, and calculating the d-axis component output by the device-level controller and the q-axis component output by the device-level controller by using a PI controller; The d-axis component output by the device-level controller, the q-axis component output by the device-level controller, and the phase angle of the output current actual value signal are input into the single-phase inverse Pike transformation unit to obtain a reference voltage signal; the reference voltage signal is used as the modulation voltage of the single-phase SPWM module and is compared with the triangular carrier to generate the first distributed trigger pulse signal, the second distributed trigger pulse signal, the third distributed trigger pulse signal, and the fourth distributed trigger pulse signal.

8. The method for constructing a simulation model of a current-limiting distributed static synchronous series compensator according to claim 7, characterized in that: The method of calculating the d-axis component instruction value output by the system level controller and the q-axis component instruction value output by the system level controller by using the PI controller includes: The d-axis component of the actual value signal of the output voltage is used as the DC side capacitor voltage command value, and the DC side capacitor voltage command value is subtracted from the DC capacitor actual voltage signal. The difference is calculated by the PI controller to obtain the d-axis component command value output by the system level controller; the q-axis component of the actual value signal of the output voltage is used as the line flow command value, and the line flow command value is subtracted from the active power signal. The difference is calculated by the PI controller to obtain the q-axis component command value output by the system level controller.

9. The method for constructing a simulation model of a current-limiting distributed static synchronous series compensator according to claim 7, characterized in that: The method of calculating the d-axis component output by the device-level controller and the q-axis component output by the device-level controller by using the PI controller includes: The d-axis component command value output by the system-level controller is subtracted from the d-axis component of the output voltage actual value signal, and the difference is calculated by the PI controller to obtain the output current d-axis component command value of the single-phase full-bridge converter; the output current d-axis component command value of the single-phase full-bridge converter is subtracted from the d-axis component of the output current actual value signal, and the difference is calculated by the PI controller and then the d-axis component output by the device-level controller is obtained through the decoupling calculation link; The q-axis component command value output by the system-level controller is subtracted from the q-axis component of the output voltage actual value signal, and the difference is calculated by the PI controller to obtain the output current q-axis component command value of the single-phase full-bridge converter; the output current q-axis component command value of the single-phase full-bridge converter is subtracted from the q-axis component of the output current actual value signal, and the difference is calculated by the PI controller and then the q-axis component output by the device-level controller is obtained through the decoupling calculation link.

10. The method for constructing a simulation model of a current-limiting distributed static synchronous series compensator according to claim 6, characterized in that: The construction of the current limiting module control circuit simulation model includes: Under normal operating conditions, that is, when the line fault signal is logically invalid, the zero crossing point of the input voltage signal is detected by the ZeroDetector module in the electromagnetic transient simulation software. When the zero crossing point of the input voltage signal has a positive first-order derivative, the first current limiting trigger pulse signal and the third current limiting trigger pulse signal are logically valid, and the second current limiting trigger pulse signal and the fourth current limiting trigger pulse signal are logically invalid; when the zero crossing point of the input voltage signal has a negative first-order derivative, the first current limiting trigger pulse signal and the third current limiting trigger pulse signal are logically invalid, and the second current limiting trigger pulse signal and the fourth current limiting trigger pulse signal are logically valid; Under a short-circuit fault condition, that is, when the line fault signal is logically valid, the first current limiting trigger pulse signal, the second current limiting trigger pulse signal, the third current limiting trigger pulse signal and the fourth current limiting trigger pulse signal are all logically invalid.

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