Chip, chip controller, chip control method and storage system

Abstract

The invention provides a chip, a chip controller, a chip control method and a storage system, and relates to the technical field of semiconductors. The chip comprises a memory channel, the memory channel comprises a plurality of sub-channels, and each sub-channel independently carries out DVFSC mode switching; preset mode information is stored in the mode register, the preset mode information indicates whether the sub-channels are in the DVFSC mode or not, and the preset mode information is used for enabling the chip controller to switch the sub-channels in the DVFSC mode under the condition that the chip controller determines that the memory channel completes the DVFSC mode switching on the basis of the preset mode information. And enabling the chip controller to execute the control operation in the DVFSC mode on the plurality of sub-channels. According to the embodiment of the invention, the DVFSC function of the chip with the independent sub-channels can be realized.

Description

Background Art

[0002] With the development of semiconductor technology, in order to further reduce chip power consumption, the core voltage dynamic voltage frequency switching (Dynamic Voltage Frequency Switch Core, DVFSC) function has become one of the research directions. DVFSC is a technology that can reduce the operating voltage of the chip from a first voltage value to a second voltage value when working at a low speed.

[0003] At present, there is a lack of a technical solution that can realize the DVFSC function of a chip with multiple independent sub-channels.

[0004] Therefore, how to implement the DVFSC function of a chip with multiple independent sub-channels has become a technical problem that needs to be solved urgently.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] The present disclosure provides a chip, a chip controller, a chip control method and a storage system, which at least to some extent overcome the problem that a chip with independent sub-channels cannot implement the DVFSC function.

[0007] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0008] According to one aspect of the present disclosure, a chip is provided, including:

[0009] A memory channel includes multiple sub-channels, wherein each sub-channel independently switches the core voltage dynamic voltage frequency switching DVFSC mode;

[0010] A mode register stores preset mode information, which indicates whether the multiple sub-channels are in DVFSC mode.

[0011] The preset mode information is used to enable the chip controller to perform control operations in the DVFSC mode on multiple sub-channels when the chip controller determines that the memory channel has completed the DVFSC mode switching based on the preset mode information.

[0012] In one embodiment, the mode register further stores a plurality of first mode information.

[0013] Wherein, the plurality of first mode information correspond to the plurality of sub-channels one by one, and each first mode information is used to indicate whether the corresponding sub-channel is in the DVFSC mode;

[0014] The preset mode information includes second mode information, and the second mode information indicates whether the memory channel completes the mode switching. Wherein, when multiple first mode information are configured as a first value indicating that the corresponding sub-channel is in the DVFSC mode, the second mode information is configured as a second value indicating that the memory channel has completed the mode switching, and the second value is used to enable the chip controller to perform control operations in the DVFSC mode on multiple sub-channels.

[0015] In one embodiment, the chip further comprises:

[0016] A first register reading circuit is used to read a plurality of first mode information from a mode register of the chip;

[0017] The register writing circuit is used to configure the second mode information to the second value when the plurality of first mode information are all configured to the first value.

[0018] In one embodiment, the number of sub-channels of the memory channel is 2, the second value is 0,

[0019] The chip also includes:

[0020] A logic operation circuit, used to perform an XOR operation on the configuration values ​​of the plurality of first mode information to obtain an XOR result; wherein, when the configuration values ​​of the plurality of first mode information are the same, the XOR result is 0; and when the configuration values ​​of the plurality of first mode information are different, the XOR result is 1;

[0021] The register writing circuit is specifically used to configure an XOR result for the second mode information.

[0022] In one embodiment, the chip further comprises:

[0023] A command receiving circuit, used for receiving a register write command sent by a chip controller, where the register write command is used for controlling a target sub-channel among the multiple sub-channels to switch to a DVFSC mode;

[0024] Furthermore, the register write circuit is further configured to configure a first value for the first mode information corresponding to the target sub-channel in response to a register write command.

[0025] In one embodiment, the mode register includes a plurality of first registers, one subchannel corresponds to at least one first register, and the first mode information corresponding to each subchannel is stored in a first field of the at least one first register corresponding thereto;

[0026] The chip also includes:

[0027] A command receiving circuit, used for receiving a register write command sent by a chip controller, where the register write command is used for controlling a target sub-channel among the multiple sub-channels to switch to a DVFSC mode;

[0028] Register write circuit, specifically used for:

[0029] In response to a register write command, determining a first field in at least one first register corresponding to a target subchannel;

[0030] A first value is stored in the determined first field.

[0031] In one embodiment, each sub-channel has an independent power switching circuit;

[0032] The chip also includes:

[0033] The power switching circuit of each sub-channel is used to switch the power supply voltage of each sub-channel from a first voltage to a second voltage in response to a register write command, so as to switch each sub-channel to the DVFSC mode by switching the power supply voltage.

[0034] In one embodiment, the preset mode information is also used to indicate whether the plurality of subchannels are already in the high-speed operation mode.

[0035] The preset mode information is also used to enable the chip controller to perform control operations in the high-speed operation mode on multiple sub-channels when the chip controller determines that the memory channel has completed the high-speed operation mode switching based on the preset mode information.

[0036] In one embodiment, the chip is a low power double data rate sixth generation LPDDR6 memory.

[0037] According to another aspect of the present disclosure, a chip controller is provided for controlling the above chip, comprising:

[0038] A second register reading circuit is used to read preset mode information from a mode register of the chip;

[0039] The control circuit is used to perform control operations in the DVFSC mode on multiple sub-channels when it is determined based on preset mode information that the memory channel has completed the DVFSC mode switching.

[0040] In one embodiment, the preset mode information includes second mode information, the second mode information indicating whether the memory channel has completed the switching of the DVFSC mode, wherein, in the case where the plurality of first mode information are configured as a first value indicating that the corresponding sub-channel is in the DVFSC mode, the second mode information is configured as a second value indicating that the memory channel has completed the switching of the DVFSC mode; wherein, the plurality of first mode information correspond one-to-one to the plurality of sub-channels, and each first mode information is used to indicate whether the corresponding sub-channel is in the DVFSC mode;

[0041] And, the control circuit is specifically used to: when the second mode information is configured as a second value, perform control operations in the DVFSC mode on the multiple sub-channels.

[0042] In one embodiment, the chip controller further includes:

[0043] A command sending circuit is used to send a register write command to the chip, the register write command is used to control a target sub-channel among multiple sub-channels to switch to DVFSC mode, and the register write command is also used to configure the first mode information corresponding to the target sub-channel of the chip to a first value.

[0044] According to another aspect of the present disclosure, a chip control method is provided and applied to the above chip, the method comprising:

[0045] Get the preset mode information from the mode register of the chip;

[0046] The preset mode information is sent to the chip controller so that the chip controller performs control operations in the DVFSC mode on the multiple sub-channels.

[0047] In one embodiment, the preset mode information includes second mode information; and the method includes:

[0048] Reading a plurality of first mode information from a mode register of the chip, wherein the plurality of first mode information corresponds to a plurality of sub-channels one by one, and each first mode information is used to indicate whether the corresponding sub-channel is in the DVFSC mode;

[0049] In the case that the plurality of first mode information are all configured as the first value, the second mode information is configured as the second value, so that the chip controller performs a control operation in the DVFSC mode on the plurality of sub-channels based on the second value.

[0050] In one embodiment, the number of sub-channels of the memory channel is 2, the second value is 0,

[0051] In a case where the plurality of first mode information are all configured as the first value, configuring the second mode information as the second value includes:

[0052] Performing an XOR operation on the configuration values ​​of the plurality of first mode information to obtain an XOR result; wherein, when the configuration values ​​of the plurality of first mode information are the same, the XOR result is 0; and when the configuration values ​​of the plurality of first mode information are different, the XOR result is 1;

[0053] The XOR result is configured for the second mode information.

[0054] According to another aspect of the present disclosure, a chip control method is provided, the method being applied to a chip controller of a chip, wherein the chip is as above;

[0055] Methods include:

[0056] Read the preset mode information from the mode register of the chip;

[0057] In a case where it is determined based on the preset mode information that the memory channel has completed the DVFSC mode switching, a control operation in the DVFSC mode is performed on the plurality of sub-channels.

[0058] In one embodiment, the preset mode information includes second mode information,

[0059] Before performing the control operation in the DVFSC mode on the multiple sub-channels, the method further includes:

[0060] When the second mode information is configured as the second value, the memory channel has completed the DVFSC mode switching.

[0061] According to another aspect of the present disclosure, there is provided a storage system, comprising:

[0062] Chip, chip as above; and,

[0063] Chip controller, chip controller as above.

[0064] The chip, chip controller, chip control method and storage system provided by the embodiments of the present disclosure, when multiple sub-channels of the same memory channel can independently switch to the DVFSC mode, since the preset mode information in the mode register can indicate whether the multiple sub-channels are in the DVFSC mode, accordingly, the chip controller can determine based on the preset mode information that the memory channel has completed the DVFSC mode switching and perform control operations on the multiple sub-channels under the DVFSC mode, thereby allowing the multiple sub-channels of the same memory channel to synchronously perform operations under the DVFSC mode, avoiding internal errors of the chip controller caused when the multiple sub-channels are not in the DVFSC mode at the same time, and enabling the chip controller to perform normal control operations under the DVFSC mode on the multiple sub-channels, thereby realizing the DVFSC function of the chip with independent sub-channels.

[0065] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0067] Figure 1 A schematic diagram showing an exemplary sub-channel command timing provided by an embodiment of the present disclosure is shown;

[0068] Figure 2 A system architecture diagram of a storage system provided by an embodiment of the present disclosure is shown;

[0069] Figure 3 A schematic diagram of an exemplary chip structure provided by an embodiment of the present disclosure is shown;

[0070] Figure 4 A schematic diagram of the structure of a chip provided by an embodiment of the present disclosure is shown;

[0071] Figure 5 A schematic diagram showing the structure of another chip provided by an embodiment of the present disclosure is shown;

[0072] Figure 6 A schematic diagram of the structure of a mode register provided by an embodiment of the present disclosure is shown;

[0073] Figure 7 A schematic diagram showing the structure of another chip provided by an embodiment of the present disclosure is shown;

[0074] Figure 8 A schematic diagram showing the structure of another chip provided by an embodiment of the present disclosure is shown;

[0075] Fig. 9 A circuit diagram of an exemplary sub-channel provided by an embodiment of the present disclosure is shown;

[0076] Fig.10 A schematic diagram of the structure of a chip controller provided by an embodiment of the present disclosure is shown;

[0077] Fig.11 A schematic diagram of a chip control method provided by an embodiment of the present disclosure is shown;

[0078] Fig.12 A logic schematic diagram of a chip control method provided by an embodiment of the present disclosure is shown;

[0079] Fig.13 A schematic flow chart of a chip control method provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0080] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0081] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0082] It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0083] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0084] It should be noted that the modifications of "one" and "plurality" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0085] Dynamic Voltage Frequency Switch Core (DVFSC) is a technology that can reduce the operating voltage of a chip from a first voltage value (such as 1.05V) to a second voltage value (such as 0.9V) when operating at a low speed.

[0086] The inventors have found through research that for chips with memory channels, taking the fifth-generation Low Power Double Data Rate 5 (LPDDR5) Synchronous Dynamic Random Access Memory (SDRAM) as an example, each memory channel will have a set of Command / Address (CA) buses and Mode Registers (MR). In order to reduce power consumption, when DVFSC is enabled, a part of the circuit inside the chip will switch the voltage from 1.05V to 0.9V, and the corresponding chip operating frequency will be reduced, and the clock frequency (timing) of the array will also switch.

[0087] And, for chips with independent sub-channels, taking the sixth-generation Low Power Double Data Rate 6 (LPDDR6) SDRAM as an example, LPDDR6 adopts the concept of sub-channels, and each memory channel can be composed of two independent sub-channels, where the two sub-channels can be integrated on the same chip (die). Exemplarily, each sub-channel can have an independent CA bus and clock (Clock, CK) line. And, each sub-channel can have its own mode register. And, the two sub-channels can share the same power supply.

[0088] The inventors have found that chips with independent sub-channels often cannot perform the DVFSC function normally.

[0089] Based on the above problems, the inventors have found through research that the reason why the DVFSC function cannot be performed normally is that for a chip with multiple sub-channels, since the multiple sub-channels are independent of each other, each sub-channel can enter the DVFSC mode independently. When different sub-channels of the same storage channel do not enter the DVFSC mode synchronously, it may cause an internal error in the chip controller.

[0090] For example, taking each storage channel including 2 sub-channels as an example, Figure 1 A schematic diagram of an exemplary sub-channel command timing provided by an embodiment of the present disclosure is shown.

[0091] like Figure 1As shown, when the chip controller needs to switch a certain memory channel to DVFSC mode, it will send the register write command (Mode Register Writing, MRW) to multiple sub-channels at the same time. However, since the two sub-channels are independent of each other, the MRW commands sent by each sub-channel to the chip-related circuits do not occur synchronously. For example, when the first sub-channel SC0 first receives the MRW command sent by the chip controller, it will switch the power supply to a low voltage (such as VDD2L) through the chip-related circuits. However, the second sub-channel SC1 did not receive the MRW command, and it cannot switch to DVFSC mode. It still performs read and write operations through read commands (Read, RD) and write commands (Write, WR) in high-speed operation mode with high voltage (such as VDD2H) as power supply. At this time, since one of the two sub-channels is in DVFSC mode and the other is in high-speed operation mode, the chip controller generates an error.

[0092] Based on this, the embodiments of the present disclosure provide a chip, a chip controller, a chip control method and a storage system, which can be applied to chip usage scenarios. In particular, the usage scenarios of LPDDR6. Through the embodiments of the present disclosure, multiple sub-channels of the same memory channel can synchronously perform operations in the DVFSC mode, avoiding internal errors of the chip controller caused when multiple sub-channels are not in the DVFSC mode at the same time, and enabling the chip controller to perform normal control operations in the DVFSC mode on multiple sub-channels, thereby realizing the DVFSC function of the chip with independent sub-channels.

[0093] Before describing the technical solutions provided by the embodiments of the present disclosure, the technical terms involved in the embodiments of the present disclosure are described first.

[0094] (1) Write clock (WCK), which is used to perform write operations.

[0095] (2) Optional read clock (RDQS), which is used for read operations.

[0096] (3) Command / Address (CA) bus, which is used to transmit address signals and command signals between the chip and external devices.

[0097] (4) Data In or Out (DQ) line, which is used to transmit data.

[0098] (5) Mode Register (MR), which is used to store information related to the chip status or configuration. The mode register is used to define the various programmable operation modes of the chip. The information in the mode register can be modified by programming.

[0099] Exemplarily, each chip may include at least one mode register. For example, each mode register may include multiple fields, wherein a field may include one or more bits. Specifically, a field may store a mode information of a chip, and different values ​​on a field correspond to different information contents of the mode information.

[0100] (6) Mode Register Writing (MRW), used to write data to the mode register of the memory. For example, MRW requires four clock rising edges to transfer the address (MA[5:0]) and operation data (OP[7:0]) to the chip particles. MRW can be completed through the coordination of the clock enable signal (CKE), the chip select signal (CS) and CA[5:0].

[0101] (7) Mode Register Read (MRR) command, which is used to read the value of the mode register of the chip particle. Exemplarily, the specified mode register can be accessed by specifying the register address, such as MA[6:0] (i.e., a mode register address format). Exemplarily, the read data can be returned in the form of DQ. For example, it can be returned in the form of DQ[7:0] (i.e., a data format).

[0102] After introducing the above technical terms, the technical solutions provided by the embodiments of the present disclosure are described below.

[0103] For ease of understanding, the present disclosure first describes the storage system involved. Figure 2 FIG. 1 shows a system architecture diagram of a storage system provided by an embodiment of the present disclosure. Figure 2 As shown, the storage system 20 may include a chip controller 21 and a chip 22. Each of them will be described below.

[0104] The chip controller 21 may refer to a device having a chip control function. Exemplarily, the chip controller 21 may be a host device (Host), such as a system on a chip (System on a Chip, SOC), etc. It should be noted that the host device may also be other host devices such as a processor (Central Processing Unit, CPU), and there is no specific limitation on this.

[0105] In some embodiments, the chip controller 21 may read the mode information stored in the mode register from the chip 22. Exemplarily, the chip controller 21 may read the mode information of the mode register through an MRR command.

[0106] In some embodiments, the chip controller 21 may write mode information to the mode register of the chip 22. For example, the chip controller 21 may write mode information to the mode register through an MRW command.

[0107] In some embodiments, the chip controller 21 may control the chip to perform operations by issuing control commands. For example, the chip controller 21 may send an RD command, a WR command, and the like.

[0108] After introducing the chip controller 21 , the chip 22 will be described next.

[0109] As for the chip 22, it can be a dynamic random access memory (DRAM) with independent sub-channels and mode registers. Exemplarily, the chip can be one of double data rate synchronous dynamic random access memory (DDR SDRAM), low data rate double data rate synchronous dynamic random access memory (LPDDRSDRAM), graphic double data rate synchronous dynamic random access memory (GDDR SDRAM), and Rambus-dynamic random access memory (RDRAM, i.e., a type of DRAM). It should be noted that the chip 22 of the embodiment of the present disclosure can also be other types of DRAM with independent sub-channels and mode registers, and there is no specific limitation on this.

[0110] In the embodiment of the present disclosure, the chip 22 may include a memory channel and a mode register. Exemplarily, the chip 12 may include one or more memory channels. In another exemplary embodiment, the chip 22 may include one or more mode registers.

[0111] For a memory channel, one memory channel may include multiple sub-channels, and the multiple sub-channels may independently switch the DVFSC mode.

[0112] Exemplarily, taking LPDDR6 as an example, one memory channel may include two sub-channels. Figure 3 FIG. 1 shows an exemplary chip structure diagram provided by an embodiment of the present disclosure. Figure 3 As shown, the memory channel may include a first sub-channel SC0 and a second sub-channel SC1.

[0113] A sub-channel may include multiple bank groups (Bank Group, BG). For example, any one of the first sub-channel SC0 and the second sub-channel SC1 may include four bank groups BG0-BG3. It should be noted that the number of bank groups is not specifically limited in the embodiments of the present disclosure.

[0114] Furthermore, a bank group may include multiple physical banks (Bank, BK), for example, any one of the bank groups BG0-BG3 may include four physical banks BK0-BK3. In the embodiments of the present disclosure, there is no specific limitation on the number of physical banks in a bank group.

[0115] Multiple subchannels can transmit 24 bits of data in parallel. Figure 3 For example, each independent sub-channel can transmit the WCK signal through the WCK line, transmit the command and address through the 4-bit CA bus (4CAs), transmit the CK signal through the CK line, transmit the RDQS signal through the RDQS line, and transmit 12-bit data through the 12-bit data transmission bus (12DQs). Accordingly, since each sub-channel can transmit 12-bit data, 24-bit data transmission can be achieved through parallel transmission of 2 sub-channels.

[0116] After introducing the memory channel, we will continue to explain the mode register.

[0117] For the mode register, it may store the relevant information of the DVFSC mode. Exemplarily, the mode register may include one or more fields for storing the relevant information of the DVFSC mode. Among them, a field may include one or more bits of a mode register. Alternatively, a field may be composed of bits of different mode registers, which is not specifically limited.

[0118] After an overall introduction to the storage system provided by the embodiment of the present disclosure, the chip involved in the embodiment of the present disclosure will be described next.

[0119] Figure 4 FIG. 1 shows a schematic diagram of the structure of a chip provided by an embodiment of the present disclosure. Figure 4 As shown, the chip 22 may include a memory channel 221 and a mode register 222. The following will describe each of them one by one.

[0120] For the memory channel 221, it may include multiple sub-channels 2211, for example, one memory channel 221 may include two sub-channels 2211. And each sub-channel 2211 independently switches the DVFSC mode. Exemplarily, each sub-channel 2211 may independently enter the DVFSC mode by switching the power supply voltage from a first voltage to a second voltage. The first voltage is greater than the second voltage.

[0121] Wherein, for the first voltage, it can be a voltage for implementing the DVFSC function of the chip. Exemplarily, the first voltage can be a voltage for implementing a high speed operation mode of the chip. Wherein, the high speed operation mode can also be referred to as a normal power mode, a high performance operation mode, etc. Exemplarily, the first voltage can be a power supply voltage V2DD2H specified by the LPDDR specification. In an example, the level of the first voltage can range from 1.01V to 1.12V. For example, the first voltage can be 1.05V.

[0122] Wherein, for the second voltage, it can be a voltage for implementing the DVFSC function of the chip. Exemplarily, the second voltage can be a voltage for implementing a low speed operation mode (low speed mode) of the chip, such as a DVFSC mode. Wherein, the low speed operation mode can also be referred to as a low power mode, a low performance operation mode, etc. Exemplarily, the second voltage can be a power supply voltage V2DD2L specified by the LPDDR specification. In an example, the second voltage can range from 0.87V to 0.97V. For example, the second voltage can be 0.9V.

[0123] In one example, the first voltage and the second voltage may be received from outside the chip 22, such as from a power management integrated circuit (PMIC). Exemplarily, the first voltage and the second voltage may be received from outside the chip 22 through different power lines.

[0124] It should be noted that other contents of the memory channel 221 can refer to the above-mentioned embodiments of the present disclosure in combination with Figure 3 The relevant description is omitted here.

[0125] After the memory channel 221 is introduced, the mode register 222 will be described next.

[0126] The mode register 222 stores preset mode information X0. The preset mode information X0 indicates whether the multiple sub-channels are in the DVFSC mode. The preset mode information X0 is used to enable the chip controller to perform control operations in the DVFSC mode on the multiple sub-channels when the chip controller determines that the memory channel 221 has completed the DVFSC mode switching based on the preset mode information X0.

[0127] Among them, the control operation in the DVFSC mode may be an operation for controlling the chip to enable it to perform the required functions in the DVFSC mode. In some embodiments, the control operation in the DVFSC mode may be issuing control commands, etc. For example, read and write commands may be issued to multiple sub-channels respectively so that they can perform read and write operations in the DVFSC mode. It should be noted that the control operation in the DVFSC mode may also be other control operations in the DVFSC mode, and there is no specific limitation on this.

[0128] In some embodiments, Figure 5 FIG. 2 shows a schematic diagram of the structure of another chip provided by an embodiment of the present disclosure. Figure 5 As shown, in the case where the mode memory 222 further stores a plurality of first mode information X1, the preset mode information X0 may include the second mode information X2.

[0129] Next, the first mode information X1 and the second mode information X2 are described one by one.

[0130] Among them, a plurality of first mode information X1 corresponds to a plurality of sub-channels 2211 one by one, and each first mode information X1 is used to indicate whether the corresponding sub-channel is in the DVFSC mode. Exemplarily, the first first mode information X1 is used to indicate whether the first sub-channel in the memory channel 221 is in the DVFSC mode; ...; the Nth first mode information X1 is used to indicate whether the Nth sub-channel in the memory channel 221 is in the DVFSC mode, and N is any positive integer greater than or equal to 2.

[0131] In some embodiments, each first mode information X1 may be implemented as a first field of a mode register. The first field may include one or more bits. Exemplarily, the first field may be represented as MRx OP[y]. It should be noted that the first field may be located in one register or in multiple registers, without specific limitation.

[0132] In one example, when the first mode information X1 is set to a first value, that is, when the first value is written in the first field, it can indicate that the subchannel corresponding to the first mode information X1 is in the DVFSC mode. Optionally, when the first mode information X1 is set to a third value, that is, when the third value is written in the first field, it can indicate that the subchannel corresponding to the first mode information X1 is not in the DVFSC mode. Exemplarily, the third value can indicate that the subchannel corresponding to the first mode information X1 is in the high-speed operation mode.

[0133] In a specific example, one of the first value and the third value is 0, and the other is 1. For example, when MRx OP[y]=0, it indicates that the corresponding subchannel is in high-speed operation mode. And, when MRx OP[y]=1, it indicates that the corresponding subchannel is in DVFSC mode.

[0134] Regarding the specific storage location of the first mode information X1, in some embodiments, Figure 6 FIG. 2 shows a schematic diagram of the structure of a mode register provided by an embodiment of the present disclosure. Figure 6 As shown, the mode register 222 includes multiple first registers MR1, one sub-channel 2211 corresponds to at least one first register MR1, and the first mode information X1 corresponding to each sub-channel 2211 is stored in the first field of at least one first register MR1 corresponding to the sub-channel 221.

[0135] In some other embodiments, part or all of the first mode information X1 may be stored in the same first mode register.

[0136] After introducing the first mode information X1, the second mode information X2 will be described next.

[0137] The second mode information X2 is used to indicate whether the memory channel has completed the mode switching. In one example, when the configuration values ​​of multiple first mode information X1 are the same (the same as the first value or the same as the third value) so that the second mode information X2 is configured as the second value, the second mode information X2 is used to indicate that the memory channel 221 completes the switching from the high-speed operation mode to the DVFSC mode, or completes the switching from the DVFSC mode to the high-speed operation mode. In another example, when the configuration values ​​of multiple first mode information X1 are all the first value, the second mode information X2 is configured as the second value (the second mode information X2 is configured as the fourth value when part or all of the first mode information X1 is the second value), the second mode information X2 is used to indicate that the memory channel 221 completes the switching from the high-speed operation mode to the DVFSC mode. In some embodiments, the second mode information X2 can be written by the chip. And, the second mode information X2 can be read by the chip controller through the MRR command.

[0138] In some embodiments, the second mode information X2 can be implemented as a second field of a mode register. The second field can include one or more bits. Exemplarily, the second field can be represented as MRa OP[b]. It should be noted that the second field can be located in one register or multiple registers, and there is no specific limitation on this.

[0139] In one example, when the second mode information X2 is set to the second value, that is, when the second value is written in the second field, it can indicate that the memory channel 221 has completed the mode switching. Optionally, when the second mode information X2 is set to the fourth value, that is, when the fourth value is written in the second field, it can indicate that the memory channel 221 is in the process of mode switching.

[0140] In a specific example, one of the second value and the fourth value is 0, and the other is 1. For example, when MRa OP[b]=0, it indicates that the memory channel 22 has completed the mode switching. And, when MRa OP[b]=1, it indicates that the memory channel 221 is in the process of mode switching.

[0141] The specific storage location of the second mode information X2 may be located in one or more first registers. For example, in the first register corresponding to any one or more subchannels. Alternatively, it may be located in one or more second registers in the mode memory. The present embodiment does not specifically limit the specific storage location of the second mode information X1.

[0142] Regarding the configuration method of the second mode information X2, the second mode information X2 can be configured as a second value when multiple first mode information are configured as first values, and the configured second value is used to enable the chip controller to perform control operations in the DVFSC mode on multiple sub-channels.

[0143] Optionally, when the second mode information X2 is configured as the fourth value, the chip controller may stop the control operation on the plurality of sub-channels.

[0144] Optionally, when the second mode information X2 is configured as the second value because the plurality of first mode information are configured as the third value, the configured second value may be used to enable the chip controller to perform control operations in the high-speed operation mode on the plurality of sub-channels.

[0145] The chip provided by the embodiment of the present disclosure, when multiple sub-channels of the same memory channel can independently switch to the DVFSC mode, because multiple first mode information in the mode register can indicate whether the multiple sub-channels are in the DVFSC mode, and because the second mode information in the mode register is configured as a second value indicating that the memory channel has completed the DVFSC mode switch when the multiple first mode information are all configured as the first value indicating that the corresponding sub-channel is in the DVFSC mode. Accordingly, the chip controller can perform control operations in the DVFSC mode on multiple sub-channels when it is determined based on the second value that the memory channel has completed the DVFSC mode switch, and multiple sub-channels of the same memory channel can synchronously perform operations in the DVFSC mode, avoiding internal errors of the chip controller caused when multiple sub-channels are not in the DVFSC mode at the same time, and enabling the chip controller to perform normal control operations in the DVFSC mode on multiple sub-channels, thereby realizing the DVFSC function of the chip with independent sub-channels.

[0146] Also, it should be noted that the chip controller only needs to use the second mode information to quickly and accurately determine whether multiple sub-channels of the same memory channel have synchronously entered the DVFSC mode, so that after quickly determining that the memory channel has completed the DVFSC mode switch, the multiple sub-channels can be quickly controlled in the DVFSC mode, thereby improving the control rate of the chip.

[0147] In some other embodiments, the preset mode information may be first mode information. Accordingly, after acquiring multiple first mode information, the chip controller may perform control operations in the SVFSC mode on multiple sub-channels when the multiple first mode information are all first values. The specific content of the first mode information may refer to the relevant description of the above-mentioned part of the embodiment of the present disclosure, and will not be described in detail.

[0148] In the chip provided by the embodiment of the present disclosure, when multiple sub-channels of the same memory channel can independently switch to the DVFSC mode, since the preset mode information in the mode register can indicate whether the multiple sub-channels are in the DVFSC mode, accordingly, the chip controller can determine based on the preset mode information that the memory channel has completed the DVFSC mode switching and perform control operations on the multiple sub-channels under the DVFSC mode, thereby allowing the multiple sub-channels of the same memory channel to synchronously perform operations under the DVFSC mode, avoiding internal errors of the chip controller caused when the multiple sub-channels are not in the DVFSC mode at the same time, allowing the chip controller to perform normal control operations under the DVFSC mode on the multiple sub-channels, thereby realizing the DVFSC function of the chip with independent sub-channels.

[0149] In one embodiment, the preset mode information is also used to indicate whether multiple sub-channels are in high-speed operation mode. The preset mode information is also used to enable the chip controller to perform control operations in the high-speed operation mode on the multiple sub-channels when it is determined based on the preset mode information that the memory channel has completed the high-speed operation mode switch.

[0150] For example, when the second mode information X2 is configured as the second value because multiple first mode information are configured as the third value, the chip controller receives the second value and determines that the chip controller has sent a register write command for controlling the sub-channel to enter the high-speed operation mode, it can be determined that the memory channel has completed the switching of the high-speed operation mode, and the controller can perform control operations in the high-speed operation mode on multiple sub-channels.

[0151] Through this embodiment, the chip controller can determine based on preset mode information that the memory channel has completed the high-speed operation mode switching and perform control operations on multiple sub-channels in the high-speed operation mode, so that multiple sub-channels of the same memory channel can synchronously perform operations in the high-speed operation mode, avoiding internal errors of the chip controller caused when multiple sub-channels are not in the high-speed operation mode at the same time, so that the chip controller can perform normal control operations in the high-speed operation mode on multiple sub-channels, thereby realizing the high-speed operation mode function of the chip with independent sub-channels.

[0152] After the initial introduction to the chip, the following section will describe other modules or circuits of the chip.

[0153] In some embodiments, Figure 7 FIG. 2 shows a schematic diagram of the structure of another chip provided by an embodiment of the present disclosure. Figure 7 As shown, the chip 22 may further include: a first register reading circuit 223 and a register writing circuit 224 .

[0154] The first register reading circuit 223 is used to read a plurality of first mode information X1 from the chip mode register 222. It should be noted that the first register reading circuit 223 can be any circuit having a mode information reading function, and there is no specific limitation on this.

[0155] The register writing circuit 224 is used to configure the second mode information X2 to the second value when the plurality of first mode information X1 are all configured to the first value. It should be noted that the register writing circuit 224 can be any circuit having a mode information writing function, and there is no specific limitation on this.

[0156] In one embodiment, the register write circuit 224 may also configure the second mode information X2 to the second value when all the first mode information X1 is configured to the third value; and, configure the second mode information X2 to the fourth value when part of the first mode information X1 is configured to the first value and another part of the first mode information X1 is configured to the first value.

[0157] In another embodiment, the register write circuit 224 may further configure the second mode information X2 to be the fourth value when part or all of the first mode information X1 is configured to be the third value.

[0158] Through the embodiment of the present disclosure, the second mode information X2 can be accurately set according to multiple first mode information X1 through the first register reading circuit 223 and the register writing circuit 224, so that the chip controller can accurately control multiple sub-channels according to the accurate second mode information X2, thereby improving the reliability of chip control.

[0159] In some embodiments, Figure 8 A schematic diagram of the structure of another chip provided by an embodiment of the present disclosure is shown. Figure 8 and Figure 7 The difference is that the chip may further include a logic operation circuit 225 .

[0160] The logic operation circuit is used to perform logic operation on the configuration values ​​of the plurality of first mode information to obtain a logic operation result. It should be noted that the logic operation circuit can be any circuit having a logic operation function, and there is no specific limitation on this.

[0161] Accordingly, the register write circuit 224 is specifically used to configure a logic operation result for the second mode information X2.

[0162] In one embodiment, when the number of sub-channels of the memory channel is 2, continue to refer to Figure 8 , the logic operation circuit may include an XOR gate XOR1. Accordingly, the second value may be 0; and the fourth value may be 1.

[0163] At this time, the logic operation circuit is used for a plurality of first mode information (ie Figure 8 The configuration values ​​of the first mode information X11 and the first mode information X12 shown in the figure are XORed to obtain an XOR result. Wherein, when the configuration values ​​of the plurality of first mode information are the same, for example, when the first mode information X11 and the first mode information X12 are both the first value or the third value, the XOR result is 0.

[0164] Furthermore, when the configuration values ​​of the plurality of first mode information are different, for example, when one of the first mode information X11 and the first mode information X12 is the first value and the other is the third value, the XOR result is 1.

[0165] The register writing circuit is specifically used to configure an XOR result for the second mode information. Exemplarily, when the XOR result is 1, MRa OP[b]=1; when the XOR result is 0, MRa OP[b]=0.

[0166] In this embodiment, the XOR gate can output 0 when the two input values ​​are the same, and output 1 when the two input values ​​are different. Accordingly, through the XOR gate, when the first mode information corresponding to the two sub-channels is 1 (both in the DVFSC mode) or 0 (both in the high-speed operation mode), the XOR gate can output 0. And, when one of the first mode information corresponding to the two sub-channels is 1 (in the DVFSC mode) and the other is 0 (in the high-speed operation mode), the XOR gate can output 1. Therefore, through the XOR result, the chip controller can stop the control operation in the DVFSC mode or stop the control operation in the high-speed operation mode when the chip is switching from the high-speed operation mode to the DVFSC mode, or from the DVFSC mode to the high-speed operation mode when the two sub-channels are not in the same mode. In other words, the chip controller will only control the chip when both sub-channels are in the high-speed operation mode or the DVFSC mode, thereby avoiding chip errors caused by the inconsistency of the operation modes of the two sub-channels and improving the reliability of chip control.

[0167] In another embodiment, the logic operation circuit may also be an XNOR gate. Accordingly, the second value may be 1, and the fourth value may be 0.

[0168] In yet another embodiment, when the first value is 1, the logic operation circuit may further include an AND gate. Accordingly, the second value may be 1, and the fourth value may be 0.

[0169] Through the OR gate, since the OR gate can output 1 when all the inputs are 1. Accordingly, through the OR gate, when the first mode information corresponding to multiple sub-channels is 1 (all in DVFSC mode), the XOR gate can output 1. And, when the first mode information corresponding to at least one sub-channel is 0 (in high-speed operation mode), the XOR gate can output 0. Therefore, through the XOR result, the chip controller can perform control operations in the DVFSC mode when the chip switches from the high-speed operation mode to the DVFSC mode and multiple sub-channels are in the DVFSC mode. The chip error caused by the inconsistent operation modes of the two sub-channels is avoided, and the reliability of chip control is improved.

[0170] In yet another embodiment, when the first value is 0, the logic operation circuit may further include an OR gate. Accordingly, the second value may be 0, and the fourth value may be 1.

[0171] It should be noted that the beneficial effects of the OR gate can be found in the relevant description of the AND gate in the above part of the embodiment of the present disclosure, and will not be elaborated on here.

[0172] In some embodiments, the first mode information X1 may be written by the chip controller through an MRW command. Accordingly, the chip may further include a command receiving circuit.

[0173] The command receiving circuit is used to receive the MRW command sent by the chip controller. The MRW command is used to control the target subchannel among multiple subchannels to switch to the DVFSC mode. Exemplarily, the target subchannel may be one or more subchannels that need to be switched to the DVFSC mode as indicated by the MRW command. It should be noted that the command receiving circuit may be any circuit capable of receiving MRW commands, such as an input / output (IO) circuit, etc., and no specific limitation is made to this.

[0174] Accordingly, the register write circuit 224 is further configured to configure a first value for the first mode information X1 corresponding to the target subchannel in response to the MRW command. Figure 8 If a MRW command for controlling the second sub-channel to perform the DVFSC mode is received, the first mode information X12 may be configured as the first value.

[0175] Through this embodiment, when the chip controller can switch the mode of the target sub-channel through the MRW command, after the command receiving circuit receives the MRW command, the register write circuit can respond to the MRW command to promptly configure the first mode information corresponding to the target sub-channel, so that the first mode information of the mode register can accurately represent the mode state of each sub-channel, and then the second mode information can be accurately determined based on the accurate first mode information, thereby improving the accuracy of chip management based on the second mode information.

[0176] In some embodiments, when the mode register includes multiple first registers, the chip further includes: a command receiving circuit.

[0177] The command receiving circuit is used to receive the MRW command sent by the chip controller. The specific content of the MRW command can refer to the relevant description of the above part of the embodiment of the present disclosure, which will not be repeated here.

[0178] And, the register write circuit in the chip is further specifically used to: determine a first field in at least one first register corresponding to the target sub-channel in response to the MRW command. Exemplarily, taking the memory channel including the first sub-channel SC0 and the second sub-channel SC1 as an example, after the chip controller sends the MRW command for switching the DVFSC mode of the first sub-channel SC0, the first field SC0_MRx OP[y] in the first register of the first sub-channel SC0 can be determined.

[0179] And, the register writing circuit is further used to store the first value in the determined first field. Continuing with the previous example, SC0_MRx OP[y]=1.

[0180] Since the first field of one or more first registers corresponding to each sub-channel is used to store the first mode information corresponding to the sub-channel, through the search of the first field in the disclosed embodiment, the first mode information can be accurately written according to the switching situation of the DVFSC mode, and then the second mode information can be accurately determined based on the accurate first mode information, thereby improving the accuracy of chip management based on the second mode information.

[0181] In some embodiments, each sub-channel has an independent power switching circuit. The power switching circuit can selectively provide the first voltage or the second voltage to the corresponding sub-channel. For example, Fig. 9 FIG. 2 shows a circuit diagram of an exemplary sub-channel provided by an embodiment of the present disclosure. Fig. 9 As shown, each sub-channel may include a first sub-circuit using the first voltage as the power supply voltage, such as an array-related circuit (Core), that is, a bus and a buffer circuit from the array (Array) to the input / output (In / Out). And, each sub-channel also includes a second sub-circuit selectively using the first voltage or the second voltage as the power supply voltage, such as a first data pass. And, each sub-channel may include a third sub-circuit using the first voltage as the power supply voltage, such as a second data pass.

[0182] Accordingly, the chip further includes: a power switching circuit 2211A for each sub-channel.

[0183] The power switching circuit 2211A of each sub-channel is used to switch the power supply voltage of the sub-channel from the first voltage to the second voltage in response to the MRW command, so as to switch each sub-channel to the DVFSC mode by switching the power supply voltage. The first voltage and the second voltage can refer to the relevant description of the above part of the embodiment of the present disclosure, which will not be repeated here.

[0184] Through this embodiment, since each sub-channel includes an independent power switching circuit, each sub-channel can switch between the first voltage and the second voltage through the power switching circuit, and then switch between the high-speed operation mode and the DVFSC mode by switching the power supply voltage, so that each sub-channel can independently switch the DVFSC mode, thereby improving the chip control accuracy.

[0185] In one example, see Fig. 9 The power switching circuit 2211A includes a first switch M1 and a second switch M2. Exemplarily, the first switch M1 and the second switch M2 may be P-type metal-oxide-semiconductor field-effect transistors (MOSFET). It should be noted that the first switch M1 and the second switch M2 may also be implemented as other switches that can be turned on or off according to a control signal, such as N-type MOSFET (NMOS), etc., and there is no specific limitation on this.

[0186] The first switch M1 includes a first control terminal, a first connection terminal and a second connection terminal.

[0187] Wherein, the first control terminal is used to receive a DVFSC signal. Exemplarily, the DVFSC signal can be used to drive the first switch M1 to close and the second switch M2 to open in the high-speed operation mode. And, drive the first switch M1 to open and the second switch M2 to close in the DVFSC mode. Exemplarily, the level of the DVFSC signal can be related to whether the sub-channel is in the DVFSC mode. For example, when the first switch M1 is a PMOS, when the sub-channel is in the DVFSC mode, the DVFSC signal can be a high-level signal. Similarly, when the sub-channel is in the high-speed operation mode, the DVFSC signal can be a low-level signal.

[0188] The first connection terminal is connected to a first voltage source. The first voltage source is used to provide a power supply voltage of a first voltage. Optionally, multiple sub-channels can use the same first voltage source. For example, the same first voltage source can be the same PMIC.

[0189] The second connection end is connected to the corresponding sub-channel. Fig. 9 The second connection end of the first switch M1 is connected to the second sub-circuit of the sub-channel, and is used to provide the first voltage to the second sub-circuit.

[0190] And, when a DVFSC signal of a first level is applied to the first control terminal, the first connection terminal and the second connection terminal can be disconnected to prevent the first voltage of the first connection terminal from being applied to the subchannel by disconnecting the first connection terminal and the second connection terminal. Exemplarily, the first level can be a high level signal.

[0191] After the first switch M1 is introduced, the second switch M2 is described next.

[0192] The second switch M2 includes a second control terminal, a third connection terminal and a fourth connection terminal.

[0193] The second control terminal is used to receive the negation signal of DVFSC, such as Fig. 9 In

[0194] The third connection terminal is connected to a second voltage source. The second voltage source is used to provide a power supply voltage of the second voltage. Optionally, multiple sub-channels can use the same second voltage source. For example, the same second voltage source can be the same PMIC.

[0195] The fourth connection end is connected to the corresponding sub-channel. Fig. 9 The second connection end of the second switch M2 is connected to the second sub-circuit of the sub-channel, and is used to provide a second voltage to the second sub-circuit.

[0196] And, when the first level negation signal is applied to the second control terminal, the third connection terminal and the fourth connection terminal are turned on, so that the second voltage of the third connection terminal is applied to the sub-channel through the conduction of the third connection terminal and the fourth connection terminal. Exemplarily, when the first level is high, the first level negation signal is low.

[0197] Accordingly, the chip also includes:

[0198] The signal sending module is used to send a DVFSC signal corresponding to a first level to a first control terminal of a first switch corresponding to a target subchannel in response to a register write command; and to apply a second level negation signal to a second control terminal of a second switch corresponding to the target subchannel.

[0199] Through this embodiment, through the DVFSC signal and the negation signal of the DVFSC signal, the first switch M1 and the second switch M2 can be selectively turned on to selectively provide the first voltage or the second voltage to the corresponding sub-channel. Thereby, it can be ensured that the sub-channel can switch between the high-speed operation mode and the DVFSC mode arbitrarily and accurately. Accordingly, each sub-channel can switch the DVFSC mode independently, thereby improving the chip control accuracy.

[0200] In some embodiments, chip 22 may be LPDDR6.

[0201] Since the memory channel of LPDDR6 includes multiple independent sub-channels, through this embodiment, the control operation in the DVFSC mode can be performed on the memory channel of LPDDR6 only after the multiple sub-channels in LPDDR6 have entered the DVFSC mode, thereby avoiding internal errors of the chip controller caused when the multiple sub-channels of LPDDR6 are not in the DVFSC mode at the same time, so that the chip controller can perform normal control operations in the DVFSC mode on the multiple sub-channels, thereby realizing the DVFSC function of LPDDR6.

[0202] After introducing the chip 22, the chip controller provided by the embodiment of the present disclosure is described below. The chip controller provided by the embodiment of the present disclosure is used to combine the above-mentioned parts of the embodiment of the present disclosure with the chip controller provided by the embodiment of the present disclosure. Figures 1 to 9 A chip 22 is shown to perform control.

[0203] Fig.10 FIG. 1 shows a schematic diagram of the structure of a chip controller provided by an embodiment of the present disclosure. Fig.10 As shown, the chip controller 21 may include a second register reading circuit 211 and a control circuit 212 .

[0204] The second register reading circuit 211 is used to read the preset mode information X0 from the mode register of the chip. It should be noted that the second register reading circuit 211 can be any circuit with a mode information reading function, such as an IO circuit, etc., and there is no specific limitation on this.

[0205] The control circuit 212 is used to perform control operations in the DVFSC mode on multiple sub-channels 2211 when it is determined based on the preset mode information that the memory channel 221 has completed the DVFSC mode switch. It should be noted that the control circuit 212 can be any circuit with a chip control function, such as an IO circuit, etc., and there is no specific limitation on this. Exemplarily, the control circuit 212 is specifically used to: send read and write commands to multiple sub-channels so that the multiple sub-channels perform read and write operations in the DVFSC mode. It should be noted that the control circuit can also send other operation commands required in the DVFSC mode to the chip 22 according to the actual control situation and specific control scenario, and there is no specific limitation on this.

[0206] The chip controller 21 provided in the embodiment of the present disclosure, when multiple sub-channels of the same memory channel can independently switch the DVFSC mode, since the preset mode information in the mode register can indicate whether the multiple sub-channels are in the DVFSC mode, accordingly, the chip controller can determine based on the preset mode information that the memory channel has completed the DVFSC mode switching and perform control operations on the multiple sub-channels under the DVFSC mode, thereby enabling the multiple sub-channels of the same memory channel to synchronously perform operations under the DVFSC mode, avoiding internal errors of the chip controller caused when the multiple sub-channels are not in the DVFSC mode at the same time, and enabling the chip controller to perform normal control operations under the DVFSC mode on the multiple sub-channels, thereby realizing the DVFSC function of the chip with independent sub-channels.

[0207] In some embodiments, when the preset mode information X0 includes the second mode information X2, the control circuit 212 is specifically used to: when the second mode information X2 is configured as a second value, perform a control operation in the DVFSC mode on multiple sub-channels. It should be noted that the specific content of the second mode information X2 can refer to the relevant description of the above part of the embodiment of the present disclosure, and no further description is given for this.

[0208] Through this embodiment, when multiple sub-channels of the same memory channel can independently switch to the DVFSC mode, because multiple first mode information in the mode register can indicate whether the multiple sub-channels are in the DVFSC mode, and because the second mode information in the mode register is configured as a second value indicating that the memory channel has completed the DVFSC mode switch when the multiple first mode information are configured as the first value indicating that the corresponding sub-channel is in the DVFSC mode. Accordingly, the chip controller can perform control operations in the DVFSC mode on multiple sub-channels when it is determined based on the second value that the memory channel has completed the DVFSC mode switch, and multiple sub-channels of the same memory channel can synchronously perform operations in the DVFSC mode, avoiding internal errors of the chip controller caused when multiple sub-channels are not in the DVFSC mode at the same time, and enabling the chip controller to perform normal control operations in the DVFSC mode on multiple sub-channels, thereby realizing the DVFSC function of the chip with independent sub-channels.

[0209] Also, it should be noted that the chip controller only needs to use the second mode information to quickly and accurately determine whether multiple sub-channels of the same memory channel have synchronously entered the DVFSC mode, so that after quickly determining that the memory channel has completed the DVFSC mode switch, the multiple sub-channels can be quickly controlled in the DVFSC mode, thereby improving the control rate of the chip.

[0210] Optionally, when the preset mode information includes a plurality of first mode information X1, the chip controller 21 is further configured to determine whether the plurality of first mode information X1 are the same, or whether the first mode information X1 are all first values. It should be noted that the specific implementation of determining whether the first mode information X1 are the same or are all first values ​​can refer to the relevant description of the logic operation circuit in the above part of the embodiment of the present disclosure, and no specific limitation is made thereto.

[0211] In some embodiments, the chip controller further includes a command sending circuit.

[0212] A command sending circuit is used to send an MRR command to the chip, where the MRR command is used to control a target subchannel among multiple subchannels to switch to the DVFSC mode, and a register write command is also used to configure the first mode information corresponding to the target subchannel of the chip to a first value.

[0213] It should be noted that the command sending circuit can be any circuit with a command sending function, such as an IO circuit, etc., and there is no specific limitation on this.

[0214] In one embodiment, the control circuit 212 is specifically used to obtain the second value, and when it is determined that it has sent a register write command for controlling the sub-channel to enter the DVFSC mode, determine that the multiple sub-channels have completed the switching of the DVFSC mode.

[0215] In another embodiment, the second register reading circuit 211 may be used to obtain one or more first mode information X1 and second mode information X2. Furthermore, the control circuit 212 may be specifically used to determine that the memory channel has completed the switching of the DVFSC mode when the first mode information X1 is a first value and the second mode information X2 is a second value.

[0216] In some embodiments, the preset mode information is also used to indicate whether multiple sub-channels are already in a high-speed operation mode. The preset mode information is also used to enable the chip controller to perform control operations in the high-speed operation mode on the multiple sub-channels when it determines that the memory channel has completed the high-speed operation mode switch based on the preset mode information.

[0217] Accordingly, in the case where the second mode information X2 is configured as the second value because multiple first mode information are configured as the third value, after the second register read circuit 211 receives the second value, the chip controller can also be used to determine that the memory channel has completed the switching of the high-speed operation mode when it determines that it has sent a register write command for controlling the sub-channel to enter the high-speed operation mode, and the controller can perform control operations in the high-speed operation mode on multiple sub-channels.

[0218] Alternatively, the chip controller may also obtain one or more first mode information X1, and determine that the memory channel has completed the switching of the high-speed operation mode when the first mode information X1 is the third value and the second mode information X2 is the second value.

[0219] Through this embodiment, the chip controller can determine based on preset mode information that the memory channel has completed the high-speed operation mode switching and perform control operations on multiple sub-channels in the high-speed operation mode, so that multiple sub-channels of the same memory channel can synchronously perform operations in the high-speed operation mode, avoiding internal errors of the chip controller caused when multiple sub-channels are not in the high-speed operation mode at the same time, so that the chip controller can perform normal control operations in the high-speed operation mode on multiple sub-channels, thereby realizing the high-speed operation mode function of the chip with independent sub-channels.

[0220] Based on the same inventive concept, the embodiment of the present disclosure also provides a chip control method. The chip control method is described in detail below in conjunction with the accompanying drawings and embodiments.

[0221] Fig.11 A schematic diagram of a chip control method provided by an embodiment of the present disclosure is shown. Fig.11 As shown, the chip control method provided in the embodiment of the present disclosure includes the following steps S1110 and S1120. The method can be combined with the above Figure 4-Figure 9 Any of the embodiments shown may be implemented by a chip.

[0222] S1110, obtaining preset mode information from a mode register of the chip.

[0223] S1120, sending the preset mode information to the chip controller, so that the chip controller performs control operations in the DVFSC mode on the multiple sub-channels.

[0224] In one embodiment, the chip control method may further include the following steps A1 and A2.

[0225] Step A1, reading a plurality of first mode information from a mode register of the chip, wherein the plurality of first mode information corresponds to a plurality of sub-channels one by one, and each first mode information is used to indicate whether the corresponding sub-channel is in the DVFSC mode.

[0226] Step A2: when the plurality of first mode information are all configured as the first value, the second mode information is configured as the second value, so that the chip controller performs control operations in the DVFSC mode on the plurality of sub-channels based on the second value.

[0227] In one embodiment, step A2 may include the following steps A21 and A22.

[0228] Step A21, performing an XOR operation on the configuration values ​​of the plurality of first mode information to obtain an XOR result, wherein when the configuration values ​​of the plurality of first mode information are the same, the XOR result is 0; and when the configuration values ​​of the plurality of first mode information are different, the XOR result is 1.

[0229] Step A22, configuring an XOR result for the second mode information.

[0230] In one embodiment, the chip control method further includes step B1 and step B2.

[0231] Step B1, receiving a register write command sent by a chip controller, wherein the register write command is used to control a target sub-channel among multiple sub-channels to switch to a DVFSC mode.

[0232] Step B2: In response to a register write command, configure a first value for the first mode information corresponding to the target subchannel.

[0233] In one embodiment, when the mode register includes a plurality of first registers, step B2 includes step B21 and step B22.

[0234] Step B21, in response to a register write command, determining a first field in at least one first register corresponding to a target subchannel.

[0235] Step B22, storing the first value in the determined first field.

[0236] In one embodiment, each sub-channel has an independent power switching circuit; the chip control method further includes step C1.

[0237] Step C1, in response to a register write command, the power supply voltage of the target sub-channel is switched from a first voltage to a second voltage through the power supply switching circuit of the target sub-channel, so that each sub-channel is switched to the DVFSC mode through the switching of the power supply voltage.

[0238] In one embodiment, when the power switching circuit includes a first switch and a second switch, step C1 may include the following step C11.

[0239] Step C11, in response to the register write command, sending a DVFSC signal corresponding to a first level to a first control terminal of a first switch corresponding to a target subchannel; and applying a negated signal of a second level to a second control terminal of a second switch corresponding to the target subchannel.

[0240] According to the chip control method provided by the embodiment of the present disclosure, when multiple sub-channels of the same memory channel can independently switch the DVFSC mode, since the preset mode information in the mode register can indicate whether the multiple sub-channels are in the DVFSC mode, accordingly, the chip controller can determine based on the preset mode information that the memory channel has completed the DVFSC mode switching and perform control operations on the multiple sub-channels under the DVFSC mode, thereby enabling the multiple sub-channels of the same memory channel to synchronously perform operations under the DVFSC mode, avoiding internal errors of the chip controller caused when the multiple sub-channels are not in the DVFSC mode at the same time, and enabling the chip controller to perform normal control operations under the DVFSC mode on the multiple sub-channels, thereby realizing the DVFSC function of the chip with independent sub-channels.

[0241] It should be noted that Fig.11 The chip control method shown can be Figure 4-Figure 9 One or more components of the device shown are executed and implemented Figure 4-Figure 9 The various processes and effects in the illustrated device embodiment are not described in detail here.

[0242] For ease of understanding, the chip control method of the embodiment of the present disclosure is described below by using an example.

[0243] In one example, taking the memory channel including the first sub-channel SC0 and the second sub-channel SC1 as an example, Fig.12 A logic schematic diagram of a chip control method provided by an embodiment of the present disclosure is shown.

[0244] like Fig.12 As shown, for the value of the first field SC0_MRx OP[y], 0 indicates that the first sub-channel SC0 is in high-speed operation mode, and 1 indicates that the first sub-channel SC0 is in DVFSC mode. For the value of the first field SC1_MRx OP[y], 0 indicates that the second sub-channel SC1 is in high-speed operation mode, and 1 indicates that the second sub-channel SC1 is in DVFSC mode. For the value of the second field MRa OP[b], it can be set according to the XOR result of the first field SC1_MRx OP[y] and the first field SC0_MRx OP[y]. Among them, 0 indicates that the mode switching of each sub-channel is completed, and 1 indicates that the mode switching of each sub-channel is in progress.

[0245] Exemplarily, if the chip receives the first MRW command MRW1 sent by the chip controller, the first MRW command MRW1 is used to switch the DVFSC mode of the first sub-channel SC0. Then the first field SC0_MRx OP[y] in the first register of the first sub-channel SC0 is changed from 0 to 1, the first field SC1_MRx OP[y] in the first register of the second sub-channel SC1 remains 0, and the second field MRa OP[b] is changed from 0 to 1. At this time, it means that the mode switching is not completed, and the chip controller continues to read the value of the second field MRa OP[b].

[0246] Then, if the chip continues to receive the second MRW command MRW2 sent by the chip controller, the second MRW command MRW2 is used to switch the second sub-channel SC1 to DVFSC mode. Then the first field SC0_MRx OP[y] in the first register of the first sub-channel SC0 remains unchanged at 1, and the first field SC1_MRx OP[y] in the first register of the second sub-channel SC1 switches from 1 to 0. At this time, since the XOR result is 0 when the inputs are all 1, the second field MRa OP[b] can be modified from 1 to 0 accordingly, indicating that the mode switching is completed, and the chip controller can read that the value of the second field MRa OP[b] is equal to 1. At this time, the first sub-channel SC0 and the second sub-channel SC1 can start read and write operations in DVFSC mode under the control of the chip controller.

[0247] Based on the same inventive concept, an embodiment of the present disclosure also provides a chip control method. Fig.13 FIG. 1 is a flow chart of another chip control method provided by an embodiment of the present disclosure, such as Fig.13 As shown, the chip control method provided in the embodiment of the present disclosure includes the following steps S1310 and S1320. The method can be combined with the above Fig.10 Any of the embodiments shown are implemented by a chip controller.

[0248] S1310, read preset mode information from the mode register of the chip.

[0249] S1320: When it is determined based on the preset mode information that the memory channel has completed the DVFSC mode switching, a control operation in the DVFSC mode is performed on the plurality of sub-channels.

[0250] In one embodiment, the chip control method further includes step D1.

[0251] Step D1, when the second mode information is configured as the second value, the memory channel has completed the DVFSC mode switching.

[0252] In one embodiment, S1320 specifically includes: sending read and write commands to the multiple sub-channels, so that the multiple sub-channels perform read and write operations in the DVFSC mode.

[0253] According to the chip control method provided by the embodiment of the present disclosure, when multiple sub-channels of the same memory channel can independently switch the DVFSC mode, since the preset mode information in the mode register can indicate whether the multiple sub-channels are in the DVFSC mode, accordingly, the chip controller can determine based on the preset mode information that the memory channel has completed the DVFSC mode switching and perform control operations on the multiple sub-channels under the DVFSC mode, thereby enabling the multiple sub-channels of the same memory channel to synchronously perform operations under the DVFSC mode, avoiding internal errors of the chip controller caused when the multiple sub-channels are not in the DVFSC mode at the same time, and enabling the chip controller to perform normal control operations under the DVFSC mode on the multiple sub-channels, thereby realizing the DVFSC function of the chip with independent sub-channels.

[0254] It should be noted that Fig.13 The chip control method shown can be Fig.10 One or more components of the device shown are executed and implemented Fig.10 The various processes and effects in the illustrated device embodiment are not described in detail here.

[0255] Based on the same inventive concept, a storage system is also provided in an embodiment of the present disclosure. The storage system may include a chip and a storage controller.

[0256] The specific contents of the chip and the storage controller can be found in the above-mentioned embodiments of the present disclosure. Figure 2-Figure 10 The relevant description is omitted here.

[0257] In the storage system provided by the embodiment of the present disclosure, when multiple sub-channels of the same memory channel can independently switch to the DVFSC mode, since the preset mode information in the mode register can indicate whether the multiple sub-channels are in the DVFSC mode, accordingly, the chip controller can determine based on the preset mode information that the memory channel has completed the DVFSC mode switching and perform control operations on the multiple sub-channels under the DVFSC mode, thereby allowing the multiple sub-channels of the same memory channel to synchronously perform operations under the DVFSC mode, avoiding internal errors of the chip controller caused when the multiple sub-channels are not in the DVFSC mode at the same time, allowing the chip controller to perform normal control operations under the DVFSC mode on the multiple sub-channels, thereby realizing the DVFSC function of the chip with independent sub-channels.

[0258] Those skilled in the art will appreciate that various aspects of the present disclosure may be implemented as systems, methods or program products. Therefore, various aspects of the present disclosure may be specifically implemented in the following forms, namely: complete hardware implementation, complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software, which may be collectively referred to herein as "circuits", "modules" or "systems".

[0259] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0260] In addition, although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0261] Through the description of the above implementation modes, it is easy for those skilled in the art to understand that the example implementation modes described here can be implemented by software, or by combining software with necessary hardware.

[0262] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein.

[0263] The present disclosure is intended to cover any variation, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the technical field not disclosed in the present disclosure. The description and examples are to be regarded as exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A chip, characterized in that: include: A memory channel, wherein the memory channel includes a plurality of sub-channels, wherein each sub-channel independently switches a core voltage dynamic voltage frequency switching DVFSC mode; a mode register, wherein the mode register stores preset mode information, wherein the preset mode information indicates whether the plurality of sub-channels are in the DVFSC mode, The preset mode information is used to enable the chip controller to perform control operations in the DVFSC mode on the multiple sub-channels when it is determined based on the preset mode information that the memory channel has completed the DVFSC mode switching.

2. The chip according to claim 1, characterized in that: The mode register also stores a plurality of first mode information, The plurality of first mode information correspond to the plurality of sub-channels one by one, and each first mode information is used to indicate whether the corresponding sub-channel is in the DVFSC mode; The preset mode information includes second mode information, The second mode information indicates whether the memory channel has completed the mode switching, wherein, when the multiple first mode information are configured as a first value indicating that the corresponding sub-channel is in the DVFSC mode, the second mode information is configured as a second value indicating that the memory channel has completed the mode switching, and the second value is used to enable the chip controller to perform control operations under the DVFSC mode on the multiple sub-channels.

3. The chip according to claim 2, characterized in that: The chip further comprises: A first register reading circuit is used to read the plurality of first mode information from the mode register of the chip; The register writing circuit is used to configure the second mode information to the second value when the plurality of first mode information are all configured to the first value.

4. The chip according to claim 2, characterized in that: The number of sub-channels of the memory channel is 2, the second value is 0, The chip further comprises: A logic operation circuit, used for performing an XOR operation on the configuration values ​​of the plurality of first mode information to obtain an XOR result; wherein when the configuration values ​​of the plurality of first mode information are the same, the XOR result is 0; and when the configuration values ​​of the plurality of first mode information are different, the XOR result is 1; The register write circuit is specifically used to configure the XOR result for the second mode information.

5. The chip according to claim 3, characterized in that: The chip further comprises: A command receiving circuit, used for receiving a register write command sent by the chip controller, wherein the register write command is used for controlling a target sub-channel among the multiple sub-channels to switch to the DVFSC mode; Furthermore, the register write circuit is further used to configure the first value for the first mode information corresponding to the target sub-channel in response to the register write command.

6. The chip according to claim 3, characterized in that: The mode register includes a plurality of first registers, one subchannel corresponds to at least one first register, and the first mode information corresponding to each subchannel is stored in the first field of the at least one first register corresponding thereto; The chip further comprises: A command receiving circuit, used for receiving a register write command sent by the chip controller, wherein the register write command is used for controlling a target sub-channel among the multiple sub-channels to switch to the DVFSC mode; The register writing circuit is specifically used for: In response to the register write command, determining a first field in at least one first register corresponding to the target subchannel; The first value is stored in the determined first field.

7. The chip according to claim 5, characterized in that: Each sub-channel has an independent power switching circuit; The chip further comprises: The power switching circuit of each sub-channel is used to switch the power supply voltage of each sub-channel from a first voltage to a second voltage in response to the register write command, so as to switch each sub-channel to the DVFSC mode by switching the power supply voltage.

8. The chip according to claim 1, characterized in that: The preset mode information is also used to indicate whether the plurality of subchannels are already in the high-speed operation mode. The preset mode information is also used to enable the chip controller to perform control operations in the high-speed operation mode on the multiple sub-channels when the chip controller determines that the memory channel has completed the high-speed operation mode switching based on the preset mode information.

9. The chip according to any one of claims 1 to 8, characterized in that: The chip is a low-power double data rate sixth-generation LPDDR6 memory.

10. A chip controller, characterized in that: Used to control the chip according to any one of claims 1 to 9; The controller comprises: A second register reading circuit is used to read the preset mode information from the mode register of the chip; The control circuit is used to perform control operations in the DVFSC mode on the multiple sub-channels when it is determined based on the preset mode information that the memory channel has completed the DVFSC mode switching.

11. The chip controller according to claim 10, characterized in that: The preset mode information includes second mode information, the second mode information indicating whether the memory channel has completed the switching of the DVFSC mode, wherein, in a case where a plurality of first mode information are configured as a first value indicating that the corresponding sub-channel is in the DVFSC mode, the second mode information is configured as a second value indicating that the memory channel has completed the switching of the DVFSC mode; wherein, the plurality of first mode information correspond one-to-one to the plurality of sub-channels, and each first mode information is used to indicate whether the corresponding sub-channel is in the DVFSC mode; Furthermore, the control circuit is specifically configured to: when the second mode information is configured as a second value, perform control operations in the DVFSC mode on the multiple sub-channels.

12. The chip controller according to claim 11, characterized in that: The chip controller also includes: A command sending circuit is used to send a register write command to the chip, wherein the register write command is used to control a target sub-channel among the multiple sub-channels to switch to the DVFSC mode, and the register write command is also used to configure the first mode information corresponding to the target sub-channel of the chip to the first value.

13. A chip control method, characterized in that: The method is applied to the chip according to any one of claims 1 to 9 above, The method comprises: Acquiring the preset mode information from a mode register of the chip; The preset mode information is sent to the chip controller, so that the chip controller performs the control operation under the DVFSC mode on the multiple sub-channels.

14. The method according to claim 13, characterized in that The preset mode information includes second mode information; The method comprises: Reading the plurality of first mode information from the mode register of the chip, wherein the plurality of first mode information corresponds to the plurality of sub-channels one by one, and each first mode information is used to indicate whether the corresponding sub-channel is in the DVFSC mode; In a case where the plurality of first mode information are all configured as first values, the second mode information is configured as a second value, so that the chip controller performs the control operation in the DVFSC mode on the plurality of sub-channels based on the second value.

15. The method according to claim 14, characterized in that The number of sub-channels of the memory channel is 2, the second value is 0, When the plurality of first mode information are all configured as first values, configuring the second mode information as a second value includes: Performing an XOR operation on the configuration values ​​of the plurality of first mode information to obtain an XOR result; wherein when the configuration values ​​of the plurality of first mode information are the same, the XOR result is 0; and when the configuration values ​​of the plurality of first mode information are different, the XOR result is 1; The XOR result is configured for the second mode information.

16. A chip control method, characterized in that: The method is applied to a chip controller of a chip, wherein the chip is as described in any one of claims 1 to 9; The method comprises: Reading the preset mode information from the mode register of the chip; In a case where it is determined based on the preset mode information that the memory channel has completed the DVFSC mode switching, a control operation in the DVFSC mode is performed on the plurality of sub-channels.

17. The method according to claim 16, characterized in that The preset mode information includes second mode information, Before performing the control operation in the DVFSC mode on the multiple sub-channels, the method further includes: In a case where the second mode information is configured as a second value, the memory channel has completed the DVFSC mode switching.

18. A storage system, characterized in that: include: A chip, wherein the chip is as described in any one of claims 1 to 9; and A chip controller, wherein the chip controller is as described in any one of claims 10-12.

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