Data rearrangement techniques for memory

Abstract

The invention relates to data rearrangement techniques for memory. A controller of a memory system may facilitate data rearrangement within a block addressable memory device based on metadata associated with prefetching data to a byte addressable memory device or a host system. For example, the controller may utilize the metadata and various access commands to rearrange associated data within the block addressable memory device such that the data is written to a single superblock of the block addressable memory device. In some examples, the controller may utilize one or more counters to determine whether to rearrange the data within the block addressable memory device.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. Patent Application No. 18 / 643,936, filed by David Andrew Roberts on April 23, 2024, entitled “DATA REARRANGEMENT TECHNIQUES FOR MEMORY,” and U.S. Provisional Patent Application No. 63 / 510,532, filed by David Andrew Roberts on June 27, 2023, entitled “DATA REARRANGEMENT TECHNIQUES FOR MEMORY,” each of which is assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to data rearrangement technology of memory. Background Art

[0004] Memory devices are used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, which are typically represented by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, any of which can be stored by the memory cell. To store information, a memory device can write (e.g., program, set, assign) a state to a memory cell. To access the stored information, a memory device can read (e.g., sense, detect, retrieve, determine) a state from a memory cell. Summary of the invention

[0005] A method is described. The method may include: accessing, by a controller of a memory system including a first memory device having a first type of memory and a second memory device having a second type of memory, first data from a first block of the first memory device; accessing, by the controller, metadata associated with the first data according to a prefetch policy based on accessing the first data; transferring, by the controller, second data from one or more second blocks of the first memory device to the second memory device based on the metadata and the prefetch policy, wherein the first block is included in a first Super Block of the first memory device and at least one of the one or more second blocks is included in a second Super Block of the first memory device; and transmitting, from the controller to the first memory device, a command for writing the first data and the second data to a third Super Block of the first memory device based on a value of a counter associated with the metadata.

[0006] An apparatus is described. The apparatus may include: a first memory device having a first type of memory; a second memory device having a second type of memory; a buffer coupled to the first memory device and the second memory device, the buffer configured to transfer data between the first memory device and the second memory device according to a prefetch operation; and a controller coupled to the first memory device, the second memory device, and the buffer, the controller configured to transmit a command to the first memory device to write first data contained in a first Super Block of the first memory device and second data contained in a second Super Block of the first memory device to a third Super Block of the first memory device based on the prefetch operation.

[0007] A method is described. The method may include: accessing, by a controller of a memory system including a first memory device having a first type of memory and a second memory device having a second type of memory, metadata associated with a prefetch operation to transfer data from the first memory device to the second memory device; and transmitting, from the controller to the first memory device, a command for writing first data associated with a first Super Block of the first memory device and second data associated with a second Super Block of the first memory device to a third Super Block of the first memory device based on a value of a counter satisfying a threshold, based on accessing the metadata. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1 to 3 An example of a system supporting data rearrangement techniques for memory according to examples as disclosed herein is presented.

[0009] Figure 4An example of a block diagram is shown that supports data reordering techniques for memory according to examples as disclosed herein.

[0010] Figures 5 to 7 An example of a flow diagram is shown that supports data rearrangement techniques for memory according to examples as disclosed herein. DETAILED DESCRIPTION

[0011] Some systems may include various types of memory that can be addressed at different granularity levels. For example, among other types of memory, the system may include memory that can be addressed at a block granularity level (which may be referred to as block-addressable memory), and include memory that can be addressed at a byte granularity level (which may be referred to as byte-addressable memory). In some cases, block-addressable memory devices (e.g., NAND flash memory, solid-state disks (SSDs) using a non-volatile memory express (NVMe) interface) may be characterized by various limitations that may negatively affect their performance. For example, these devices may include high sequential access latency (e.g., accessing sequentially addressed blocks), even higher random access latency (e.g., accessing random blocks), asymmetric latency (e.g., higher write latency than read latency), lower bandwidth relative to byte-addressable memory devices, loss (e.g., low write endurance), or a combination thereof. However, these block-addressable memories may also include non-volatile memories of high storage capacity, which, for example, may be relatively cheaper than byte-addressable memories. Conversely, some byte-addressable memories (e.g., dynamic random access memory (DRAM), for example, attached via a compute express link (CXL) interface) may exhibit lower latency, higher bandwidth, and higher access symmetry, for example, for fine-grained (e.g., page row size) sequential and random access operations relative to block-addressable memories. However, these byte-addressable memories may also include volatile memory, which may not be suitable for storing data for extended periods of time (e.g., not connected to a power source).

[0012] According to examples described herein, a controller of a system including block-addressable and byte-addressable memory devices (e.g., hybrid memory modules) can direct data rearrangement such that performance and efficiency of the block-addressable memory devices can be improved. For example, the controller can utilize metadata associated with pre-fetching data from the block-addressable memory devices and various access commands to rearrange associated data within the block-addressable memory devices such that the data is written to a single super block (e.g., page row) of the block-addressable memory devices. Such data rearrangement can enable the controller to manipulate and store data within a super block of the block-addressable memory device such that storage of data within the super block can be efficiently utilized, for example, to subsequently perform sequential data access (e.g., rather than random access).

[0013] In some examples, the controller may utilize one or more counters (e.g., confidence components) to determine whether to reorder data of a block in a block-addressable memory device. For example, a counter that tracks the amount of access to metadata associated with a prefetch may be used to reorder data that may be subsequently accessed, e.g., as part of a prefetch operation. Additionally or alternatively, the data cache organization and replacement strategies in the byte-addressable memory devices described herein may be used to further facilitate efficient data management and data transfer between byte-addressable memory and block-addressable memory, e.g., to reduce losses and increase write bandwidth. These techniques may be implemented in a main memory-like setup, such as a CXL main memory module, which may allow common and predictable main memory cycle stepping to drive a memory-side data prefetcher (e.g., traditionally only seen on a host processor chip), such that overall bandwidth may be increased while latency and losses may be reduced.

[0014] Features of the present disclosure are illustrated and described in the context of systems and architectures. Features of the present disclosure are further illustrated and described in the context of systems, block diagrams, and flow charts.

[0015] Figure 1 An example of a system 100 supporting data rearrangement techniques for memory according to examples as disclosed herein is illustrated. The system 100 may include a portion of an electronic device, such as a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a vehicle, a smartphone, a wearable device, an Internet-connected device, a vehicle controller, a system on a chip (SoC), or other fixed or portable electronic system, among other examples. The system 100 includes a host system 105, a memory system 110, and one or more channels 115 coupling the host system 105 with the memory system 110 (e.g., to support a communication coupling). The system 100 may include any number of one or more memory systems 110 coupled to the host system 105.

[0016] The host system 105 may include one or more components (e.g., circuitry, processing circuitry, processing components) that use memory to perform processes, any one or more of which may be referred to as a processor 125 or included in a processor 125. The processor 125 may include at least one of one or more processing elements that may be co-located or distributed, including a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a controller, discrete gate or transistor logic, one or more discrete hardware components, or a combination thereof. The processor 125 may be a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC or components thereof, among other examples.

[0017] The host system 105 may also include at least one of one or more components (e.g., circuitry, logic, instructions) that implement the functionality of an external memory controller (e.g., a host system memory controller), which may be referred to as a host system controller 120 or included in the host system controller 120. For example, the host system controller 120 may issue commands or other signaling for operating the memory system 110, such as write commands, read commands, configuration signaling, or other operational signaling. In some examples, the host system controller 120 or associated functions described herein may be implemented by the processor 125 or may be part of the processor 125. For example, the host system controller 120 may be hardware, instructions (e.g., software, firmware), or some combination thereof implemented by the processor 125 or other components of the host system 105. In various examples, the host system 105 or the host system controller 120 may be referred to as a host.

[0018] The memory system 110 provides physical memory locations (e.g., addresses) that can be used or referenced by the system 100. The memory system 110 can include a memory system controller 140, one or more memory devices 155 (e.g., memory packages, memory dies, memory chips) operable to store data, and one or more memory devices 170. The memory system 110 can be configured for operation with different types of host systems 105, and can respond to commands from the host system 105 (e.g., from the host system controller 120). For example, the memory system 110 (e.g., the memory system controller 140) can receive a write command indicating that the memory system 110 is to store data received from the host system 105, or receive a read command indicating that the memory system 110 is to provide data stored in the memory device 155 or the memory device 170 to the host system 105, or receive a refresh command indicating that the memory system 110 is to refresh data stored in the memory device 155 or the memory device 170, as well as other types of commands and operations.

[0019] The memory system controller 140 may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control the operation of the memory system 110. The memory system controller 140 may include hardware or instructions that support the memory system 110 to perform various operations, and may be operable to receive, transmit, or respond to commands, data, or control information related to the operation of the memory system 110. The memory system controller 140 may be operable to communicate with one or more of the host system controller 120, one or more memory devices 155, one or more memory devices 170, or the processor 125. In some examples, the memory system controller 140 may control the operation of the memory system 110 in cooperation with the host system controller 120, a controller 145 coupled to one or more memory devices 155, a local controller 160 of a memory device 155, a controller 150 coupled to one or more memory devices 170, a controller 175 of a memory device 170, a local controller 177 of a memory array 180 of a memory device 170, or any combination thereof. Although examples of memory system controller 140 are illustrated as a separate component of memory system 110, in some examples, aspects of the functionality of memory system 110 may be implemented by processor 125, host system controller 120, or any combination thereof.

[0020] The memory system 110 may be a hybrid memory system (eg, a hybrid memory module) including various types of memory devices operable to store data. Figure 1In an example of , memory device 155 may be a volatile memory device (e.g., a memory device including volatile memory cells), and memory device 170 may be a non-volatile memory device (e.g., a memory device including non-volatile memory cells). For example, each memory device 155 may include one or more memory arrays 165, and each memory device 170 may include one or more memory arrays 180. A memory array may be a collection of memory cells (e.g., a two-dimensional array, a three-dimensional array), wherein each memory cell is operable to store data (e.g., as one or more storage bits). Memory array 165 may include volatile memory cells of various architectures, such as random access memory (RAM) cells, dynamic RAM (DRAM) cells, synchronous dynamic RAM (SDRAM) cells, static RAM (SRAM) cells, or combinations thereof, as well as other types of volatile memory cells. The memory array 180 may include non-volatile memory cells of various architectures, such as NAND (e.g., NAND flash) memory, read-only memory (ROM), phase change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof, as well as other types of non-volatile memory cells.

[0021] In some examples, each memory device 155 may include a local controller 160. The local controller 160 may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control the operation of the memory device 155. In some examples, the local controller 160 may be operable to communicate (e.g., receive or transmit data or commands or both) with the memory system controller 140, such as via the controller 145. For example, the controller 145 may be a volatile memory controller coupled to the memory system controller 140, which may be operable to control the operation of the one or more memory devices 155. The controller 145 may be coupled to or included in the memory system controller 140 and may be operable to communicate signaling between the memory system controller 140 and the one or more memory devices 155. In some examples, the memory system 110 may not include the memory system controller 140 and / or the controller 145, and the local controller 150 or the host system controller 120 may perform the functions of the memory system controller 140 and / or the controller 145 described herein. In some examples, the local controller 150, the controller 145, the memory system controller 140, or a combination thereof may include a decoding component operable to access addresses of the memory array 165, a sensing component to sense states of memory cells of the memory array 165, a writing component to write states to memory cells of the memory array 165, or various other components operable to support the described operations of the memory system 110.

[0022] The memory device 170 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM) or a non-volatile DIMM (NVDIMM), among other devices.

[0023] The memory device 170 may include a controller 175. The controller 175 may be coupled and communicate with the host system 105, for example, via the memory system controller 140, the controller 150, or a combination thereof. For example, the controller 150 may be a non-volatile memory controller coupled with the memory system controller 140, which may be operable to control the operation of one or more memory devices 170. The controller 150 may be coupled with or included in the memory system controller 140 and may be operable to communicate signaling between the memory system controller 140 and the one or more memory devices 170.

[0024] Controller 175 may be an example of a controller or control component configured to cause memory device 170 to perform various operations according to examples as described herein. Controller 175 may also be coupled and communicated with memory array 180 to perform operations such as reading data, writing data, erasing data, or refreshing data at memory array 180, as well as other such operations, which may be collectively referred to as access operations. In some cases, controller 175 may receive commands from host system 105 and / or memory system controller 140 and communicate with one or more memory arrays 180 to perform such commands. For example, controller 175 may receive commands or operations from host system 105 (e.g., via memory system controller 140 and / or controller 150) or from memory system controller 140 (e.g., via controller 150) and may convert the commands or operations into instructions or appropriate commands to achieve desired access of memory array 180.

[0025] The controller 175 may be configured for other operations associated with the memory array 180. For example, the controller 175 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations (e.g., error detection operations or error correction operations), encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 or the memory system controller 140 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory array 180.

[0026] Controller 175 may include hardware such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to controller 175. Controller 175 may be or include a microcontroller, dedicated logic circuitry (e.g., FPGA, ASIC, DSP), or any other suitable processor or processing circuitry.

[0027] The controller 175 may also include local memory. In some cases, the local memory may include ROM or other memory that may store operating code (e.g., executable instructions) that may be executed by the controller 175 to perform the functions attributed to the controller 175 herein. In some cases, the local memory may additionally or alternatively include SRAM or other memory that may be used by the controller 175 for internal storage or calculations related to the functions attributed to the controller 175 herein, for example. Additionally or alternatively, the local memory may act as a cache for the controller 175. For example, data may be stored in the local memory when it is read from or written to the memory array 180, and the data may be available within the local memory for subsequent retrieval or manipulation (e.g., updating) by the host system 105 or the memory system controller 140 according to the cache policy (e.g., with reduced latency relative to the memory array 180).

[0028] although Figure 1 The examples of memory device 170 in have been illustrated as including controller 175, but in some cases, memory device 170 may not include controller 175. For example, memory device 170 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105), memory system controller 140, controller 150, one or more local controllers 177 (which may be located internal to memory array 180), or a combination thereof to perform the functions attributed herein to controller 175.

[0029] In some examples, the memory array 180 may include a local controller 177 (e.g., on the same die or within the same package) that may perform operations on one or more memory cells of the respective memory array 180. The local controller 177 may operate in conjunction with the controller 175 or may perform one or more functions attributed to the controller 175 herein.

[0030] In some cases, memory array 180 may be or include NAND devices (e.g., NAND flash devices). Memory array 180 may be or include die 182 (e.g., memory die). For example, in some cases, memory array 180 may be a package including one or more die 182. In some instances, die 182 may be an electronic device-level semiconductor piece cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 182 may include one or more planes 184, and each plane 184 may include a set of corresponding block groups 186, wherein each block group 186 may include a set of corresponding blocks 188, and each block 188 may include a set of memory cells. In some instances, block groups 186 may be referred to as blocks, and blocks 188 may be referred to as pages.

[0031] In some cases, a plane 184 may refer to several groups of block groups 186, and in some cases, concurrent operations may be performed on different planes 184. For example, concurrent operations may be performed on memory cells within different block groups 186, as long as the different block groups 186 are in different planes 184. In some cases, individual block groups 186 may be referred to as physical blocks, and a virtual block 190 may refer to a group of block groups 186 within which concurrent operations may occur. For example, concurrent operations may be performed on block groups 186-a, 186-b, and 186-c within planes 184-a, 184-b, and 184-c, respectively, and block groups 186-a, 186-b, and 186-c may be collectively referred to as virtual blocks 190. In some cases, a virtual block may include block groups 186 from different memory arrays 180. In some cases, block groups 186 within a virtual block 190 may have the same block address within their respective planes 184 (e.g., block group 186-a may be "block 0" of plane 184-a, block group 186-b may be "block 0" of plane 184-b, and so on). In some cases, performing concurrent operations in different planes 184 may be subject to one or more restrictions, such as performing concurrent operations on memory cells within different blocks 188 that have the same block address within their respective planes 184 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 184).

[0032] In some cases, block groups 186 may include memory cells organized into rows (blocks 188) and columns (e.g., strings, not shown). For example, memory cells in the same block 188 may share a common word line (e.g., be coupled to a common word line), and memory cells in the same string may share a common digit line (which may alternatively be referred to as a bit line) (e.g., be coupled to a common digit line).

[0033] For some NAND architectures, memory cells may be read and programmed (e.g., written) at a first granularity (e.g., at a block granularity, or portions thereof) but may be erased at a second granularity (e.g., at a block group granularity). That is, a block 188 may be the smallest unit of memory (e.g., a group of memory cells) that may be independently programmed or read (e.g., concurrently programmed or read as part of a single programming or reading operation), and a block group 186 may be the smallest unit of memory (e.g., a group of memory cells) that may be independently erased (e.g., concurrently erased as part of a single erase operation). Furthermore, in some cases, a NAND memory cell may be erased before it may be rewritten with new data. Thus, for example, in some cases, a used block 188 may not be updated until the entire block group 186 that includes the block 188 has been erased.

[0034] In some examples, a Super Block 192 may refer to a single row of blocks 188 of a virtual block 190. For example, a Super Block 192 corresponding to the first row of virtual blocks 190 may include the first block 188 of each block group 186 included in the virtual block 190. In some examples, a Super Block 192 may include the same block 188 within each plane 184 of a die 182. In some examples, a Super Block 192 may be referred to as a page row.

[0035] In some cases, to update some data within a block group 186 while retaining other data within the block group 186, the controller 175 may copy the data to be retained to a new block group 186 and write the updated data to one or more remaining pages of the new block group 186. The memory array (e.g., local controller 177) or controller 175 may mark or otherwise designate the data retained in the old block group 186 as invalid or obsolete and may update a logical-to-physical (L2P) mapping table to associate the logical address (e.g., LBA) of the data with the new, valid group 186 instead of the old, invalid group 186. In some examples, the L2P mapping table may be or be included in a flash translation layer (FTL) mapping table maintained by the memory device 170. In some cases, such copying and remapping may be performed rather than erasing and rewriting the entire old block group 186, for example due to latency or wear considerations. In some cases, one or more copies of the L2P mapping table may be stored within memory cells of memory array 180 (eg, within one or more block groups 186 or planes 184) for use (eg, reference and update) by local controller 177 or controller 175.

[0036] In some cases, an L2P mapping table may be maintained and data may be marked as valid or invalid at a block granularity level, and a block 188 may contain valid data, invalid data, or no data. Invalid data may be outdated data, which may be due to a newer or updated version of the data being stored in a different block 188 of the memory array 180. Invalid data may have been previously programmed to an invalid block 188, but may no longer be associated with a valid logical address (e.g., a logical address referenced by the host system 105 or the memory system controller 140). Valid data may be the latest version of such data stored on the memory array 180. A block 188 that does not contain data may be a block 188 that has never been written to or has been erased and may be referred to as an empty block. A super block 192 that does not contain data may be a super block 192 that has never been written to or has been erased and may be referred to as an empty super block.

[0037] In some cases, the controller 175 or the local controller 177 may perform operations (e.g., as part of one or more media management algorithms) with respect to the memory array 180, such as wear leveling, background refresh, garbage collection, scrubbing, block scanning, health monitoring, or other, or any combination thereof. For example, within the memory array 180, a block group 186 may have some blocks 188 containing valid data and some blocks 188 containing invalid data. To avoid waiting for all blocks 188 in a block group 186 to have invalid data in order to erase and reuse the block group 186, an algorithm known as "garbage collection" may be invoked to allow the block group 186 to be erased and released as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting a block group 186 containing valid and invalid data, selecting a block 188 in a block group 186 containing valid data, copying the valid data from the selected block 188 to a new location (e.g., a free block 188 in another block group 186), marking the data in a previously selected block 188 as invalid, and erasing the selected block group 186. Thus, the number of block groups 186 that have been erased may be increased so that more block groups 186 are available to store subsequent data (e.g., data subsequently received from the host system 105 or the memory system controller 140).

[0038] The host system 105 (e.g., host system controller 120) and the memory system 110 (e.g., memory system controller 140) may communicate information (e.g., data, commands, control information, configuration information) using one or more channels 115. Each channel 115 may be an example of a transmission medium that carries information, and each channel 115 may include one or more signal paths (e.g., transmission media, electrical conductors, conductive paths) between terminals (e.g., nodes, pins, contacts) associated with components of the system 100. Terminals may be examples of conductive input or output points of devices of the system 100, and terminals may operate as part of a channel 115. To support communication via channel 115, host system 105 (e.g., host system controller 120) and memory system 110 (e.g., memory system controller 140) may include a receiver (e.g., latch) for receiving signals, a transmitter (e.g., driver) for transmitting signals, a decoder for decoding or demodulating received signals, or an encoder for encoding or modulating signals to be transmitted, as well as other components that support signaling via channel 115, which may be included in corresponding interface portions of the corresponding systems.

[0039] The channels 115 are dedicated to conveying one or more types of information, and the channels 115 may include unidirectional channels, bidirectional channels, or both. For example, the channels 115 may include one or more command and address channels, one or more clock signal channels, one or more data channels, and other channels or combinations thereof. In some examples, the channels 115 may be configured to provide power from one system to another (e.g., from the host system 105 to the memory system 110 according to a regulated voltage). In some examples, at least a subset of the channels 115 may be configured according to a protocol (e.g., a logic protocol, a communication protocol, an operating protocol, an industry standard), which may support configuration operations of the host system 105 and the memory system 110 and interaction between the host system 105 and the memory system 110.

[0040] In some examples, the system 100 may include a switch (not shown) for selectively coupling the host system 105 with the memory system 110. In some examples, the switch may be a CXL switch, a PCIe switch, a Gen-Z switch, an OpenCAPI switch, or an Ethernet switch, as well as corresponding instances of other types of switches that support selectively coupling the host system 105 (e.g., an on-chip processor) to the memory system 110 (e.g., an off-chip storage device).

[0041] In some examples, memory device 155 may be referred to as or include byte-addressable memory, and memory device 170 may be referred to as or include block-addressable memory. For example, memory device 155 may be operable to store data that can be accessed and manipulated at a byte granularity level. For example, a byte included in memory device 155 may have a unique address that can be used to read data from the byte or write data to the byte. Memory device 170 may be operable to store data that can be accessed and manipulated at a block granularity level. For example, memory device 170 may include data that can be stored in a block 188 that can be a fixed size. Block 188 may be associated with a unique address that can be used to read data from block 188 or write data to block 188.

[0042] In some examples, memory device 170 (e.g., or other block-addressable memory) is characterized by various limitations that may negatively affect performance, such as relatively higher latency (e.g., sequential access latency, random access latency, asymmetric latency), lower bandwidth, higher loss, or a combination thereof relative to memory device 155. However, memory device 170 may also be associated with high storage capacity of non-volatile memory. In contrast, memory device 155 (e.g., or other byte-addressable memory) may exhibit lower latency and higher bandwidth for fine-grained (e.g., page-row size) sequential and random access operations. However, memory device 155 may also include volatile memory that may not be suitable for storing data for extended periods of time.

[0043] According to the examples described herein, the memory system controller 140 may direct data rearrangement such that the performance and efficiency of the memory system 110 may be improved. For example, the memory system controller 140 may utilize metadata and various access commands to rearrange associated data within the memory device 170 such that the data is written to a single super block 192 of the memory device 170. This data rearrangement may enable the memory system controller 140 to manipulate and store data within other super blocks 192 of the memory device 170 such that the storage of each super block 192 may be efficiently utilized while supporting subsequent sequential (e.g., and / or parallel) data accesses. Additionally or alternatively, data cache organization and replacement strategies may be used to further facilitate efficient data management and data transfer between the memory device 155 and the memory device 170. These techniques may be implemented in a main memory-like setup such as a CXL main memory module, which may allow common and predictable main memory cycle stepping to drive the memory-side data prefetcher such that the overall bandwidth may be increased while latency and loss may be reduced.

[0044] In addition to applicability in systems as described herein, techniques for data rearrangement may generally be implemented to improve the performance of various electronic devices and systems, including games. Some electronic device applications, including games and other high-performance applications, may be associated with relatively high processing requirements while also benefiting from relatively fast response times to improve the user experience. Thus, it may be desirable to increase processing speed, reduce response time, or otherwise improve the performance of electronic devices. Implementation of the techniques described herein may improve the performance of electronic devices by improving memory access speeds, which may reduce processing or latency times, improve response times, or otherwise improve the user experience, among other benefits.

[0045] Additionally or alternatively, techniques for data rearrangement may generally be implemented to support virtual reality or augmented reality applications. As the presence and use of virtual, augmented, extended, and other reality devices increase, electronic devices that support unique aspects of these technologies may be needed. For example, virtual reality and augmented reality devices and applications may benefit from faster processing to enhance user immersion, and wearable electronic devices that support virtual reality or augmented reality may be affected by various size, weight, or other considerations. Implementation of the techniques described herein may support virtual, augmented, extended, and other reality devices or technologies by improving response speed, resulting in an enhanced user experience, among other benefits.

[0046] Additionally or alternatively, techniques for data rearrangement may generally be implemented to support artificial intelligence applications. As the use of artificial intelligence increases to support machine learning, analysis, decision making, or other related applications, electronic devices that support artificial intelligence applications and processes may be needed. For example, artificial intelligence applications may be associated with accessing relatively large amounts of data for analytical purposes and may benefit from memory devices that can effectively and efficiently store relatively large amounts of data or access stored data relatively quickly. Implementation of the techniques described herein may support artificial intelligence and / or machine learning techniques by improving memory access speeds and increasing memory capacity or density, among other benefits.

[0047] Figure 2 An example of a system 200 (eg, a memory system) supporting data rearrangement techniques for memory according to an example disclosed herein is described. Figure 1 Aspects of the described system 100 or one or more components thereof (eg, memory system 110, memory device 155, memory device 170) implement system 200. System 200 may include core 205, which may be used with reference to Figure 1 The host system 105 is described as being coupled (e.g., via a CXL switch), included in the host system 105, or an instance of the host system 105. In some examples, the core 205 can be an example of a processor on a chip. The core 205 can be coupled to the controller 210, which can be as described in reference Figure 1 An example of the memory system controller 140 is described or included in the memory system controller 140. In addition, although the non-limiting examples of the system 200 are generally described herein in terms of applicability to a memory system, a memory subsystem, a memory device, or a combination thereof, examples of the system 200 are not limited thereto. For example, aspects of the present disclosure may also be applied to any computing system, computing subsystem, processing system, processing subsystem, component, device, structure, or other type of system or subsystem used for applications such as data collection, data processing, data storage, networking, communication, power, artificial intelligence, single chip system, control, telemetry, sensing and monitoring, digital entertainment, or any combination thereof.

[0048] The system 200 may also include a memory device 215 (eg, a NAND device, an SSD device), which may be as described in reference Figure 1 1. For example, the memory device 215 may be an example of a block addressable memory device. The memory device 215 may include one or more super blocks 290 (e.g., super blocks 290-a to 290-d), which may be as described in reference to Figure 1An example of one or more super blocks 192 described herein. Super block 290 may include a set of blocks 291 operable to store data 295 (e.g., data 295-a to 295-n). Block 291 may be as described with reference to Figure 1 188 described herein. The memory device 215 may include a map 235. The map 235 may be an example of a flash translation layer (FTL) mapping table or another LBA mapping table that may provide a logical to physical mapping of data 295 within a block 291. The map 235 may also indicate which blocks 291 are included in a corresponding super block 290. The memory device 215 may also include a controller 240. The controller 240 may be as described in reference to Figure 1 An example of a controller 175 is described.

[0049] System 200 may include a memory device 220 (eg, a DRAM device), which may be as described in reference Figure 1 An example of a memory device 155 is described. For example, the memory device 155 may be an example of a byte-addressable memory device. The memory device 220 may include a metadata cache 255, an addressable region 250, and a cache 245. The metadata cache 255 may be operable to store metadata 286, which may be used to support pre-fetch operations. For example, the metadata 286 may indicate a history of one or more previous access sequences that may be replayed in advance (e.g., when the starting point of a previously observed sequence begins). Thus, the metadata 286 may be used to predict subsequent data accesses based on the observed sequence to support pre-fetching data based on the prediction. Figure 2 In an example of, metadata 286 may support the implementation of a temporary prefetcher, such as a managed irregular stream buffer (MISB) prefetcher. For example, metadata 286 may map a physical address of data 295 to a structure address 275 of data 295 (e.g., a physical address of data 295-e to a structure address 275-a, and so on) and map a structure address 275 to a physical address of data 295 (e.g., a structure address 275-a to a physical address of data 295-e, and so on). In some examples, metadata cache 255 may store one or more counters 260 (e.g., counter 260-a, counter 260-b) associated with metadata 286. For example, counter 260 may be used to count the number of accesses to the corresponding metadata 286. In some examples, counter 260 may be referred to as a confidence counter.

[0050] The addressable region 250 may be a flat address space that is directly accessible by a host system such as the core 205. For example, the core 205 and the memory device 220 may be coupled via the bus 206, and the core 205 may directly access the memory device 220 (e.g., the addressable region 250) via the bus 206. The cache 245 may include a volatile memory operable to store the data 295. The cache 245 may be addressable at a byte granularity level. In some examples, the cache 245 may store frequently accessed data 295 or pre-fetched data 295. The cache 245 may be associated with a higher bandwidth and lower access latency relative to the memory device 215. Therefore, the cache 245 may provide high bandwidth and low latency access to the data 295, while the memory device 215 may provide non-volatile and high capacity storage of the data 295.

[0051] The system 200 may include a controller 210. The controller 210 may include a cache 225 that may store metadata 286. In some examples, the cache 225 may be referred to as a metadata cache. In some examples, the controller 210 may include (e.g., generate, maintain, store) one or more counters 260. The controller 210 may, for example, increment the counter 260 for each access to metadata 286 associated with the counter 260. For example, if the metadata 286-a is accessed, such as to support prefetching, the controller 210 may increment the counter 260-a. The controller 210 may also include a buffer 230. The buffer 230 may temporarily store accessed or prefetched data 295. In some examples, data 295 transferred between the memory device 215 and the memory device 220 may be transferred via the buffer 230. In some examples, buffer 230 may include sufficient storage space to store an amount of data 295 that may be stored by one or more super blocks 290 , which may allow data 295 to be efficiently transferred between memory device 215 and memory device 220 .

[0052] Controller 210 may facilitate communications between core 205 and memory devices 215 and 220. For example, controller 210 may be coupled to core 205 via bus 207, to memory device 215 via bus 212, and to memory device 220 via bus 232. Communications between core 205 and memory devices 215 and 220 may be routed via controller 210 via respective buses.

[0053] The controller 210, which may be an example of a prefetch controller, may support (e.g., control, facilitate, perform) prefetching data 295 from (e.g., stored in) the memory device 215 to the memory device 220 (e.g., or directly to the core 205, such as directly to the host system memory). The controller 210 may support prefetching using metadata 286 stored in one or more of the cache 225 or the metadata cache 255. In some examples, the controller 210 may learn data accesses requested by the core 205 (e.g., generate and store metadata 286 indicating data accesses) to predict future data accesses. For example, the controller 210 may receive an access command (e.g., a request) from the memory device 220 to access the data 295. In response to the access command, the controller 210 may access the cache 245 of the memory device 220 to determine whether the cache 245 contains the requested data 295. In the event that the requested data 295 is not located in the cache 245 , the controller 210 may access the memory device 215 to retrieve the data 295 and transfer the data 295 to the cache 245 (eg, and / or to the core 205 ).

[0054] The controller 210 may perform one or more pre-fetch operations according to a pre-fetch strategy, for example, based on the fact that the cache 245 does not store the requested data 295 (e.g., which may be referred to as a cache miss). For example, in response to a cache miss, the controller 210 may initiate a pre-fetch strategy and access the cache 225 to determine whether metadata 286 associated with the requested data 295 is stored in the cache 225. If the metadata 286 is not included in the cache 225, the controller 210 may transfer the metadata 286 from the metadata cache 255 to the cache 225. The controller 210 may utilize the metadata 286 to predict future data requests. For example, if the data 295-a is the requested data 295, the controller 210 may access the metadata 286-a to determine the structure address 275-c. The controller 210 may increment the structure address 275-c to the structure address 275-d to determine the next predicted data 295 to be accessed. For example, the controller 210 may use metadata 286 to map a structure address 275-d to data 295-b to determine which data 295 to prefetch to the cache 245. The controller 210 may move (e.g., copy, transfer, prefetch) the data 295-b to the cache 245 of the memory device 220 so that the data 295-b may be easily accessed for potential future requests (e.g., to avoid subsequent cache misses of the data 295-b). Thus, the controller 210 may utilize metadata 286 associated with the data 295 to prefetch data associated with a future access from the memory device 215 to the memory device 220 before receiving a command from the core 205 to access the future data, so that access latency associated with the system 200 may be reduced.

[0055] In some cases, the controller 210 may prefetch additional data 295 into the cache 245 in response to a cache miss. For example, using metadata 286, the controller 210 may determine to prefetch data 295-c and 295-d into the cache 245 in response to a cache miss of data 295-a. In some cases, the data 295 prefetched by the controller 210 may be located in different Super Blocks 290 of the memory device 215. For example, data 295-b may be located in Super Block 290-b, and data 295-c and 295-d may be located in Super Block 290-c. Accessing data 295 in different Super Blocks 290 may be associated with a higher latency (e.g., may have a random access latency compared to a sequential access latency) than accessing data 295 in the same Super Block 290, which may increase the latency of the prefetch operation and reduce the performance of the system 200.

[0056] According to examples described herein, the controller 210 may initiate data rearrangement techniques to improve performance and efficiency of the system 200. For example, a cache miss of data 295-a in the cache 245 may trigger loading of the data 295-a and prefetching of additional data 295 to the cache 245. For example, the controller 210 accesses the metadata 286-a to identify the data 295-b for prefetching and may use the buffer 230 to transfer the data 295-b to the cache 245. The controller 210 may increment the counter 260-a based on accessing the metadata 286-a.

[0057] exist Figure 2 In an example of , metadata 286 - a may exclude the next structure address 275 (e.g., structure address 275 - e) after structure address 275 - d, and controller 210 may determine whether metadata 286 (e.g., metadata 286 - b) including the next structure address 275 is stored in cache 225. Figure 2 286-b may not be stored to the cache 225, and the controller 210 may transfer the metadata 286-b to the cache 225. The controller 210 may use the metadata 286-b to identify additional data 295-c (e.g., corresponding to the structure address 275-e) and data 295-d (e.g., corresponding to the structure address 275-f) for prefetching and may use the buffer 230 to transfer the data 295-c and 295-d to the cache 245. For example, depending on the number of blocks 291 included in the super block 290 as described herein, the buffer 230 and the metadata 286 may be used to prefetch other amounts of data 295. The controller 210 may increment the counter 260-b based on accessing the metadata 286-b.

[0058] In some examples, the controller 210 may transfer (e.g., retrieve, pre-fetch) data 295 (e.g., data 295-a, 295-b, 295-c, ​​and 295-d) to the addressable region 250 or the core 205 instead of to the cache 245. By pre-fetching to the addressable region 250, or otherwise operating in the flat address space of the host system memory, it may not be necessary to pre-fetch the data 295 to the cache 245. Operating in the addressable region 250 may allow the data 295 to be moved directly into the memory of the core 205, which may be beneficial for the core 205 utilizing a particular protocol (e.g., the CXL protocol). In this case, various pre-fetch suggestions (e.g., pre-fetch data 295) may be stored in the addressable region 250 as a list that the core 205 can read, and the pre-fetch data 295 may be swapped into the host memory.

[0059] In some examples, the controller 210 may determine that the value of the counter 260 satisfies (e.g., is greater than, greater than, or equal to) a threshold value and may initiate a reordering of the data 295, for example, to reduce latency associated with future accesses of the data 295. To support the reordering of the data 295, the controller 210 may prefetch an amount of the data 295 based on the amount of data that can be stored by the super block 290. For example, the controller 210 may set the amount of data 295 to be prefetched to correspond to N-1, where N is the number of blocks 291 included in the super block 290. For example, in Figure 2 In the example of , the data 295 to be reordered may include data 295-a corresponding to data retrieved in response to a cache miss, and pre-fetched data 295-b, 295-c, ​​and 295-d. Thus, the amount of data 295 buffered by buffer 230 (e.g., as part of retrieved data 295-a and pre-fetched data 295-b, 295-c, ​​and 295-d) may be the same as the size of super block 290.

[0060] In some examples, when buffering data 295 to buffer 230, controller 210 may transfer (e.g., write) data 295 to cache 245 (e.g., in the order in which it was retrieved and pre-fetched). That is, controller 210 may write data 295-b, data 295-c, ​​and 295-d to cache 245 so that the contents of buffer 230 are copied to cache 245.

[0061] After buffering the data 295 in the buffer 230, the contents of the buffer 230 may also be written (e.g., copied) to an empty Super Block 290 (e.g., Super Block 290-d) so that the data 295 is reordered within the memory device 215 relative to before the data 295 was retrieved and pre-fetched. For example, the data 295 buffered to the buffer 230 may be from more than one Super Block in the Super Block 290 (e.g., Super Block 290-b, Super Block 290-c). To support reordering the data 295 so that the data 295 is stored in the same Super Block 290, the controller 210 may transmit the data 295 stored in the buffer 230 to the controller 240 along with a Super Block Write Identifier (e.g., a hint, a write command including the Super Block Write Identifier). The Super Block Write Identifier may indicate that the data 295 is to be written to the same Super Block 290. For example, the Super Block Write Identifier may indicate to the controller 240 that the received data 295 (e.g., data 295-a to 205-d) is associated with a predicted sequence associated with a prefetched block 291 and is written to the same Super Block 290 (e.g., an empty Super Block 290), for example, to reduce latency associated with subsequent accesses of the data 295.

[0062] In some examples, the controller 240 may ignore the SuperBlock Write Identifier (e.g., hint), and the Data 295 may remain in one or more SuperBlocks 290. In some examples, the controller 240 may ignore the SuperBlock Write Identifier based on determining that the Block 291 in which the received Data 295 is currently stored is contained in the same SuperBlock 290. Alternatively, in the event that the controller 240 determines that the Data 295 was originally stored in Blocks 291 of more than one SuperBlock in a SuperBlock 290, the controller 240 may write the Data 295 received from the buffer 230 of the controller 210 to an empty SuperBlock 290 (e.g., SuperBlock 290-d), for example, in the same order in which it was received. The controller 240 may update the mapping 235 to indicate that the data 295 is stored in the super block 290-d (e.g., has been copied to the super block 290-d), which may invalidate the data 295 in the scattered blocks 291 within the super block 290 (e.g., invalidate the data 295 stored in the blocks 291 of the super blocks 290-b and 290-c).

[0063] By reordering the data 295 so that portions of the data 295 with high access counts may be located within the same Super Block 290 rather than being scattered across different Super Blocks 290, the bandwidth and latency of the system 200 may be improved. For example, reordering the data 295 may serialize a sequence of data 295 into the same Super Block 290 with a relatively high confidence that all of the data 295 of the sequence will be requested at the same time the next time (e.g., based on the values ​​of one or more counters 260 satisfying a threshold). Thus, the sequence of data 295 may be accessed sequentially or in parallel (e.g., due to being located in the same Super Block 290), which may reduce the latency of accessing the sequence of data 295 compared to performing random accesses to access the data 295.

[0064] According to various techniques, it may be determined that the data 295 is from a different Super Block 290. For example, based on receiving the data 295 and the Super Block Write Identifier from the buffer 230, the controller 240 may access the map 235, in which one of the Super Blocks 290 the block 291 currently storing the data 295 is included. Additionally or alternatively, a data read attribute "block identifier" may be introduced to indicate from which Super Block 290 a given data 295 is retrieved. For example, as part of reading the data 295, for example, as part of retrieving the data 295 in response to a cache miss or as part of pre-fetching the data 295, the corresponding identifier may indicate to the controller 240 and / or the controller 210 in which Super Block 290 the data 295 is stored. Thus, the corresponding identifier of the data 295 may indicate whether the data 295 buffered to the buffer 230 is from the same Super Block 290 or at least two different Super Blocks 290.

[0065] In some examples, the controller 210 may reorder the data 295 as a background operation. For example, in some cases, the controller 210 may facilitate the reordering of the data 295 while prefetching the data 295 (e.g., data 295-b to 295-d) (e.g., a Super Block Write Identifier may be transmitted and / or the data 295 may be written to the same Super Block). In some other cases, the controller 210 may utilize the metadata 286 to reorder the data 295 during periods of low bandwidth utilization, low power mode, or when the memory system (e.g., memory system 110) including the controller 210 is in an idle state, rather than reordering the data 295 in conjunction with performing a prefetch operation (e.g., concurrently with performing a prefetch operation). For example, the controller 210 may recognize that the memory system is in an idle state and traverse the metadata 286 stored in the cache 225 and / or the metadata cache 255, for example, to determine whether any of the counters 260 meet a data reorder threshold. If the threshold is met, the controller 210 may cause the associated data 295 to be reordered. Partially rearranging data 295 as a background operation can help save power and reduce workload on system 200 while still allowing efficient data rearrangement. This data rearrangement can also reduce prefetch latency, for example, by performing the data rearrangement before performing associated prefetch operations.

[0066] The counter 260 for triggering data rearrangement (e.g., and data prefetching) may be implemented according to various techniques. For example, the counter 260 may be implemented as a saturating reuse counter. Here, the counter 260 may include one or more bits for each corresponding block of metadata 286. If metadata 286 is loaded into the cache 255 from the metadata cache 255, the controller 210 may reset the corresponding counter 260 to zero. When the metadata 286 is in the cache 225, the controller 210 may increment the counter 260 each time the metadata 286 is accessed. The counter 260 may be associated with one or more thresholds for triggering data rearrangement and data prefetching. For example, in the event that the value of the counter 260 satisfies (e.g., reaches or exceeds) a first threshold, the controller 210 may use the metadata 286 associated with the counter 260 to perform one or more prefetches of the data 295. In the event that the value of the counter 260 may satisfy a second threshold, the controller 210 may initiate a data rearrangement operation. In some examples, the second threshold may be greater than the first threshold.

[0067] Additionally or alternatively, the counter 260 may be implemented as a persistent metadata counter. Here, the value of the counter 260 may be saved when the associated block of metadata 286 is evicted from the cache 225, and the value of the counter 260 may be reused and adjusted when the associated block of metadata 286 is reloaded into the cache 225. For example, metadata 286 may be evicted from the cache 225 to the metadata cache 255, for example, according to a cache replacement policy, such as a least recently used (LRU) cache replacement policy, as well as other types of cache replacement policies. The controller 210 may store the value of the counter 260 for counting accesses to the metadata 286 at the time of the eviction and the timestamp of the eviction. The controller 210 may then transfer (e.g., reload) the metadata 286 back to the cache 225 and use the stored timestamp to determine the duration between storing the value of the counter (e.g., the eviction of the metadata 286) and the transfer of the metadata 286. The controller 210 may update the stored value of the counter 260 based on the duration. For example, a number corresponding to the amount of time that has elapsed may be subtracted from the stored value of counter 260. For example, controller 210 may reduce the value of counter 260 by a value that is proportional to the duration. In some examples, counter 260 may be associated with one or more thresholds (e.g., a first threshold and a second threshold) for triggering data prefetching and data rearrangement.

[0068] In some other examples, counter 260 may not be used in association with triggering data reordering. For example, without utilizing (eg, or deactivating) counter 260, controller 210 may prefetch data 295 and initiate reordering of data 295 upon each cache miss.

[0069] In some examples, the confidence associated with a data prefetch may be defined as the likelihood that a prefetch suggestion using the associated metadata 286 results in a cache hit (e.g., whether the prefetched data is actually used). Here, each cache line of cache 245 may include a "prefetch" bit indicating whether the data of the cache line is prefetched into the cache (e.g., installed by a prefetcher such as controller 210), and a pointer to a block of metadata 286 for prefetched data (e.g., data 295). Upon a cache hit (e.g., data is requested by core 205 and transmitted to core 205), controller 210 may increment a counter 260 associated with the block of metadata 286. In some examples, this incrementing of counter 260 may be performed instead of incrementing counter 260 based on accessing metadata 286 in cache 225.

[0070] In some examples, the system 200 may support persistent storage of pre-fetch metadata, where the metadata 286 may be backed up to persistent storage (e.g., non-volatile storage) upon power loss or in response to a command to back up the metadata 286 (e.g., to storage of the memory device 215). For example, based on a power loss event (e.g., based on receiving an indication of a power loss event (e.g., power loss of the memory system)) or a command from the core 205 to store the metadata 286 to non-volatile storage (e.g., based on an address range, program identifier, or host identifier that owns the metadata 286), the controller 210 may store (e.g., transfer) the metadata 286 in the cache 225 to the non-volatile storage of the system 200 (e.g., memory device 215) to preserve the pre-fetch predictions associated with the metadata 286 when the system 200 (e.g., memory system) is restarted. Additionally or alternatively, based on a power loss event, the metadata 286 of the metadata cache 255 may be stored to the memory device 215 to be restored upon a subsequent power-on (e.g., restart) event. For example, based on a power-on event following a power loss event, metadata 286 may be transferred from memory device 215 to metadata cache 255. Supporting persistent metadata storage may enable fast restart of data pre-fetching using pre-trained predictions (e.g., rather than generating new metadata 286 after each power-on event).

[0071] In some examples, the context field may be transmitted from the core 205 to the controller 210 along with the read request to improve the effectiveness of the controller 210. The data contained in the context field may allow the controller 210 to separate prefetch streams by instructions, threads, or processes that may be initiating cache misses. By doing so, the controller 210 may predict which of the data 295 may be accessed next and may prefetch them accordingly. Additionally, by separating prefetch streams based on the data contained in the context field, the prefetcher may avoid interference between different threads or processes.

[0072] Figure 3 An example of a system 300 supporting data rearrangement techniques for memory according to an example disclosed herein is shown. Figure 1 and 2 One or more aspects of the described systems 100 or 200 or one or more components thereof implement the system 300. The system 300 may include a core 305, which may be as described in reference Figure 2 The core 305 may be coupled to a controller 310, which may be an instance of or included in the memory system controller 140 or the controller 210, as described with reference to FIGS. Figure 1 and 2 described.

[0073] The system 300 may also include a memory device 315, which may be as described in reference Figure 1 and 2 315 may include one or more superblocks 355, which may include one or more blocks 385 operable to store data 350. Memory device 315 may include map 325, which may be an example of map 235. Memory device 315 may also include controller 330, which may be as described with reference to FIG. Figure 1 The controller 175 described or as referenced Figure 2 An example of controller 240 is described.

[0074] System 300 may include a memory device 320, which may be as described in detail with reference to Figure 1 and 2 320 may include a metadata cache 345, an addressable region 340, and a cache 335, each of which may be as described in reference to FIG. Figure 2 Examples of metadata cache 255, addressable region 250, and cache 245 are described.

[0075] Cache 335 may be constructed to reduce wear and tear on memory device 315 and increase write bandwidth to memory device 315. For example, cache 335 may include one or more of cache lines 370 (e.g., cache line 370-a, cache line 370-b, cache line 370-c, cache line 370-d). Each of cache lines 370 may be divided into sectors 375, which may each be the size of a block 385. In some examples, the size of each of cache lines 370 may correspond to the size of superblock 355 (e.g., 512-byte sectors 375 with an 8-kilobyte cache line size). For example, cache line 370-a may include sector 375-a, sector 375-b, sector 375-c, and sector 375-d, and the size of each of sectors 375 may be equal to the size of one of blocks 385, so that the size of cache line 370-a may be equal to the size of super block 355. Cache 335 may store data 350 transferred between memory device 315 and memory device 320. For example, sector 375-a may store data 350-a, sector 375-b may store data 350-b, sector 375-c may store data 350-c, and sector 375-d may store data 350-d. Data 350 stored in cache 335 may be easily used by controller 310 or core 305.

[0076] In some examples, one or more of the cache lines 370 may include modified sectors 390. For example, cache line 370-c may include three of the modified sectors 390 and cache line 370-d may include one modified sector 390, while cache lines 370-a and 370-b may not include modified sectors 390 (e.g., and may be referred to as clean cache lines 370). Modified sectors 390 may include, for example, data 350 that is modified relative to corresponding data recorded in memory device 315 (e.g., or other main memory). When replacing a cache line 370 (e.g., deleting data of cache line 370 from cache 335 in favor of storing other data in cache 335), controller 310 may first write the contents of modified sectors 390 of cache line 370 to memory device 315 before deleting cache line 370 so that data may not be lost. However, writing data to memory device 315 may be time consuming and degrade memory device 315. Therefore, reducing the number of write operations to memory device 315 may reduce wear on memory device 315 and may improve overall performance of system 300.

[0077] In some examples, a cache replacement policy may be implemented to reduce wear and tear on memory device 315 and increase write bandwidth to memory device 315. Additionally, a sector cache line structure may support reduced wear and increased write bandwidth. For example, controller 310 (e.g., or a controller associated with memory device 320, such as controller 145 or local controller 160) may select one of cache lines 370 for replacement in a priority order (e.g., priority order) indicated by the cache replacement policy. For example, the priority order may instruct the controller 310 to first select a cache line 370 for replacement that does not include a modified sector 390 (e.g., cache line 370-a or 370-b), if there is no cache line 370 without a remaining modified sector 390, then select the cache line 370 with the most (e.g., the largest number) of modified sectors 390 (e.g., cache line 370-c), and finally select the cache line 370 with a smaller number of modified sectors 390 (e.g., cache line 370-d). In the event that the cache 335 may include more than one of the cache lines 370 that does not include a modified sector 390 (e.g., a cache line 370 that includes unmodified data and excludes modified data), the controller 310 may determine that the cache line 370 that may be replaced without a modified sector 390 is the least recently used of the cache lines 370. In the event that the controller 310 may replace a cache line 370 (e.g., cache line 370-b) that does not include a modified sector 390, the data stored in the sectors 375 of the unmodified cache line may already be up to date and may not need to be written to the memory device 315. Thus, the controller 310 may delete the data of such a cache line (e.g., cache line 370-a or 370-b) without writing the data back to the memory device 315, which may reduce writes to the memory device 315, thereby reducing wear on the memory device 315 and saving time and performance that would otherwise be spent on writing to the memory device 315.

[0078] Writing a large amount of modified data to the memory device 315 in a single replacement operation may increase (e.g., maximize) write bandwidth relative to writing a smaller amount of modified data, where the controller 310 may replace the cache line 370 (e.g., cache line 370-c) containing the most modified sectors 390 or replace to another cache line 370 (e.g., cache line 370-d) containing the modified sectors 390. In this case, the controller 310 may access the modified sectors 390 of the selected cache line 370 and may write (e.g., transfer) the modified data stored to the modified sectors 390 to the memory device 315. Then, the controller 310 may delete the selected cache line 370. Thus, implementing a sector cache and replacement strategy may result in the controller 310 efficiently storing data to the cache 335 and replacing cache lines 370 of the cache 335, which may improve the overall performance of the system 300.

[0079] Figure 4 A block diagram 400 is shown of a memory system 420 supporting data rearrangement techniques for memory according to examples as disclosed herein. The memory system 420 may be a memory system as described in reference to Figures 1 to 3 4. The memory system 420 or its various components may be examples of means for performing various aspects of the data rearrangement techniques of memory as described herein. For example, the memory system 420 may include an access component 425, a transfer component 430, a command component 435, a write component 440, a mapping component 445, a counter component 450, a state component 455, a prefetch component 460, or any combination thereof. Components of each of these components or subcomponents thereof (e.g., one or more processors, one or more memories) may communicate with each other directly or indirectly (e.g., via one or more buses).

[0080] The access component 425 may be configured as or otherwise support means for accessing first data from a first block of a first memory device by a controller of a memory system including a first memory device having a first type of memory and a second memory device having a second type of memory. In some examples, the access component 425 may be configured as or otherwise support means for accessing metadata associated with the first data according to a pre-fetch strategy by the controller based on accessing the first data. The transfer component 430 may be configured as or otherwise support means for transferring second data from one or more second blocks of a first memory device to a second memory device by the controller based on the metadata and the pre-fetch strategy, wherein the first block is included in a first super block of the first memory device and at least one of the one or more second blocks is included in a second super block of the first memory device. The command component 435 may be configured as or otherwise support means for transmitting a command for writing the first data and the second data to a third super block of the first memory device from the controller to the first memory device based on a value of a counter associated with the metadata.

[0081] In some examples, write component 440 may be configured as or otherwise support means for writing the first data and the second data to the third super block based on a command by the first memory device.

[0082] In some examples, write component 440 may be configured as or otherwise support means for ignoring, by the first memory device, a command for writing first data and second data to a third super block, wherein after the command is transmitted based on the ignore, the first data is retained in the first block and the second data is retained in one or more second blocks.

[0083] In some examples, to support transmitting the second data, the transmitting component 430 may be configured to or otherwise support means for transmitting the second data based on the amount of data that can be stored by the corresponding super block, wherein the amount of the first data and the second data is equal to the amount of data that can be stored by the corresponding super block.

[0084] In some examples, the second data is transferred to the cache of the second memory device concurrently with the transmission, execution, or both of a command to write the first data and the second data to the third super block.

[0085] In some examples, to support transmission of a command for writing the first data and the second data to a third super block, command component 435 may be configured as or otherwise support means for transmitting an indication that the first data and the second data are associated with a predicted sequence of blocks associated with a prefetch operation.

[0086] In some examples, access component 425 may be configured or otherwise support means for accessing a mapping table based on a command by a first memory device to determine that a first block is included in a first Super Block and at least one of one or more second blocks is included in a second Super Block. In some examples, write component 440 may be configured or otherwise support means for writing first data and second data to a third Super Block based on a command and determination by a first memory device. In some examples, mapping component 445 may be configured or otherwise support means for updating a mapping table based on writing the first data and second data to a third Super Block by a first memory device to indicate that the first data and second data are stored in a third Super Block.

[0087] In some examples, access component 245 may be configured to or otherwise support means for determining that a first block is included in a first super block and at least one of one or more second blocks is included in a second super block based on a first identifier associated with the first block and a second identifier associated with at least one of the one or more second blocks.

[0088] In some examples, the counter component 450 may be configured as or otherwise support means for updating a value of a counter associated with the metadata based on accessing metadata associated with the first data, wherein the value of the counter satisfies a threshold based on the updated value, and wherein a command is transmitted based on the value of the counter satisfying the threshold.

[0089] In some examples, the command is transmitted based on the value of the counter satisfying a threshold. In some examples, to support transmitting the second data, the transmitting component 430 may be configured to or otherwise support means for transmitting the second data according to the pre-fetch strategy based on the value of the counter satisfying a second threshold, wherein the second threshold is less than the threshold.

[0090] In some instances, the transfer component 430 may be configured or otherwise support means for evicting, by the controller, the metadata from a metadata cache of the controller after transmitting the second data. In some instances, the counter component 450 may be configured or otherwise support means for storing, by the controller, a value of a counter and a timestamp associated with the evicted metadata based on the evicted metadata. In some instances, the transfer component 430 may be configured or otherwise support means for transmitting, by the controller, the metadata to the metadata cache according to a prefetch policy after storing the value. In some instances, the counter component 450 may be configured or otherwise support means for determining, based on the timestamp, a duration between storing the value of the counter and transmitting the metadata to the metadata cache. In some instances, the counter component 450 may be configured or otherwise support means for updating the value of the counter based on the duration.

[0091] In some examples, to support updating the value of the counter, the counter component 450 can be configured or otherwise support means for decreasing the value of the counter by a second value that is proportional to the duration.

[0092] In some examples, to support transferring the second data, transfer component 430 can be configured or otherwise support means for transferring the second data to a cache of the second memory device or a portion of the second memory device directly addressable by the host system.

[0093] In some examples, write component 440 can be configured or otherwise support means for storing metadata to the first memory device based on a power loss event associated with the memory system, a second command to store metadata, or a combination thereof.

[0094] In some examples, transfer component 430 can be configured or otherwise support means for transferring metadata from a first memory device to a second memory device based on a power on event following a power loss event.

[0095] In some examples, a respective super block of the first memory device includes a set of respective blocks.

[0096] Additionally or alternatively, access component 425 may be configured to or otherwise support means for accessing metadata associated with a pre-fetch operation by a controller of a memory system including a first memory device having a first type of memory and a second memory device having a second type of memory to transfer data from the first memory device to the second memory device. Command component 435 may be configured to or otherwise support means for transmitting, based on the access metadata, a command for writing first data associated with a first Super Block of the first memory device and second data associated with a second Super Block of the first memory device to a third Super Block of the first memory device based at least in part on a value of a counter satisfying a threshold, from the controller to the first memory device.

[0097] In some examples, state component 455 can be configured or otherwise support means for identifying a state of the memory system by the controller, wherein the state includes a low bandwidth utilization state, a low power state, an idle state, or a combination thereof, wherein metadata is accessed based on the identification.

[0098] In some examples, the command is transmitted based on the counter satisfying a threshold while the memory system is in the state.

[0099] In some examples, prefetch component 460 can be configured or otherwise support means for performing, by a controller, a prefetch operation based on accessing metadata, wherein commands are transmitted based on performing the prefetch operation.

[0100] Additionally or alternatively, command component 435 may be configured or otherwise support means for transmitting, through a controller of a memory system including a first memory device having a first type of memory and a second memory device having a second type of memory, a command for accessing data associated with a block of a super block of the first memory device. Transfer component 430 may be configured or otherwise support means for transferring data from the block to a cache of the second memory device based on the command, wherein the cache is associated with a cache line size equal to the size of the super block, and wherein each cache line of the cache includes a number of sectors, the size of the respective sector being equal to the size of the block.

[0101] In some examples, the described functionality of the memory system 420 or its various components may be supported by or may refer to at least a portion of at least one processor, where such at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some examples, the described functionality of the memory system 420 or its various components may be implemented at least in part by instructions (e.g., stored in a memory, a non-transitory computer-readable medium) that are executable by such at least one processor.

[0102] Figure 5 A flowchart illustrating a method 500 for supporting data rearrangement techniques for memory according to an example as disclosed herein is shown. The operations of the method 500 may be implemented by a memory system or components thereof as described herein. For example, the method 500 may be implemented by a memory system or components thereof as described herein. Figures 1 to 4 The described memory system performs the operations of method 500. In some examples, the memory system may execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0103] At 505, the method may include, by a controller of a memory system including a first memory device having a first type of memory and a second memory device having a second type of memory, accessing first data from a first block of the first memory device. The operation of 505 may be performed according to examples as disclosed herein. In some examples, the system including a first memory device having a first type of memory (e.g., memory device 170, 215) and a second memory device having a second type of memory (e.g., memory device 155, 220) may include a controller (e.g., controller 140, 210) that may access the first data 295 from the first block 291 of the first memory device ... Figure 4 The described access component 425 performs aspects of the operations of 505 .

[0104] At 510, the method may include accessing, by the controller, metadata associated with the first data according to a pre-fetch strategy based on accessing the first data. The operation of 510 may be performed according to examples as disclosed herein. In some examples, the controller 140, 210 may access metadata 286 associated with the first data 295 (e.g., located in the cache 225, the metadata cache 255) according to the pre-fetch strategy. In some examples, the controller 140, 210 may access metadata 286 associated with the first data 295 (e.g., located in the cache 225, the metadata cache 255) according to the pre-fetch strategy. Figure 4 The described access component 425 performs aspects of the operations of 510 .

[0105] At 515, the method may include transferring, by a controller, second data from one or more second blocks of a first memory device to a second memory device based on the metadata and according to a pre-fetch policy, wherein the first block is included in a first super block of the first memory device and at least one of the one or more second blocks is included in a second super block of the first memory device. The operation of 515 may be performed according to examples as disclosed herein. In some examples, a controller (e.g., controller 140, 210) may transfer, based on the metadata 286 and according to a pre-fetch policy, second data 295 from one or more second blocks 291 of a first memory device (e.g., memory device 170, 215) to a second memory device (e.g., memory device 155, 220), wherein the first block 291 is included in a first super block 290 of the first memory device and at least one of the one or more second blocks 291 is included in a second super block 290 of the first memory device. In some examples, the controller (e.g., controller 140, 210) may transfer, based on the metadata 286 and according to a pre-fetch policy, second data 295 from one or more second blocks 291 of a first memory device (e.g., memory device 170, 215) to a second memory device (e.g., memory device 155, 220), wherein the first block 291 is included in a first super block 290 of the first memory device and at least one of the one or more second blocks 291 is included in a second super block 290 of the first memory device. Figure 4 Aspects of the operations of the described transport component 430 performing 515 .

[0106] At 520, the method may include transmitting from the controller to the first memory device a command for writing the first data and the second data to a third Super Block of the first memory device based on the value of the counter associated with the metadata satisfying the threshold. The operation of 520 may be performed according to examples as disclosed herein. In some examples, the controller (e.g., controller 140, 210) may transmit to the first memory device (e.g., memory device 155, 220) a command for writing the first data 295 and the second data 295 to a third Super Block 290 of the first memory device based on the value of the counter 260 associated with the metadata 286 satisfying the threshold. In some examples, the controller (e.g., controller 140, 210) may transmit to the first memory device (e.g., memory device 155, 220) a command for writing the first data 295 and the second data 295 to a third Super Block 290 of the first memory device based on the value of the counter 260 associated with the metadata 286 satisfying the threshold. Figure 4 Aspects of the operations of command component 435 execution 520 are described.

[0107] In some examples, an apparatus as described herein may perform one or several methods, such as method 500. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0108] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, components, or instructions for each of the following, or any combination thereof: accessing first data from a first block of a first memory device having a first type of memory and a second memory device having a second type of memory by a controller of a memory system comprising the first memory device having a first type of memory and a second memory device having a second type of memory; accessing metadata associated with the first data according to a prefetch strategy based on accessing the first data by the controller; transferring second data from one or more second blocks of the first memory device to the second memory device by the controller based on the metadata and the prefetch strategy, wherein the first block is included in a first superblock of the first memory device and at least one of the one or more second blocks is included in a second superblock of the first memory device; and transmitting a command for writing the first data and the second data to a third superblock of the first memory device from the controller to the first memory device based on a value of a counter associated with the metadata.

[0109] Aspect 2: The method, apparatus, or non-transitory computer-readable medium according to Aspect 1, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for writing the first data and the second data to the third super block based on the command through the first memory device.

[0110] Aspect 3: The method, apparatus or non-transitory computer-readable medium according to Aspect 1, further comprising an operation, feature, circuit system, logic, component or instruction or any combination thereof for ignoring, by the first memory device, the command for writing the first data and the second data to the third super block, wherein after the command transmission based on the ignoring, the first data is retained in the first block and the second data is retained in the one or more second blocks.

[0111] Aspect 4: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 3, wherein transmitting the second data includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for transmitting the second data based on the amount of data that can be stored by the corresponding super block, wherein the amount of the first data and the second data is equal to the amount of data that can be stored by the corresponding super block.

[0112] Aspect 5: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 4, wherein the second data is transferred to the cache of the second memory device simultaneously with the transmission, execution, or both of the command to write the first data and the second data to the third super block.

[0113] Aspect 6: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 5, wherein transmitting the command for writing the first data and the second data to the third super block includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for transmitting an indication that the first data and the second data are associated with a predicted sequence of blocks associated with a prefetch operation.

[0114] Aspect 7: A method, apparatus or non-transitory computer-readable medium according to any one of Aspects 1 to 6, further comprising operations, features, circuit systems, logic, components or instructions or any combination thereof for: accessing a mapping table based on the command by the first memory device to determine that the first block is included in the first super block and at least one of the one or more second blocks is included in the second super block; writing the first data and the second data to the third super block based on the command and the determination by the first memory device; and updating the mapping table based on writing the first data and the second data to the third super block by the first memory device to indicate that the first data and the second data are stored in the third super block.

[0115] Aspect 8: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 7, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for determining that the first block is included in the first super block and that at least one of the one or more second blocks is included in the second super block based on a first identifier associated with the first block and a second identifier associated with the at least one of the one or more second blocks.

[0116] Aspect 9: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 8, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for updating the value of the counter associated with the metadata based on accessing the metadata associated with the first data, wherein the value of the counter satisfies a threshold based on updating the value, and wherein the command is transmitted based on the value of the counter satisfying the threshold.

[0117] Aspect 10: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 9, wherein the command is transmitted based on the value of the counter satisfying a threshold, and wherein transmitting the second data includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for transmitting the second data according to the prefetch strategy based on the value of the counter satisfying a second threshold, wherein the second threshold is less than the threshold.

[0118] Aspect 11: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 10, further comprising operations, features, circuit systems, logic, components, or instructions for: evicting the metadata from a metadata cache of the controller by the controller after transmitting the second data; storing the value of the counter and a timestamp associated with the eviction of the metadata by the controller based on the eviction of the metadata; transmitting the metadata to the metadata cache by the controller according to the prefetch policy after storing the value; determining a duration between storing the value of the counter and transmitting the metadata to the metadata cache based on the timestamp; and updating the value of the counter based on the duration.

[0119] Aspect 12: A method, apparatus, or non-transitory computer-readable medium according to Aspect 11, wherein updating the value of the counter includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for reducing the value of the counter by a second value proportional to the duration.

[0120] Aspect 13: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 12, wherein transferring the second data includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for transferring the second data to a cache of the second memory device or a portion of the second memory device that can be directly addressed by a host system.

[0121] Aspect 14: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 13, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for storing the metadata to the first memory device based on a power loss event associated with the memory system, a second command for storing the metadata, or a combination thereof.

[0122] Aspect 15: The method, apparatus, or non-transitory computer-readable medium of Aspect 14, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for transferring the metadata from the first memory device to the second memory device based on a power-on event following the power loss event.

[0123] Aspect 16: The method, apparatus, or non-transitory computer-readable medium of any of Aspects 1-15, wherein a respective super block of the first memory device comprises a set of respective blocks.

[0124] Figure 6 A flowchart illustrating a method 600 for supporting data rearrangement techniques for memory according to an example as disclosed herein is shown. The operations of the method 600 may be implemented by a memory system or components thereof as described herein. For example, the method 600 may be implemented by a memory system or components thereof as described herein. Figures 1 to 4 The described memory system performs the operations of method 600. In some examples, the memory system may execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0125] At 605, a method may include accessing, by a controller of a memory system including a first memory device having a first type of memory and a second memory device having a second type of memory, metadata associated with a prefetch operation to transfer data from the first memory device to the second memory device. The operation of 605 may be performed according to examples as disclosed herein. In some examples, a controller (e.g., controller 140, 210) of a memory system (e.g., memory system 110) including a first memory device having a first type of memory (e.g., memory device 170, 215) and a second memory device having a second type of memory (e.g., memory device 155, 220) may access metadata 286 associated with a prefetch operation (e.g., which may be located in cache 225, metadata cache 255) to transfer data from the first memory device to the second memory device. In some examples, the metadata 286 may be accessed by a controller (e.g., controller 140, 210) as described in reference to Figure 4 Aspects of the operations of access component 425 performing 605 are described.

[0126] At 610, the method may include transmitting, from a controller to the first memory device, based on the access metadata, a command for writing first data associated with a first Super Block of the first memory device and second data associated with a second Super Block of the first memory device to a third Super Block of the first memory device based at least in part on a value of a counter satisfying a threshold. The operation of 610 may be performed according to examples as disclosed herein. In some examples, a controller (e.g., controller 140, 210) may transmit, to the first memory device, based on the access metadata 286, a command for writing first data 295 associated with a first Super Block 290 of a first memory device (e.g., memory devices 155, 215) and second data 295 associated with a second Super Block 290 of the first memory device to a third Super Block 290 of the first memory device based at least in part on a value of a counter 260 satisfying a threshold. In some examples, the operation of 610 may be performed according to examples as disclosed herein. Figure 4 Aspects of the operations of command component 435 execution 610 are described.

[0127] In some examples, an apparatus as described herein may perform one or several methods, such as method 600. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0128] Aspect 17: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, components, or instructions for each of the following, or any combination thereof: accessing metadata associated with a prefetch operation to transfer data from the first memory device to the second memory device by a controller of a memory system including a first memory device having a first type of memory and a second memory device having a second type of memory and based on accessing the metadata, transmitting from the controller to the first memory device a command for writing first data associated with a first super block of the first memory device and second data associated with a second super block of the first memory device to a third super block of the first memory device based at least in part on a value of a counter satisfying a threshold.

[0129] Aspect 18: The method, apparatus, or non-transitory computer-readable medium of Aspect 17, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for identifying, by the controller, a state of the memory system, wherein the state comprises a low bandwidth utilization state, a low power state, an idle state, or a combination thereof, wherein the metadata is accessed based on the identification.

[0130] Aspect 19: The method, apparatus, or non-transitory computer-readable medium of Aspect 18, wherein the command is transmitted based on the counter satisfying the threshold when the memory system is in the state.

[0131] Aspect 20: The method, apparatus, or non-transitory computer-readable medium of Aspect 17, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for performing the pre-fetch operation by the controller based on accessing the metadata, wherein the command is transmitted based on performing the pre-fetch operation.

[0132] Figure 7 A flowchart illustrating a method 700 for supporting data rearrangement techniques for memory according to an example as disclosed herein is shown. The operations of the method 700 may be implemented by a memory system or components thereof as described herein. For example, the method 700 may be implemented by a memory system or components thereof as described herein. Figures 1 to 4 The described memory system performs the operations of method 700. In some examples, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0133] At 705, a method may include transmitting, by a controller of a memory system including a first memory device having a first type of memory and a second memory device having a second type of memory, a command to access data associated with a block of a super block of the first memory device. The operation of 705 may be performed according to examples as disclosed herein. In some examples, a controller 310 of a memory system (e.g., memory system 110 such as system 300) including a first memory device having a first type of memory (e.g., memory device 315) and a second memory device having a second type of memory (e.g., memory device 320) may transmit a command to access data 350 associated with a block 385 of a super block 355 of the first memory device. In some examples, the command may be transmitted by a controller as described in reference to Figure 4 The described access component 425 performs aspects of the operations of 705 .

[0134] At 710, the method may include transferring the data from the block to a cache of the second memory device based on the command, wherein the cache is associated with a cache line size equal to the size of the super block, and wherein each cache line of the cache includes a number of sectors, the size of the corresponding sector being equal to the size of the block. The operation of 710 may be performed according to examples as disclosed herein. In some examples, the controller 310 may transfer the data 350 from the block 385 to a cache 335 of the second memory device based on the command, wherein the cache 335 may be associated with a cache line size equal to the size of the super block 355, and wherein each cache line 370 of the cache 335 may include a number of sectors 375, the size of the corresponding sector 375 being equal to the size of the block 385. In some examples, the controller 310 may transfer the data 350 from the block 385 to a cache 335 of the second memory device based on the command, wherein the cache 335 may be associated with a cache line size equal to the size of the super block 355, and wherein each cache line 370 of the cache 335 may include a number of sectors 375, the size of the corresponding sector 375 being equal to the size of the block 385. Figure 4 The described transfer component 430 performs aspects of the operations of 710 .

[0135] In some examples, an apparatus as described herein may perform one or several methods, such as method 700. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0136] Aspect 21: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: transmitting, by a controller of a memory system comprising a first memory device having a first type of memory and a second memory device having a second type of memory, a command for accessing data associated with a block of a superblock of the first memory device; and transferring the data from the block to a cache of the second memory device based on the command, wherein the cache is associated with a cache line size equal to the size of the superblock, and wherein each cache line of the cache comprises a certain number of sectors, the size of the corresponding sector being equal to the size of the block.

[0137] It should be noted that the aspects described herein describe possible implementations, and that operations and steps may be rearranged or otherwise modified and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0138] An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:

[0139] Aspect 22: An apparatus comprising: a first memory device having a first type of memory; a second memory device having a second type of memory; a buffer coupled to the first memory device and the second memory device, the buffer being configured to transfer data between the first memory device and the second memory device according to a prefetch operation; and a controller coupled to the first memory device, the second memory device and the buffer, the controller being configured to transmit a command to the first memory device for writing first data contained in a first super block of the first memory device and second data contained in a second super block of the first memory device to a third super block of the first memory device based on the prefetch operation.

[0140] Aspect 23: The apparatus of aspect 22, wherein the first memory device is configured to: write the first data and the second data to the third super block based on the command.

[0141] Aspect 24: An apparatus according to Aspect 22, wherein the first memory device is configured to: ignore the command for writing the first data and the second data to the third super block, wherein after the transmission of the command based on ignoring the command, the first data remains in the first super block and the second data remains in the second super block.

[0142] Aspect 25: An apparatus according to any one of Aspects 22 to 24, wherein the controller includes a metadata cache configured to store metadata associated with the data and a counter for counting accesses to the metadata, and the controller is configured to transmit the command based on the value of the counter satisfying a threshold.

[0143] Aspect 26: An apparatus according to Aspect 25, wherein the controller is further configured to: transfer the metadata from the second memory device to the metadata cache based on the prefetch operation; set the value of the counter to zero based on the transfer of the metadata to the metadata cache; and when the metadata is located in the metadata cache, increment the value of the counter for each access to the metadata, wherein the value of the counter satisfies the threshold based on incrementing the value of the counter.

[0144] Aspect 27: The apparatus of aspect 25, wherein the controller is further configured to: evict the metadata from the metadata cache to the second memory device; and store the value of the counter at the time of the eviction of the metadata and a timestamp of the eviction of the metadata.

[0145] Aspect 28: An apparatus according to Aspect 27, wherein the controller is further configured to: transfer the metadata from the second memory device to the metadata cache after storing the value of the counter; determine the duration between storing the value of the counter and transferring the metadata to the metadata cache based on the timestamp; and update the value of the counter based on the duration.

[0146] Aspect 29: The apparatus of any one of aspects 22 to 28, wherein the controller is configured to transmit the command based on performing the prefetch operation.

[0147] Aspect 30: An apparatus according to any one of Aspects 22 to 29, wherein the first memory device includes a second controller, the second controller being configured to: access a mapping table of the first memory device based on the command to determine that the first data is included in the first super block and the second data is included in the second super block; and update the mapping table to indicate that the first data and the second data are stored in the third super block based on writing the first data and the second data to the third super block according to the command.

[0148] Aspect 31: An apparatus according to any one of Aspects 22 to 30, wherein the controller is further configured to: transmit to the first memory device a second command for writing third data contained in a fourth super block and fourth data contained in a fifth super block to a sixth super block of the first memory device based on a state of the apparatus, the state of the apparatus including a low bandwidth utilization state, a low power state, an idle state, or a combination thereof.

[0149] An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:

[0150] Aspect 32: An apparatus comprising: a first memory device having a first type of memory and comprising one or more super blocks, each super block comprising a certain number of blocks; and a second memory device having a second type of memory and coupled to the first memory device, the second memory device comprising a cache having a cache line size equal to the size of a corresponding super block, wherein each cache line of the cache comprises a certain number of sectors, wherein the size of the corresponding sector is equal to the size of a block of the first memory device.

[0151] Aspect 33: The apparatus according to Aspect 32 further comprises: a controller coupled to the first memory device and the second memory device, the controller being configured to transfer data between the one or more super blocks of the first memory device and one or more cache lines of the cache.

[0152] Aspect 34: An apparatus according to any one of Aspects 32 to 33, wherein the second memory device is configured to: select one or more cache lines of the cache to be replaced according to a replacement policy indicating a priority order for cache line replacement, the priority order indicating replacing cache lines containing unmodified data and excluding modified data, and then replacing cache lines having a larger number of modified data relative to other cache lines containing modified data.

[0153] Aspect 35: The apparatus of aspect 34, wherein the second memory device is configured to: delete a selected cache line based on the cache line including unmodified data and excluding modified data.

[0154] Aspect 36: An apparatus according to any one of Aspects 34 to 35, wherein the controller is further configured to transfer modified data from a selected cache line containing the modified data to the first memory device, and the second memory device is configured to delete the selected cache line after transferring the modified data to the first memory device.

[0155] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0156] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with (e.g., in conductive contact with, connected to, coupled to) each other if there is any electrical path (e.g., conductive path) between the components that can support the flow of signals (e.g., charge, current, voltage) between the components at any time. The conductive path between components that are in electronic communication with (e.g., in conductive contact with, connected to, coupled to) each other may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components or may be an indirect conductive path that includes an intermediate component (e.g., a switch, transistor, or other component). In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., a switch or transistor).

[0157] The term "coupled" (e.g., "electrically coupled") may refer to a state of moving from an open circuit relationship between components, where signals are currently unable to communicate between the components (e.g., through conductive paths), to a closed circuit relationship between the components, where signals are able to communicate between the components (e.g., through conductive paths). When a component, such as a controller, couples other components together, the component may induce a change that allows signals to flow between the other components through conductive paths that previously did not permit signal flow.

[0158] As used herein, including in the claims, the article "a" before a noun is open-ended and is understood to refer to "at least one" of the noun or "one or more" of the noun. Therefore, the terms "one", "at least one", "one or more", and "at least one of one or more" may be interchangeable. For example, if a claim recites a "component" that performs one or more functions, each of the individual functions may be performed by a single component or any combination of multiple components. Therefore, a "component" having a characteristic or performing a function may refer to "at least one of one or more components" having a specific characteristic or performing a specific function. The subsequent use of the term "the / said" to refer to the component introduced with the article "a" may refer to any one or all of the one or more components. For example, a component introduced with the article "a" may be understood to mean "one or more components", and then referring to a "component" in the claims may be understood to be equivalent to referring to "at least one of one or more components".

[0159] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species, including but not limited to phosphorus, boron, or arsenic.

[0160] The switching components (e.g., transistors) discussed herein may be field effect transistors (FETs), and may include a source (e.g., a source terminal), a drain (e.g., a drain terminal), a channel between the source and the drain, and a gate (e.g., a gate terminal). The conductivity of the channel may be controlled (e.g., modulated) by applying a voltage to the gate, which may cause the channel to become conductive in some examples. The switching components may be examples of n-type FETs or p-type FETs.

[0161] The description set forth herein in conjunction with the drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0162] In the accompanying drawings, similar components or features may have the same reference label. Similar components may be distinguished by following the reference label with one or more dashes and an additional label to distinguish among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components with the same first reference label without regard to the additional reference label.

[0163] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions (e.g., code). Due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features that implement the functions may be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations.

[0164] The illustrative blocks and modules described herein may be implemented or executed using a processor designed to perform the functions described herein, such as a DSP, ASIC, FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or any type of processor. A processor may also be implemented as at least one of one or more computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0165] As used herein, including in the claims, "or" as used in a list of items (for example, a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, so that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" can be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on".

[0166] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media or combination of multiple media that can be accessed by a computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disk storage, magnetic disk storage or other magnetic storage, or any other non-transitory media or combination of media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a computer or processor.

[0167] The description and drawings are provided to enable those skilled in the art to make or use the present disclosure. Those skilled in the art will appreciate various modifications to the present disclosure, and the techniques disclosed herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be in the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: accessing, by a controller of a memory system including a first memory device having a first type of memory and a second memory device having a second type of memory, first data from a first block of the first memory device; accessing, by the controller, metadata associated with the first data according to a pre-fetch policy based on accessing the first data; transferring, by the controller, second data from one or more second blocks of the first memory device to the second memory device based on the metadata and the prefetch policy, wherein the first block is included in a first super block of the first memory device and at least one of the one or more second blocks is included in a second super block of the first memory device; and A command to write the first data and the second data to a third super block of the first memory device is transmitted from the controller to the first memory device based on a value of a counter associated with the metadata.

2. The method according to claim 1, further comprising: The first data and the second data are written to the third super block by the first memory device based on the command.

3. The method according to claim 1, further comprising: The command for writing the first data and the second data to the third super block is ignored by the first memory device, wherein after the transmission of the command based on the ignored command, the first data remains in the first block and the second data remains in the one or more second blocks.

4. The method of claim 1, wherein transmitting the second data comprises: The second data is transmitted based on an amount of data that can be stored by a corresponding Super Block, wherein the amount of the first data and the second data is equal to the amount of data that can be stored by the corresponding Super Block.

5. The method of claim 1, wherein concurrently with the transmission, execution, or both of the command to write the first and second data to the third super block, the second data is transferred to a cache of the second memory device.

6. The method according to claim 1, further comprising: accessing, by the first memory device based on the command, a mapping table to determine that the first block is included in the first Super Block and the at least one of the one or more second blocks is included in the second Super Block; writing, by the first memory device, the first data and the second data to the third super block based on the command and the determination; and The mapping table is updated by the first memory device based on writing the first data and the second data to the third Super Block to indicate that the first data and the second data are stored in the third Super Block.

7. The method according to claim 1, further comprising: It is determined based on a first identifier associated with the first block and a second identifier associated with the at least one of the one or more second blocks that the first block is included in the first Super Block and the at least one of the one or more second blocks is included in the second Super Block.

8. The method according to claim 1, further comprising: The value of the counter associated with the metadata is updated based on accessing the metadata associated with the first data, wherein the value of the counter satisfies a threshold based on updating the value, and wherein the command is transmitted based on the value of the counter satisfying the threshold.

9. The method of claim 1 , wherein the command is transmitted based on the value of the counter satisfying a threshold, and wherein transmitting the second data comprises: The second data is transmitted according to the prefetch policy based on the value of the counter satisfying a second threshold, wherein the second threshold is less than the threshold.

10. The method according to claim 1, further comprising: evicting, by the controller, the metadata from a metadata cache of the controller after transmitting the second data; storing, by the controller based on evicting the metadata, the value of the counter and a timestamp associated with evicting the metadata; transferring, by the controller, the metadata to the metadata cache according to the prefetch policy after storing the value; determining, based on the timestamp, a duration between storing the value of the counter and the transmitting the metadata to the metadata cache; and The value of the counter is updated based on the duration.

11. The method according to claim 1, further comprising: The metadata is stored to the first memory device based on a power loss event associated with the memory system, a second command to store the metadata, or a combination thereof.

12. The method of claim 1, wherein a respective super block of the first memory device comprises a set of respective blocks.

13. An apparatus comprising: a first memory device having a first type of memory; a second memory device having a second type of memory; a buffer coupled to the first memory device and the second memory device, the buffer configured to transfer data between the first memory device and the second memory device according to a prefetch operation; and A controller coupled to the first memory device, the second memory device, and the buffer, the controller being configured to transmit to the first memory device a command for writing first data contained in a first super block of the first memory device and second data contained in a second super block of the first memory device to a third super block of the first memory device based on the prefetch operation.

14. The apparatus of claim 13, wherein the first memory device is configured to: writing the first data and the second data to the third super block based on the command; or The command for writing the first data and the second data to the third Super Block is ignored, wherein after the transmission of the command based on ignoring the command, the first data remains in the first Super Block and the second data remains in the second Super Block.

15. The apparatus of claim 13, wherein: The controller includes a metadata cache configured to store metadata associated with the data and a counter for counting accesses to the metadata, and The controller is configured to transmit the command based on the value of the counter satisfying a threshold value.

16. The apparatus of claim 15, wherein the controller is further configured to: transferring the metadata from the second memory device to the metadata cache based on the prefetch operation; setting the value of the counter to zero based on the transmitting the metadata to the metadata cache; and The value of the counter is incremented for each access of the metadata while the metadata is in the metadata cache, wherein the value of the counter satisfies the threshold based on incrementing the value of the counter.

17. The apparatus of claim 15, wherein the controller is further configured to: evicting the metadata from the metadata cache to the second memory device; storing the value of the counter at the time of the eviction of the metadata and a timestamp of the eviction of the metadata; transferring the metadata from the second memory device to the metadata cache after storing the value of the counter; determining, based on the timestamp, a duration between storing the value of the counter and the transmitting the metadata to the metadata cache; and The value of the counter is updated based on the duration.

18. The apparatus of claim 13, wherein the controller is further configured to: A second command for writing the third data contained in the fourth super block and the fourth data contained in the fifth super block to the sixth super block of the first memory device is transmitted to the first memory device based on the state of the device, wherein the state of the device includes a low bandwidth utilization state, a low power state, an idle state, or a combination thereof.

19. A method comprising: accessing, by a controller of a memory system including a first memory device having a first type of memory and a second memory device having a second type of memory, metadata associated with a prefetch operation to transfer data from the first memory device to the second memory device; and Based on accessing the metadata, a command is transmitted from the controller to the first memory device to write first data associated with a first super block of the first memory device and second data associated with a second super block of the first memory device to a third super block of the first memory device based on a value of a counter satisfying a threshold.

20. The method of claim 19, further comprising: A state of the memory system is identified by the controller, wherein the state comprises a low bandwidth utilization state, a low power state, an idle state, or a combination thereof, wherein the metadata is accessed based on the identification.

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