A wafer-level chip batch programming and testing method

Abstract

The present invention discloses a wafer-level chip batch programming and testing method, which relates to the technical field of chip batch programming and testing, and includes the following steps: Step 1, etch a plurality of chips on a wafer and reserve a scribing lane area. The scribing lane area is distributed in a crisscross pattern and is used to deploy a programming communication network and communication connections; Step 2, utilize the crisscross scribing lane area to construct a data communication network on the wafer. The data communication network arranges devices and metal connections for chip programming and communication in each scribing lane area. By performing batch programming and testing at the wafer level, the present invention improves the programming efficiency and success rate, reduces operation steps, and enhances production efficiency. By constructing a data communication network and using a unique device identifier, independent identification and control of chips are achieved. The comprehensive electrical performance testing combined with the clustering algorithm accurately detects and analyzes anomalies, improving product quality and production reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of chip batch programming and testing, and particularly to a wafer-level chip batch programming and testing method. Background Art

[0002] When RFID tag chips leave the factory, some device information (TID, EPC, and security information) needs to be programmed into the storage area of the chips one by one. The traditional programming method is generally to program the chips one by one after dicing the chips, during or after the chip packaging process. The programming efficiency is low and it is not easy to carry out large-scale production and testing. In addition, after the chips are packaged into tags, there is a certain probability of failure in programming the tag data through the RFID reader in the air interface. This is mainly because the uneven distribution of radio frequency energy in the air interface may cause some tags to fail to obtain sufficient programming voltage, resulting in unsuccessful programming.

[0003] The above information disclosed in the background art section is only used to enhance the understanding of the background of the present disclosure. Therefore, it may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0004] The purpose of the present invention is to provide a wafer-level chip batch programming and testing method. By performing batch and large-scale programming and testing at the wafer level, data programming is achieved before the chips are diced, effectively improving the programming efficiency of the chips, reducing the operation steps, and significantly improving the production efficiency. By directly constructing a data communication network on the wafer, a stable programming voltage and a reliable communication line are provided to ensure that each chip can obtain sufficient programming voltage, improving the programming success rate and avoiding programming failures caused by uneven radio frequency energy distribution. Secondly, it allows the testing and data programming of chips to be carried out simultaneously on the wafer, providing wide coverage of testing and yield guarantee, reducing the chip waste caused by programming failures, and saving costs and materials. The deployment of the serial data communication network makes the communication network of each BLOCK area independent and flexible, enabling independent verification and testing. Each chip can be independently identified and controlled through the unique device identifier (ROM_ID), improving the accuracy and flexibility of testing and programming. In the comprehensive electrical performance testing, the present invention can quickly detect and analyze anomalies, screen out problem areas through clustering algorithms, improve the accuracy and efficiency of fault detection, and improve the overall product quality and production reliability, so as to solve the problems in the above background art.

[0005] To achieve the above purpose, the present invention provides the following technical solution: A wafer-level chip batch programming and testing method, comprising the following steps:

[0006] Step 1: Etch multiple chips on the wafer and reserve the dicing street area. The dicing street area is distributed in a crisscross pattern and is used to deploy the programming communication network and communication connections.

[0007] Step 2: Utilize the crisscross distributed dicing street area to construct a data communication network on the wafer. The data communication network arranges metal connections for chip programming and communication in each dicing street area.

[0008] Step 3: Divide the wafer into multiple BLOCK regions. Each BLOCK region corresponds to an independent serial communication network. The serial communication network connects all the chips within the BLOCK region through the metal connections in the dicing street area, and the regions are divided according to the maximum area of a single exposure.

[0009] Step 4: Set a serial communication interface controller in the dicing street area within each BLOCK region. The serial communication interface controller is responsible for managing the communication with all the chips within the BLOCK region, controlling the data programming logic, and connecting to external devices through the port PAD to achieve power supply and data read / write operations of the wafer.

[0010] Step 5: Connect the relevant PIN nodes of each chip to the communication network through metal wires, enabling each chip to perform data transmission and programming operations through the communication network.

[0011] Step 6: Set a unique device identifier ROM_ID on each chip. Use the ROM_ID in the serial communication network to identify and locate each chip, achieving independent identification and programming control of multiple chips on the wafer.

[0012] Preferably, the process of etching multiple chips on the wafer and reserving the dicing street area is as follows:

[0013] Cut a thin wafer from a high-purity single-crystal silicon ingot, and perform a fine planarization process on the surface of the wafer to ensure the smoothness and flatness of the wafer surface.

[0014] Evenly coat a layer of photosensitive photoresist on the cleaned wafer surface. Subsequently, according to the designed chip circuit and dicing street area layout, project light onto the wafer surface coated with photoresist using a mask template to form a photolithography pattern.

[0015] After photolithography, the wafer enters the etching process. During the etching process, remove the unnecessary parts according to the photolithography pattern to form multiple independent chip areas and dicing street areas.

[0016] After etching, the dicing street area is used to deploy the programming communication network and communication connections.

[0017] Preferably, the metal wires include BURN wires, PROG wires, VCC wires, and GND wires to support chip data programming and power supply requirements.

[0018] Preferably, a data communication network is constructed on the wafer by using the scribe lane regions distributed in a crisscross pattern. The specific steps are as follows:

[0019] Determine the layout of the scribe lane regions on the wafer. The scribe lane regions are the reserved spaces on the wafer for future chip separation and the layout of the communication network. According to the size and arrangement of the chips, evenly divide the crisscross scribe lane regions on the wafer;

[0020] Coat a photoresist on the wafer surface and generate the pattern of the communication network in the scribe lane regions through a photolithography process;

[0021] Use a mask template to project light onto the photoresist, exposing the parts where metal wires need to be formed. The regions not irradiated by light will retain the photoresist to protect the underlying wafer surface from etching;

[0022] After photolithography, the wafer enters the dry etching process. Use plasma etching technology to remove the exposed parts of the photoresist, forming trenches for laying metal wires. The trenches match the crisscross layout of the scribe lanes to construct the path of the data communication network;

[0023] Deposit a metal material in the trenches formed by etching. After deposition, perform photolithography and etching again to remove the excess metal and retain the parts in the trenches to form the final metal wires.

[0024] Preferably, the wafer is divided into multiple BLOCK regions, and each BLOCK region corresponds to an independent serial communication network. The specific steps are as follows:

[0025] Determine the maximum area of a single exposure of the lithography equipment. According to the size of the chip DIE and the layout on the wafer, set the width of the scribe lane as W scribe , the height of the chip as H chip , the width of the chip as W chip , according to A max , W scribe , H chip , W chip Calculate the size of a BLOCK region. The calculation formula is:

[0026] ,

[0027] In the formula, N block represents the number of BLOCK regions that can be included in a single exposure area, A max represents the maximum area of a single exposure, which represents the maximum effective area of a single exposure of the lithography equipment. Denotes the floor symbol;

[0028] After determining the size of the BLOCK area, the wafer is divided into several blocks, each block being an independent BLOCK. Let the total area of the wafer be A wafer The wafer is divided into multiple BLOCK areas. The calculation expression for the total number of BLOCK areas that can be divided on the wafer is:

[0029] ,

[0030] In the formula, M block Denotes the total number of BLOCK areas that can be divided on the wafer, and A chip Denotes the area of each chip;

[0031] In the dicing street area, metal wires for the serial communication network are arranged, including BURN wires, PROG wires, VCC wires, and GND wires. All the chips within each BLOCK area are connected to an independent serial communication network controller through the metal wires;

[0032] After constructing the serial communication network, a comprehensive electrical performance test and verification are carried out to ensure that the independent communication network of each BLOCK area works properly and the connection of all metal wires and chips is complete and error-free. During the test, the communication network of each BLOCK area is independently verified through the controller. The specific verification expression is:

[0033] ,

[0034] T test Denotes the total test time of the communication networks of all BLOCK areas on the entire wafer, and t connect,i Denotes the connection test time of the wires of the i-th BLOCK area, and t signal,i Denotes the signal transmission test time of the i-th BLOCK area.

[0035] Preferably, the total test time of the communication networks of all BLOCK areas on the entire wafer is compared and analyzed with a pre-set reference threshold range of the total test time. If the total test time is not within the reference threshold range of the total test time, it is determined that the total test time is abnormal. If the total test time is within the reference threshold range of the total test time, it is determined that the total test time is not abnormal.

[0036] Preferably, when the total test time of the communication networks of all BLOCK areas on the entire wafer is abnormal, a clustering algorithm is used to screen out the BLOCK areas with abnormal signal transmission test times. The specific steps are as follows:

[0037] Collect the signal transmission test time t of each BLOCK areasignal，i , where t signal,i is the signal transmission test time of the i-th BLOCK block, and the average value μ of the signal transmission test time is calculated t and the standard deviation σ t . Then, the test time of each BLOCK block is standardized to a Z-score. The standardization formula is:

[0038] ,

[0039] In the formula, Zi is the standardized score of the signal transmission test time of the i-th BLOCK block;

[0040] In the initial stage of cluster analysis, the initial cluster centers are determined through a clustering algorithm. The standardized data is randomly divided into multiple classes, and the mean and standard deviation of each class are calculated as the initial cluster centers. The purpose of this step is to provide a reasonable starting point for subsequent iterative optimization. The calculation expression is: In the formula, represents the mean of the initial k-th class, represents the standard deviation of the initial k-th class, represents the set of BLOCK blocks included in the initial k-th class, represents the number of BLOCK blocks in the initial k-th class;

[0041] Through the iterative optimization process, the mean and standard deviation of each class are updated. After each iteration, each BLOCK block is reallocated to its nearest cluster center, and the mean and standard deviation of the new class are calculated. The iteration continues until the cluster centers converge, that is, the clustering results no longer change significantly. The calculation expression for clustering iteration update is: In the formula, represents the mean of the k-th class after the (t + 1)-th iteration, represents the standard deviation of the k-th class after the (t + 1)-th iteration, represents the set of BLOCK blocks included in the k-th class in the t-th iteration, represents the number of BLOCK blocks in the k-th class in the t-th iteration;

[0042] According to the clustering results, the mean μ abnormal and the standard deviation σ abnormal of the abnormal class are determined, and the BLOCK blocks with abnormal signal transmission test times are screened out and marked. The specific expression is: In the formula, A i is the abnormal mark of the i-th BLOCK block. 1 indicates abnormal, and 0 indicates normal. μ abnormalrepresents the mean value of the data points marked as the abnormal category, σ abnormal represents the standard deviation of the data points marked as the abnormal category,

[0043] wherein, C abnormal represents the set of all data points included in the abnormal category, |C abnormal | represents the number of data points in the abnormal category.

[0044] Preferably, a serial communication interface controller is set in the scribing lane area within each BLOCK block, and the specific steps are as follows:

[0045] Determine the layout and size in the scribing lane area within each BLOCK block to accommodate the serial communication interface controller. The scribing lane area is the interval area between chips and is used as the dividing line during wafer dicing;

[0046] Once the layout and size of the scribing lane area are determined, design the serial communication interface controller. After the design is completed, integrate the controller into the scribing lane area, and use precision lithography and etching processes to print the circuit pattern of the controller onto the wafer surface;

[0047] After the integration of the controller is completed, lay out the connection circuits between the serial communication interface controller and all the chips within the BLOCK block;

[0048] Connect the serial communication interface controller to external devices through the port PAD.

[0049] Preferably, connect the relevant PIN nodes of each chip to the communication network through metal wires, so that each chip can perform data transmission and programming operations through the communication network. The specific steps are as follows:

[0050] Determine the layout and functions of the PIN nodes of each chip. The PIN nodes are the interfaces for the chip to make electrical connections with the external world;

[0051] Design the metal connection path of the communication network. The design of the metal connection establishes an effective electrical connection between the chip and the communication network to ensure the stability and low latency of signal transmission;

[0052] After the design is completed, perform lithography and metal deposition processes. First, coat a layer of photoresist on the wafer surface, and then expose the pre-designed metal connection pattern to the photoresist through a mask. The exposed area is developed to leave channels for depositing metal. Next, deposit metal materials into the exposed area to form metal wires connecting the chip PIN nodes and the communication network;

[0053] After the metal deposition is completed, the metal layer is etched and patterned to remove the excess metal and retain the wire portions specified in the design.

[0054] In the above technical solution, the technical effects and advantages provided by the present invention are as follows:

[0055] Through wafer-level batch and large-volume programming and testing, the present invention performs data programming before the chips are diced. This significantly improves the programming efficiency of the chips. Compared with the traditional method, there is no need to wait until after the chips are diced and packaged to perform single-chip programming, reducing the operation steps and improving the overall production efficiency.

[0056] The present invention directly constructs a data communication network on the wafer. Through a stable programming voltage and reliable communication lines, it ensures that each chip can obtain sufficient programming voltage, thereby improving the success rate of programming and avoiding the problem of programming failure caused by uneven distribution of radio frequency energy.

[0057] By performing programming and testing at the wafer level, the present invention can simultaneously perform chip testing and data programming, providing wide coverage testing and yield guarantee for both on-chip and off-chip of the chips. Compared with the traditional method of programming and testing each chip one by one, this not only improves the production efficiency but also reduces the risk of chips being discarded due to programming failure, saving costs and materials.

[0058] The serial data communication network deployed by the present invention on the wafer makes the communication network of each BLOCK independent and flexible. Each BLOCK can be independently verified and tested. By using a unique device identifier (ROM_ID) in the communication network, independent identification and programming control of each chip can be achieved, increasing the flexibility and accuracy of data programming and testing, enabling the production line to quickly locate and solve abnormal chips, and improving the overall reliability of the product.

[0059] By performing comprehensive electrical performance testing and verification after the serial communication network is constructed, the present invention can ensure that the independent communication network of each BLOCK works properly and verify the integrity of the connection of all metal wires and chips. This testing method allows for precise monitoring and analysis of the total testing time of the communication networks of all BLOCKs on the entire wafer. If there is an abnormality in the total testing time, the clustering algorithm can be quickly used to screen out the BLOCKs with abnormal signal transmission testing time, greatly improving the accuracy and efficiency of fault detection, ensuring that problems can be identified and solved in a timely manner during mass production, and helping to improve the overall quality of the product and the reliability of production. Description of the Drawings

[0060] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required for use in the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, other accompanying drawings can also be obtained based on these drawings.

[0061] Figure 1 This is a method flow chart of a wafer-level chip batch programming and testing method of the present invention.

[0062] Figure 2 This is a schematic diagram of a wafer-level programming communication network of the present invention.

[0063] In the figure:

[0064] 101, wafer; 102, chip; 103, scribe lane area; 104, BLOCK block; 105, port PAD; 106, scribe lane; 107, PIN node; 108, device identifier ROM_ID; 109, serial communication interface controller. Detailed implementation manners

[0065] Now, example embodiments will be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the example embodiments to those skilled in the art.

[0066] The present invention provides a Figure 1 wafer-level chip batch programming and testing method as shown below, including the following steps:

[0067] Step 1: Etch a plurality of chips on the wafer and reserve a scribe lane area. The scribe lane area is distributed in a crisscross pattern and is used to deploy a programming communication network and communication connections, without occupying the standard chip DIE area, making full use of the wafer area;

[0068] The process of etching a plurality of chips on the wafer and reserving a scribe lane area is specifically as follows:

[0069] Cut a thin wafer from a high-purity single-crystal silicon ingot. To ensure the accuracy of the etching process and the performance of the chips, the surface of the wafer needs to be finely planarized, including processes such as chemical mechanical polishing (CMP), etc., to ensure the smoothness and flatness of the wafer surface. This step also includes cleaning the wafer surface to remove any tiny particles and contaminants that may affect subsequent etching and processing. Through high-precision cleaning processes, such as ultrasonic cleaning and deionized water rinsing, ensure that the wafer surface is dust-free and pollution-free, laying a foundation for the accuracy of the etching process.

[0070] A photosensitive photoresist is evenly coated on the surface of the cleaned wafer. This photoresist can undergo chemical changes in response to light of a specific wavelength. Subsequently, according to the layout of the designed chip circuit and scribe lane area, a mask is used to project light onto the wafer surface coated with photoresist, forming a photolithography pattern. The photolithography pattern design not only includes the detailed circuit layout of the chip but also takes into account the reserved positions in the scribe lane area to ensure that subsequent etching and dicing operations can be carried out accurately. This step is completed by high-precision photolithography equipment, usually using deep ultraviolet (DUV) lithography technology to achieve nanoscale pattern accuracy.

[0071] After photolithography, the wafer enters the etching process. Etching can be divided into dry etching and wet etching, and the specific choice depends on the required precision and material properties. During the etching process, according to the photolithography pattern, the unnecessary parts are removed to form multiple independent chip areas (DIE) and scribe lane areas. The scribe lane areas are usually distributed in a matrix form on the wafer, running through the entire wafer surface, forming a grid-like gap. At this time, the precise size and position of the scribe lane areas are very crucial because they not only need to provide enough space for subsequent chip dicing but also need to provide a suitable layout area for the programming communication network and communication connections.

[0072] After etching, the scribe lane areas are used to deploy the programming communication network and communication connections. In this step, engineers utilize the gaps in the scribe lane areas and, through further photolithography and metal deposition processes, arrange communication connections for data programming and testing in these areas. These connections usually include BURN lines (for high-voltage programming), PROG lines (for data communication), VCC lines (for power supply), and GND lines (for grounding). These metal lines form an efficient communication network, making subsequent batch chip programming and testing operations more convenient and efficient. This design avoids occupying the standard chip DIE area, effectively saving the wafer usage area.

[0073] Step 2: Utilize the crisscrossed scribe lane areas to construct a data communication network on the wafer. The data communication network arranges metal connections for chip programming and communication in each scribe lane area, where the metal connections include BURN lines, PROG lines, VCC lines, and GND lines to support chip data programming and power supply requirements;

[0074] Utilize the crisscrossed scribe lane areas to construct a data communication network on the wafer. The specific steps are as follows:

[0075] Determine the layout of the scribe lane area on the wafer. The scribe lane area is the reserved space on the wafer for future chip separation and the layout of the communication network. According to the size and arrangement of the chips, the scribe lane area with crisscrossing horizontal and vertical lines is evenly divided on the wafer. The width and position of these scribe lanes need to be precisely designed to ensure that each chip can be safely separated during the subsequent cutting process, while leaving enough space for laying the metal wires of the communication network. This step is usually carried out when designing the chip mask to ensure that the scribe lane area can meet the requirements of wafer-level mass production.

[0076] Coat the wafer surface with photoresist and generate the pattern of the communication network in the scribe lane area through the photolithography process. The purpose of the photolithography process is to form precise metal wire channels in the scribe lane area, providing a basis for subsequent metal deposition. By using a specific mask, light is projected onto the photoresist, exposing the parts where metal wires need to be formed. The areas not irradiated by light will retain the photoresist, protecting the underlying wafer surface from etching. This step ensures that the data communication network can be precisely formed in the scribe lane area and provides a pattern basis for subsequent circuit wiring.

[0077] After photolithography, the wafer enters the dry etching process. Using plasma etching technology, the exposed parts of the photoresist are removed to form trenches for laying metal wires. These trenches match the horizontal and vertical layout of the scribe lanes, precisely constructing the path of the data communication network. During this process, the depth and width of the etching need to be precisely controlled to ensure that the trenches can accommodate the metal layers deposited in the subsequent steps while avoiding damaging other parts of the chip. The precision of dry etching is crucial because it determines the electrical characteristics and stability of the communication network.

[0078] In the trenches formed by etching, metal materials such as aluminum or copper are deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD) methods to form metal wires. The deposited metal layer needs to be thick enough to ensure its low-resistance characteristics when transmitting current and data. After deposition, photolithography and etching are carried out again to remove the excess metal, leaving only the part in the trenches to form the final metal wires. These metal wires include BURN wires (for providing programming high voltage), PROG wires (for data communication), VCC wires (for power supply), and GND wires (for grounding). They together form the data communication network on the wafer, which can provide the necessary programming and testing functions for each chip.

[0079] Step 3: Divide the wafer into multiple BLOCK regions. Each BLOCK region corresponds to an independent serial communication network. The serial communication network connects all the chips within the BLOCK region through the metal wiring in the scribing lane area, and the regions are divided according to the maximum area of a single exposure.

[0080] Divide the wafer into multiple BLOCK regions. Each BLOCK region corresponds to an independent serial communication network. The specific steps are as follows:

[0081] Determine the maximum area of a single exposure of the lithography equipment. This parameter depends on the exposure area capability of the lithography machine and is the key factor determining the area of each BLOCK region. According to the size of the chip DIE and the layout on the wafer, let the width of the scribing lane (the interval between chips) be W scribe , the height of the chip be H chip , the width of the chip be W chip , according to A max , W scribe , H chip , W chip Calculate the size of a BLOCK region. The calculation expression is:

[0082] ,

[0083] In the formula, N block represents the number of BLOCK regions that can be included in a single exposure area, and A max represents the maximum area of a single exposure, which represents the maximum effective area of a single exposure of the lithography equipment;

[0084] After determining the size of the BLOCK region, divide the wafer into several regions. Each region is an independent BLOCK, ensuring that these regions are evenly distributed on the entire wafer. Let the total area of the wafer be A wafer , divide the wafer into multiple BLOCK regions. The calculation expression for the total number of BLOCK regions that can be divided on the wafer is:

[0085] ,

[0086] In the formula, M block represents the total number of BLOCK regions that can be divided on the wafer, and A chip represents the area of each chip;

[0087] In the scribing lane area, lay the metal wiring for the serial communication network, including BURN line, PROG line, VCC line, and GND line. All the chips within each BLOCK region are connected to an independent serial communication network controller through the metal wiring.

[0088] After the serial communication network is constructed, comprehensive electrical performance tests and verifications are carried out to ensure that the independent communication network of each BLOCK block works properly and all metal wire connections and chip connections are complete and error-free. During the test, the communication network of each BLOCK block needs to be independently verified through the corresponding controller. The specific verification expression is:

[0089] ,

[0090] T test represents the total test time of the communication networks of all BLOCK blocks on the entire wafer, and t connect,i represents the wire connection test time of the i-th BLOCK block, and t signal,i represents the signal transmission test time of the i-th BLOCK block;

[0091] Compare and analyze the total test time of the communication networks of all BLOCK blocks on the entire wafer with the pre-set reference threshold range of the total test time. If the total test time is not within the reference threshold range of the total test time (i.e., below the lower limit or above the upper limit), it is determined that the total test time is abnormal. If the total test time is within the reference threshold range of the total test time, it is determined that the total test time is not abnormal.

[0092] When the total test time of the communication networks of all BLOCK blocks on the entire wafer is abnormal, a clustering algorithm is used to screen out the BLOCK blocks with abnormal signal transmission test time. The specific steps are as follows:

[0093] Collect the signal transmission test time t signal，i , where t signal,i is the signal transmission test time of the i-th BLOCK block, calculate the average value μ t (the average value of the signal transmission test times of all BLOCK blocks) and the standard deviation σ t (the standard deviation of the signal transmission test times of all BLOCK blocks). Then, standardize the test time of each BLOCK block to Z-score to eliminate the absolute value difference between different BLOCKs and make different test times comparable. The standardization formula is:

[0094] ,

[0095] In the formula, Z i is the standardized score (Z-score) of the signal transmission test time of the i-th BLOCK block;

[0096] In the initial stage of clustering analysis, clustering algorithms such as K-means are used to determine the initial clustering centers. The standardized data is randomly divided into multiple classes, and the mean and standard deviation of each class are calculated as the initial clustering centers. The purpose of this step is to provide a reasonable starting point for subsequent iterative optimization. The calculation expression is as follows: In the formula, represents the mean of the initial k-th class, represents the standard deviation of the initial k-th class, represents the set of BLOCK blocks included in the initial k-th class, represents the number of BLOCK blocks in the initial k-th class;

[0097] Through the iterative optimization process, the mean and standard deviation of each class are updated. After each iteration, each BLOCK block is reallocated to its nearest clustering center, and the mean and standard deviation of the new class are calculated. The iteration continues until the class centers converge, that is, the clustering results no longer change significantly. Through this process, the classes containing abnormal data (abnormal classes) can be identified. The calculation expression for clustering iteration update is as follows: In the formula, represents the mean of the k-th class after the (t + 1)-th iteration, represents the standard deviation of the k-th class after the (t + 1)-th iteration, represents the set of BLOCK blocks included in the k-th class in the t-th iteration, represents the number of BLOCK blocks in the k-th class in the t-th iteration;

[0098] According to the clustering results, determine the mean μ abnormal and standard deviation σ abnormal of the abnormal class, screen out the BLOCK blocks with abnormal signal transmission test time, and mark them. The specific expression is as follows: In the formula, A i is the abnormal mark of the i-th BLOCK block, 1 means abnormal, 0 means normal, μ abnormal represents the mean of the class marked as abnormal, σ abnormal represents the standard deviation of the class marked as abnormal,

[0099] In the formula, C abnormal represents the set of all data points included in the abnormal class, |C abnormal | represents the number of data points in the abnormal class.

[0100] Step 4: Set up a serial communication interface controller in the scribe lane area within each BLOCK. The serial communication interface controller is responsible for managing the communication with all the chips within the BLOCK, controlling the data programming logic, and connecting to external devices through ports PAD to achieve power supply and data read / write operations for the wafer.

[0101] To set up a serial communication interface controller in the scribe lane area within each BLOCK, the specific steps are as follows:

[0102] Determine the appropriate layout and size in the scribe lane area (scribe lane) within each BLOCK to accommodate the serial communication interface controller. The scribe lane area is the interstitial area between chips and is typically used as the dividing line during wafer dicing. When designing this area, it is necessary to ensure that its width and length are large enough to accommodate the controller and its connected circuits and metal wiring, without interfering with the other functional layouts of the chips. This step involves precise calculations and designs to ensure maximum utilization of space and improve the integration of chips and communication lines.

[0103] Once the layout and size of the scribe lane area are determined, the design of the serial communication interface controller can be carried out. The design of this controller should take into account various functional requirements, including data transmission, signal conversion, and logic control, etc. The controller usually contains multiple input and output ports and is responsible for communicating with all the chips within the BLOCK. When designing the controller, efficient digital circuit design methods need to be adopted to ensure that it can achieve all the required functions within a limited space. After the design is completed, the controller is integrated into the scribe lane area, and the circuit pattern of the controller is printed onto the wafer surface using precision lithography and etching processes.

[0104] After the integration of the controller is completed, the connection circuits between the serial communication interface controller and all the chips within the BLOCK need to be laid out. The connection circuits are usually composed of metal wiring and are used to connect the output ports of the controller to the input ports of each chip. The layout and design of the metal wiring need to consider signal integrity and transmission efficiency to avoid signal interference and excessive resistance. The wiring process requires the use of processes such as lithography, deposition, and etching to precisely lay the metal wiring in the channels between the scribe lane area and the chips, ensuring that all chips can communicate effectively with the controller.

[0105] After ensuring that the communication lines between the controller and the chip are laid out, it is also necessary to connect the serial communication interface controller to external devices through the port PAD. The port PAD is a metal contact point on the surface of the wafer, allowing external devices to make electrical connections with the controller inside the wafer through methods such as probes. This connection is used to supply power to the wafer and perform data read and write operations. The design of the port PAD needs to take into account the size of the probe, contact pressure, and signal transmission requirements to ensure a stable electrical connection when connecting external devices, while avoiding damage to the wafer surface.

[0106] Step Five: Connect the relevant PIN nodes of each chip to the communication network through metal wires, enabling each chip to perform data transmission and programming operations through the communication network;

[0107] Connect the relevant PIN nodes of each chip to the communication network through metal wires, enabling each chip to perform data transmission and programming operations through the communication network. The specific steps are as follows:

[0108] It is necessary to determine the layout and functions of the PIN nodes of each chip. These PIN nodes are the interfaces for the chip to make electrical connections with the external world, and each PIN node usually has specific functions, such as power input (VCC), ground (GND), data input / output (PROG), programming control (BURN), etc. During the design phase, engineers will carefully arrange the positions and connection paths of these PIN nodes according to the functional requirements of the chip and the requirements of the communication network. Ensure that the position of each PIN node is not only convenient for connection to the metal wires of the communication network but also needs to consider the integrity of signal transmission and electrical performance.

[0109] Next, design the metal connection path of the communication network. The design of the metal connection needs to establish an effective electrical connection between the chip and the communication network to ensure the stability and low latency of signal transmission. During the design process, it is necessary to consider the layout of each BLOCK area on the wafer, select the best metal connection path, and avoid crossing and interference with other circuits. At the same time, the width and thickness of the metal wire also need to be accurately calculated to support the necessary current and signal transmission rate. All these design details need to be simulated and optimized in the circuit layout design software to ensure that the final electrical connection meets the design specifications.

[0110] After the design is completed, the lithography and metal deposition processes are carried out. First, a layer of photoresist is coated on the surface of the wafer, and then the pre-designed metal wiring pattern is exposed onto the photoresist through a mask. The exposed area is developed, leaving channels for metal deposition. Next, through physical vapor deposition (PVD) or chemical vapor deposition (CVD) methods, a metal material (such as aluminum or copper) is deposited onto the exposed area to form metal wires connecting the chip PIN nodes and the communication network. The thickness and uniformity of the metal deposition need to be precisely controlled to ensure that the electrical performance and mechanical strength meet the requirements.

[0111] After the metal deposition is completed, the metal layer needs to be etched and patterned to remove the excess metal, leaving only the specified wiring parts in the design. This step is achieved by immersing the wafer in a chemical etching solution or using plasma etching technology to remove the unprotected part of the metal by the photoresist. The control during the etching process is very crucial because it determines the precise width and shape of the metal wiring, directly affecting the quality and reliability of signal transmission. The patterned metal wiring will form clear electrical paths connecting each chip's PIN node to the communication network.

[0112] Step 6: Set a unique device identifier ROM_ID on each chip, and use ROM_ID in the serial communication network to identify and locate each chip, realizing independent identification and programming control of multiple chips on the wafer;

[0113] Set a unique device identifier ROM_ID on each chip, and use ROM_ID in the serial communication network to identify and locate each chip, realizing independent identification and programming control of multiple chips on the wafer. The specific steps are as follows:

[0114] It is necessary to design the format and storage method of ROM_ID. ROM_ID is a unique identifier used to distinguish and identify each chip in the communication network. The design of ROM_ID should ensure its uniqueness throughout the production batch. Usually, it adopts a binary format, such as 8-bit, 16-bit or higher-bit encoding, and its length is determined according to the required uniqueness and security. The storage method depends on the memory structure of the chip. ROM_ID is usually stored in a read-only memory (ROM) or an electrically erasable programmable read-only memory (EEPROM) to ensure its immutability. This step needs to consider the generation rules and allocation strategies of ROM_ID to ensure that each chip obtains a unique identifier during the design stage.

[0115] After determining the format and storage method of the ROM_ID, the next step is to write the ROM_ID into the memory during the chip manufacturing process. This process is usually carried out in the final stage before chip packaging. Using dedicated equipment or test instruments, the ROM_ID data is written into the read-only memory of the chip through a programming interface. Since the ROM_ID is immutable, the programming process requires strict control to ensure that the ROM_ID of each chip is correctly written and does not repeat. In some high-precision production lines, the programming of the ROM_ID can be completed by automated equipment to ensure speed and accuracy.

[0116] After the ROM_ID is written into the memory, verification and testing are required to ensure that the ROM_ID is correctly written and can be reliably read. The verification process usually uses the same programming interface to verify the integrity and correctness of the ROM_ID by means of readback. The test instrument will read the ROM_ID of each chip one by one and compare it with the preset standard value. If there are errors or mismatches, the chip will be marked as a defective product and further inspection or reprogramming is required. This step is very important to ensure that the ROM_ID of each chip has been strictly verified before leaving the factory.

[0117] After the chip is installed in the communication network, the serial communication interface controller uses the ROM_ID to identify and locate each chip. When an external device interacts with the chip through the communication network, the controller will first send a request command asking all chips to report their ROM_IDs. Each chip, according to the received command, sends its ROM_ID back to the controller through the serial communication network. The controller determines the unique identity and location of each chip based on the received ROM_ID data and then performs targeted operations such as data reading, writing, or burning. Using the ROM_ID for identification and location can avoid confusion and ensure that the operations of each chip can be executed independently and accurately.

[0118] Finally, the ROM_ID is used to achieve independent burn control and data management for multiple chips on the wafer. During the chip production process, the external device establishes communication with all the chips on the wafer through the serial communication interface controller, uses the ROM_ID to select the target chip, and performs specific data burning and programming operations. In this way, the burn control can be accurate to the level of a single chip, ensuring that each chip receives the correct data and stores it in the designated storage area. In addition, the ROM_ID can also be used for chip traceability management. During subsequent testing, assembly, and maintenance processes, by recording the ROM_ID of each chip and its operation log, quality control and problem tracking can be conveniently carried out.

[0119] Through wafer-level batch and large-volume programming and testing, data programming is performed before the chips are diced, significantly improving the programming efficiency of the chips. Compared with the traditional method, there is no need to wait until the chips are diced and packaged before programming each chip individually, reducing the operation steps and improving the overall production efficiency.

[0120] The present invention directly constructs a data communication network on the wafer. Through a stable programming voltage and a reliable communication line, it ensures that each chip can obtain sufficient programming voltage, thereby improving the success rate of programming and avoiding the problem of programming failure caused by uneven distribution of radio frequency energy.

[0121] By performing programming and testing at the wafer level, the present invention can simultaneously perform chip testing and data programming, providing wide coverage testing and yield guarantee for both on-chip and off-chip of the chips. Compared with the traditional method of programming and testing each chip one by one, this not only improves the production efficiency, but also reduces the risk of chips being discarded due to programming failure, saving costs and materials.

[0122] The serial data communication network deployed on the wafer by the present invention makes the communication network of each BLOCK independent and flexible. Each BLOCK can be independently verified and tested. By using a unique device identifier (ROM_ID) in the communication network, independent identification and programming control of each chip can be achieved, increasing the flexibility and accuracy of data programming and testing, enabling the production line to quickly locate and solve abnormal chips, and improving the overall reliability of the product.

[0123] By performing comprehensive electrical performance testing and verification after constructing the serial communication network, the present invention can ensure that the independent communication network of each BLOCK works properly and verify that all metal wire connections to the chips are complete and error-free. This testing method allows for precise monitoring and analysis of the total testing time of the communication networks of all BLOCKs on the entire wafer. If there is an abnormality in the total testing time, the clustering algorithm can be quickly used to screen out the BLOCKs with abnormal signal transmission testing time, greatly improving the accuracy and efficiency of fault detection, ensuring that problems can be identified and solved in a timely manner during mass production, and helping to improve the overall quality of the product and the reliability of production.

[0124] The above formulas are all dimensionless and take their numerical values for calculation. The formulas are obtained by collecting a large amount of data for software simulation to get a formula closest to the actual situation. The preset parameters in the formulas are set by those skilled in the art according to the actual situation.

[0125] Only certain exemplary embodiments of the present invention have been described by way of illustration. Without doubt, for those of ordinary skill in the art, the described embodiments can be modified in various different ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and description are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A wafer-level chip batch burning and testing method, characterized in that: The following steps are involved: Step 1: Etch multiple chips on the wafer and reserve scribe lane areas, which are crisscrossed and used to deploy the burning communication network and communication lines; Step 2: Using the crisscrossed scribe lanes, a data communication network is constructed on the wafer. The data communication network is equipped with metal wires for chip programming and communication in each scribe lane. Step 3: Divide the wafer into multiple BLOCK blocks. Each BLOCK block corresponds to an independent serial communication network. The serial communication network connects all chips in the BLOCK block through metal connections in the dicing area, and divides the blocks according to the maximum area of ​​single illumination. Step 4: A serial communication interface controller is set in the dicing lane area in each BLOCK block. The serial communication interface controller is responsible for managing the communication with all chips in the BLOCK block, controlling the data burning logic, and connecting external devices through the port PAD to realize the power supply and data reading and writing operations of the wafer; Step 5: Connect the relevant PIN nodes of each chip to the communication network through metal wires, so that each chip can perform data transmission and burning operations through the communication network; Step 6: Set a unique device identifier ROM_ID on each chip, use ROM_ID to identify and locate each chip in the serial communication network, and realize independent identification and burning control of multiple chips on the wafer; When the total test time of all BLOCK communication networks on the entire wafer is abnormal, a clustering algorithm is used to screen out the BLOCK blocks with abnormal signal transmission test time. The specific steps are as follows: Collect the signal transmission test time t of each BLOCK block signal，i , where t signal，i The signal transmission test time of the i-th BLOCK block, calculate the average signal transmission test time μ t and standard deviation σ t Then, the test time of each BLOCK block is standardized to Z-score, and the standardized formula is: ， In the formula, Z i The normalized fraction of the signal transmission test time of the i-th BLOCK block; In the initial stage of cluster analysis, the clustering algorithm is used to determine the initial cluster center, the standardized data is randomly divided into multiple classes, and the mean and standard deviation of each class are calculated as the initial cluster center. The purpose of this step is to provide a reasonable starting point for subsequent iterative optimization. The calculation expression is: In the formula, represents the initial mean of the kth class, represents the initial standard deviation of the kth class, Indicates the initial set of BLOCK blocks contained in the kth category. Indicates the number of BLOCK blocks in the initial k-th category; Through the iterative optimization process, the mean and standard deviation of each class are updated. After each iteration, each BLOCK block is redistributed to its nearest cluster center, and the mean and standard deviation of the new class are calculated. The iteration continues until the category center converges, that is, the clustering result no longer changes significantly. The calculation expression for clustering iterative update is: In the formula, represents the mean of the kth class after the t+1th iteration, represents the standard deviation of the kth category after the t+1th iteration, Indicates the set of BLOCK blocks contained in the k-th category in the t-th iteration, Indicates the number of BLOCK blocks in the kth category at the tth iteration; According to the clustering results, determine the mean μ of the abnormal category abnormal and standard deviation σ abnormal , filter out the BLOCK blocks with abnormal signal transmission test time and mark them. The specific expression is: In the formula, A i The abnormal flag of the i-th BLOCK, 1 means abnormal, 0 means normal, μ abnormal represents the mean of the classes marked as abnormal, σ abnormal represents the standard deviation of the category marked as abnormal, In the formula, C abnormal represents the set of all data points contained in the abnormal category, |C abnormal | represents the number of data points in the anomaly class.

2. A wafer-level chip batch burning and testing method according to claim 1, characterized in that: The process of etching multiple chips on a wafer and reserving the scribe line area is as follows: Thin wafers are cut from high-purity single-crystal silicon ingots, and the surface of the wafers is finely planarized to ensure that the surface of the wafers is smooth and flat; A layer of photosensitive photoresist is evenly coated on the cleaned wafer surface. Then, according to the designed chip circuit and scribe line area layout, a mask is used to project light onto the photoresist-coated wafer surface to form a photolithography pattern. After the photolithography is completed, the wafer enters the etching process. During the etching process, the unnecessary parts are removed according to the photolithography pattern to form multiple independent chip areas and scribe line areas; After etching is completed, the scribe line area is used to deploy the burned-in communication network and communication lines.

3. A wafer-level chip batch burning and testing method according to claim 1, characterized in that: Metal connections include BURN lines, PROG lines, VCC lines, and GND lines to support chip data burning and power supply requirements.

4. A wafer-level chip batch burning and testing method according to claim 1, characterized in that: Using the crisscrossing scribe lanes, a data communication network is constructed on the wafer. The specific steps are as follows: Determine the layout of the scribe lanes on the wafer. The scribe lanes are reserved on the wafer for future chip separation and communication network layout. According to the size and arrangement of the chips, the scribe lanes are evenly divided on the wafer. Coating photoresist on the surface of the wafer and generating a pattern of the communication network in the scribe line area by photolithography; Use a mask to project light onto the photoresist to expose the parts where metal connections need to be formed. The photoresist will remain in the areas not exposed to light, protecting the wafer surface below from being etched. After photolithography, the wafer enters the dry etching process, using plasma etching technology to remove the exposed part of the photoresist, forming grooves for laying metal wiring. The grooves match the vertical and horizontal layout of the scribe line to build the path of the data communication network; Metal material is deposited in the groove formed by etching. After deposition, photolithography and etching are performed again to remove excess metal and retain the part in the groove to form the final metal connection.

5. A wafer-level chip batch burning and testing method according to claim 1, characterized in that: Divide the wafer into multiple BLOCK blocks, each BLOCK block corresponds to an independent serial communication network. The specific steps are as follows: Determine the maximum single illumination area of ​​the lithography equipment. According to the size of the chip DIE and the layout on the wafer, the width of the scribe line is set to w scribe , the chip height is H chip , chip width is W chip , according to A max 、w scribe , H chip , W chip Calculate the size of a BLOCK block. The calculation expression is: ， Where N block Indicates the number of BLOCK blocks that can be included in a single lighting area, A max It represents the maximum area of ​​single illumination, and represents the maximum effective area of ​​single exposure of the lithography equipment. Represents the rounding symbol; After determining the size of the BLOCK, the wafer is divided into several blocks, each of which is an independent BLOCK. Suppose the total area of ​​the wafer is A. wafer , the wafer is divided into multiple BLOCK blocks, and the calculation expression for the total number of BLOCK blocks that can be divided on the wafer is: ， Where M block Indicates the total number of BLOCK blocks that can be divided on the wafer, A chip Indicates the area of ​​each chip; In the dicing area, metal lines for the serial communication network are laid out, including BURN lines, PROG lines, VCC lines, and GND lines. All chips in each BLOCK block are connected to an independent serial communication network controller through metal lines. After the serial communication network is built, a comprehensive electrical performance test and verification is carried out to ensure that the independent communication network of each BLOCK block works normally and all metal wires and chip connections are intact. During the test, the communication network of each BLOCK block is independently verified by the controller. The specific verification expression is: ， T test Represents the total test time of all BLOCK communication networks on the entire wafer, t connect，i Indicates the connection test time of the i-th BLOCK block, t signal，i Indicates the signal transmission test time of the i-th BLOCK block.

6. A wafer-level chip batch burning and testing method according to claim 5, characterized in that: The total test time of all BLOCK block communication networks on the entire wafer is compared and analyzed with the pre-set total test time reference threshold range. If the total test time is not within the total test time reference threshold range, it is judged that there is an abnormality in the total test time. If the total test time is within the total test time reference threshold range, it is judged that there is no abnormality in the total test time.

7. A wafer-level chip batch burning and testing method according to claim 1, characterized in that: A serial communication interface controller is set up in the dicing lane area within each BLOCK block. The specific steps are as follows: The layout and size of the scribe lane area in each BLOCK block are determined to accommodate the serial communication interface controller. The scribe lane area is the spacing area between chips and is used as a dividing line when cutting the wafer. Once the layout and size of the scribe lane area are determined, the serial communication interface controller is designed. After the design is completed, the controller is integrated into the scribe lane area and the circuit pattern of the controller is printed on the wafer surface using precision lithography and etching processes; After the controller is integrated, lay out the connection circuits between the serial communication interface controller and all the chips in the BLOCK block; The serial communication interface controller is connected to external devices through the port PAD.

8. A wafer-level chip batch burning and testing method according to claim 1, characterized in that: Connect the relevant PIN nodes of each chip to the communication network through metal wires, so that each chip can perform data transmission and burning operations through the communication network. The specific steps are as follows: Determine the layout and function of each chip's PIN nodes, which are the interface for the chip to electrically connect to the outside world; Design the metal wiring path of the communication network. The design of the metal wiring establishes an effective electrical connection between the chip and the communication network to ensure the stability and low latency of signal transmission; After the design is completed, the photolithography and metal deposition processes are carried out. First, a layer of photoresist is coated on the surface of the wafer, and then the pre-designed metal connection pattern is exposed to the photoresist through a mask. The exposed area is developed to leave a channel for depositing metal. Next, metal material is deposited on the exposed area to form a metal line connecting the chip PIN node and the communication network; After metal deposition is complete, the metal layer is etched and patterned to remove excess metal and retain the designated wiring sections in the design.

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