Memory initialization method, computer device, storage medium and program product

Abstract

The present invention relates to the technical field of servers, and discloses a memory initialization method, a computer device, a storage medium and a program product. The method comprises: in the memory initialization stage, running a memory initialization code to determine the current startup mode; if the current startup mode is the first mode, obtaining memory parameter information of a memory module, training the first memory module, obtaining a first training value, and completing the initialization of the first memory module; copying the memory training code to the first memory module; sending notification information to the remaining central processing unit cores in parallel, so that the remaining central processing unit cores train the remaining memory modules based on the memory parameter information and the memory training code, and obtain the remaining training values; saving the first training value and the remaining training value to a target storage area, and restarting the server; if the current startup mode is the second mode, completing the initialization of the memory module based on the training value of the target storage area. The present invention realizes the rapid initialization of the memory.

Description

Technical Field

[0001] The present invention relates to the technical field of servers, and in particular to a memory initialization method, a computer device, a storage medium and a program product. Background Art

[0002] Memory is a vital component of computer systems. It is responsible for temporarily storing the calculation data of the central processing unit (CPU) and the data exchanged with external memory. The operating system and the running program instructions rely on memory for fast data access. At the same time, the Basic Input Output System (BIOS) is responsible for initializing the hardware and loading the operating system into the memory, thereby starting the entire system. The collaborative work between memory and BIOS is crucial for the stable operation of the server system.

[0003] In the Unified Extensible Firmware Interface (UEFI) BIOS boot process, memory initialization is an important part of the Pre-EFI Initialization (PEI) stage.

[0004] In the related art, when performing memory initialization in the PEI stage, a memory initialization code is obtained, and the memory initialization code is run on a flash memory (Flash), and multiple memory modules are initialized in series, thereby completing the memory initialization.

[0005] However, this method of running the memory initialization code on the flash memory and serially initializing multiple memory modules to complete the memory initialization makes the memory initialization take a long time and the initialization speed is slow. Summary of the invention

[0006] In view of this, the present invention provides a memory initialization method, a computer device, a storage medium and a program product to solve the problem in the related art that the memory initialization code is run on a flash memory, and multiple memory modules are initialized serially to complete the memory initialization, resulting in a long memory initialization time and a slow initialization speed.

[0007] In a first aspect, the present invention provides a memory initialization method, applied to a first central processing unit core, the method comprising:

[0008] In the memory initialization phase, the memory initialization code is run to determine the current startup mode;

[0009] If the current startup mode is the first mode, obtaining memory parameter information of the memory module;

[0010] Based on the memory parameter information, training the first memory module to obtain a first training value;

[0011] Based on the first training value, completing initialization of the first memory module;

[0012] Copying the memory training code in the memory initialization code to the first memory module;

[0013] Sending notification information to the remaining CPU cores in parallel, so that the remaining CPU cores respond to the notification information, train the remaining memory modules based on the memory parameter information and the memory training code, and obtain remaining training values;

[0014] Saving the first training value and the remaining training values ​​to a target storage area, and restarting the server;

[0015] If the current startup mode is the second mode, acquiring the first training value and the remaining training value from the target storage area;

[0016] Based on the first training value and the remaining training value, the memory module is initialized.

[0017] The memory initialization method provided in this embodiment determines the current startup mode by running the memory initialization code in the memory initialization stage. When the current startup mode is the first mode, the first memory module is first trained based on the memory parameter information of the memory module to obtain the first training value. The first memory module is initialized based on the first training value. The memory training code is copied to the first memory module, and the remaining central processing unit cores are used to train the remaining memory modules in parallel according to the memory parameter information and the memory training code to obtain the remaining training values, and the first training value and the remaining training value are saved to the target storage area, and the server is restarted. When the current startup mode is the second mode, the memory module is initialized based on the first training value and the remaining training value. The method of using the first central processing unit core to first initialize a memory module, copying the memory training code to the memory module, triggering the remaining central processing unit cores to execute the memory training code in the memory module in parallel, and then completing the initialization of all memory modules reduces the time consumption of memory initialization, improves the speed of memory initialization, and realizes fast initialization of memory.

[0018] In an optional implementation, the running the memory initialization code to determine the current startup mode includes:

[0019] Running the memory initialization code to determine whether the target storage area includes the first training value and the remaining training value;

[0020] In a case where the target storage area does not include the first training value and the remaining training value, determining that the current startup mode is the first mode;

[0021] In a case where the target storage area includes the first training value and the remaining training value, it is determined that the current startup mode is the second mode.

[0022] The memory initialization method provided in this embodiment accurately determines the current startup mode by judging whether the target storage area includes the first training value and the remaining training values, avoids unnecessary initialization steps, and speeds up the startup speed of the system.

[0023] In an optional implementation manner, the acquiring memory parameter information of the memory module includes:

[0024] Based on the address information of the memory module, memory parameter information of the memory module is obtained.

[0025] The memory initialization method provided in this embodiment can quickly and accurately obtain the memory parameter information by obtaining the memory parameter information of the memory module according to the address information of the memory module.

[0026] In an optional implementation, completing the initialization of the first memory module based on the first training value includes:

[0027] Writing the first training value into a register of a first memory controller corresponding to the first memory module, so that the first memory module is in a working state;

[0028] Based on the memory parameter information, determining a decoding address of the first memory module;

[0029] Based on the decoded address of the first memory module, the first memory module is mapped to the memory address space of the central processing unit, and the memory address space of the central processing unit is set to be valid, so as to complete the initialization of the first memory module.

[0030] The memory initialization method provided in this embodiment writes the first training value into the register of the first memory controller corresponding to the first memory module to put the first memory module into a working state, determines the decoding address of the first memory module based on the memory parameter information, maps the first memory module to the memory address space of the central processing unit based on the decoding address of the first memory module, and sets the memory address space of the central processing unit to be valid, thereby accurately completing the initialization of the first memory module and improving the overall performance and reliability of the system.

[0031] In an optional implementation, copying the memory training code in the memory initialization code to the first memory module includes:

[0032] Determining the number of memory training codes to be copied based on the number of memory modules;

[0033] Based on the number of the memory training codes to be copied, dividing the first storage area of ​​the first memory module into a plurality of first storage sub-areas;

[0034] The memory training code is copied into a plurality of first storage sub-areas.

[0035] The memory initialization method provided in this embodiment can execute the initialization process of multiple memory modules in parallel by copying the memory training code to multiple first storage sub-areas of the first memory module, thereby significantly reducing the memory initialization time and improving the system startup speed.

[0036] In an optional implementation, the sending notification information to the remaining CPU cores in parallel so that the remaining CPU cores respond to the notification information, train the remaining memory modules based on the memory parameter information and the memory training code, and obtain the remaining training values, including:

[0037] Based on the number of the memory modules, selecting a target CPU core from the remaining CPU cores;

[0038] Sending notification information to the target CPU core in parallel, so that the target CPU core responds to the notification information, trains the remaining memory modules based on the memory parameter information and the corresponding memory training code in the first storage sub-area, and obtains the remaining training values;

[0039] Among them, one target central processing unit core corresponds to a memory training code in the first storage sub-area, and one memory training code in the first storage sub-area corresponds to a remaining memory module.

[0040] The memory initialization method provided in this embodiment sends notification information to the target central processor core in parallel, so that the target central processor can start training the remaining memory modules in parallel to obtain the remaining training values, thereby reducing the time required for memory initialization and improving the system startup speed.

[0041] In an optional embodiment, the method further includes:

[0042] Based on the number of the memory modules, dividing the second storage area of ​​the first memory module into a plurality of second storage sub-areas;

[0043] Storing the first training value in the corresponding second storage sub-area;

[0044] Sending notification information to the target CPU core in parallel, so that the target CPU core stores the obtained remaining training values ​​into the corresponding second storage sub-area;

[0045] Among them, the remaining training value corresponding to a remaining memory module corresponds to a second storage sub-area.

[0046] The memory initialization method provided in this embodiment divides the second storage area of ​​the first memory module into multiple second storage sub-areas. The remaining training values ​​of each remaining memory module can be stored in a second storage sub-area, thereby avoiding interference and conflict between data, and realizing efficient and orderly storage of the training values ​​of each memory module, thereby significantly improving the performance and reliability of the system.

[0047] In an optional implementation, the step of saving the first training value and the remaining training values ​​to a target storage area includes:

[0048] Circularly checking whether corresponding training values ​​are stored in the plurality of second storage sub-areas;

[0049] If it is checked that the corresponding training values ​​are stored in the plurality of second storage sub-areas, the first training value and the remaining training values ​​in the plurality of second storage sub-areas are read, and the first training value and the remaining training values ​​are saved in the transfer buffer area;

[0050] In the driver execution environment stage, the first training value and the remaining training values ​​in the transfer buffer are read, and the first training value and the remaining training values ​​are saved in the target storage area.

[0051] The memory initialization method provided in this embodiment ensures that all necessary training values ​​have been correctly stored by cyclically checking whether corresponding training values ​​are stored in multiple second storage sub-areas, thereby avoiding initialization failure or system abnormality caused by missing some training values, ensuring the integrity and consistency of the training values ​​of the memory module, and improving the performance and reliability of the system.

[0052] In an optional implementation, completing the initialization of the memory module based on the first training value and the remaining training value includes:

[0053] Writing the first training value into a register of a first memory controller corresponding to the first memory module, so that the first memory module is in a working state;

[0054] Writing the remaining training values ​​into the register of the target memory controller of the corresponding remaining memory module so that the remaining memory module is in a working state;

[0055] Based on the memory parameter information, determining a decoding address of the first memory module and a decoding address of the remaining memory modules;

[0056] Based on the decoded address of the first memory module and the decoded addresses of the remaining memory modules, the first memory module and the remaining memory modules are mapped to the memory address space of the central processing unit, and the memory address space of the central processing unit is set valid to complete the initialization of the memory modules.

[0057] The memory initialization method provided in this embodiment ensures that each memory module can be correctly started and enter the working state by writing the first training value into the register of the first memory controller corresponding to the first memory module, and writing the remaining training values ​​into the register of the target memory controller corresponding to the remaining memory modules. This avoids the risk of memory modules not being able to work properly due to configuration errors and improves the performance and stability of the system.

[0058] In an optional implementation manner, after setting the memory address space of the central processing unit to be valid, the method further includes:

[0059] Performing a read and write test on the memory module, wherein the memory module includes a first memory module and remaining memory modules;

[0060] In the case where both the read and write tests of the memory module are passed, determining that the initialization of the memory module is successfully completed;

[0061] If at least one memory module fails the read / write test, it is determined that the initialization of the memory module fails.

[0062] The memory initialization method provided in this embodiment can verify whether each memory module can correctly read and write data through read and write tests, thereby ensuring that the memory module can work normally after initialization, avoiding system instability or data loss caused by memory failure, and improving system reliability.

[0063] In an optional embodiment, the method further includes:

[0064] In the case that the initialization of the memory module fails, the execution of the stages after the memory initialization stage is stopped, and error logs are recorded, so that the user can locate the cause of the failure of the initialization of the memory module according to the error logs.

[0065] The memory initialization method provided in this embodiment stops executing the stages after the memory initialization stage when the initialization of the memory module fails, thereby preventing the system from continuing to run in an erroneous state, avoiding further failures or data corruption, and improving the reliability and maintainability of the system.

[0066] In a second aspect, the present invention provides a server, comprising: a first central processing unit core, wherein the first central processing unit core is used to execute the memory initialization method of the first aspect or any corresponding embodiment thereof.

[0067] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the memory initialization method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0068] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the memory initialization method of the first aspect or any corresponding embodiment thereof.

[0069] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions, wherein the computer instructions are used to enable a computer to execute the memory initialization method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0071] Figure 1 It is a structural schematic diagram of a multi-way server system in the related art;

[0072] Figure 2 It is a boot flow chart of UEFI BIOS in the related art;

[0073] Figure 3 It is a structural diagram of UEFI BIOS in the related art;

[0074] Figure 4 It is a flowchart of executing MRC code and completing memory initialization in the related art;

[0075] Figure 5 is a flow chart of a memory initialization method according to an embodiment of the present invention;

[0076] Figure 6 is a flow chart of another memory initialization method according to an embodiment of the present invention;

[0077] Figure 7 is a flowchart of another memory initialization method according to an embodiment of the present invention;

[0078] Figure 8 is a schematic diagram of copying a memory training code to a first memory module and saving a training value to the first memory module according to an embodiment of the present invention;

[0079] Fig. 9 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0080] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0081] Memory is a vital component in a computer system, also known as internal memory and main memory. It is responsible for temporarily storing the CPU's calculation data and data exchanged with external memory such as hard disks. It is also used to store the instructions, data, variables, function call parameters and return values ​​of the running program.

[0082] Memory provides space for temporary storage of data, allowing the computer system to quickly read and write data during execution, improving the system's response speed.

[0083] BIOS is the basic input and output system of the computer system. It is a piece of software code fixed on the computer motherboard. When the computer system starts, BIOS is responsible for initializing the hardware devices and loading the operating system into the memory. Among them, when the computer system starts, BIOS loads the operating system and other necessary software from the auxiliary storage into the memory. The memory is responsible for storing the operating system and continuously storing the data and instructions required by the program during program execution. After completing the initialization, BIOS finally hands over the control to the operating system, thereby starting the entire system.

[0084] In terms of memory management, BIOS is responsible for managing the allocation and release of system memory. It will detect and identify installed memory modules and record their information in the system configuration table. BIOS also provides some basic memory management functions, such as switching to protection mode, setting memory mapping tables, etc.

[0085] It can be seen that the collaboration between memory and BIOS is crucial to the stable operation of the server system.

[0086] Figure 1 Schematic diagram of a multi-way server system in the related art. Figure 1 As shown, the multi-way server system includes two CPUs, namely CPU0 and CPU1, and a BIOS chip, which is a UEFI BIOS.

[0087] CPU0 and CPU1 are connected through UltraPath Interconnect (UPI), and CPU0 and BIOS chip are connected through Serial Peripheral Interface (SPI).

[0088] The multi-way server system further includes 32 memory modules, which are connected to the multi-way server system through dual inline memory module (DIMM) slots. It is understandable that one memory module is connected to the server through one DIMM slot. Each DIMM slot is connected to the CPU, that is, each memory module is connected to the CPU. The memory module can be a double data rate memory (DDR memory).

[0089] Understandably, Figure 1 This is only an example of the structure of a multi-way server system. The multi-way server system used in the embodiment of the present invention is not limited thereto, and may also include more or fewer CPUs, more or fewer memory modules, etc., without specific limitation.

[0090] Figure 2 This is a boot flow chart of UEFI BIOS in the related art. Figure 2 As shown, when starting Figure 1 In the multi-way server system shown in FIG. 1 , when the UEFI BIOS is used to complete the initialization of the multi-way server system, the startup process of the UEFI BIOS generally includes the following stages, that is, the initialization process of the multi-way server system completed by the UEFI BIOS generally includes the following stages:

[0091] 1. Security Phase (SEC): The first phase to be executed after power-on. It is the starting point of the entire system. The computer system first enters this phase after power-on. This phase mainly handles system startup, restart, and abnormal signals. At this time, only the CPU and CPU internal resources are initialized, and external devices and memory are not initialized.

[0092] 2. Pre-EFI Initialization (PEI): Most of the code in this stage runs on the flash memory, mainly for initializing the CPU and related hardware. The memory reference code (MRC) contained in the BIOS runs in this stage, that is, memory initialization is performed in this stage.

[0093] Among them, the MRC code is run to complete the memory initialization. After the memory initialization is completed, other modules in the PEI stage are copied to the memory, and other modules in the PEI stage are run to complete the initialization of the CPU and related hardware.

[0094] 3. Dynamic Executable (DXE): This stage mainly involves a lot of driver loading and initialization work. The relevant modules and codes are copied to the memory and run in the memory.

[0095] 4. Boot Device Selection (BDS): This stage performs other initialization actions.

[0096] UEFI BIOS is stored in flash memory. Figure 3 Schematic diagram of the structure of UEFI BIOS in the related art. Figure 3 As shown, UEFI BIOS includes SEC stage module, PEI stage module, BDS stage module, DXE stage module and non-volatile random access memory (NVRAM) area.

[0097] Among them, the SEC stage module is used to execute the code of the SEC stage, the PEI stage module is used to execute the code of the PEI stage, the BDS stage module is used to execute the code of the BDS stage, and the DXE stage module is used to execute the code of the DXE stage. The NVRAM area is used to store information. The code running in the DXE stage and the BDS stage can call the variable information saving (SetVariable) service to save information to this area to ensure that the information is retained and not lost when the server system is powered off and restarted.

[0098] The PEI stage module includes multiple PEI stage sub-modules and MRC modules. The multiple PEI stage sub-modules include Figure 3 The PEI stage submodule 1, PEI stage submodule 2, PEI stage submodule N, PEI stage submodule N+1, etc. The PEI stage submodule is used to initialize the CPU and related hardware. The MRC module is used to run the MRC code and initialize the memory.

[0099] Among them, during the startup process of UEFI BIOS, different boot modes (bootMode) can be set in the PEI stage. The current boot mode can be obtained and updated through the current boot mode acquisition parameter GetBootMode() and the current boot mode setting parameter SetBootMode(). PEI stage modules, DXE stage modules, BDS stage modules, etc. can call GetBootMode() to determine whether certain modules are running based on the current boot mode set.

[0100] Exemplarily, the boot mode of UEFI BIOS may include:

[0101] / / ************************************************************

[0102] / / EFI_BOOT_MODE

[0103] / / ************************************************************

[0104] typedef UINT32 EFI_BOOT_MODE;

[0105] #define BOOT_WITH_FULL_CONFIGURATION 0x00

[0106] #define BOOT_WITH_MINIMAL_CONFIGURATION 0x01

[0107] #define BOOT_ASSUMING_NO_CONFIGURATION_CHANGES 0x02

[0108] #define BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS 0x03

[0109] #define BOOT_WITH_DEFAULT_SETTINGS 0x04

[0110] #define BOOT_ON_S4_RESUME 0x05

[0111] #define BOOT_ON_S5_RESUME 0x06

[0112] #define BOOT_WITH_MFG_MODE_SETTINGS 0x07

[0113] #define BOOT_ON_S2_RESUME 0x10

[0114] #define BOOT_ON_S3_RESUME 0x11

[0115] #define BOOT_ON_FLASH_UPDATE 0x12

[0116] #define BOOT_IN_RECOVERY_MODE 0x20

[0117] 0x21 - 0xF..F Reserved Encodings

[0118] It should be noted that as a storage device, the memory needs to be initialized after the multi-way server system is powered on so that the CPU can read and write data through the established interface. Since the motherboards and the boards used by each machine are different, each machine needs to perform specific initialization on the memory when it is turned on. The MRC code, i.e. the memory initialization code, is generally provided by the CPU or BIOS manufacturer. When executing the MRC code, the CPU first reads the memory parameter information in the Serial Presence Detect (SPD) chip on the memory module through the Inter-Integrated Circuit (I2C) bus. Then, the MRC code performs specific initialization actions on the memory by reading the memory parameter information in the SPD according to the program code set by the CPU manufacturer.

[0119] Figure 4 FIG. 1 is a flow chart of executing MRC code and completing memory initialization in the related art. Figure 4 As shown in Figure 1 Taking the execution of MRC code on the multi-way server system as an example, the process of executing MRC code and completing memory initialization is described. The process includes the following steps:

[0120] The first step is to start executing the MRC code and read the SPD information of the memory modules of DIMM slot 0 to DIMM slot 31 in sequence.

[0121] Each DIMM slot is defined with a unique I2C address. The SPD is located on the memory module. When the memory module is connected to the corresponding DIMM slot, the SPD is connected to the CPU through the I2C bus. Through the I2C bus, the SPD information of the memory modules in DIMM slots 0 to DIMM slots 31 is read in sequence according to the unique I2C address. The SPD information is the memory parameter information in the SPD.

[0122] The second step is to initialize the memory modules of DIMM slot 0 to DIMM slot 31 in sequence.

[0123] After the SPD information of the memory modules in DIMM slot 0 to DIMM slot 31 is obtained, the memory modules in DIMM slot 0 to DIMM slot 31 are initialized in sequence according to the SPD information of the memory modules in DIMM slot 0 to DIMM slot 31.

[0124] The third step is to obtain the parameter values ​​of the memory modules of DIMM slot 0-DIMM slot 31 after training.

[0125] The fourth step is to write the trained parameter values ​​of the memory modules of DIMM slot 0 to DIMM slot 31 into the memory controller registers at the corresponding positions.

[0126] The fifth step is to map the decoded addresses of the memory modules of DIMM slot 0-DIMM slot 31 to the CPU memory address space.

[0127] Step 6: Set the CPU memory address space to be valid.

[0128] The seventh step is to perform read and write tests on the CPU memory address space.

[0129] Step 8: Call the PEI service to report the current CPU memory address space to the PEI scheduler, and the MRC code execution ends.

[0130] It can be understood that when the CPU memory address space read and write test passes, it is determined that the initialization of all memory modules is successfully completed, and the PEI service is called to report the current CPU memory address space to the PEI scheduler so that the PEI scheduler continues to execute the subsequent PEI stage process.

[0131] The MRC code runs on the flash memory and is executed sequentially when initializing the memory modules of each DIMM slot.

[0132] The flash memory interface is generally a serial interface with a slow read and write speed. The supported read speed is about 10MB-100MB, but no special initialization is required in the software, and the CPU can read the content when it is powered on. The DDR memory interface is a parallel interface with a fast read and write speed. The supported read speed is 2400MB-6400MB, but a lot of initialization steps are required before the CPU can use it as a storage space and read and write the content.

[0133] It can be seen that the read and write speed of the flash memory is much lower than the read and write speed of the DDR memory. The MRC code runs slowly on the flash memory, resulting in a longer time and slower initialization speed for the memory.

[0134] Furthermore, the sequential initialization of the memory modules of each DIMM slot makes the code execution efficiency low. In a multi-way server system, when there are many memory configurations, it takes a long time to perform memory initialization using related technologies, and the initialization speed is slow.

[0135] An embodiment of the present invention provides a memory initialization method, which initializes a memory module by a first central processing unit core, copies a memory training code to the memory module, triggers the remaining central processing unit cores to execute the memory training code in the memory module in parallel, and then completes the initialization of all memory modules to reduce the time consumption of memory initialization, improve the speed of memory initialization, and achieve the effect of fast memory initialization.

[0136] According to an embodiment of the present invention, a memory initialization method embodiment is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0137] In this embodiment, a memory initialization method is provided, which can be used for a first central processing unit core in a server, wherein the server may include multiple CPUs, each CPU may include multiple central processing unit cores, and the first central processing unit core may be any central processing unit core in the server. Figure 5 is a flowchart of a memory initialization method according to an embodiment of the present invention. Figure 5 As shown, the process includes the following steps:

[0138] Step S501, in the memory initialization stage, the memory initialization code is run to determine the current startup mode.

[0139] Among them, the server starts and runs BIOS to perform hardware initialization. Specifically, the first central processing unit core in the server first executes the SEC stage code in the BIOS, and then runs the code before the MRC code in the PEI stage, and then reaches the memory initialization stage in the PEI stage to run the memory initialization code, that is, the MRC code.

[0140] Determine the current boot mode of the BIOS by running the memory initialization code.

[0141] Step S502: if the current startup mode is the first mode, then obtain memory parameter information of the memory module.

[0142] In this embodiment, two new BIOS startup modes are defined, one is the fastest startup mode with the least memory (DimmMiniFast), and the other is the fastest startup mode with all memory recognized (DimmFullFast). The first mode is the DimmMiniFast mode, in which only one memory module is initialized and available, the other memory modules are unavailable, and the BIOS can be started.

[0143] When the current startup mode is the first mode, the first memory module needs to be initialized, wherein the first memory module can be any memory module in the server. To initialize the first memory module, first obtain memory parameter information of the memory module. The memory parameter information of the memory module includes memory parameter information corresponding to all memory modules.

[0144] Step S503: training the first memory module based on the memory parameter information to obtain a first training value.

[0145] After the memory parameter information of the memory module is acquired, the first memory module is trained according to the memory parameter information of the first memory module to obtain a first training value.

[0146] It should be noted that memory training is a key step in memory initialization, which is used to ensure that various parameters of the memory module (such as timing, voltage, frequency, etc.) are configured correctly so that it can work correctly under predetermined conditions.

[0147] By training the memory modules, the optimal memory configuration parameters can be found, thereby optimizing the memory read and write speed and stability.

[0148] Memory training can also detect potential failures of memory modules and attempt to repair or bypass these issues, ensuring system reliability.

[0149] It can be understood that the first training value may be an optimal memory configuration parameter of the first memory module.

[0150] Step S504: completing initialization of the first memory module based on the first training value.

[0151] After the first training value is obtained, the first memory module is initialized according to the first training value.

[0152] Step S505: copy the memory training code in the memory initialization code to the first memory module.

[0153] After completing the initialization of the first memory module, the first central processing unit core reads the memory initialization code in the BIOS Read-Only Memory (ROM) and copies the memory training code in the memory initialization code to the first memory module.

[0154] Step S506, sending notification information to the remaining CPU cores in parallel, so that the remaining CPU cores respond to the notification information, train the remaining memory modules based on the memory parameter information and the memory training code, and obtain the remaining training values.

[0155] The first CPU core sends notification information to the other CPU cores in parallel, and the notification information is Inter-Processor Interrupt (IPI) information. The IPI information is a communication method between different CPU cores in a multi-core CPU.

[0156] The remaining central processing unit cores receive the notification information, and in response to the notification information, train the remaining memory modules in parallel based on the memory parameter information and the memory training code in the first memory module to obtain remaining training values ​​corresponding to the remaining memory modules.

[0157] Step S507, saving the first training value and the remaining training values ​​to the target storage area, and restarting the server.

[0158] After the remaining training value is obtained, the first training value and the remaining training value are saved to a target storage area, which is an NVRAM area of ​​the BIOS.

[0159] After the first training value and the remaining training values ​​are saved in the target storage area, a system restart service (resetsystem service) is called to restart the server, re-run the BIOS, and return to execute step S501 and subsequent steps.

[0160] Step S508: if the current startup mode is the second mode, obtaining the first training value and the remaining training values ​​from the target storage area.

[0161] The second mode is DimmFullFast. In this mode, all memory modules need to be initialized, all memory modules are available and the BIOS can be started.

[0162] When the current startup mode is the second mode, the first training value and the remaining training values ​​are acquired from the target storage area.

[0163] Step S509: completing initialization of the memory module based on the first training value and the remaining training values.

[0164] After the first training value and the remaining training values ​​are obtained from the target storage area, the memory module is initialized according to the first training value and the remaining training values.

[0165] The memory initialization method provided in this embodiment determines the current startup mode by running the memory initialization code in the memory initialization stage. When the current startup mode is the first mode, the first memory module is first trained based on the memory parameter information of the memory module to obtain the first training value. The first memory module is initialized based on the first training value. The memory training code is copied to the first memory module, and the remaining memory modules are trained in parallel by the remaining central processing unit cores according to the memory parameter information and the memory training code to obtain the remaining training value. The first training value and the remaining training value are saved to the target storage area, and the server is restarted. When the current startup mode is the second mode, the memory module is initialized based on the first training value and the remaining training value. The first central processing unit core is used to initialize a memory module first, and the memory training code is copied to the memory module, and the remaining central processing unit cores are triggered to execute the memory training code in the memory module in parallel, thereby completing the initialization of all memory modules. The memory training codes of multiple memory modules are executed in parallel from the memory module, which reduces the time consumption of memory initialization, improves the speed of memory initialization, and realizes the rapid initialization of memory.

[0166] In this embodiment, a memory initialization method is provided, which can be used for a first central processing unit core in a server. Figure 6 is a flowchart of a memory initialization method according to an embodiment of the present invention. Figure 6 As shown, the process includes the following steps:

[0167] Step S601, in the memory initialization phase, the memory initialization code is run to determine the current startup mode.

[0168] Specifically, the above step S601 includes:

[0169] Step S6011, running the memory initialization code to determine whether the target storage area includes the first training value and the remaining training values.

[0170] In the memory initialization stage, the first central processing unit core runs the memory initialization code to determine whether the target memory includes the first training value and the remaining training values.

[0171] Step S6012: When the target storage area does not include the first training value and the remaining training value, determine that the current startup mode is the first mode.

[0172] The target storage area does not include the first training value and the remaining training value, indicating that all memory modules have not been initialized, and it is determined that the current startup mode is the first mode.

[0173] It should be noted that, when the target storage area does not include the first training value and the remaining training value, the SetBootMode() parameter is called to set the current boot mode to the first mode.

[0174] Step S6013: When the target storage area includes the first training value and the remaining training value, determine that the current startup mode is the second mode.

[0175] The target storage area includes the first training value and the remaining training value, which means that all modules can be initialized according to the first training value and the remaining training value, and the current startup mode is determined to be the second mode.

[0176] It should be noted that, when the target storage area includes the first training value and the remaining training value, the SetBootMode() parameter is called to set the current boot mode to the second mode.

[0177] Step S602: if the current startup mode is the first mode, obtain memory parameter information of the memory module.

[0178] Specifically, the above step S602 includes:

[0179] Step S6021, based on the address information of the memory module, obtaining memory parameter information of the memory module.

[0180] Among them, each memory slot is defined with a unique I2C address, and the SPD is located on the memory module. When the memory is connected to the memory slot, the SPD on the memory module is connected to the CPU through the I2C bus. The MRC code is run to read the SPD information of the memory module corresponding to the DIMM slot in sequence according to the unique I2C address through the I2C bus.

[0181] Step S603: Based on the memory parameter information, the first memory module is trained to obtain a first training value. Figure 5 Step S503 of the illustrated embodiment will not be described in detail here.

[0182] Step S604: completing initialization of the first memory module based on the first training value.

[0183] Specifically, the above step S604 includes:

[0184] Step S6041, writing the first training value into the register of the first memory controller corresponding to the first memory module, so that the first memory module is in a working state.

[0185] After the first training value is obtained, the first training value is written into a register of a first memory controller corresponding to the first memory module, so that the first memory module is in a working state.

[0186] Step S6042: Determine a decoding address of the first memory module based on the memory parameter information.

[0187] Wherein, according to the memory parameter information of the first memory module, the decoding address of the first memory module is determined, and the decoding address includes the start address and the end address of the first memory module.

[0188] Step S6043, based on the decoded address of the first memory module, mapping the first memory module to the memory address space of the central processing unit, and setting the memory address space of the central processing unit to be valid, so as to complete the initialization of the first memory module.

[0189] Among them, after obtaining the decoding address of the first memory module, the first memory module is mapped to the memory address space of the central processing unit according to the decoding address of the first memory module, that is, the first memory module is mapped to the memory address space of the central processing unit according to the memory capacity, start address and end address of the first memory module.

[0190] Setting the memory address space of the central processing unit to be valid means setting the memory address space of the first memory module to be valid. At this time, the address range of the memory address space readable and writable by the CPU is from 0 to the memory capacity of the first memory module.

[0191] Step S605, copy the memory training code in the memory initialization code to the first memory module. Figure 5 Step S505 of the illustrated embodiment will not be described in detail here.

[0192] Step S606, sending notification information to the remaining CPU cores in parallel, so that the remaining CPU cores respond to the notification information, train the remaining memory modules based on the memory parameter information and the memory training code, and obtain the remaining training values. Figure 5 Step S506 of the illustrated embodiment will not be described in detail here.

[0193] Step S607: Save the first training value and the remaining training values ​​to the target storage area, and restart the server. Figure 5 Step S507 of the illustrated embodiment will not be described in detail here.

[0194] Step S608: If the current startup mode is the second mode, the first training value and the remaining training value are obtained from the target storage area. Figure 5 Step S508 of the illustrated embodiment will not be described in detail here.

[0195] Step S609: Initialize the memory module based on the first training value and the remaining training values. Figure 5 Step S509 of the illustrated embodiment will not be described in detail here.

[0196] The memory initialization method provided in this embodiment accurately determines the current startup mode by judging whether the target storage area includes the first training value and the remaining training values, avoids unnecessary initialization steps, and speeds up the startup speed of the system.

[0197] By acquiring the memory parameter information of the memory module according to the address information of the memory module, the memory parameter information can be acquired quickly and accurately.

[0198] By writing the first training value into the register of the first memory controller corresponding to the first memory module, the first memory module is put into working state, and based on the memory parameter information, the decoding address of the first memory module is determined. Based on the decoding address of the first memory module, the first memory module is mapped to the memory address space of the central processing unit, and the memory address space of the central processing unit is set to be valid, the initialization of the first memory module can be completed accurately, thereby improving the overall performance and reliability of the system.

[0199] In some optional implementations, the above step S605 includes:

[0200] Step a1, determining the number of memory training codes to be copied based on the number of memory modules.

[0201] The number of memory training codes to be copied is determined according to the number of memory modules in the current server, and the number of memory training codes to be copied is the same as the number of memory modules.

[0202] Step a2: dividing the first storage area of ​​the first memory module into a plurality of first storage sub-areas based on the number of memory training codes to be copied.

[0203] The first memory module is divided into a first storage area, and according to the number of memory training codes to be copied, the first storage area is divided into a corresponding number of first storage sub-areas.

[0204] Step a3: copy the memory training code to multiple first storage sub-areas.

[0205] It can be understood that, according to the order of the memory modules, the memory training codes corresponding to the memory modules are copied to the corresponding first storage sub-areas, and one first storage sub-area includes a memory training code.

[0206] The memory initialization method provided in this embodiment can execute the initialization process of multiple memory modules in parallel by copying the memory training code to multiple first storage sub-areas of the first memory module, thereby significantly reducing the memory initialization time and improving the system startup speed.

[0207] In some optional implementations, the above step S606 includes:

[0208] Step b1, based on the number of memory modules, select the target CPU core from the remaining CPU cores.

[0209] In this embodiment, the number of CPU cores in the server is greater than the number of memory modules as an example, and target CPU cores with the same number as the memory modules are selected from the remaining CPU cores except the first CPU core.

[0210] It should be noted that a corresponding number of target CPU cores may be randomly selected from the remaining CPU cores.

[0211] Filter the target CPU cores from the remaining CPU cores based on the number of memory modules, including:

[0212] According to the order of the CPU cores in the server, target CPU cores having the same number as the memory modules are selected from the remaining CPU cores in sequence.

[0213] Alternatively, a performance monitoring tool is used to obtain performance data of each of the remaining CPU cores, and based on the performance data, the remaining CPU cores are sorted from high to low in performance, and target CPU cores with the same number of memory modules as those with the highest sorting results are selected.

[0214] Alternatively, a system monitoring tool is used to obtain load data of each of the remaining CPU cores, and based on the load data, the remaining CPU information is sorted, wherein the higher the load, the lower the sorting, and the target CPU cores with the same number of memory modules as the top of the sorting results are screened out.

[0215] Among them, the target CPU core is screened according to the order of the CPU cores in the server, which does not require additional monitoring tools or complex algorithms and is easy to implement and maintain. The method of using performance data to screen the target CPU core can better utilize system resources, improve the overall performance of the system, and speed up the initialization of memory. The method of using load data to screen the target CPU core can improve the stability and response speed of the system and increase the speed of memory initialization.

[0216] In practical applications, one of the above methods can be used to screen the target CPU core according to the actual situation.

[0217] Step b2, sending notification information to the target central processing unit core in parallel, so that the target central processing unit core responds to the notification information, trains the remaining memory modules based on the memory parameter information and the corresponding memory training code in the first storage sub-area, and obtains the remaining training values.

[0218] Among them, one target central processing unit core corresponds to a memory training code in the first storage sub-area, and one memory training code in the first storage sub-area corresponds to a remaining memory module.

[0219] It can be understood that, for any target central processing unit core, after the target central processing unit core receives the notification information, in response to the notification information, based on the memory parameter information of the remaining memory module corresponding to the target central processing unit core and the memory training code in the first storage sub-area corresponding to the target central processing unit core, the remaining memory module corresponding to the target central processing unit core is trained to obtain the remaining training value of the remaining memory module.

[0220] The memory initialization method provided in this embodiment sends notification information to the target central processor core in parallel, so that the target central processor can start training the remaining memory modules in parallel to obtain the remaining training values, thereby reducing the time required for memory initialization and improving the system startup speed.

[0221] In some optional implementations, the memory initialization method further includes:

[0222] Step c1: dividing the second storage area of ​​the first memory module into a plurality of second storage sub-areas based on the number of memory modules.

[0223] The second storage area is divided from the first memory module, and according to the number of memory modules in the server, the second storage area is divided into a corresponding number of second storage sub-areas.

[0224] Step c2: storing the first training value in the corresponding second storage sub-area.

[0225] It can be understood that the first training values ​​are stored in the corresponding second storage sub-areas according to the order of the first memory modules in all memory modules.

[0226] Step c3, sending notification information to the target CPU core in parallel, so that the target CPU core stores the obtained remaining training values ​​into the corresponding second storage sub-area.

[0227] Among them, the remaining training value corresponding to a remaining memory module corresponds to a second storage sub-area.

[0228] The memory initialization method provided in this embodiment divides the second storage area of ​​the first memory module into multiple second storage sub-areas. The remaining training values ​​of each remaining memory module can be stored in a second storage sub-area, thereby avoiding interference and conflict between data, and realizing efficient and orderly storage of the training values ​​of each memory module, thereby significantly improving the performance and reliability of the system.

[0229] In some optional implementations, the above step S607 includes:

[0230] Step d1, cyclically checking whether corresponding training values ​​are stored in all the second storage sub-areas.

[0231] After the first CPU core sends notification information to the target CPU core in parallel, it is cyclically checked whether corresponding training values ​​are stored in all the second storage sub-areas, and the training values ​​include the first training value and the remaining training values.

[0232] Step d2: if it is checked that the corresponding training values ​​are stored in the plurality of second storage sub-areas, the first training value and the remaining training values ​​in the plurality of second storage sub-areas are read, and the first training value and the remaining training values ​​are saved in the transfer buffer area.

[0233] Among them, if it is checked that corresponding training values ​​are stored in multiple second storage sub-areas, it means that the training of all memory modules has been completed, the first training value and the remaining training values ​​are read from the multiple second storage sub-areas, and a handover data block (and-Off Block, abbreviated as: HOB) is created, that is, a transfer buffer area, and the first training value and the remaining training values ​​are saved in the transfer buffer area.

[0234] It should be noted that HOB is an important data structure used to transfer information between different startup stages.

[0235] Step d3, in the driver execution environment stage, read the first training value and the remaining training values ​​in the transfer buffer area, and save the first training value and the remaining training values ​​to the target storage area.

[0236] It should be noted that, in the first mode, the first central processing unit core skips executing other modules in the PEI stage. When running to the driver execution environment stage, the first central processing unit core reads the first training value and the remaining training values ​​in the transfer buffer area, and calls the Setvariable service to save the first training value and the remaining training values ​​to the NVRAM area.

[0237] The memory initialization method provided in this embodiment ensures that all necessary training values ​​have been correctly stored by cyclically checking whether corresponding training values ​​are stored in multiple second storage sub-areas, thereby avoiding initialization failure or system abnormality caused by missing some training values, ensuring the integrity and consistency of the training values ​​of the memory module, and improving the performance and reliability of the system.

[0238] In some optional implementations, the above step S609 includes:

[0239] Step e1, writing the first training value into the register of the first memory controller corresponding to the first memory module, so that the first memory module is in a working state.

[0240] After the first training value and the remaining training values ​​are obtained, in the second mode, the first training value is written into a register of the first memory controller corresponding to the first memory module, so that the first memory module is in a working state.

[0241] Step e2, writing the remaining training values ​​into the registers of the target memory controllers of the corresponding remaining memory modules, so that the remaining memory modules are in working state.

[0242] In the second mode, the remaining training values ​​are written into the registers of the target memory controllers of the corresponding remaining memory modules, so that the remaining memory modules are in a working state.

[0243] Step e3: determining a decoding address of the first memory module and decoding addresses of the remaining memory modules based on the memory parameter information.

[0244] It is understandable that in the second mode, it is also necessary to obtain the memory parameter information of the memory module, and determine the decoding address of the first memory module and the decoding addresses of the remaining memory modules according to the memory parameter information.

[0245] Step e4, based on the decoded address of the first memory module and the decoded addresses of the remaining memory modules, mapping the first memory module and the remaining memory modules to the memory address space of the central processing unit, and setting the memory address space of the central processing unit valid to complete the initialization of the memory modules.

[0246] After obtaining the decoding address of the first memory module and the decoding address of the remaining memory modules, the first memory module and the remaining memory modules are mapped to the memory address space of the central processing unit based on the decoding address of the first memory module and the decoding address of the remaining memory modules, and the memory address space of the central processing unit is set valid, that is, the memory address space of the first memory module and the remaining memory modules is set valid, and the initialization of all memory modules is completed.

[0247] The memory initialization method provided in this embodiment ensures that each memory module can be correctly started and enter the working state by writing the first training value into the register of the first memory controller corresponding to the first memory module, and writing the remaining training values ​​into the register of the target memory controller corresponding to the remaining memory modules. This avoids the risk of memory modules not being able to work properly due to configuration errors and improves the performance and stability of the system.

[0248] In some optional implementations, after setting the memory address space of the central processing unit to be valid, the memory initialization method further includes:

[0249] Step f1, performing a read and write test on the memory module, the memory module includes a first memory module and remaining memory modules.

[0250] After the memory module is initialized, it is necessary to perform a read and write test on the memory module, that is, to perform a read and write test on the memory address space of the memory module to determine whether the memory module has successfully completed the initialization.

[0251] Step f2: when the read and write tests of the memory module are passed, it is determined that the initialization of the memory module is successfully completed.

[0252] It should be noted that, when the read and write tests of the memory module are passed, the PEI service is called to report the current CPU memory address space to the PEI scheduler, so that the PEI scheduler continues to execute the subsequent PEI stage process.

[0253] Step f3: if at least one memory module fails the read / write test, determining that the initialization of the memory module fails.

[0254] The memory initialization method provided in this embodiment can verify whether each memory module can correctly read and write data through read and write tests, thereby ensuring that the memory module can work normally after initialization, avoiding system instability or data loss caused by memory failure, and improving system reliability.

[0255] In some optional implementations, the memory initialization method further includes:

[0256] Step g1, when the initialization of the memory module fails, the execution of the stages after the memory initialization stage is stopped, and error logs are recorded, so that the user can locate the cause of the failure of the initialization of the memory module according to the error logs.

[0257] The memory initialization method provided in this embodiment stops executing the stages after the memory initialization stage when the initialization of the memory module fails, thereby preventing the system from continuing to run in an erroneous state, avoiding further failures or data corruption, and improving the reliability and maintainability of the system.

[0258] In order to make the memory initialization method of the embodiment of the present invention clearer, the memory initialization method of the embodiment of the present invention is described in conjunction with a specific embodiment. In this specific embodiment, the server includes two CPUs, 32 memory modules (DIMM0-DIMM31), and each CPU includes 16 CPU cores. Figure 7 is a flowchart of a memory initialization method according to an embodiment of the present invention. Figure 7 As shown, the memory initialization method includes the following steps:

[0259] In the first step, the server is powered on, the BIOS is running, and CPU0 core0 starts to run the SEC phase code. It should be noted that this embodiment is described by taking CPU0 core0 executing the memory initialization method as an example.

[0260] In the second step, CPU0 core0 runs the code before the MRC code in the PEI stage, that is, runs the module before the MRC in the PEI stage.

[0261] The third step is to execute to the MRC part to determine whether all memory modules DIMM0-DIMM31 are not initialized, that is, by reading the MRC-PARM-HOB-NV variable in the BIOS NVRAM area to determine whether the MRC-PARM-HOB-NV content exists.

[0262] If it does not exist, call SetBootMode() to set the current boot mode to DimmMiniFast mode.

[0263] If it exists, call SetBootMode() to set the current boot mode to DimmFullFast mode.

[0264] In case the current boot mode is DimmMiniFast mode, the fourth step to the nineteenth step are executed.

[0265] In case the current boot mode is the DimmFullFast mode, steps 20 to 27 are executed.

[0266] The fourth step is to read the SPD information of DIMM0 and obtain the memory capacity of DIMM0, which is called DIMM0SIZE.

[0267] The fifth step is to initialize the training of DIMM0 to obtain the parameter value of DIMM0 after training, that is, the first training value, called PARAM0.

[0268] Step 6. Write PARAM0 to register PARAM0-TRQSD0 of the memory controller (CPU0-UMC0-DIMM0) corresponding to DIMM0.

[0269] Step 7: Map the decoded address of DIMM0, DIMM0-SIZE, to the memory address space of the CPU.

[0270] Step 8: Set the memory address space of DIMM0 to be valid. At this time, the address range of the memory address space (DIMM0SPACE) that can be read and written by CPU0 and CPU1 is 0 - DIMM0SIZE. Report the current CPU memory address space to the PEI scheduler by calling the PEI service InstallEfiMemory to determine the current readable and writable memory address space.

[0271] In the ninth step, CPU0 core0 reads the contents of the MRC module in the BIOS ROM and copies 32 copies of the memory training code (other parts are not copied) to DIMM0SPACE. Figure 8 is a schematic diagram of copying the memory training code to the first memory module and saving the training value to the first memory module according to an embodiment of the present invention, such as Figure 8 As shown, the first memory module is DIMM0, and the memory training codes are MRC-CODE0 to MRC-CODE31.

[0272] Step 10: divide part of the memory address space of DIMM0 into 32 parts for storing the parameter structure after the corresponding DIMM training, that is, the training value of the memory module, such as Figure 8 MRC-PARM0 to MRC-PARM31 in.

[0273] Step 11. DIMM0 has been trained and PARAM0 is copied to the MRC-PARM0 area.

[0274] Step 12: Send IPI information to other CPU cores in parallel. Specifically, CPU0 CORE0 sends IPI information to CPU CORE1, CPU CORE2, until CPU CORE31, and executes MRC-CODE1 to MRC-CODE31 in sequence.

[0275] For example:

[0276] CPU0 CORE0 sends IPI information to CPU0 CORE1 to notify it to execute MRC-CODE1. After MRC-CODE1 is executed, the memory training information of DIMM1, i.e., the training value, is stored in the MRC-PARM1 area;

[0277] CPU0 CORE0 sends IPI information to CPU0 CORE2 to notify it to execute MRC-CODE2. After MRC-CODE2 is executed, the memory training information of DIMM2 is stored in the MRC-PARM2 area;

[0278] CPU0 CORE0 sends IPI information to CPU1 CORE0 to notify it to execute MRC-CODE16. After MRC-CODE16 is executed, the memory training information of DIMM16 is stored in the MRC-PARM16 area;

[0279] CPU0 CORE0 sends IPI information to CPU1 CORE15, notifying it to execute MRC-CODE31. After MRC-CODE31 is executed, the memory training information of DIMM31 is stored in the MRC-PARM31 area.

[0280] The process of other CPU cores training the memory module is similar to the above example and will not be repeated here.

[0281] In step 13, CPU0 CORE0 loops through memory module areas MRC-PARAM0 to MRC-PARAM31 until all memory modules are trained.

[0282] Step 14: CPU0 CORE0 reads the contents of MRC-PARAM0, MRC-PARAM1…MRC-PARAM31, creates a HOB, and defines it as MRC-PARM-HOB.

[0283] Step 15: The first MRC execution of CPU0 CORE0 is completed.

[0284] Step 16: Because in DimmMiniFast mode, CPU0 CORE0 executes MRC to complete DIMM0 memory initialization, skips executing other modules in the PEI stage, only copies the necessary modules in the PEI stage to the memory, and runs the necessary modules in the PEI stage.

[0285] In the seventeenth step, CPU0 CORE runs to the DXE stage.

[0286] Step 18. In DimmMiniFast mode, the necessary modules of the DXE stage run, read the content of MRC-PARM-HOB, and call the Setvariable service to save the content of MRC-PARM-HOB into NVRAM, which is called MRC-PARM-HOB-NV.

[0287] Step 19: Call the resetsystem service to restart the system. It is understandable that after restarting the system, the first step and subsequent steps are re-executed.

[0288] Step 20, read the content in MRC-PARM-HOB-NV to obtain MRC-PARAM0, MRC-PARAM1...MRC-PARAM31.

[0289] In the 21st step, the read contents are written into the registers of the memory controller corresponding to the DIMM in sequence.

[0290] Step 22: Map the decoded address of DIMM0-DIMM31, DIMM0-SIZE-DIMM31-SIZE, to the memory address space of the CPU.

[0291] Step 23: Set the memory address space of DIMM0-DIMM31 to be valid.

[0292] Step 24: Perform read and write tests on the memory address space of DIMM0-DIMM31.

[0293] Step 25: Call the PEI service InstallEfiMemory to report the current CPU memory address space to the PEI scheduler.

[0294] In the twenty-sixth step, CPU0 CORE0 executes the MRC code to complete the memory initialization of DIMM0-DIMM31.

[0295] Step 27: Continue to execute other module contents. In the DimmFullFast mode, continue to execute all other modules in the PEI stage, all other modules in the DXE stage, and the BDS stage to boot into the operating system (OS).

[0296] The memory initialization method provided in this embodiment utilizes the first central processing unit core to first initialize a memory module, copies the memory training code to the memory module, triggers the remaining central processing unit cores to execute the memory training code in the memory module in parallel, and then completes the initialization of all memory modules, thereby reducing the time consumption of memory initialization, improving the speed of memory initialization, and realizing fast initialization of memory.

[0297] In this embodiment, a server is also provided. The server includes a first central processing unit core. The first central processing unit core is used to execute the memory initialization method shown in the above embodiment.

[0298] The embodiment of the present invention also provides a computer device, see Fig. 9 , Fig. 9 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Fig. 9 As shown, the computer device includes: one or more processors 901, memory 902, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Each component utilizes different buses to communicate with each other, and can be installed on a common mainboard or installed in other ways as required. The processor can process the instructions executed in the computer device, including instructions stored in the memory or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Fig. 9 A processor 901 is taken as an example.

[0299] The processor 901 may be a central processing unit, a network processor or a combination thereof. The processor 901 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable logic gate array, a general purpose array logic or any combination thereof.

[0300] The memory 902 stores instructions executable by at least one processor 901 so as to enable at least one processor 901 to implement the method shown in the above embodiment.

[0301] The memory 902 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 902 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 902 may optionally include a memory remotely arranged relative to the processor 901, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0302] The memory 902 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 902 may also include a combination of the above types of memory.

[0303] The computer device also includes a communication interface 903, which is used for the computer device to communicate with other devices or a communication network.

[0304] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0305] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0306] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A memory initialization method, characterized in that: Applied to a first central processing unit core, the method comprises: In the memory initialization phase, the memory initialization code is run to determine the current startup mode; If the current startup mode is the first mode, obtaining memory parameter information of the memory module; Based on the memory parameter information, training the first memory module to obtain a first training value; Based on the first training value, completing initialization of the first memory module; Copying the memory training code in the memory initialization code to the first memory module; Sending notification information to the remaining CPU cores in parallel, so that the remaining CPU cores respond to the notification information, train the remaining memory modules based on the memory parameter information and the memory training code, and obtain remaining training values; Saving the first training value and the remaining training values ​​to a target storage area, and restarting the server; If the current startup mode is the second mode, acquiring the first training value and the remaining training value from the target storage area; Based on the first training value and the remaining training value, completing initialization of the memory module; The running memory initialization code to determine the current startup mode includes: Running a memory initialization code to determine whether the target storage area includes the first training value and the remaining training value; In a case where the target storage area does not include the first training value and the remaining training value, determining that the current startup mode is the first mode; In a case where the target storage area includes the first training value and the remaining training value, determining that the current startup mode is the second mode; The method further comprises: after restarting the server, returning to execute the step of running the memory initialization code in the memory initialization phase and determining the current startup mode; The first memory module is a double data rate memory.

2. The method according to claim 1, characterized in that The obtaining of memory parameter information of the memory module includes: Based on the address information of the memory module, memory parameter information of the memory module is obtained.

3. The method according to claim 1, characterized in that The initializing the first memory module based on the first training value includes: Writing the first training value into a register of a first memory controller corresponding to the first memory module, so that the first memory module is in a working state; Based on the memory parameter information, determining a decoding address of the first memory module; Based on the decoded address of the first memory module, the first memory module is mapped to the memory address space of the central processing unit, and the memory address space of the central processing unit is set to be valid, so as to complete the initialization of the first memory module.

4. The method according to claim 1, characterized in that The step of copying the memory training code in the memory initialization code to the first memory module comprises: Determining the number of memory training codes to be copied based on the number of memory modules; Based on the number of the memory training codes to be copied, dividing the first storage area of ​​the first memory module into a plurality of first storage sub-areas; The memory training code is copied into a plurality of first storage sub-areas.

5. The method according to claim 4, characterized in that The sending notification information to the remaining CPU cores in parallel so that the remaining CPU cores respond to the notification information, train the remaining memory modules based on the memory parameter information and the memory training code, and obtain the remaining training values, comprises: Based on the number of the memory modules, selecting a target CPU core from the remaining CPU cores; Sending notification information to the target CPU core in parallel, so that the target CPU core responds to the notification information, trains the remaining memory modules based on the memory parameter information and the corresponding memory training code in the first storage sub-area, and obtains the remaining training values; Among them, one target central processing unit core corresponds to a memory training code in the first storage sub-area, and one memory training code in the first storage sub-area corresponds to a remaining memory module.

6. The method according to claim 5, characterized in that The method further comprises: Based on the number of the memory modules, dividing the second storage area of ​​the first memory module into a plurality of second storage sub-areas; Storing the first training value in the corresponding second storage sub-area; Sending notification information to the target CPU core in parallel, so that the target CPU core stores the obtained remaining training values ​​into the corresponding second storage sub-area; Among them, the remaining training value corresponding to a remaining memory module corresponds to a second storage sub-area.

7. The method according to claim 6, characterized in that The step of saving the first training value and the remaining training values ​​to a target storage area includes: Circularly checking whether corresponding training values ​​are stored in the plurality of second storage sub-areas; If it is checked that the corresponding training values ​​are stored in the plurality of second storage sub-areas, the first training value and the remaining training values ​​in the plurality of second storage sub-areas are read, and the first training value and the remaining training values ​​are saved in the transfer buffer area; In the driver execution environment stage, the first training value and the remaining training values ​​in the transfer buffer are read, and the first training value and the remaining training values ​​are saved in the target storage area.

8. The method according to claim 1, characterized in that The initializing the memory module based on the first training value and the remaining training value includes: Writing the first training value into a register of a first memory controller corresponding to the first memory module, so that the first memory module is in a working state; Writing the remaining training values ​​into the register of the target memory controller of the corresponding remaining memory module so that the remaining memory module is in a working state; Based on the memory parameter information, determining a decoding address of the first memory module and a decoding address of the remaining memory modules; Based on the decoded address of the first memory module and the decoded addresses of the remaining memory modules, the first memory module and the remaining memory modules are mapped to the memory address space of the central processing unit, and the memory address space of the central processing unit is set valid to complete the initialization of the memory modules.

9. The method according to claim 8, characterized in that After setting the memory address space of the central processing unit to be valid, the method further includes: Performing a read and write test on the memory module, wherein the memory module includes a first memory module and remaining memory modules; In the case where both the read and write tests of the memory module are passed, determining that the initialization of the memory module is successfully completed; If at least one memory module fails the read / write test, it is determined that the initialization of the memory module fails.

10. The method according to claim 1, characterized in that The method further comprises: In the case that the initialization of the memory module fails, the execution of the stages after the memory initialization stage is stopped, and error logs are recorded, so that the user can locate the cause of the failure of the initialization of the memory module according to the error logs.

11. A server, characterized in that: include: A first central processing unit core, wherein the first central processing unit core is used to execute the memory initialization method according to any one of claims 1 to 10.

12. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the memory initialization method according to any one of claims 1 to 10 by executing the computer instructions.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the memory initialization method according to any one of claims 1 to 10.

14. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to enable a computer to execute the memory initialization method according to any one of claims 1 to 10.

Images