Computing System, Data Processing Method, Device, Apparatus, Medium, and Program Product

Abstract

Embodiments of the present application provide a computing system, a data processing method, a device, a device, a medium, and a program product. In the embodiments of the present application, when the data volume of the target data to be exchanged between the hardware processing unit and the processor is less than or equal to the set data volume threshold, according to the field definition of the hardware descriptor, a target hardware descriptor carrying the target data is generated, realizing an elastic change of the field definition of the hardware descriptor. Then, the target hardware descriptor is written into the data queue in the memory. In this way, the receiver of the target data (hardware processing unit or processor) can read the target hardware descriptor from the memory and directly obtain the target data from the target hardware descriptor. The receiver of the target data can obtain the target data with only one memory access operation, without having to read the target data from other memory areas, which can reduce the number of memory accesses of the receiver of the target data, thereby reducing the resource consumption of memory access.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a computing system, a data processing method, a device, an apparatus, a medium, and a program product. Background Art

[0002] A Domain Specific Architecture (DSA) is a programmable hardware processor customized for a specific domain and can be used to accelerate certain applications. The DSA allows for optimization within a specific domain, thereby achieving higher performance. By customizing the hardware or architecture, the execution efficiency can be significantly improved, the latency can be reduced, and the energy consumption can be optimized in certain specific tasks.

[0003] The DSA hardware can be integrated as a separate Root Complex Integrated Endpoint (RCiEP) device into the socket of a Central Processing Unit (CPU). The DSA hardware can achieve hardware acceleration for data processing. However, when the CPU and the DSA hardware interact to execute a computing task, they need to frequently access the memory to exchange data. These frequent memory access operations consume a large amount of system resources and affect the overall performance of the system. Summary of the Invention

[0004] Multiple aspects of this application provide a computing system, a data processing method, a device, an apparatus, a medium, and a program product, which can reduce the number of memory accesses when exchanging data between a processor and a hardware processing unit.

[0005] An embodiment of this application provides a computing system, including: a processor, a hardware processing unit, and a memory; the processor and the hardware processing unit are respectively electrically connected to the memory; the memory stores a data queue for storing hardware descriptors; the hardware descriptor is a data structure for describing information about the data exchanged between the hardware processing unit and the processor;

[0006] The hardware processing unit or the processor is configured to, when the data volume of the target data to be exchanged between the hardware processing unit and the processor is less than or equal to a set data volume threshold, generate a target hardware descriptor carrying the target data according to the field definition of the hardware descriptor; and write the target hardware descriptor into the data queue for the recipient of the target data to read the target hardware descriptor from the data queue and obtain the target data from the target hardware descriptor.

[0007] An embodiment of the present application further provides a data processing method, which is applicable to a processor or a hardware processing unit. The processor and the hardware processing unit are respectively electrically connected to a memory. The memory stores a data queue for storing hardware descriptors. The hardware descriptor is a data structure that describes information about the data exchanged between the hardware processing unit and the processor.

[0008] The method includes:

[0009] In a case where the amount of target data to be exchanged between the hardware processing unit and the processor is less than or equal to a set data amount threshold, a target hardware descriptor carrying the target data is generated according to the field definition of the hardware descriptor.

[0010] The target hardware descriptor is written into the data queue for the recipient of the target data to read the target hardware descriptor from the data queue and obtain the target data from the target hardware descriptor.

[0011] An embodiment of the present application further provides a data processing method, which is applicable to a hardware processing unit or a processor. The processor and the hardware processing unit are respectively electrically connected to a memory. The memory stores a data queue for storing hardware descriptors. The hardware descriptor is a data structure that describes information about the data exchanged between the hardware processing unit and the processor.

[0012] The method includes:

[0013] Read a target hardware descriptor from the data queue. The target hardware descriptor is a hardware descriptor carrying the target data generated by the provider of the target data according to the field definition of the hardware descriptor in a case where the amount of target data to be exchanged between the hardware processing unit and the processor is less than or equal to a set data amount threshold.

[0014] Obtain the target data from the target hardware descriptor.

[0015] An embodiment of the present application further provides a hardware processing device, including: a memory access engine and a computing engine. The memory computing engine and the computing engine are electrically connected. The hardware processing device is used to be electrically connected to a memory, and the memory is electrically connected to a processor. The memory stores a second data queue, and the hardware descriptor in the second data queue is a data structure that describes information about the data provided by the hardware processing device to the processor.

[0016] The computing engine is configured to generate a target hardware descriptor carrying the target data according to the field definitions of the hardware descriptor when the amount of data of the target data to be exchanged between the hardware processing device and the processor is less than or equal to a set data volume threshold.

[0017] The memory access engine is configured to: write the target hardware descriptor into the second data queue for the processor to read the target hardware descriptor from the second data queue and obtain the target data from the target hardware descriptor.

[0018] On the other hand, the memory further stores a first data queue; the hardware descriptor in the first data queue is a data structure describing the information of the data obtained by the hardware processing device from the processor.

[0019] The memory access engine is further configured to: read a first hardware descriptor from the first data queue; and obtain the target original data from the first hardware descriptor; the first hardware descriptor is a hardware descriptor carrying the target original data generated by the processor according to the field definitions of the hardware descriptors in the first data queue when the amount of data of the target original data corresponding to the target computing request is less than or equal to a set first data volume threshold.

[0020] The computing engine is further configured to perform calculations on the target original data to obtain a target calculation result corresponding to the target computing request.

[0021] An embodiment of the present application further provides an electronic device, including: a memory and a processor; the memory includes a memory and other storage media; the processor is electrically connected to the memory; the memory is used to be electrically connected to a hardware processing unit; the other storage media is used to store a computer program; the memory stores a data queue; the hardware descriptor in the data queue is a data structure describing the information of the data to be exchanged between the hardware processing unit and the processor.

[0022] The processor is coupled to the memory and the other storage media and is configured to execute the computer program to perform the steps in the foregoing data processing method executed by the processor.

[0023] An embodiment of the present application further provides a computer-readable storage medium storing computer instructions, which, when executed by one or more processors, cause the one or more processors to perform the steps in the foregoing various data processing methods.

[0024] An embodiment of the present application also provides a computer program product, including a computer program, which, when executed by one or more processors, causes the one or more processors to execute the steps in the above data processing methods.

[0025] In an embodiment of the present application, when the data volume of the target data to be exchanged between the hardware processing unit and the processor is less than or equal to a set data volume threshold, according to the field definition of the hardware descriptor, a target hardware descriptor carrying the target data is generated, realizing an elastic change in the field definition of the hardware descriptor. Then, the target hardware descriptor is written into the data queue in the memory. In this way, the recipient of the target data (the hardware processing unit or the processor) can read the target hardware descriptor from the memory and directly obtain the target data from the target hardware descriptor. Among them, the recipient of the target data only needs one memory access operation to obtain the target data, without having to read the target data from other memory areas, which can reduce the number of memory accesses of the recipient of the target data, thereby reducing the resource consumption of memory access. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the present application, and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation of the present application. In the drawings:

[0027] Figure 1 FIG. 12 is a schematic structural diagram of a computing system provided by a traditional solution and a schematic diagram of the interaction process between the CPU and the DSA hardware in the computing system;

[0028] Figure 2 FIG. 16 is a schematic structural diagram of a traditional hardware descriptor;

[0029] Figure 3 and Figure 4 FIG. 22 is a schematic structural diagram of a computing system provided by an embodiment of the present application and a schematic diagram of the interaction process between the processor and the hardware processing unit in the computing system;

[0030] Figure 5 FIG. 26 is another schematic diagram of the interaction process between the processor and the hardware processing unit provided by an embodiment of the present application;

[0031] Figure 6 FIG. 30 is a schematic diagram of the detailed interaction process between the processor and the hardware processing unit provided by an embodiment of the present application;

[0032] Figure 7 and Figure 8 FIG. 36 is a schematic flowchart of a data processing method provided by an embodiment of the present application;

[0033] Figure 9a FIG. 40 is a schematic structural diagram of a hardware processing device provided by an embodiment of the present application;

[0034] Figure 9b This is a schematic structural diagram of the electronic device provided by the embodiment of the present application. Detailed implementation manners

[0035] To make the objectives, technical solutions, and advantages of the present application clearer, the technical solutions of the present application will be clearly and completely described below in conjunction with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0036] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or fully authorized by all parties. Moreover, the collection, use, and processing of relevant data need to comply with the relevant laws, regulations, and standards of relevant countries and regions, and corresponding operation entrances are provided for users to select authorization or rejection.

[0037] Figure 1 This is a schematic diagram of the interaction process between the computing system provided by the traditional solution and the CPU and DSA hardware in the computing system. As Figure 1 shown, in the traditional solution, the DSA hardware can be an RCiEP device encapsulated in a system-on-chip (SoC). Alternatively, the DSA hardware can also be an independent peripheral component interconnect express (PCIe) device connected to the system through a PCIe slot. When the DSA hardware executes a computing task, the CPU needs to allocate two memory areas for the DSA hardware. One memory area is used to store the submission queue, and the other memory area is used to store the completion queue. Generally, such queues have a minimum unit, that is, the minimum unit read or written by the DSA hardware. These two queues are a way for the CPU and the DSA hardware to interact with data.

[0038] In practice, the smallest unit in the aforementioned submission queue and completion queue is a hardware descriptor. A hardware descriptor is a data structure defined by the developer of the hardware processing unit, and this data structure is used to describe the information of the data exchanged between the hardware processing unit and a processor (such as a CPU). The recipient of the data (the hardware processing unit or the processor) can read the data from the memory according to the information of the data described by the hardware descriptor.

[0039] Currently, the hardware descriptors designed in the industry are generally 64 bytes. As Figure 2 shown, the hardware descriptors in the submission queue usually include: an Operation Code field, a Source Address field, and a Destination Address field. Among them, the Operation Code field is used to indicate which calculation operation the DSA hardware performs; the Source Address field is used to indicate the location of the original data of this operation in the memory; the Destination Address field is used to indicate the location in the memory where the DSA hardware stores the calculation result, that is, the memory address of the data provided by the DSA to the CPU. The hardware descriptors in the completion queue include: a Status field, a Destination Address field, etc. Among them, the Status field is used to indicate the completion status of the task executed by the DSA hardware, and its value can be completed, failed, or an error occurred, etc. The Destination Address field is used to indicate the location of the calculation result of this operation in the memory, and the CPU can obtain the calculation result from the corresponding memory location according to this Destination Address field.

[0040] As Figure 1 shown, the CPU, the memory, and the DSA hardware are interconnected through an Input / Output (IO) structure (Fabric). Among them, the IO structure is a high-speed interconnect interface connecting different components, mainly used to transfer data between different devices within the system. The IO structure provides a unified platform, enabling different IO devices to communicate through standard interfaces, improving the flexibility and scalability of the system. Figure 1 An exemplary interaction process of the CPU and the DSA coordinating to execute a calculation task is given. As Figure 1 shown, this interaction process mainly includes the following steps:

[0041] 1. According to the calculation request, the CPU fills in the hardware descriptor, writes the hardware descriptor into the submission queue, and writes the original data corresponding to the calculation request into the memory area pre-allocated for the original data, that is, Figure 1 the "first memory area" in

[0042] 2. When the DSA hardware senses that a new task has been written to the submission queue, it reads the new task into the data buffer area (Buffer) inside the DSA hardware according to the minimum unit (i.e., the size of the hardware descriptor).

[0043] Specifically, the Direct Memory Access (DMA) engine in the DSA hardware reads the hardware descriptor into the data buffer area inside the DSA hardware using the DMA method. Among them, the DMA engine is a hardware component specifically designed to achieve data transfer between the kernel and IO devices (such as DSA hardware). By handing over the data transfer task to the DMA engine for processing, the speed and efficiency of data transfer can be significantly improved, and the burden on the CPU can be reduced.

[0044] 3. The DSA hardware parses the read hardware descriptor and extracts the source address and destination address from the hardware descriptor.

[0045] 4. The DSA hardware reads the original data to be calculated from the memory into the data buffer area (Buffer) inside the DSA hardware according to the source address.

[0046] Specifically, the DMA engine in the DSA hardware reads the original data into the data buffer area inside the DSA hardware using the DMA method.

[0047] 5. The DSA hardware calculates the original data according to the operation indicated by the opcode field of the hardware descriptor to obtain the calculation result.

[0048] Specifically, the calculation engine in the DSA hardware calculates the original data according to the operation indicated by the opcode field of the hardware descriptor to obtain the calculation result. The calculation engine refers to a hardware module specifically designed to accelerate specific types of calculation tasks. Such hardware is usually customized to optimize the performance of specific algorithms or application fields.

[0049] 6. The DSA hardware writes the calculation result to the memory area indicated by the destination address, that is Figure 1 the "second memory area" in

[0050] Specifically, the DMA engine in the DSA hardware writes the calculation result to the memory area indicated by the destination address using the DMA method.

[0051] 7. The DSA hardware writes the task execution status and the destination address to the hardware descriptor corresponding to the completion queue, and writes the hardware descriptor to the completion queue in the memory.

[0052] Specifically, the DMA engine in the DSA hardware writes the hardware descriptor to the completion queue in the memory using the DMA method.

[0053] 8. The DSA hardware notifies the CPU that the calculation is completed. The CPU reads the hardware descriptor from the completion queue in the memory and reads the calculation result from the memory according to the destination address recorded in the hardware descriptor.

[0054] Figure 1 Only a brief description is given of the interaction process between the CPU and the DSA hardware when executing a calculation task. Among them, steps 1 and 8 involve the CPU's access operations to the memory, and the CPU needs to perform 4 memory access operations. Steps 2, 4, 6, and 7 all involve the DSA hardware's access operations to the memory, that is, the DSA hardware needs to perform at least 4 memory access operations to execute a calculation task. In the actual process of executing a calculation task, a calculation task is often divided into multiple small subtasks. Each subtask corresponds to a hardware descriptor in the submission queue and a hardware descriptor in the completion queue. Each subtask requires the CPU and the DSA hardware to perform 4 memory access operations each, which requires frequent and large amounts of memory access, consuming a large amount of system resources and affecting the overall performance of the system.

[0055] In order to reduce the number of memory accesses by hardware processing units such as the DSA hardware when executing a calculation task, in some embodiments of the present application, when the data volume of the target data to be exchanged between the hardware processing unit and the processor is less than or equal to the set data volume threshold, according to the field definition of the hardware descriptor, a target hardware descriptor carrying the target data is generated, realizing an elastic change in the field definition of the hardware descriptor. Then, the target hardware descriptor is written into the data queue in the memory. In this way, the receiving party (hardware processing unit or processor) of the target data can read the target hardware descriptor from the memory and directly obtain the target data from the target hardware descriptor. Among them, the receiving party of the target data only needs one memory access operation to obtain the target data, and there is no need to read the target data from other memory areas, which can reduce the number of memory accesses of the receiving party of the target data, thereby reducing the resource consumption of memory access.

[0056] The following will describe in detail the technical solutions provided by the embodiments of the present application with reference to the accompanying drawings.

[0057] It should be noted that the same reference numerals represent the same object or the same step in the following drawings and embodiments. Therefore, once an object or a step is defined in one drawing or embodiment, it does not need to be further discussed in the subsequent drawings and embodiments.

[0058] Figure 3 and Figure 4 is a schematic structural diagram of the computing system provided by the embodiment of the present application. As Figure 3 and Figure 4As shown in the figure, the computing system mainly includes: a processor 10, a hardware processing unit 20, and a memory 30. Among them, the processor 10 and the hardware processing unit 20 are respectively electrically connected to the memory 30. The processor 10 and the hardware processing unit 20 can be electrically connected to the memory 30 through a data bus. The data bus can be a serial interface data bus, such as a Peripheral Component Interconnect (PCI) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) serial interface, an RS485 interface, or an RS232 interface, etc., but not limited thereto. Preferably, the processor 10 and the hardware processing unit 20 are electrically connected to the memory 30 through a PCIe interface, which can improve the data transmission speed between the processor 10 and the hardware processing unit 20 and the memory 30.

[0059] The processor 10 is a general-purpose processor that executes program code according to a predetermined instruction set. A program is composed of a series of machine language instructions that tell the processor how to process data. The processor 10 is generally a Central Processing Unit (CPU). The processor 10 processes data using a computer program, which is generally referred to as software computing.

[0060] The hardware processing unit 20, also known as DSA hardware, refers to a hardware processor that processes data using a Hardware Description Language (HDL). Among them, the hardware description language can be a Very-High-Speed Integrated Circuit Hardware Description Language (VHDL), Verilog HDL, System Verilog, or System C, etc. The hardware processing unit 20 can be a Field-Programmable Gate Array (FPGA), a Programmable Array Logic device (PAL), a General Array Logic device (GAL), a Complex Programmable Logic Device (CPLD), etc.; or, the hardware processing unit 20 can also be an Application Specific Integrated Circuit (ASIC).

[0061] The hardware processing unit 20 is a programmable integrated circuit that allows users to define its functions at the hardware level. The hardware processing unit 20 contains a large number of programmable logic blocks, which can be connected by programming to form complex digital circuits. Therefore, the data processing performed by the hardware processing unit 20 can be called hardware computing, which can achieve hardware acceleration of data processing.

[0062] According to the above Figure 1 In the interaction process between the CPU and the DSA hardware shown, it can be seen that regardless of the scale of the data volume exchanged between the CPU and the DSA hardware in actual operation, even for 1-byte of raw data or calculation results, the CPU core and the DSA hardware each need to perform 4 memory access operations. Frequent and large-scale memory access consumes a large amount of system resources and affects the overall performance of the system.

[0063] According to Figure 2 In the data structure of the hardware descriptor shown, some fields in the hardware descriptor are still unused, such as the optional fields that have not been used yet. Among them, the optional fields refer to other fields in the hardware descriptor other than the necessary basic fields, and these fields can be optionally selected by the user whether to use them. In the embodiments of the present application, the unused fields in the hardware descriptor are defined as target fields, that is, the target fields are the idle fields in the hardware descriptor. Therefore, when the data volume of the target data to be exchanged between the processor 10 and the hardware processing unit 20 is large, the Figure 1 In the manner shown, the data exchange between the processor 10 and the hardware processing unit 20 is realized. Such a hardware descriptor that can dynamically change the definition or meaning of some fields can be called a flexible hardware descriptor. Flexibility means that the definition of some fields of the hardware descriptor is flexibly variable. A flexible hardware descriptor refers to a hardware processing unit 20 such as DSA hardware that dynamically defines the meaning of the fields in the hardware descriptor.

[0064] For example, when the data volume of the target data to be exchanged between the processor 10 and the hardware processing unit 20 is relatively small, the target field in the hardware descriptor is used to store the target data to be exchanged; when the data volume of the target data to be exchanged between the processor 10 and the hardware processing unit 20 is large, the Figure 1 In the manner shown, the data exchange between the processor 10 and the hardware processing unit 20 is realized. At this time, the target field in the hardware descriptor is used to store other data or is left empty, etc. During use, the meaning or definition of the target field of the hardware descriptor is variable. Therefore, such a hardware descriptor can be called a flexible hardware descriptor.

[0065] Based on such a flexible hardware descriptor defined by the hardware processing unit 20, the embodiments of the present application have improved the interaction process between the processor 10 and the hardware processing unit 20. The following will be combined withFigure 3 , Figure 4 and Figure 5 An exemplary description is given of the interaction process between the processor 10 and the hardware processing unit 20 provided in the embodiments of the present application.

[0066] In the embodiments of the present application, for the convenience of description and distinction, the data to be exchanged between the hardware processing unit 20 and the processor 10 is defined as target data. Among them, the target data can be the data that the hardware processing unit 20 needs to read from the memory, or the data that the hardware processing unit 20 needs to write into the memory.

[0067] In the embodiments of the present application, as Figure 3 and Figure 4 shown, the memory 30 stores a data queue for storing hardware descriptors. The hardware descriptor is the basic unit (also called the minimum unit) of the data queue. The hardware processing unit 20 can read data from the data queue in units of hardware descriptors, or write data to the data queue in units of hardware descriptors. In some embodiments, if the target data is the data that the hardware processing unit 20 needs to read from the memory, the recipient of the target data is the hardware processing unit 20, and the data queue is the submission queue described above. Figure 2 In other embodiments, if the target data is the data that the hardware processing unit 20 needs to write into the memory, the recipient of the target data is the processor 10, and the data queue is the completion queue described above. Figure 2 In the embodiments of the present application, for the convenience of description and distinction, the data queue (i.e., the submission queue) used when the hardware processing unit 20 needs to read data from the memory is defined as the first data queue; the data queue (i.e., the completion queue) used when the hardware processing unit 20 needs to write data to the memory is defined as the second data queue. Among them, as Figure 3 shown, the hardware descriptor in the first data queue is a data structure that describes the information of the data obtained by the hardware processing unit from the processor. As Figure 4 shown, the hardware descriptor in the second data queue is a data structure that describes the information of the data provided by the hardware processing unit to the processor.

[0068] In the embodiments of the present application, the data that the hardware processing unit 20 needs to read from the memory and the data that the hardware processing unit 20 needs to write into the memory are collectively referred to as the target data to be exchanged between the hardware processing unit 20 and the processor 10.

[0069] Based on the elastic hardware descriptor proposed in the embodiments of the present application, that is, a hardware descriptor with a definition of elastic variability of unused fields. In the embodiments of the present application, as Figure 3 and Figure 4As shown in Step 1, when the amount of target data to be exchanged between the hardware processing unit 20 and the processor 10 is less than or equal to a set data volume threshold, a target hardware descriptor carrying the target data can be generated according to the field definition of the hardware descriptor. The data volume threshold can be determined by the total length of the hardware descriptor, the length of the basic fields in the hardware descriptor, and the operation code. Specifically, the data volume threshold is less than or equal to the data volume defined by the operation code in the hardware descriptor and less than or equal to the data length A obtained by subtracting the length of the basic fields from the total length of the hardware descriptor. For example, the data volume value can be the minimum of the data volume defined by the operation code and the data length A.

[0070] As Figure 2 shown, for the hardware descriptors in the first data queue (i.e., the submission queue), its basic fields include: an operation code field, a source address field, and a destination address field. For the hardware descriptors in the second data queue (i.e., the completion queue), its basic fields include: a destination address field and a task status field.

[0071] Specifically, when the amount of target data to be exchanged between the hardware processing unit 20 and the processor 10 is less than or equal to the set data volume threshold, the processor 10 or the hardware processing unit 20 can write the target data into the unused fields (such as the target fields) of the hardware descriptor according to the field definition of the hardware descriptor to obtain a target hardware descriptor carrying the target data.

[0072] Of course, the processor 10 or the hardware processing unit 20 can also determine the values of other fields of the hardware descriptor and write the values of other fields of the hardware descriptor into the corresponding fields according to the field definition of the hardware descriptor, thereby obtaining a target hardware descriptor carrying the target data.

[0073] Further, as Figure 3 and Figure 4 shown in Step 2, the processor 10 or the hardware processing unit 20 can write the target hardware descriptor into the data queue. In this way, as Figure 3 and Figure 4 shown in Step 3 and Step 4, the recipient of the target data can read the target hardware descriptor from the data queue and directly obtain the target data from the target hardware descriptor. That is, the recipient of the target data only needs one memory access operation to obtain the target data, without having to read the target data from other memory areas, which can reduce the number of memory accesses of the recipient of the target data, thereby reducing the resource consumption of memory access.

[0074] On the other hand, the processor 10 or the hardware processing unit 20 only needs to write the target data into the target hardware descriptor and store it in the memory, without having to store the target data in other areas of the memory, which can also save memory resources.

[0075] Of course, if the amount of target data is greater than the set data volume threshold, the processor 10 or the hardware processing unit 20 can write the target data to the corresponding target memory area in the memory. Among them, the target memory area is the memory area allocated by the processor 10 for the target data. In this way, the recipient of the target data can obtain the target data from the target memory area.

[0076] Next, from the perspective that the target data is the original data corresponding to the calculation request that the hardware processing unit 20 needs to read from the memory 30, and the target data is the calculation result corresponding to the calculation request that the hardware processing unit 20 needs to write to the memory 30, an exemplary description of the process of data exchange between the processor 10 and the hardware processing unit 20 based on the flexible hardware descriptor will be given.

[0077] In some embodiments, as Figure 3 and Figure 5 shown, the target data is the data that the hardware processing unit 20 needs to read from the memory 30. The target data can be the original data corresponding to the calculation request, that is, the original data requested to be calculated by the calculation request. For the convenience of description and distinction, the calculation request currently processed by the processor 10 is defined as the target calculation request, and the original data corresponding to the target calculation request is defined as the target original data. In this embodiment, the data queue includes the aforementioned first data queue (i.e., the submission queue). The hardware descriptor in the first data queue is a data structure that describes the information of the data obtained by the hardware processing unit 20 from the processor 10. The recipient of the target data is the hardware processing unit 20.

[0078] In this embodiment, the processor 10 generates the target hardware descriptor. Specifically, as Figure 3 and Figure 5 shown in step 1, when the amount of the target original data is less than or equal to the set data volume threshold, the processor 10 can generate a hardware descriptor carrying the target original data according to the field definition of the hardware descriptor in the first data queue, and this hardware descriptor is the target hardware descriptor.

[0079] Specifically, the processor 10 can respond to the target calculation request, obtain the target original data corresponding to the target calculation request as the target data; and determine whether the amount of the target original data is less than or equal to the set data volume threshold; if the determination result is yes, then generate a hardware descriptor carrying the target original data according to the field definition of the hardware descriptor in the first data queue, and this hardware descriptor is the target hardware descriptor.

[0080] Specifically, according to Figure 2From the basic structure of the hardware descriptors in the first data queue (i.e., the submission queue) shown, the hardware descriptors in the first data queue include: a source address field and a target field. Among them, the source address field is used to record the memory address information of the original data corresponding to the computation request; while the target field is an unused field in the hardware descriptors in the first data queue and can be autonomously defined by the hardware processing unit. Based on this, when the processor 10 generates a hardware descriptor carrying the target original data, it can, according to the field definition of the hardware descriptors in the first data queue, write invalid memory address information into the source address field of the hardware descriptor and write the target original data into the target field of the hardware descriptor to obtain a hardware descriptor carrying the target original data, that is, the target hardware descriptor.

[0081] Among them, the invalid memory address information can be pre-set memory address information, which does not belong to normal memory address information, such as 0x7f7f7f7f7f7f7f7f, etc. In this way, the hardware processing unit 20 can judge whether to directly obtain the target original data to be computed from this hardware descriptor or read the target original data from the target memory area in the memory according to whether the memory address information stored in the source address field of the hardware descriptor read from the first data queue is invalid memory address information.

[0082] Alternatively, a flag bit can be set in the target field. This flag bit can identify whether the target hardware descriptor carries the target original data. Based on this, when the data volume of the target original data is less than or equal to the set data volume threshold, the processor 10 can, according to the field definition of the hardware descriptors in the first data queue, set the flag bit in the target hardware descriptor to the first identifier indicating that the target hardware descriptor carries the target original data and write the target original data into the target field of the hardware descriptor to obtain a hardware descriptor carrying the target original data, that is, the target hardware descriptor. In this way, the hardware processing unit 20 can judge whether to directly obtain the target original data to be computed from this hardware descriptor or read the target original data from the target memory area in the memory according to whether the flag bit of the hardware descriptor read from the first data queue is the first identifier. When the data volume of the target original data is greater than the set data volume threshold, according to the field definition of the hardware descriptors in the first data queue, the flag bit in the target hardware descriptor is set to the second identifier indicating that the target hardware descriptor does not carry the target original data. For example, the first identifier can be binary "1" and the second identifier can be binary "0", etc.

[0083] Furthermore, as Figure 5 shown in step 2, the processor 10 can write the target hardware descriptor into the first data queue. Correspondingly, as Figure 5As shown in step 3, the hardware processing unit 20 can read the target hardware descriptor from the first data queue. Specifically, as Figure 5 shown, the DMA engine in the hardware processing unit 20 can read the target hardware descriptor from the first data queue in the DMA mode, such as reading the target hardware descriptor from the first data queue to the cache in the hardware processing unit 20 in the DMA mode.

[0084] In some embodiments, the processor 10 can maintain a write pointer corresponding to the first data queue; when the target hardware descriptor is written into the first data queue, the processor 10 can increment the write pointer by 1 and notify the hardware processing unit 20 that a new hardware descriptor has been written into the first data queue. The hardware processing unit 20 can determine that a new hardware descriptor has been written into the first data queue in response to this notification. Further, when the hardware processing unit 20 senses that a new hardware descriptor has been written into the first data queue, it can use the DMA engine to read the target hardware descriptor from the first data queue in the DMA mode.

[0085] Further, the hardware processing unit 20 can obtain the memory address information stored in the source address field from the target hardware descriptor. Further, if the memory address information stored in the source address field is invalid memory address information, then as Figure 5 shown in step 4, the hardware processing unit 20 obtains the target original data from the target hardware descriptor. Specifically, the DMA engine in the hardware processing unit 20 can obtain the target original data from the target hardware descriptor.

[0086] Specifically, the hardware processing unit 20 can parse the target hardware descriptor to obtain the memory address information stored in the source address field of the target hardware descriptor; and determine whether the memory address information stored in the source address field of the target hardware descriptor is the set invalid memory address information; if the judgment result is yes, the hardware processing unit 20 obtains the target original data from the target hardware descriptor. Specifically, the hardware processing unit 20 can obtain the target original data from the target field of the target hardware descriptor. Or, the hardware processing unit 20 can parse the target hardware descriptor to obtain the value of the flag bit; and if the value of the flag bit is the first identifier, the hardware processing unit 20 can also obtain the target original data from the target field of the target hardware descriptor.

[0087] Through the above method, when the data volume of the target original data is less than or equal to the set data volume threshold, the hardware processing unit 20 only needs to read the target hardware descriptor from the first data queue in the memory, and can directly obtain the target original data from the target hardware descriptor, without having to read the target original data from the memory according to the memory address information stored in the source address field, which can reduce the memory access times of the hardware processing unit and reduce the resource consumption of memory access.

[0088] On the other hand, when the data volume of the target original data is less than or equal to the set data volume threshold, the processor only needs to write the target hardware descriptor into the first data queue in the memory, without separately allocating a memory space for the target original data, which can save memory resources. The processor also does not need to write the target original data into a separate memory space, which can also reduce the number of times the processor accesses the memory and reduce the resource consumption of memory access.

[0089] Further, as Figure 5 shown in step 5, after the hardware processing unit 20 obtains the target original data from the target hardware descriptor, it can calculate the target original data to obtain a target calculation result. In the embodiments of the present application, the specific implementation manner of the target original data is not limited. In some embodiments, as Figure 2 shown, the hardware descriptor in the first data queue further includes: an opcode field for recording the opcode corresponding to the calculation request, and the opcode is used to indicate which calculation operation the hardware processing unit executes. Correspondingly, when the processor 10 generates a hardware descriptor carrying the target original data, it can also determine the target opcode corresponding to the target calculation request in response to the target calculation request. Specifically, the processor 10 can parse the target calculation request to determine the calculation method of the target calculation request (defined as the target calculation method); and determine the target opcode corresponding to the target calculation request according to the target calculation method. In the embodiments of the present application, the specific content of the calculation method is not limited. For example, the calculation method can be hash calculation, key exchange, or key generation, etc. The opcode corresponding to the calculation method is defined by the manufacturer of the hardware processing unit and is pre-configured in the processor and the hardware processing unit. The processor 10 can obtain the opcode corresponding to the target calculation method as the target opcode from the pre-configured correspondence between the calculation method and the opcode.

[0090] Further, the processor 10 can write the target opcode into the opcode field of the target hardware descriptor. Correspondingly, the hardware processing unit 20 can obtain the target opcode from the opcode field of the target hardware descriptor; and calculate the target original data according to the calculation method corresponding to the target opcode to obtain a target calculation result. Specifically, as Figure 5 shown, the calculation engine in the hardware processing unit can obtain the target opcode from the opcode field of the target hardware descriptor; and calculate the target original data according to the calculation method corresponding to the target opcode to obtain a target calculation result.

[0091] To further reduce the number of memory accesses, as Figure 5As shown in step 5, for the target calculation result, the hardware processing unit 20 may also carry the target calculation result in the hardware descriptor when the target calculation result is less than or equal to the set data volume threshold. In the embodiments of the present application, for the convenience of description and distinction, the data volume threshold used when determining whether the target data (such as the target original data) read by the hardware processing unit from the memory needs to be carried in the hardware descriptor is defined as the first data volume threshold; and the data volume threshold used when determining whether the data (such as the target calculation result) written by the hardware descriptor to the memory needs to be carried in the hardware descriptor is defined as the second data volume threshold. Among them, the first data volume threshold and the second data volume threshold may be the same or different. Among them, the first data volume threshold is specifically determined by the total length of the hardware descriptors in the first data queue (i.e., the submission queue), the length of the basic fields in the hardware descriptor, and the operation code in the hardware descriptor. The first data volume threshold may be less than or equal to the maximum data volume that can be calculated by the operation code in the hardware descriptor in the first data queue, and less than or equal to the data length B obtained by subtracting the length of the basic fields from the total length of the hardware descriptor. For example, the first data volume threshold may be the minimum value of the obtained data length B and the maximum data volume that can be calculated by the operation code in the hardware descriptor.

[0092] The second data volume threshold is specifically determined by the total length of the hardware descriptors in the second data queue (i.e., the completion queue), the length of the basic fields in the hardware descriptor, and the operation code in the target hardware descriptor read from the first data queue. The first data volume threshold may be less than or equal to the length Y of the calculation result corresponding to the operation code in the target hardware descriptor in the first data queue, and less than or equal to the data length C obtained by subtracting the length of the basic fields of the hardware descriptor in the second data queue from the total length of the hardware descriptor in the second data queue. For example, the second data volume threshold may be the minimum value of the data length C and the length Y of the calculation result corresponding to the operation code in the target hardware descriptor in the first data queue, that is, the second data volume threshold may be equal to the minimum value of C and Y.

[0093] Specifically, when the data volume of the target calculation result is less than or equal to the set second data volume threshold, the hardware processing unit 20 may generate a hardware descriptor carrying the target calculation result according to the field definition of the hardware descriptor in the second data queue. In the embodiments of the present application, for the convenience of description and distinction, the hardware descriptor carrying the target original data generated by the foregoing processor 10 is defined as the first hardware descriptor; and the hardware descriptor carrying the target calculation result generated by the hardware processing unit 20 is defined as the second hardware descriptor.

[0094] Specifically, when the data volume of the target calculation result is less than or equal to the set second data volume threshold, the hardware processing unit 20 may write the target calculation result into the target field of the second hardware descriptor according to the field definition of the hardware descriptor in the second data queue, so as to obtain a hardware descriptor carrying the target calculation result, that is, the second hardware descriptor.

[0095] In the embodiments of the present application, the specific implementation manner for the hardware processing unit 20 to determine whether the data volume of the target calculation result is less than or equal to the set second data volume threshold is not limited. In some embodiments, the hardware processing unit 20 may count the data volume of the target calculation result and determine whether the data volume of the target calculation result is less than or equal to the set second data volume threshold.

[0096] In other embodiments, since the lengths of the calculation results of some calculation tasks are fixed. For example, the hash algorithm can convert a series of data into a value with a fixed length. Another example is that in the key generation algorithm, the length of the generated key is fixed, and so on. Based on this, the processor 10 may determine the data volume of the target calculation result, that is, the length of the target calculation result, according to the calculation method corresponding to the target calculation request. Further, if the data volume of the target calculation result is less than or equal to the set second data volume threshold, when the processor 10 generates the first hardware descriptor carrying the target original data, it may write invalid memory address information into the destination address field of the first hardware descriptor. Among them, the invalid memory address information written into the destination address field of the first hardware descriptor may be the same as or different from the invalid memory address information written into the source address field of the first hardware descriptor. For the convenience of description and distinction, the invalid memory address information written into the source address field of the first hardware descriptor is defined as invalid first memory address information, and the invalid memory address information written into the destination address field of the first hardware descriptor is defined as invalid second memory address information. Among them, the first memory address information and the second memory address information may be the same or different.

[0097] Correspondingly, the hardware processing unit 20 may obtain the memory address information stored in the destination address field from the first hardware descriptor; and when the memory address information stored in the destination address field obtained from the first hardware descriptor is invalid second memory address information, determine that the data volume of the target calculation result is less than or equal to the second data volume threshold, and generate a hardware descriptor carrying the target calculation result according to the field definition of the hardware descriptor in the second data queue.

[0098] Further, as Figure 5As shown in step 6, the hardware processing unit 20 may write the second hardware descriptor into the second data queue. In this embodiment, when the data volume of the target calculation result is less than or equal to the set second data volume threshold, the hardware processing unit carries the target calculation result in the second hardware descriptor and writes it into the second data queue in the memory, without writing the target calculation result into another separate memory area. This can reduce the number of times the hardware processing unit writes data to the memory, that is, reduce the memory access times of the hardware processing unit, thereby reducing the resource consumption of memory access. In addition, since the hardware processing unit does not need to write the target calculation result into a separate memory area, there is no need to allocate another separate memory space for the target calculation result, which can save memory resources.

[0099] Correspondingly, as Figure 5 shown in steps 7 and 8, the processor 10 may read the second hardware descriptor from the second data queue and obtain the target calculation result from the second hardware descriptor. The processor only needs to read the second hardware descriptor from the memory to directly obtain the target calculation result from the second hardware descriptor, without reading the memory separately to obtain the target calculation result, which can reduce the memory access times of the processor, thereby reducing the resource consumption of memory access.

[0100] In the embodiment of the present application, in order to enable the processor 10 to perceive whether it obtains the target calculation result from the second hardware descriptor or reads the target calculation result from the corresponding area of the memory, when generating the second hardware descriptor carrying the target calculation result, the hardware processing unit 20 may also write invalid second memory address information into the destination address field of the second hardware descriptor. The destination address field of the second hardware descriptor is used to record the memory address information of the data provided by the hardware processing unit to the processor.

[0101] Accordingly, the processor 10 can read the second hardware descriptor from the second data queue. In some embodiments, the processor 10 can periodically query whether there is a new hardware operator written to the second data queue according to a set query period; if it is queried that there is a new hardware operator written, the processor 10 can obtain the newly written hardware operator in the current query period from the second data queue; then, obtain the memory address information stored in the destination address field from the read hardware operator; and in the case where the memory address information is the invalid second memory address information, obtain the target calculation result from the hardware operator. Similarly, if the hardware operator read from the second data queue is the second hardware operator, the memory address information stored in the destination address field can be obtained from the second hardware descriptor; and in the case where the memory address information stored in the destination address field of the second hardware descriptor is the invalid second memory address information, obtain the target calculation result from the second hardware descriptor. Among them, when the target calculation result is less than or equal to the second data volume threshold, the destination address field of the second hardware descriptor writes the invalid second memory address information. The processor 10 can determine where to obtain the target calculation result according to the value of the destination address field, providing guidance information for the processor on where to obtain the target calculation result.

[0102] The data provided by the hardware processing unit shown in the foregoing embodiments to the processor is the calculation result corresponding to the calculation request of the processor. Of course, the data provided by the hardware processing unit to the processor can also be other data, which is not associated with the calculation request obtained by the processor. The following combines the above Figure 4 An exemplary description is given of the process of the hardware processing unit providing data to the processor.

[0103] In Figure 4 , the target data is the data provided by the hardware processing unit to the processor, and the recipient of the target data is the processor 10. In the embodiments of the present application, the hardware processing unit 20 can be the calculation result corresponding to the foregoing calculation request, or can also be other data, such as data received from other devices, etc. Accordingly, when the data volume of the target data is less than or equal to the set second data volume threshold, the hardware processing unit 20 can generate a hardware descriptor (defined as the third hardware descriptor) carrying the target data according to the field definition of the hardware descriptor in the second data queue. The third hardware descriptor is the target hardware descriptor in this embodiment.

[0104] Specifically, when the data volume of the target data is less than or equal to the set second data volume threshold, the hardware processing unit 20 can write the target data into the target field of the second hardware descriptor according to the field definition of the hardware descriptor in the second data queue to obtain the third hardware descriptor carrying the target data.

[0105] Further, the hardware processing unit 20 may write the third hardware descriptor into the second data queue. In this embodiment, when the data volume of the target data is less than or equal to the set second data volume threshold, the hardware processing unit carries the target calculation result in the third hardware descriptor and writes it into the second data queue in the memory, without the need to write the target data into another separate memory area, which can reduce the number of times the hardware processing unit writes data to the memory, that is, reduce the memory access times of the hardware processing unit, thereby reducing the resource consumption of memory access. In addition, since the hardware processing unit no longer needs to write the target data into a separate memory area, there is no need to allocate another separate memory space for the target data, which can save memory resources.

[0106] Correspondingly, the processor 10 may read the third hardware descriptor from the second data queue and obtain the target data from the third hardware descriptor. The processor only needs to read the third hardware descriptor from the memory and can directly obtain the target data from the third hardware descriptor, without the need to read the memory separately to obtain the target data, which can reduce the memory access times of the processor, thereby reducing the resource consumption of memory access.

[0107] In the embodiment of the present application, in order to enable the processor 10 to perceive whether it obtains the target calculation result from the third hardware descriptor or reads the target data from the corresponding area of the memory, when generating the third hardware descriptor carrying the target calculation result, the hardware processing unit 20 may also write invalid second memory address information into the destination address field of the third hardware descriptor.

[0108] Correspondingly, the processor 10 may read the third hardware descriptor from the second data queue and obtain the memory address information stored in the destination address field from the third hardware descriptor; and when the memory address information stored in the destination address field of the third hardware descriptor is invalid second memory address information, obtain the target data from the third hardware descriptor. Among them, the destination address field of the second hardware descriptor writes invalid second memory address information when the target calculation result is less than or equal to the second data volume threshold. The processor 10 can determine where to obtain the target calculation result according to the value of the destination address field, providing guidance information for the processor on where to obtain the target data.

[0109] To facilitate understanding of the interaction process between the hardware processing unit and the processor provided in the embodiment of the present application, the following will be specifically described in conjunction with Figure 6 the specific embodiments shown. As Figure 6 shown, the interaction process between the hardware processing unit and the processor provided in the embodiment of the present application mainly includes the following steps:

[0110] Step 1: In response to a target computing request, the processor 10 obtains target original data corresponding to the target computing request, determines the target computing method of the target computing request; and determines the target operation code corresponding to the target computing request according to the target computing method.

[0111] Step 2: Write the target operation code into the operation code field of the first hardware descriptor.

[0112] Step 3: The processor 10 determines whether the data volume Q1 of the target original data is less than or equal to a set first data volume threshold Q0; and determines whether the data volume P1 of the calculation result corresponding to the target computing method is less than or equal to a set second data volume threshold P0. If the judgment result is: Q1 ≤ Q0 and P1 ≤ P0, then execute Steps 4-6 and then execute Step 9; if the judgment result is: Q1 ≤ Q0 and P1 > P0, then execute Steps 4-5 and Step 8 and then execute Step 9; if the judgment result is: Q1 > Q0 and P1 ≤ P0, then execute Step 7 and 6 and then execute Step 9; if the judgment result is Q1 > Q0 and P1 > P0, then execute Step 7 and 8 and then execute Step 9.

[0113] Step 4: Write the target original data into the target field of the first hardware operator.

[0114] Step 5: Write invalid first memory address information into the source address field of the first hardware descriptor.

[0115] Step 6: Write invalid second memory address information into the destination address field of the first hardware descriptor.

[0116] Step 7: The processor 10 allocates a first target memory area for the target original data, writes the target original data into the first target memory area, and writes the memory address information of the first target memory area into the source address field of the first hardware descriptor.

[0117] Step 8: The processor 10 allocates a second target memory area for the target calculation result and writes the memory address information of the second target memory area into the destination address field of the first hardware descriptor.

[0118] Step 9: The processor 10 writes the first hardware descriptor into the first data queue.

[0119] Step 10: The hardware processing unit 20 senses that a new hardware descriptor is written into the first data queue, and uses the DMA engine to read the first hardware descriptor from the first data queue into the cache area in the hardware processing unit.

[0120] Step 11: The hardware processing unit 20 parses the first hardware descriptor to obtain the memory address information stored in the source address field of the first hardware descriptor, the target operation code stored in the operation code field, and the memory address information stored in the destination address field.

[0121] Step 12: The hardware processing unit 20 determines whether the memory address information stored in the source address field of the first hardware descriptor is invalid first memory address information; if so, it executes Step 13; if not, it executes Step 14.

[0122] Step 13: Obtain the target original data from the first hardware descriptor, and then execute Step 15.

[0123] Step 14: Use the DMA engine to read the target original data from the memory area indicated by the memory address information stored in the source address field of the first hardware descriptor, store it in the cache area within the hardware processing unit, and then execute Step 15.

[0124] Step 15: Use the computing engine in the hardware processing unit 20 to calculate the target original data according to the target calculation method corresponding to the target operation code to obtain the target calculation result.

[0125] Step 16: The hardware processing unit 20 determines whether the memory address information stored in the destination address field of the first hardware descriptor is invalid second memory address information. If so, it executes Step 17, if not, it executes Step 18.

[0126] Step 17: The hardware processing unit 20 writes the target calculation result into the target field of the second hardware descriptor according to the field definition of the hardware descriptor in the second data queue; and writes the invalid second memory address information into the destination address field of the second hardware descriptor.

[0127] Step 18: The DMA engine in the hardware processing unit 20 writes the target calculation result into the second target memory area indicated by the memory address information stored in the destination address field of the first hardware descriptor, and writes the memory address information of the second target memory area into the destination address field of the second hardware descriptor.

[0128] Step 19: The DMA engine in the hardware processing unit 20 writes the second hardware descriptor into the second data queue.

[0129] Step 20: The processor 10 reads the second hardware descriptor from the second data queue.

[0130] Step 21: The processor 10 obtains the memory address information stored in the destination address field of the second hardware descriptor from the second hardware descriptor; and determines whether the memory address information stored in the destination address field of the second hardware descriptor is invalid second memory address information; if the determination result is yes, then execute Step 22; if the determination result is no, then execute Step 23.

[0131] Step 22: Obtain the target calculation result from the second hardware descriptor.

[0132] Step 23: Read the target calculation result from the memory area indicated by the memory address information stored in the destination address field of the second hardware descriptor.

[0133] According to Figure 6 the interaction process between the hardware processing unit and the processor shown, when the data volumes of the original data and the calculation result corresponding to the calculation request are both small (less than or equal to the corresponding data volume thresholds), the processor performs 2 memory accesses (one is to write the first hardware descriptor to the first data queue in the memory, and the other is to read the second hardware descriptor from the second data queue in the memory), and the hardware processing unit performs 2 memory accesses (one is to read the first hardware descriptor from the first data queue in the memory, and the other is to write the second hardware descriptor to the second data queue in the memory). Compared with Figure 1 the interaction process between the hardware processing unit and the processor shown, both the processor and the hardware processing unit reduce 2 memory access operations, which helps to reduce the resource consumption of memory access. Especially for the hardware processing unit, it reduces at most 2 DMA operations, which greatly improves the performance of the hardware using this hardware, and theoretically can achieve a performance improvement of about 50%.

[0134] The implementation of the execution logic of the hardware processing unit is to connect logic blocks through a hardware programming language to form a digital circuit. Therefore, the execution logic of the hardware processing unit provided in the embodiments of the present application can provide guidance for the hardware design of the hardware processing unit and realize the optimization of the hardware processing unit.

[0135] In addition to the computing system provided in the foregoing embodiments, the embodiments of the present application also provide a data processing method. The data processing method provided in the embodiments of the present application will be exemplarily described below from the perspectives of the processor and the hardware processing unit respectively.

[0136] Figure 7 is a schematic flowchart of the data processing method provided in the embodiments of the present application. This method is applicable to a processor or a hardware processing unit. As Figure 7 shown, this data processing method mainly includes the following steps:

[0137] 701. When the data volume of the target data to be exchanged between the hardware processing unit and the processor is less than or equal to the set data volume threshold, a target hardware descriptor carrying the target data is generated according to the field definition of the hardware descriptor.

[0138] 702. Write the target hardware descriptor into the data queue for the recipient of the target data to read the target hardware descriptor from the data queue and obtain the target data from the target hardware descriptor.

[0139] Figure 8 It is a schematic flowchart of another data processing method provided by an embodiment of the present application. This method is applicable to a hardware processing unit or a processor. As Figure 8 shown, this data processing method mainly includes the following steps:

[0140] 801. Read a target hardware descriptor from the data queue; the target hardware descriptor is a hardware descriptor carrying the target data generated by the provider of the target data according to the field definition of the hardware descriptor when the data volume of the target data to be exchanged between the hardware processing unit and the processor is less than or equal to the set data volume threshold.

[0141] 802. Obtain the target data from the target hardware descriptor.

[0142] In this embodiment, the processor and the hardware processing unit are respectively electrically connected to the memory; the memory stores a data queue for storing hardware descriptors; the hardware descriptor is a data structure describing the information of the data exchanged between the hardware processing unit and the processor.

[0143] It should be noted that when the Figure 7 shown data processing method is executed by the processor, Figure 8 the shown data processing method corresponds to being executed by the hardware processing unit. Correspondingly, when the Figure 7 shown data processing method is executed by the hardware processing unit, Figure 8 the shown data processing method corresponds to being executed by the processor.

[0144] Define the data to be exchanged between the hardware processing unit and the processor as target data. Among them, the target data can be the data that the hardware processing unit needs to read from the memory or the data that the hardware processing unit needs to write into the memory.

[0145] Based on the elastic hardware descriptor proposed in the embodiment of the present application, that is, a hardware descriptor with a flexible definition of unused fields. In the embodiment of the present application, in step 701, when the data volume of the target data to be exchanged between the hardware processing unit and the processor is less than or equal to the set data volume threshold, a target hardware descriptor carrying the target data can be generated according to the field definition of the hardware descriptor.

[0146] Specifically, when the amount of the target data to be exchanged between the hardware processing unit and the processor is less than or equal to the set data amount threshold, according to the field definition of the hardware descriptor, the target data is written into the unused field (such as the target field) of the hardware descriptor to obtain a target hardware descriptor carrying the target data.

[0147] Of course, the values of other fields of the hardware descriptor can also be determined, and according to the field definition of the hardware descriptor, the values of other fields of the hardware descriptor are written into the corresponding fields, so as to obtain a target hardware descriptor carrying the target data.

[0148] Further, in step 702, the target hardware descriptor can be written into the data queue. In this way, for the receiver of the target data, in step 801, the target hardware descriptor can be read from the data queue, and in step 802, the target data can be directly obtained from the target hardware descriptor. That is, the receiver of the target data only needs one memory access operation to obtain the target data, without having to read the target data from other memory areas, which can reduce the number of memory accesses of the receiver of the target data, thereby reducing the resource consumption of memory access.

[0149] On the other hand, the processor or the hardware processing only needs to write the target data into the target hardware descriptor and store it in the memory, without having to store the target data in other areas of the memory, which can also save memory resources.

[0150] Of course, if the amount of the target data is greater than the set data amount threshold, the target data can be written into the corresponding target memory area in the memory. Wherein, the target memory area is the memory area allocated by the processor for the target data. In this way, the receiver of the target data can obtain the target data from the target memory area.

[0151] In some embodiments, the target data is the data that the hardware processing unit needs to read from the memory. The target data can be the original data corresponding to the calculation request, that is, the original data to be calculated by the calculation request. For the convenience of description and distinction, the processor and the currently processed calculation request are defined as the target calculation request, and the original data corresponding to the target calculation request is defined as the target original data. In this embodiment, the data queue includes the aforementioned first data queue (i.e., the submission queue). The receiver of the target data is the hardware processing unit.

[0152] In this embodiment, the target hardware descriptor is generated by the processor. Specifically, when the amount of the target original data is less than or equal to the set data amount threshold, according to the field definition of the hardware descriptor in the first data queue, a hardware descriptor carrying the target original data is generated, and this hardware descriptor is the target hardware descriptor.

[0153] Specifically, in response to a target computing request, the target original data corresponding to the target computing request may be obtained as the target data; and it is determined whether the data volume of the target original data is less than or equal to a set data volume threshold; if the determination result is yes, a hardware descriptor carrying the target original data is generated according to the field definition of the hardware descriptor in the first data queue, and this hardware descriptor is the target hardware descriptor.

[0154] Specifically, the hardware descriptor in the first data queue includes: a source address field and a target field. Among them, the source address field is used to record the memory address information of the original data corresponding to the computing request; and the target field is an unused field (i.e., a free field) in the hardware descriptor in the first data queue, which can be independently defined by the hardware processing unit. Based on this, when generating a hardware descriptor carrying the target original data, according to the field definition of the hardware descriptor in the first data queue, invalid memory address information may be written into the source address field of the hardware descriptor, and the target original data is written into the target field of the hardware descriptor to obtain a hardware descriptor carrying the target original data, that is, the target hardware descriptor.

[0155] Among them, the invalid memory address information may be pre-set memory address information, and this memory address information does not belong to normal memory address information. In this way, the hardware processing unit can determine whether to directly obtain the target original data to be calculated from the hardware descriptor according to whether the memory address information stored in the source address field of the hardware descriptor read from the first data queue is invalid memory address information; or read the target original data from the target memory area in the memory.

[0156] Further, the target hardware descriptor may be written into the first data queue. Correspondingly, the hardware processing unit can read the target hardware descriptor from the first data queue. Specifically, the DMA method may be used to read the target hardware descriptor from the first data queue, such as using the DMA method to read the target hardware descriptor from the first data queue into the cache in the hardware processing unit.

[0157] Further, the hardware processing unit can obtain the memory address information stored in the source address field from the target hardware descriptor. Further, if the memory address information stored in the source address field is invalid memory address information, the hardware processing unit obtains the target original data from the target hardware descriptor.

[0158] Specifically, the target hardware descriptor can be parsed to obtain the memory address information stored in the source address field of the target hardware descriptor; and it is determined whether the memory address information stored in the source address field of the target hardware descriptor is the set invalid memory address information; if the determination result is yes, the hardware processing unit obtains the target original data from the target hardware descriptor. Specifically, the hardware processing unit can obtain the target original data from the target field of the target hardware descriptor. In this way, when the data volume of the target original data is less than or equal to the set data volume threshold, the hardware processing unit only needs to read the target hardware descriptor from the first data queue in the memory, and can directly obtain the target original data from the target hardware descriptor, without having to read the target original data from the memory according to the memory address information stored in the source address field, which can reduce the number of memory accesses of the hardware processing unit and reduce the resource consumption of memory access.

[0159] On the other hand, when the data volume of the target original data is less than or equal to the set data volume threshold, the processor only needs to write the target hardware descriptor into the first data queue in the memory, without having to allocate a separate memory space for the target original data, which can save memory resources. The processor also needs to write the target original data into a separate memory space, which can also reduce the number of memory accesses of the processor and reduce the resource consumption of memory access.

[0160] After the hardware processing unit obtains the target original data from the target hardware descriptor, it can calculate the target original data to obtain the target calculation result. In the embodiments of the present application, the specific implementation manner of the target original data is not limited. In some embodiments, the hardware descriptor in the first data queue further includes: an opcode field for recording the opcode corresponding to the calculation request, and the opcode is used to indicate which calculation operation the hardware processing unit performs. Correspondingly, when generating the hardware descriptor carrying the target original data, the processor can also determine the target opcode corresponding to the target calculation request in response to the target calculation request. Further, the target opcode can be written into the opcode field of the target hardware descriptor.

[0161] Correspondingly, the hardware processing unit can obtain the target opcode from the opcode field of the target hardware descriptor; and calculate the target original data according to the calculation method corresponding to the target opcode to obtain the target calculation result. Specifically, the calculation engine in the hardware processing unit can obtain the target opcode from the opcode field of the target hardware descriptor; and calculate the target original data according to the calculation method corresponding to the target opcode to obtain the target calculation result.

[0162] To further reduce the number of memory accesses, for the target calculation result, the hardware processing unit may also carry the target calculation result in the hardware descriptor when the target calculation result is less than or equal to the set data volume threshold. In the embodiments of the present application, for the convenience of description and distinction, the data volume threshold used when determining whether the target data (such as the target original data) read by the hardware processing unit from the memory needs to be carried in the hardware descriptor is defined as the first data volume threshold; and the data volume threshold used when determining whether the data written by the hardware descriptor to the memory (such as the target calculation result) needs to be carried in the hardware descriptor is defined as the second data volume threshold.

[0163] Specifically, when the data volume of the target calculation result is less than or equal to the set second data volume threshold, the hardware processing unit may generate a hardware descriptor carrying the target calculation result according to the field definition of the hardware descriptor in the second data queue. In the embodiments of the present application, for the convenience of description and distinction, the hardware descriptor carrying the target original data generated by the foregoing processor is defined as the first hardware descriptor; and the hardware descriptor carrying the target calculation result generated by the hardware processing unit is defined as the second hardware descriptor.

[0164] Specifically, when the data volume of the target calculation result is less than or equal to the set second data volume threshold, the hardware processing unit may write the target calculation result into the target field of the second hardware descriptor according to the field definition of the hardware descriptor in the second data queue, so as to obtain a hardware descriptor carrying the target calculation result, that is, the second hardware descriptor.

[0165] In some embodiments, the hardware processing unit may count the data volume of the target calculation result and determine whether the data volume of the target calculation result is less than or equal to the set second data volume threshold.

[0166] In other embodiments, since the length of the calculation result of some calculation tasks is fixed. Based on this, the processor may determine the data volume of the target calculation result, that is, the length of the target calculation result, according to the calculation method corresponding to the target calculation request. Further, if the data volume of the target calculation result is less than or equal to the set second data volume threshold, when the processor generates the first hardware descriptor carrying the target original data, it may write invalid memory address information into the destination address field of the first hardware descriptor. For the convenience of description and distinction, the invalid memory address information written into the source address field of the first hardware descriptor is defined as invalid first memory address information, and the invalid memory address information written into the destination address field of the first hardware descriptor is defined as invalid second memory address information. Among them, the first memory address information and the second memory address information may be the same or different.

[0167] Accordingly, the hardware processing unit can obtain the memory address information stored in the destination address field from the first hardware descriptor; and when the memory address information stored in the destination address field obtained from the first hardware descriptor is invalid second memory address information, determine that the data volume of the target calculation result is less than or equal to the second data volume threshold, and generate a hardware descriptor carrying the target calculation result according to the field definition of the hardware descriptor in the second data queue.

[0168] Furthermore, the hardware processing unit can write the second hardware descriptor into the second data queue. In this embodiment, when the data volume of the target calculation result is less than or equal to the set second data volume threshold, the hardware processing unit carries the target calculation result in the second hardware descriptor and writes it into the second data queue in the memory, without having to write the target calculation result into another separate memory area, which can reduce the number of times the hardware processing unit writes data to the memory, that is, reduce the memory access times of the hardware processing unit, thereby reducing the resource consumption of memory access. In addition, since the hardware processing unit does not need to write the target calculation result into a separate memory area, there is no need to allocate another separate memory space for the target calculation result, which can save memory resources.

[0169] Accordingly, the processor can read the second hardware descriptor from the second data queue and obtain the target calculation result from the second hardware descriptor. The processor only needs to read the second hardware descriptor from the memory and can directly obtain the target calculation result from the second hardware descriptor, without having to read the memory separately to obtain the target calculation result, which can reduce the memory access times of the processor, thereby reducing the resource consumption of memory access.

[0170] In the embodiment of the present application, in order to enable the processor to perceive whether it obtains the target calculation result from the second hardware descriptor or reads the target calculation result from the corresponding area of the memory, when generating the second hardware descriptor carrying the target calculation result, the hardware processing unit can also write the invalid second memory address information into the destination address field of the second hardware descriptor. Among them, the destination address field of the second hardware descriptor is used to record the memory address information of the data provided by the hardware processing unit to the processor.

[0171] Accordingly, the processor can read the second hardware descriptor from the second data queue. Further, the memory address information stored in the destination address field can be obtained from the second hardware descriptor; and in the case where the memory address information stored in the destination address field of the second hardware descriptor is invalid second memory address information, the target calculation result can be obtained from the second hardware descriptor. Among them, when the target calculation result is less than or equal to the second data volume threshold, the invalid second memory address information is written into the destination address field of the second hardware descriptor. The processor can determine where to obtain the target calculation result according to the value of the destination address field, which provides guiding information for the processor on where to obtain the target calculation result.

[0172] The data provided by the hardware processing unit to the processor shown in the foregoing embodiment is the calculation result corresponding to the calculation request of the processor. Of course, the data provided by the hardware processing unit to the processor can also be other data, which is not associated with the calculation request obtained by the processor.

[0173] In some other embodiments, the target data is the data provided by the hardware processing unit to the processor, and the recipient of the target data is the processor. In the embodiments of the present application, the hardware processing unit can be the calculation result corresponding to the foregoing calculation request, or can be other data, such as data received from other devices, etc. Accordingly, when the data volume of the target data is less than or equal to the set second data volume threshold, the hardware processing unit can generate a hardware descriptor carrying the target data (defined as the third hardware descriptor) according to the field definition of the hardware descriptor in the second data queue. The third hardware descriptor is the target hardware descriptor in this embodiment.

[0174] Specifically, when the data volume of the target data is less than or equal to the set second data volume threshold, the hardware processing unit can write the target data into the target field of the second hardware descriptor according to the field definition of the hardware descriptor in the second data queue, so as to obtain the third hardware descriptor carrying the target data.

[0175] Further, the hardware processing unit can write the third hardware descriptor into the second data queue. In this implementation manner, when the data volume of the target data is less than or equal to the set second data volume threshold, the hardware processing unit carries the target calculation result in the third hardware descriptor and writes it into the second data queue in the memory, without having to write the target data into another separate memory area, which can reduce the number of times the hardware processing unit writes data to the memory, that is, reduce the number of memory accesses of the hardware processing unit, thereby reducing the resource consumption of memory access. In addition, since the hardware processing unit does not need to write the target data into a separate memory area, there is no need to allocate another separate memory space for the target data, which can save memory resources.

[0176] Accordingly, the processor can read the third hardware descriptor from the second data queue and obtain the target data from the third hardware descriptor. The processor only needs to read the third hardware descriptor from the memory and can directly obtain the target data from the third hardware descriptor, without the need to additionally read the memory to obtain the target data, which can reduce the number of memory accesses by the processor and thus reduce the resource consumption of memory access.

[0177] In the embodiments of the present application, in order to enable the processor to perceive whether it obtains the target calculation result from the third hardware descriptor or reads the target data from the corresponding area of the memory, when the hardware processing unit generates the third hardware descriptor carrying the target calculation result, it can also write the invalid second memory address information into the destination address field of the third hardware descriptor.

[0178] Accordingly, the processor can read the third hardware descriptor from the second data queue, and can obtain the memory address information stored in the destination address field from the third hardware descriptor; and when the memory address information stored in the destination address field of the third hardware descriptor is the invalid second memory address information, obtain the target data from the third hardware descriptor. Among them, the destination address field of the second hardware descriptor writes the invalid second memory address information when the target calculation result is less than or equal to the second data volume threshold. The processor can determine where to obtain the target calculation result according to the value of the destination address field, which provides guiding information for the processor to obtain the target data from where.

[0179] It should be noted that the execution subject of each step of the method provided in the above embodiments can be the same device, or the method can also be executed by different devices as the execution subject. For example, the execution subjects of steps 801 and 802 can be device A; for another example, the execution subject of step 801 can be device A, and the execution subject of step 802 can be device B; and so on.

[0180] In addition, in some of the processes described in the above embodiments and the accompanying drawings, multiple operations appear in a specific order, but it should be clearly understood that these operations can be executed not in the order in which they appear in this article or in parallel. The operation numbers such as 801 and 802 are only used to distinguish different operations, and the numbers themselves do not represent any execution order. In addition, these processes can include more or fewer operations, and these operations can be executed in sequence or in parallel.

[0181] Accordingly, the embodiments of the present application also provide a computer-readable storage medium storing computer instructions, which when executed by one or more processors, cause the one or more processors to execute the steps in the data processing methods provided in the foregoing embodiments.

[0182] An embodiment of the present application also provides a computer program product, including a computer program, which, when executed by one or more processors, causes the one or more processors to execute the steps in the data processing methods provided in the foregoing embodiments.

[0183] In the embodiments of the present application, the specific implementation form of the computer program product is not limited. In some embodiments, the computer program product can be implemented as an application program (APP), a mini-program, a computer-side client, a program module, a plug-in, an installation package, a software development kit (SDK), an optical disc image file (such as an ISO file), a plug-in, or software in the form of software as a service (SaaS), etc., but not limited thereto.

[0184] Figure 9a It is a schematic structural diagram of the hardware processing device provided in the embodiments of the present application. As Figure 9a shown, the hardware processing device mainly includes: a memory access engine 901 and a computing engine 902. The memory access engine 901 and the computing engine 902 are electrically connected. Among them, the memory access engine 901 can be a DMA engine.

[0185] The hardware processing device is used to be electrically connected to the memory; the memory is electrically connected to the processor; the memory stores a second data queue, and the hardware descriptors in the second data queue are data structures that describe the information of the data provided by the hardware processing device to the processor.

[0186] In some embodiments of the present application, the memory also stores a first data queue; the hardware descriptors in the first data queue are data structures that describe the information of the data obtained by the hardware processing device from the processor.

[0187] The memory access engine 901 is used to read a first hardware descriptor from the first data queue; and obtain target original data from the first hardware descriptor; the first hardware descriptor is a hardware descriptor carrying the target original data generated by the processor according to the field definition of the hardware descriptor in the first data queue when the data volume of the target original data corresponding to the target calculation request is less than or equal to a set first data volume threshold.

[0188] The computing engine 902 is used to perform calculations on the target original data to obtain the target calculation result corresponding to the target calculation request.

[0189] In some embodiments, the memory access engine 901 reads the first hardware descriptor from the first data queue into the cache 903 in a DMA manner.

[0190] In some embodiments, the hardware descriptors in the first data queue include a source address field and a destination field. The source address field is used to record the memory address information of the data obtained by the hardware processing device from the processor. When the data volume of the target original data is less than or equal to a set first data volume threshold, the processor writes invalid first memory address information into the source address field of the first hardware descriptor according to the field definition of the hardware descriptor in the first data queue, and writes the target original data into the destination field of the first hardware descriptor to obtain the first hardware descriptor.

[0191] When the memory access engine 901 obtains the target original data from the first hardware descriptor, it is specifically configured to: obtain the memory address information stored in the source address field of the first hardware descriptor from the first hardware descriptor; and when the memory address information stored in the source address field of the first hardware descriptor is invalid first memory address information, obtain the target original data from the first hardware descriptor.

[0192] In some other embodiments, the memory further stores a second data queue; the hardware descriptors in the second data queue are data structures for describing the information of the data provided by the hardware processing device to the processor. The computing engine 902 is further configured to: when the data volume of the target calculation result is less than or equal to a set second data volume threshold, generate a second hardware descriptor carrying the target calculation result according to the field definition of the hardware descriptor in the second data queue. Correspondingly, the memory access engine 901 is configured to write the second hardware descriptor into the second data queue for the processor to read the second hardware descriptor from the second data queue and obtain the target calculation result from the second hardware descriptor.

[0193] Furthermore, the hardware descriptors in the first data queue include a destination address field for recording the memory address information of the data provided by the hardware processing device to the processor; when the data volume of the target calculation result is less than or equal to the second data volume threshold, the processor writes invalid second memory address information into the destination address field of the first hardware descriptor. Correspondingly, the computing engine 902 is further configured to: obtain the memory address information stored in the destination address field of the first hardware descriptor from the first hardware descriptor; and when the memory address information stored in the destination address field of the first hardware descriptor is invalid second memory address information, determine that the data volume of the target calculation result is less than or equal to the second data volume threshold.

[0194] In some embodiments, the hardware descriptor in the first data queue further includes: an opcode field for recording the opcode corresponding to the calculation request. In response to a target calculation request, the processor determines the target opcode corresponding to the target calculation request and writes the target opcode into the opcode field in the first hardware descriptor. Accordingly, when the calculation engine 902 performs calculations on the target raw data, it is specifically configured to: obtain the target opcode from the opcode field of the first hardware descriptor; perform calculations on the target raw data according to the calculation method corresponding to the target opcode to obtain the target calculation result.

[0195] In some embodiments of the present application, the calculation engine 901 is configured to generate a target hardware descriptor carrying the target data according to the field definition of the hardware descriptor when the data volume of the target data to be exchanged between the hardware processing device and the processor is less than or equal to the set data volume threshold.

[0196] Accordingly, the memory access engine 902 is configured to: write the target hardware descriptor into the second data queue for the processor to read the target hardware descriptor from the second data queue and obtain the target data from the target hardware descriptor.

[0197] In some embodiments, when generating the target hardware descriptor carrying the target data, the calculation engine 901 is specifically configured to: write the invalid second memory address information into the destination address field of the third hardware descriptor according to the field definition of the hardware descriptor in the second data queue, and write the target data into the target field of the third hardware descriptor, so that when the memory address information stored in the destination address field of the third hardware descriptor is the invalid second memory address information, the processor can obtain the target calculation result from the third hardware descriptor.

[0198] Figure 9b This is a schematic structural diagram of the electronic device provided in the embodiments of the present application. As Figure 9b shown, the electronic device includes: a memory 90a and a processor 90b. Among them, the memory 90a includes a memory 90a1 and other storage media 90a2. The memory 90a1 can store data queues. The hardware descriptor in the data queue is a data structure for describing the data to be exchanged between the processor 90a and the hardware processing unit. In this embodiment, the other storage media in the memory 90a are used to store computer programs. The processor 90a can be communicatively connected to the hardware processing unit.

[0199] When the processor 90a is communicatively connected to the hardware processing unit, the processor 90b is coupled to the memory 90a and is configured to execute a computer program to perform the steps in the data processing method executed by the processor provided in the foregoing embodiments. For the specific implementation manners of the steps, reference may be made to the relevant descriptions in the foregoing embodiments, and details are not described herein again.

[0200] In some alternative embodiments, such as Figure 9b shown, the electronic device may further include optional components such as a communication component 90c, a power supply component 90d, a display component 90e, and an audio component 90f. Figure 9b Only some components are schematically shown, which does not mean that the electronic device must include Figure 9b all the components shown, nor does it mean that the electronic device can only include Figure 9b the components shown.

[0201] In addition, Figure 9b the components within the dashed box are optional components rather than essential components, and can be determined according to the product form of the electronic device. The electronic device of this embodiment can be implemented as a terminal device such as a desktop computer, a laptop computer, a mobile phone, or an Internet of Things device; it can also be various server devices such as a traditional server, a cloud server, or a server cluster.

[0202] In the embodiment of the present application, the memory is used to store computer programs and can be configured to store various other data to support operations on the device where it is located. Among them, the processor can execute the computer programs stored in the memory to implement corresponding control logics. The memory can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random-Access Memory (SRAM), Electrically Erasable Programmable Read Only Memory (EEPROM), Electrical Programmable Read Only Memory (EPROM), Programmable Read Only Memory (PROM), Read Only Memory (ROM), magnetic memory, flash memory, a magnetic disk, or an optical disc.

[0203] In the embodiments of the present application, the processor may be any hardware processing device capable of executing the above method logic. Optionally, the processor may be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or a Microcontroller Unit (MCU); it may also be a programmable device such as a Field-Programmable Gate Array (FPGA), a Programmable Array Logic (PAL), a General Array Logic (GAL), or a Complex Programmable Logic Device (CPLD); or it may be an Advanced RISC Machines (ARM) processor or a System on Chip (SoC), etc., but not limited thereto.

[0204] In the embodiments of the present application, the communication component is configured to facilitate communication between the device where it is located and other devices in a wired or wireless manner. The device where the communication component is located can access a wireless network based on a communication standard, such as Wireless Fidelity (WiFi), 2G or 3G, 4G, 5G, or a combination thereof. In an exemplary embodiment, the communication component receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component can also be implemented based on Near Field Communication (NFC) technology, Radio Frequency Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra Wide Band (UWB) technology, Bluetooth (BT) technology, or other technologies.

[0205] In an embodiment of the present application, the display component may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the display component includes a touch panel, the display component can be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can sense not only the boundaries of touch or swipe actions, but also detect the duration and pressure associated with the touch or swipe operation.

[0206] In an embodiment of the present application, the power supply component is configured to provide power to various components of the device where it is located. The power supply component may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for the device where the power supply component is located.

[0207] In an embodiment of the present application, the audio component may be configured to output and / or input audio signals. For example, the audio component includes a microphone (MIC). When the device where the audio component is located is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is configured to receive external audio signals. The received audio signals can be further stored in the memory or transmitted via the communication component. In some embodiments, the audio component further includes a speaker for outputting audio signals. For example, for a device with a language interaction function, voice interaction with the user can be implemented through the audio component.

[0208] It should be noted that the descriptions such as "first" and "second" in this article are used to distinguish different messages, devices, modules, etc., and do not represent a sequence, nor do they limit that "first" and "second" are of different types.

[0209] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, Compact Disc Read-Only Memory (CD-ROM), optical memory, etc.) containing computer-usable program code.

[0210] This application is described with reference to the flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram can be implemented by computer program instructions, and the combination of the flows and / or blocks in the flowchart and / or block diagram can also be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in one or more of the flows Figure 1 one or more of the flows and / or blocks Figure 1 or means for implementing the functions specified in one or more of the blocks.

[0211] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including instruction means, and the instruction means implement the functions specified in one or more of the flows Figure 1 one or more of the flows and / or blocks Figure 1 or means for implementing the functions specified in one or more of the blocks.

[0212] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more of the flows Figure 1 one or more of the flows and / or blocks Figure 1 or means for implementing the functions specified in one or more of the blocks.

[0213] In a typical configuration, a computing device includes one or more processors (such as CPUs), an input / output interface, a network interface, and a memory.

[0214] The memory may include non-permanent memory in a computer-readable medium, in the form of random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash memory (flashRAM). The memory is an example of a computer-readable medium.

[0215] The storage medium of a computer is a readable storage medium, also known as a readable medium. Readable storage media include permanent and non-permanent, removable and non-removable media and can implement information storage by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of the storage medium of a computer include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory, or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD), or other optical storage, magnetic cassette tapes, disk storage, or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media do not include transitory media such as modulated data signals and carrier waves.

[0216] It should also be noted that the term "comprising", "including", or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements that are inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the above elements.

[0217] The above content is only an embodiment of the present application and is not used to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

Claims

1. A computing system, characterized in that: include: Processors, hardware processing units and memory; The processor and the hardware processing unit are electrically connected to the memory respectively; The memory stores a first data queue; The hardware descriptor in the first data queue is a data structure that describes information about data obtained by the hardware processing unit from the processor; The hardware descriptor in the first data queue includes: a source address field and a target field, the source address field is used to record the memory address information of the data obtained by the hardware processing unit from the processor; the target field is a free field in the hardware descriptor in the first data queue; The processor is configured to, when the amount of target data to be exchanged between the hardware processing unit and the processor is less than or equal to a set data amount threshold, write invalid first memory address information into a source address field of the first hardware descriptor according to a field definition of the hardware descriptor, and write target data into a target field of the first hardware descriptor to obtain the first hardware descriptor; the target data is data to be obtained by the hardware processing unit from the processor; and write the first hardware descriptor into the first data queue; The hardware processing unit is used to read the first hardware descriptor from the first data queue, and obtain the target data from the first hardware descriptor when the memory address information stored in the source address field of the first hardware descriptor is the invalid first memory address information.

2. A computing system, characterized in that: include: Processors, hardware processing units and memory; The processor and the hardware processing unit are electrically connected to the memory respectively; The memory stores a second data queue; The hardware descriptor in the second data queue is a data structure that describes information about data provided by the hardware processing unit to the processor; The hardware processing unit is configured to, when the amount of target data to be exchanged between the hardware processing unit and the processor is less than or equal to a set data amount threshold, write the invalid second memory address information into a destination address field of a third hardware descriptor and write the target data into a target field of the third hardware descriptor according to the field definition of the hardware descriptor in the second data queue, so as to obtain a third hardware descriptor carrying the target data; the target data is data to be provided to the processor by the hardware processing unit; and writing the third hardware descriptor into the second data queue; The processor is configured to read the third hardware descriptor from the second data queue, and obtain the target data from the third hardware descriptor when the memory address information stored in the destination address field of the third hardware descriptor is the invalid second memory address information.

3. A data processing method, applicable to a processor, characterized in that: The processor and the hardware processing unit are electrically connected to the memory respectively; the memory stores a first data queue; the hardware descriptor in the first data queue is a data structure describing information about data obtained by the hardware processing unit from the processor; The hardware descriptor in the first data queue includes: a source address field and a target field, the source address field is used to record the memory address information of the data obtained by the hardware processing unit from the processor; the target field is a free field in the hardware descriptor in the first data queue; The method comprises: When the amount of target data to be exchanged between the hardware processing unit and the processor is less than or equal to a set data amount threshold, according to the field definition of the hardware descriptor in the first data queue, writing invalid first memory address information into the source address field of the first hardware descriptor, and writing target data into the target field of the first hardware descriptor, so as to obtain the first hardware descriptor; the target data is the data to be obtained by the hardware processing unit from the processor; The first hardware descriptor is written into the first data queue so that the hardware processing unit can read the first hardware descriptor from the first data queue, and obtain the target data from the first hardware descriptor when the memory address information stored in the source address field of the first hardware descriptor is the invalid first memory address information.

4. The method according to claim 3, characterized in that The target data is target original data corresponding to the target calculation request; the hardware processing unit calculates the target original data to obtain a target calculation result.

5. The method according to claim 4, characterized in that The memory further stores a second data queue; the hardware descriptor in the second data queue is a data structure describing information of data provided by the hardware processing unit to the processor; the hardware processing unit generates a second hardware descriptor carrying the target calculation result according to the field definition of the hardware descriptor in the second data queue when the data amount of the target calculation result is less than or equal to the set second data amount threshold; and writing the second hardware descriptor into the second data queue; The method further comprises: The second hardware descriptor is read from the second data queue, and the target calculation result is obtained from the second hardware descriptor.

6. The method according to claim 4, characterized in that The hardware descriptor in the first data queue includes: a destination address field for recording memory address information of data provided by the hardware processing unit to the processor; The step of writing the invalid first memory address information into the source address field of the first hardware descriptor according to the field definition of the hardware descriptor in the first data queue, and writing the target data into the target field of the first hardware descriptor to obtain the first hardware descriptor comprises: According to the field definition of the hardware descriptor in the first data queue, writing the invalid first memory address information into the source address field of the first hardware descriptor, and writing the target original data into the target field of the first hardware descriptor; and When the data volume of the target calculation result is less than or equal to a second data volume threshold, invalid second memory address information is written into the destination address field of the first hardware descriptor to obtain the first hardware descriptor, so that the hardware processing unit can determine that the data volume of the target calculation result is less than or equal to the second data volume threshold when the memory address information stored in the destination address field of the first hardware descriptor is the invalid second memory address information.

7. The method according to claim 5, characterized in that The hardware descriptor in the second data queue further includes: a destination address field, which is used to record the memory address information of the data provided by the hardware processing unit to the processor; the hardware processing unit, when the data amount of the target calculation result is less than or equal to the second data amount threshold, writes the invalid second memory address information into the destination address field of the second hardware descriptor; The obtaining the target calculation result from the second hardware descriptor includes: When the memory address information stored in the destination address field of the second hardware descriptor is the invalid second memory address information, the target calculation result is obtained from the second hardware descriptor.

8. The method according to claim 4, characterized in that The hardware descriptor in the first data queue further includes: an operation code field, which is used to record the operation code corresponding to the calculation request; the method further includes: In response to the target computing request, determining a target operation code corresponding to the target computing request; The step of generating a first hardware descriptor carrying the target original data according to the field definition of the hardware descriptor in the first data queue includes: According to the field definition of the hardware descriptor in the first data queue, the target opcode is written into the opcode field in the first hardware descriptor, and the target original data is written into the target field in the first hardware descriptor to obtain the first hardware descriptor, so that the hardware processing unit can obtain the target opcode from the opcode field of the first hardware descriptor; and the target original data is calculated according to the calculation method corresponding to the target opcode to obtain the target calculation result.

9. A data processing method, applicable to a hardware processing unit, characterized in that: The hardware processing unit and the processor are electrically connected to the memory respectively; the memory stores a second data queue; The hardware descriptor in the second data queue is a data structure describing information of data provided by the hardware processing unit to the processor; the method comprises: When the amount of target data to be exchanged between the hardware processing unit and the processor is less than or equal to a set data amount threshold, according to the field definition of the hardware descriptor in the second data queue, the invalid second memory address information is written into the destination address field of the third hardware descriptor, and the target data is written into the target field of the third hardware descriptor to obtain a third hardware descriptor carrying the target data; the target data is the data to be provided to the processor by the hardware processing unit; The third hardware descriptor is written into the second data queue so that the processor can read the third hardware descriptor from the second data queue, and obtain the target data from the third hardware descriptor when the memory address information stored in the destination address field of the third hardware descriptor is the invalid second memory address information.

10. A data processing method, applicable to a hardware processing unit, characterized in that: The hardware processing unit and the processor are electrically connected to the memory respectively; the memory stores a first data queue; the hardware descriptor in the first data queue is a data structure describing information about data obtained by the hardware processing unit from the processor; The hardware descriptor in the first data queue includes: a source address field and a target field, the source address field is used to record the memory address information of the data obtained by the hardware processing unit from the processor; The method comprises: A first hardware descriptor is read from the first data queue; the first hardware descriptor is a hardware descriptor carrying the target original data generated by the processor according to the field definition of the hardware descriptor in the first data queue when the data volume of the target original data corresponding to the target computing request is less than or equal to the set first data volume threshold; the source address field of the first hardware descriptor stores invalid first memory address information, and the target field of the first hardware descriptor stores the target original data; In a case where the memory address information stored in the source address field of the first hardware descriptor is the invalid first memory address information, acquiring the target original data from the first hardware descriptor; The target original data is calculated to obtain a target calculation result corresponding to the target calculation request.

11. The method according to claim 10, characterized in that The memory further stores a second data queue; the hardware descriptor in the second data queue is a data structure describing information of data provided by the hardware processing unit to the processor; the method further includes: When the data volume of the target calculation result is less than or equal to a set second data volume threshold, generating a second hardware descriptor carrying the target calculation result according to the field definition of the hardware descriptor in the second data queue; The second hardware descriptor is written into the second data queue, so that the processor reads the second hardware descriptor from the second data queue and obtains the target calculation result from the second hardware descriptor.

12. The method according to claim 11, characterized in that The hardware descriptor in the first data queue includes: a destination address field, which is used to record the memory address information of the data provided by the hardware processing unit to the processor; the processor writes the invalid second memory address information into the destination address field of the first hardware descriptor when the data amount of the target calculation result is less than or equal to the second data amount threshold; The method further comprises: Acquire, from the first hardware descriptor, memory address information stored in a destination address field of the first hardware descriptor; When the memory address information stored in the destination address field of the first hardware descriptor is the invalid second memory address information, it is determined that the data amount of the target calculation result is less than or equal to the second data amount threshold.

13. A data processing method, applicable to a processor, characterized in that: The processor and the hardware processing unit are electrically connected to the memory respectively; the memory stores a second data queue; the hardware descriptor in the second data queue is a data structure describing information of data provided by the hardware processing unit to the processor; The method comprises: and reading a third hardware descriptor from the second data queue; the third hardware descriptor is a third hardware descriptor carrying the target data obtained by the hardware processing unit writing invalid second memory address information into a destination address field of the third hardware descriptor and writing the target data into a target field of the third hardware descriptor according to the field definition of the hardware descriptor in the second data queue when the data volume of the target data is less than or equal to a set data volume threshold; the target data is data to be provided to the processor by the hardware processing unit; In a case where the memory address information stored in the destination address field of the third hardware descriptor is invalid second memory address information, the target data is obtained from the third hardware descriptor.

14. A hardware processing device, characterized in that: include: Memory access engine and calculation engine; The memory computing engine and the computing engine are electrically connected; The hardware processing device is used to be electrically connected to the memory, and the memory is electrically connected to the processor; The memory stores a second data queue, wherein the hardware descriptor in the second data queue is a data structure describing information of data provided by the hardware processing device to the processor; The computing engine is configured to, when the amount of target data to be exchanged between the hardware processing device and the processor is less than or equal to a set data amount threshold, write invalid second memory address information into a destination address field of a target hardware descriptor according to a field definition of the hardware descriptor in the second data queue, and write the target data into a target field of the target hardware descriptor, so as to obtain a target hardware descriptor carrying the target data; The memory access engine is used to: write the target hardware descriptor into the second data queue so that the processor can read the target hardware descriptor from the second data queue, and obtain the target data from the target hardware descriptor when the memory address information stored in the destination address field of the target hardware descriptor is the invalid second memory address information.

15. The device according to claim 14, characterized in that The memory also stores a first data queue; the hardware descriptor in the first data queue is a data structure describing information of data obtained by the hardware processing device from the processor; The memory access engine is further used to: read a first hardware descriptor from the first data queue; and obtaining target original data corresponding to the target calculation result from the first hardware descriptor; The first hardware descriptor is a hardware descriptor carrying the target original data, generated by the processor according to the field definition of the hardware descriptor in the first data queue when the data volume of the target original data is less than or equal to the set first data volume threshold; The computing engine is further used to compute the target original data to obtain a target computing result corresponding to the target computing request.

16. An electronic device, characterized in that: include: Memory and processor; the memory includes internal memory and other storage media; the processor is electrically connected to the memory; The memory is used to be electrically connected to the hardware processing unit; The other storage medium is used to store the computer program; The memory stores a data queue; the hardware descriptor in the data queue is a data structure describing information of data to be exchanged between the hardware processing unit and the processor; The processor is coupled to the memory and the other storage media, and is configured to execute the computer program for performing the steps in the method of any one of claims 3-8 and 13.

17. A computer-readable storage medium storing computer instructions, characterized in that: When the computer instructions are executed by one or more processors, the one or more processors are caused to execute the steps in the method according to any one of claims 3 to 13.

18. A computer program product, characterized in that The method comprises a computer program which, when executed by one or more processors, causes the one or more processors to execute the steps of the method according to any one of claims 3 to 13.

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