A clock management circuit for automotive-grade MCUs
The dual PLL dual clock generation path in the MCU clock management circuit addresses the vulnerability of single path failures by enabling automatic switching to a redundant path, enhancing system stability and reliability.
Patent Information
- Application Number
- CN202411231800.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-04
- Publication Date
- 2025-07-15
- Estimated Expiration
- 2044-09-04
AI Technical Summary
The clock management circuit of existing automotive MCUs is in the single PLL single clock generation path. Any part of the abnormality will cause clock abnormality, the system will not work properly, and lack stability and robustness.
The dual PLL dual clock generation path design is adopted, and a clock generation path and some logic circuits are added. The flexible switching of the clock generation path is achieved through multiplexers and configuration registers to ensure that one path is switched to another path when it is abnormal.
It realizes automatic switching to the backup clock source when any PLL is out of lock, improves the stability and robustness of the system, ensures that the clock management circuit can still work normally in abnormal situations, and the circuit structure is simple and easy to implement.
Smart Images
Figure CN119201554B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of automotive-grade MCU clock management circuits, and specifically to a clock management circuit for automotive-grade MCUs. Background Art
[0002] ISO 26262 requires automotive original equipment manufacturers and their component suppliers to follow and document the functional safety development process (from the start of specification until mass production release) in order for the vehicle to obtain operating qualification. By definition, functional safety significantly reduces the risk of failures, which can be divided into two categories: systematic failures and random failures. The former can only be eliminated by changing the manufacturing process, operating procedures, design of the documentation, or other relevant factors. The latter are unpredictable failures that occur during the life cycle of the hardware. According to the probability distribution, these failures may be due to permanent or transient interference environments, or may be caused by the performance of internal technologies during the life cycle of the system.
[0003] As one of the important control components of an automobile, the MCU is classified as a special type of element (SEooC, Safety Elements out of Context) in ISO 26262. Its functional safety must strictly follow ISO 26262 from definition to mass production stage. SEooC requires the use of assumptions (AoU) to reflect the expected safety concepts, requirements, and mechanisms to be used. The internal clock architecture of the MCU is complex, and the frequency of the clock signal is crucial for the correctness and performance of the chip's operation. If the frequency exceeds the specified limit, it may lead to performance, protocol, and timing failures.
[0004] Such as Figure 1As shown in the figure, a general clock management circuit mainly consists of a clock generation module, a power consumption management module, a PLL, and an oscillator. The clock management circuit is responsible for generating clock signals of various frequencies for each module (such as CPU, I / O interface, etc.) required within the SoC chip, and at the same time completing the management function of these clocks, that is, turning off, turning on, or even changing the working clocks of certain modules according to application requirements. The input of the clock management circuit is generally an external input clock of the chip or an output clock of the built-in oscillator. Usually, a phase-locked loop (PLL) circuit is integrated within the SoC chip to multiply the input clock frequency to obtain the high-frequency clock required inside the chip. The multiplied clock can then be divided by different multiples according to the application configuration information to obtain the working clocks of each module within the chip. Among them, the power consumption management module has a set of control and status registers for clock management logic, which are configured by the AHB bus interface. These registers include: clock selection control register, PLL control register, low-power control register, and clock gating status register, etc. The chip generates the required clock control signals through these configurable registers. For example, the external clock or oscillator clock is selected as the multiplied input of the PLL through the clock selection control register; the PLL multiplication factor is configured through the PLL control register to obtain the multiplied output clock of the PLL; the output clocks of each module and the gating switches are controlled through the low-power control register.
[0005] In the prior art, it is usually a single PLL and single clock generation path. Once any part in the clock generation path has an abnormality, the generated clock will also be abnormal, and the system can only work under the abnormal clock. Based on this, the present invention proposes a clock management circuit for a vehicle-grade MCU to solve the above problems. Summary of the Invention
[0006] (I) Technical problems to be solved
[0007] In view of the deficiencies of the prior art, the present invention provides a clock management circuit for a vehicle-grade MCU. The clock management circuit of this vehicle-grade MCU is a dual-PLL and dual-clock generation path. By adding a PLL, a clock generation path, and some logic circuits, the clock generation path can be flexibly switched, so that when the clock generated by a certain path is abnormal, the system can switch to the other path to work normally.
[0008] (II) Technical solutions
[0009] To achieve the above object, the present invention provides the following technical solutions: A clock management circuit for a vehicle - grade MCU, comprising: an externally - connected OSC module of the chip, which generates the main source clock of the chip; an internally - built OSC module of the chip, which generates the backup source clock of the chip; an externally - connected low - frequency clock module of the chip, which generates the secondary backup source clock of the chip; multiplexers, where multiplexer 1 and multiplexer 2 are three - input single - output multiplexers, multiplexer 3 and multiplexer 4 are two - input single - output multiplexers, and multiplexer 5 and multiplexer 6 are four - input single - output multiplexers; a configuration register, which is a register module of the system for configuring control signals; a system PLL, which is a Phase - locked Loop (PLL) for amplifying the frequency of the output clock of multiplexer 1, generating a high - frequency clock, and then, after clock frequency division, serving as the system clock; a backup PLL, which is the same PLL as the system PLL for amplifying the frequency of the output clock of multiplexer 2, generating a high - frequency clock, and then, after clock frequency division, serving as the peripheral clock; a clock frequency - division module for dividing the high - frequency clock output by the PLL according to a set frequency - division coefficient to obtain a low - frequency clock with a specific frequency required by the system.
[0010] Preferably, the externally - connected OSC module of the chip is an external oscillator (crystal oscillator), the externally - connected OSC module of the chip is input through the chip pins, and the internally - built OSC module of the chip is an internal oscillator (crystal oscillator).
[0011] Preferably, the externally - connected low - frequency clock module of the chip is a low - frequency clock signal, which is input through the chip pins.
[0012] The clock flow of the above - mentioned circuit is as follows:
[0013] S1. After the chip is powered on and reset, the chip source clock defaults to the externally - connected OSC of the chip. At this time, the PLL is not started, and the chip is in the working state of the low - frequency clock;
[0014] S2. After the system configures the relevant registers (such as PLL configuration parameters, frequency - division coefficients of clock frequency division, multiplexer selection signals, etc.), then turn on the system PLL and the backup PLL;
[0015] S3. Wait for the two PLLs to lock, and then the input of the clock frequency division will automatically switch to the high - frequency clock output by the PLL;
[0016] S4. The clock output by the PLL is further divided by frequency to obtain the clock frequency required for the normal operation of the system.
[0017] (III) Beneficial effects
[0018] Compared with the prior art, the present invention provides a clock management circuit for automotive-grade MCUs, which has the following beneficial effects:
[0019] The clock management circuit of the present invention is a dual-PLL dual-clock generation path. By adding a PLL, a clock generation path, and some logic circuits, the clock generation path can be flexibly switched. Thus, when the clock generated by a certain path is abnormal, the system can switch to the other path to work normally. Furthermore, when any PLL loses lock, the chip source clock can be automatically switched to the osc clock, and the use of two identical clock paths increases the stability of the system. When the output clock of any path is abnormal, it can be switched to the output clock of the other path. The entire circuit structure is simple, the implementation difficulty is low, and the entire circuit structure has high robustness. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 is the clock management circuit diagram in the prior art;
[0021] Figure 2 is the clock management circuit diagram of an automotive-grade MCU proposed by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0022] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
[0023] The existing structure is usually a single-PLL single-clock generation path. Once any part in the clock generation path has an abnormality, the generated clock will also be abnormal, and the system can only work under the abnormal clock. Please refer to Figure 2 , the clock management circuit of the present invention is a dual-PLL dual-clock generation path. By adding a PLL, a clock generation path, and some logic circuits, the clock generation path can be flexibly switched. Thus, when the clock generated by a certain path is abnormal, the system can switch to the other path to work normally.
[0024] Specifically, the clock management circuit of this automotive-grade MCU includes: an externally-connected OSC module of the chip, which generates the main source clock of the chip; an internally-built OSC module of the chip, which generates the backup source clock of the chip; an externally-connected low-frequency clock module of the chip, which generates the secondary backup source clock of the chip; multiplexers. Multiplexer 1 and multiplexer 2 are three-input single-output multiplexers, multiplexer 3 and multiplexer 4 are two-input single-output multiplexers, and multiplexer 5 and multiplexer 6 are four-input single-output multiplexers; a configuration register, which is a register module of the system for configuring control signals; a system PLL, which is a Phase-locked Loop (PLL) for amplifying the frequency of the output clock of multiplexer 1 to generate a high-frequency clock, and then, after clock division, serving as the system clock; a backup PLL, which is the same PLL as the system PLL for amplifying the frequency of the output clock of multiplexer 2 to generate a high-frequency clock, and then, after clock division, serving as the peripheral clock; a clock division module for dividing the high-frequency clock output by the PLL according to a set division coefficient to obtain a low-frequency clock with a specific frequency required by the system.
[0025] Among them, the externally-connected OSC module of the chip is an external oscillator (crystal oscillator), and the externally-connected OSC module of the chip is input through the chip pins. The internally-built OSC module of the chip is an internal oscillator (crystal oscillator), and the externally-connected low-frequency clock module of the chip is a low-frequency clock signal, which is input through the chip pins.
[0026] During operation, after the chip is powered on and reset, the chip source clock defaults to the externally-connected OSC of the chip. At this time, the PLL is not started, and the chip is in the working state of the low-frequency clock. After the relevant registers of the system are configured (such as PLL configuration parameters, division coefficients of clock division, multiplexer selection signals, etc.), the system PLL and the backup PLL are then turned on. After waiting for the two PLLs to lock, the input of the clock division will automatically switch to the high-frequency clock output by the PLL, and the PLL output clock is then divided to obtain the clock frequency required for the normal operation of the system.
[0027] In the solution of the present invention, three clock source inputs are provided: an externally-connected OSC of the chip, an internally-built OSC of the chip, and an externally-connected low-frequency clock of the chip. The function of the clock source is to provide a stable and accurate low-frequency source clock for the chip. The purpose of setting three clock source inputs is to improve the robustness of the system clock. Among them, the externally-connected OSC of the chip is the working clock source when the chip operates normally, and the accuracy requirement is the highest; the internally-built OSC of the chip is the standby clock source, which can be switched to this clock source to make the chip continue to work when the externally-connected OSC of the chip is abnormal. The externally-connected low-frequency clock of the chip is the secondary standby clock source, which is used in the extreme case where both the externally-connected OSC of the chip and the internally-built OSC of the chip are abnormal, and the accuracy requirement is the lowest. The three clock source inputs pass through the multiplexer 1 and the multiplexer 2 respectively and then are output to the system PLL and the standby PLL as the input clock of the PLL. The outputs of the multiplexer 1 and the multiplexer 2 are controlled by the selection signal, and the control signal is configured by the configuration register module. After the chip is powered on and reset, the default value of the control signal is 0 (that is, the output is default to the externally-connected OSC of the chip).
[0028] In addition, the system PLL and the standby PLL are two completely identical PLLs. The function of the PLL is to amplify the clock frequency of the clock source to obtain a high-frequency clock. There are two purposes for setting two PLLs. One is to use redundant design. When the system PLL is abnormal, the output of the multiplexer 5 can be switched to the standby PLL; the other is that having an additional standby PLL can provide clocks of more frequencies to meet the clock requirements of the peripherals.
[0029] The multiplexer 5 and the multiplexer 6 are two identical four-input single-output multiplexers. The purpose of setting a four-input single-output multiplexer is to increase the flexibility of clock selection. Among them, inputs 0, 1, 2, and 3 of the multiplexer 5 are the externally-connected OSC of the chip, the output clock of the system PLL, the internally-built OSC of the chip, and the output clock of the standby PLL respectively. Inputs 0, 1, 2, and 3 of the multiplexer 6 are the externally-connected OSC of the chip, the output clock of the standby PLL, the internally-built OSC of the chip, and the output clock of the system PLL respectively. The outputs of the multiplexer 5 and the multiplexer 6 are controlled by the selection signal, and the control signals are the output signals of the multiplexer 3 and the multiplexer 4 respectively. After the chip is powered on and reset, the default value of the control signal is 0 (that is, the output is default to the externally-connected OSC of the chip).
[0030] Multiplexers 3 and 4 are two identical two-input single-output multiplexers, whose function is to control the outputs of multiplexers 5 and 6. When the system PLL power switch signal and the standby PLL power switch signal are 1 (at this time, the two PLL powers are turned off), the outputs of multiplexers 3 and 4 are the selection signals of multiplexers 5 and 6 configured by the configuration register; when the system PLL power switch signal and the standby PLL power switch signal are 0 (at this time, the two PLL powers are turned on), the output of multiplexer 3 is the logical AND of the multiplexer 5 selection signal and the Lock signal of the system PLL output, and the output of multiplexer 4 is the logical AND of the multiplexer 6 selection signal and the Lock signal of the standby PLL output. The purpose of this is that when the PLL output clock is not stable, the lock signal of the PLL output is 2'b00. At this time, the result of the logical AND is 2'b00, and the selection signals of multiplexers 5 and 6 are 2'b00 (at this time, the system clock is the externally connected OSC of the chip); when the PLL output clock is stable, the lock signal of the PLL output is 2'b11. At this time, the result of the logical AND is the selection signals of multiplexers 5 and 6, and the selection signals of multiplexers 5 and 6 are controlled by the configuration register (at this time, the system clock is the PLL output clock). When the PLL is abnormal and a lock lose occurs (the PLL output clock is unstable, and at this time the lock signal will change from high level to low level), the selection signals of multiplexers 5 and 6 jump to 2'b00 (at this time, the system clock is the externally connected OSC of the chip).
[0031] The output clocks of multiplexers 5 and 6 respectively pass through clock frequency division (in actual use, due to different required clock frequencies, different frequency divisions will be performed to output clocks of different frequencies, rather than just one clock frequency division module as shown in the figure) to obtain the clocks of specific frequencies required by the system.
[0032] The clock management circuit of the present invention is a dual-PLL dual-clock generation path. By adding a PLL, a clock generation path, and some logic circuits, the clock generation path can be flexibly switched, so that when the clock generated by a certain path is abnormal, the system can switch to another path to work normally. Furthermore, when any PLL loses lock, the chip source clock can be automatically switched to the osc clock, and the use of two identical clock paths increases the stability of the system. When the output clock of any path is abnormal, it can be switched to the output clock of another path. The entire circuit structure is simple, the implementation difficulty is low, and the entire circuit structure has high robustness.
[0033] Although the embodiments of the present invention have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.
Claims
1. A clock management circuit for an automotive-grade MCU, characterized in that, Including: An externally-connected OSC module of the chip, which is the main source clock for generating the chip; An internally-built OSC module of the chip, which is the backup source clock for generating the chip; An externally-connected low-frequency clock module of the chip, which is the secondary backup source clock for the chip; Multiplexers. Multiplexer 1 and Multiplexer 2 are three-input single-output multiplexers, Multiplexer 3 and Multiplexer 4 are two-input single-output multiplexers, and Multiplexer 5 and Multiplexer 6 are four-input single-output multiplexers; A configuration register, which is a register module for configuring control signals in the system; A system PLL, which is a Phase-locked Loop, used to amplify the frequency of the output clock of Multiplexer 1, generate a high-frequency clock, and then use it as the system clock after clock division; A backup PLL, which is the same PLL as the system PLL, used to amplify the frequency of the output clock of Multiplexer 2, generate a high-frequency clock, and then use it as the peripheral clock after clock division; A clock division module, used to divide the high-frequency clock output by the PLL according to the set division coefficient to obtain a low-frequency clock with a specific frequency required by the system; The system PLL and the backup PLL are two identical PLLs. The PLL is used to amplify the clock frequency of the clock source to obtain a high-frequency clock. When the system PLL is abnormal, the output of Multiplexer 5 switches to the backup PLL, and the backup PLL is used to meet the clock requirements of the peripherals. Multiplexer 5 and Multiplexer 6 are two identical four-input single-output multiplexers, used to increase the flexibility of clock selection. Multiplexer 3 and 4 are two identical two-input single-output multiplexers, used to control the outputs of Multiplexer 5 and 6; The externally-connected OSC module of the chip is an external oscillator crystal, and the externally-connected OSC module of the chip is input through the chip pins. The internally-built OSC module of the chip is an internal oscillator crystal; The externally-connected low-frequency clock module of the chip is a low-frequency clock signal, which is input through the chip pins; The externally-connected OSC of the chip is the working clock source when the chip is running normally. The internally-built OSC of the chip is the backup clock source. When the externally-connected OSC of the chip is abnormal, it switches to this backup clock source to enable the chip to continue working. The externally-connected low-frequency clock of the chip is the secondary backup clock source, used for the extreme situation where both the externally-connected OSC and the internally-built OSC of the chip are abnormal. The three clock source inputs pass through Multiplexer 1 and Multiplexer 2 respectively and then output to the system PLL and the backup PLL as the input clock of the PLL.
2. The clock flow of the circuit according to claim 1, characterized in that Including the following steps: S1. After the chip is powered on and reset, the chip source clock defaults to the externally-connected OSC of the chip. At this time, the PLL is not started, and the chip is in the working state of the low-frequency clock; S2. After the system configures the relevant registers, then turn on the system PLL and the backup PLL;
Citation Information
Patent Citations
Frequency-controllable redundant clock board and server
CN109857191A
Frequency switching circuit
CN113541686A