Memory address mapping method, memory controller, processor and electronic equipment
The memory address mapping method addresses suboptimal access efficiency by transposing hole bits in the memory particle address to improve flexibility and efficiency in accessing discontinuous memory spaces.
Patent Information
- Application Number
- CN202411222951.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-02
- Publication Date
- 2024-12-27
AI Technical Summary
Existing memory address mapping methods that fix hole bits in the memory particle address to the highest bit of the physical address result in suboptimal memory access efficiency due to lack of flexibility in addressing discontinuous memory spaces.
A memory address mapping method that determines whether the bit value of hole bits needs to be transposed based on an optimal address mapping table, swapping hole bits with high-order bits when necessary to ensure correct memory access, thereby maintaining flexibility and improving access efficiency.
This approach ensures correct memory access while optimizing access efficiency by dynamically handling hole bits, ensuring that memory particle addresses with faster access speeds are mapped to lower-order physical addresses.
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Figure CN119201763A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of electronic circuits, and specifically relates to a memory address mapping method, a memory controller, a processor and an electronic device. Background Art
[0002] The address conversion module in the memory controller is generally used to complete the conversion between the physical address and the memory particle address in the memory chip, wherein the memory particle address is the address of the smallest storage unit (cell) in the memory chip.
[0003] When there are holes in the memory granule address, the problem that address mapping needs to solve is how to effectively use the memory space to avoid the inability to access the memory normally due to address holes. The current related technology handles the holes in the memory granule address by mapping the holes in the memory granule address to the highest bit of the physical address. Although this processing method has the advantages of simple design and universal address conversion, it is not the optimal address mapping relationship from the perspective of memory access efficiency. Therefore, the method of mapping the holes in the address granule to the highest bit of the physical address may not have the problem of optimal access efficiency. Summary of the invention
[0004] In view of this, the purpose of the present application is to provide a memory address mapping method, a memory controller, a processor and an electronic device to improve the memory access efficiency of a memory with holes.
[0005] The embodiment of the present application is implemented as follows:
[0006] In a first aspect, an embodiment of the present application provides a memory address mapping method, comprising: receiving a target physical address to be accessed, wherein the target physical address is a memory address; if there is a hole bit in the memory particle address, determining whether the bit value corresponding to the hole bit in the target physical address needs to be transposed; if so, transposing the bit value corresponding to the hole bit in the target physical address to ensure that the target physical address after the transposition can correctly access the memory; according to a preset optimal address mapping table, mapping the target after the transposition to the memory particle address, wherein the optimal address mapping table is an address mapping table with optimal memory access efficiency, and the memory particle address is used to access the memory.
[0007] In the above embodiment, after obtaining the target physical address, it is determined whether the bit value corresponding to the hole bit in the target physical address needs to be transposed. If transposition is required, the bit value corresponding to the hole bit in the target physical address is transposed to ensure that the target physical address after transposition can correctly access the memory. After that, according to the preset optimal address mapping table, the target after transposition is physically mapped to the memory particle address, thereby achieving access to the memory. Since the address mapping is performed based on the optimal address mapping table (i.e., the address mapping table with the best memory access efficiency), the hole bit in the memory particle address is no longer fixedly mapped to the highest bit of the physical address. In this way, the flexibility of the hole bit mapping relationship can be maintained, which can not only solve the problem of memory particle address holes, but also take into account access efficiency.
[0008] In combination with a possible implementation manner of the embodiment of the first aspect, determining whether the bit value corresponding to the hole bit in the target physical address needs to be transposed includes: determining whether the bit value corresponding to the hole bit in the target physical address is within a normal range; wherein, if the bit value corresponding to the hole bit in the target physical address is not within the normal range, determining that the bit value corresponding to the hole bit in the target physical address needs to be transposed.
[0009] In the above embodiment, whether transposition processing is required can be determined by judging whether the bit value corresponding to the hole bit in the target physical address is within the normal range. Transposition processing is performed only when the bit value corresponding to the hole bit in the target physical address is not within the normal range, thereby ensuring that the target physical address after the transposition processing can correctly access the memory to solve the problem of memory particle address holes.
[0010] In combination with a possible implementation manner of the embodiment of the first aspect, determining whether the bit value corresponding to the hole bit in the target physical address is within a normal range includes: determining a hole value corresponding to the bit value of the hole bit; determining whether the hole value is greater than a preset maximum value of the hole bit; wherein, if the hole value is greater than the maximum value of the hole bit, the bit value corresponding to the hole bit in the target physical address is not within the normal range.
[0011] In the above embodiment, by judging whether the hole value is greater than the preset maximum value of the hole bit, it can be quickly and accurately determined whether the bit value corresponding to the hole bit in the target physical address needs to be transposed, which is conducive to improving the judgment efficiency.
[0012] In combination with a possible implementation manner of the embodiment of the first aspect, determining whether the bit value corresponding to the hole bit in the target physical address is within a normal range includes: determining whether the bit value of the hole bit can be found in all the bit values that the hole bit can take; wherein, if the bit value of the hole bit cannot be found in all the bit values that the hole bit can take, then the bit value corresponding to the hole bit in the target physical address is not within the normal range.
[0013] In the above embodiment, by judging whether the bit value of the hole bit can be found in all the bit values that the preset hole bit can take, it is judged whether the bit value corresponding to the hole bit in the target physical address is within the normal range, and then it can be accurately determined whether the bit value corresponding to the hole bit in the target physical address needs to be transposed.
[0014] In combination with a possible implementation method of the first aspect, obtaining the bit value corresponding to the hole bit in the target physical address includes: obtaining the bit corresponding to the hole bit in the target physical address according to the mapping distribution of the hole bit on the physical address in the optimal address mapping table; obtaining the bit value corresponding to the bit of the hole bit in the target physical address.
[0015] In the above embodiment, according to the mapping distribution of the hole bit on the physical address in the optimal address mapping table, the bit position of the hole bit can be accurately located, and the bit value of the hole bit can be obtained according to the bit value of the bit position.
[0016] In combination with a possible implementation manner of the embodiment of the first aspect, the bit value corresponding to the hole bit in the target physical address is transposed, including: transposing the bit value corresponding to the hole bit in the target physical address with the high-order bit value in the target physical address to obtain the target physical address after transposition, wherein the number of high-order bits is consistent with the number of hole bits.
[0017] In the above embodiment, the bit value corresponding to the hole bit in the target physical address is swapped with the high-order bit value in the target physical address, so as to ensure that the target physical address after the swapping can correctly access the memory.
[0018] In combination with a possible implementation manner of the embodiment of the first aspect, the method further includes: when the answer is no, physically mapping the target to a memory granule address according to the optimal address mapping table, and accessing the memory based on the memory granule address.
[0019] In the above embodiment, when the transposition process is not required, the target can be directly physically mapped to the memory particle address according to the optimal address mapping table, which can ensure access efficiency.
[0020] In the second aspect, an embodiment of the present application also provides a memory controller, including: a hole bit preprocessing module and an address conversion module; the hole bit preprocessing module is used to receive a target physical address to be accessed, wherein the target physical address is a memory address; if there is a hole bit in the memory particle address, determine whether the bit value corresponding to the hole bit in the target physical address needs to be transposed; if yes, transpose the bit value corresponding to the hole bit in the target physical address to ensure that the target physical address after the transposition can correctly access the memory; an address conversion module is connected to the hole bit preprocessing module, and the address conversion module is used to map the target after the transposition to the memory particle address according to a preset optimal address mapping table, wherein the optimal address mapping table is an address mapping table with optimal memory access efficiency, and the memory particle address is used to access the memory.
[0021] In combination with a possible implementation manner of the embodiment of the second aspect, the hole bit preprocessing module includes: a register group and a hole bit preprocessing unit, the register group is used to store the mapping distribution of the hole bits in the optimal address mapping table on the physical address, and the preset hole bit value; the hole bit preprocessing unit is used to obtain the bit value corresponding to the hole bit in the target physical address according to the mapping distribution of the hole bits in the optimal address mapping table on the physical address stored in the register group, and determine whether the bit value corresponding to the hole bit in the target physical address needs to be transposed according to the bit value of the hole bit and the hole bit value stored in the register group.
[0022] In combination with a possible implementation manner of the second aspect embodiment, the hole bit preprocessing module is also used to send the target physical address directly to the address conversion module when the answer is no; the address conversion module is also used to physically map the target to the memory particle address according to the optimal address mapping table.
[0023] In the third aspect, an embodiment of the present application also provides a processor, comprising: an MMU and a memory controller provided in the above-mentioned second aspect embodiment and / or any possible implementation method combined with the second aspect embodiment, the MMU and the memory controller are connected, and the MMU is used to send a memory access request to the memory controller.
[0024] In a fourth aspect, an embodiment of the present application further provides an electronic device, comprising: a memory and a processor as provided in the embodiment of the third aspect above, wherein the processor is connected to the memory.
[0025] In the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone.
[0026] Other features and advantages of the present application will be described in the following description. The purpose and other advantages of the present application can be realized and obtained through the structures specifically pointed out in the written description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. The above and other purposes, features and advantages of the present application will be more clearly shown in the drawings.
[0028] Figure 1 A flow chart of a memory address mapping method provided in an embodiment of the present application is shown.
[0029] Figure 2 A module schematic diagram of a memory controller provided in an embodiment of the present application is shown.
[0030] Figure 3 A schematic diagram showing the principle of address conversion performed by a memory controller provided in an embodiment of the present application is shown.
[0031] Figure 4 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION
[0032] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, and cannot be used to limit the scope of protection of the present application. It will be appreciated by those skilled in the art that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other.
[0033] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, the terms "comprises," "comprising," or any other variation thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or apparatus that includes a series of elements includes not only those elements, but also other elements that are not explicitly listed, or also includes elements that are inherent to such process, method, article, or apparatus.
[0034] In the description of the embodiments of the present application, unless otherwise clearly specified or limited, the technical term "connection" may refer to a direct connection or an indirect connection through an intermediate medium.
[0035] In order to improve the way of handling the hole bits existing in the memory particle address in the related art, the existing access efficiency may not be optimal. The embodiment of the present application provides a memory address mapping method. When there is a hole in the memory particle address, it is determined whether the bit value corresponding to the hole bit in the target physical address needs to be transposed. When transposition is required, the bit value corresponding to the hole bit in the target physical address is transposed, and then the transposed target is physically mapped to the memory particle address according to the preset optimal address mapping table. If transposition is not required, the target is directly physically mapped to the memory particle address according to the preset optimal address mapping table. In this way, the flexibility of the hole bit mapping relationship can be maintained, which can not only solve the problem of memory particle address holes, but also take into account access efficiency.
[0036] Combine the following Figure 1 The memory address mapping method provided in the embodiment of the present application is described. The memory address mapping method can be applied to a memory controller, that is, the execution subject of the method can be a memory controller.
[0037] S1: Receive the target physical address to be accessed.
[0038] When the memory management unit (MMU) needs to access the memory, it can send a memory access request to the memory controller, where the memory access request includes the target physical address to be accessed (ie, the memory address). Memory address mapping is the mapping between the physical address and the memory particle address.
[0039] S2: If there is a hole in the memory particle address, determine whether the bit value corresponding to the hole in the target physical address needs to be transposed.
[0040] For better understanding, before introducing the implementation principle of S2, the principles of hole bits and memory address mapping involved in this application are first explained.
[0041] A hole is a bit with restrictions in the address of a memory particle. This bit cannot take any value, but can only take a partial value. The reason for the existence of a hole in the address of a memory particle is usually that the storage capacity of the memory does not meet the 2 n The relationship between them will lead to the phenomenon of discontinuous addresses, that is, address holes.
[0042] Take the three-channel HBM3 (High Bandwidth Memory) memory as an example. If the storage capacity of a single physical channel of HBM3 is: 12Gb = 1.5GB, the number of banks (storage bodies) is 48. Among them, the "b" in "12Gb" represents bit, and the "B" in "1.5GB" represents Byte. 48 banks require 6 bits to address, but in theory, 6 bits can address 64 banks. For 48 banks, as shown in Table 1, the range of bank_id is only 6'b:00 0000~10 1111(47), and B0, B1, B2, and B3 in the 6 bits can take any value of 0 or 1. However, B5 and B4 can only take the values: 2'b00, 2'b01, 2'b10, and cannot take the value 2'b11, so B5 and B4 are empty bits. Among them, Table 1 shows the values of the 6 bits corresponding to the 48 banks.
[0043] Table 1
[0044] B5 B4 B3 B2 B1 B0 0 0 0 / 1 0 / 1 0 / 1 0 / 1 0 1 0 / 1 0 / 1 0 / 1 0 / 1 1 0 0 / 1 0 / 1 0 / 1 0 / 1
[0045] If the hole bits in the memory particle address are not processed and directly mapped, the target physical address may not be able to access the memory correctly. Ignoring the influence of the hole bits, for the sake of access efficiency, if the optimal address mapping relationship is as shown in Table 2, the shaded (or gray) part in Table 2 is the hole bit, B5 and B4 are mapped to bit16 and bit15 of the physical address respectively (just an example). When accessing a physical address such as 0x18000, since the values of B5 and B4 are 2'b11 at this time, they do not exist in the memory particle address, making the above-mentioned access physical address cannot be accessed normally and needs to be skipped, which will cause the problem of discontinuous physical address.
[0046] Table 2
[0047]
[0048] Continuing with the example of a single physical channel of HBM3 with a storage capacity of 1.5GB and a bank number of 48, its physical address addressing range is: 0~31'b101 1111 1111 1111 1111 1111 11111111. It can be seen from the physical address addressing range that the highest two bits of the physical address can be at most 2'b10, and the B5 and B4 addresses are mapped to the highest bits, which can just match each other. Therefore, in order to solve the problem of being unable to access the memory normally due to address holes in the related technology, when performing memory address mapping, the hole bits in the memory particle address will be fixedly mapped to the highest bit of the physical address. The address mapping relationship at this time is shown in Table 3.
[0049] Table 3
[0050]
[0051] Although this processing method has the advantages of simple design and universal address conversion. However, from the perspective of memory access efficiency, it is not the optimal address mapping relationship. Because, for the sake of access efficiency, if the hole bit in the memory particle address is a memory particle address with a faster access speed, it should be mapped to the lower bit of the physical address as much as possible. Therefore, the method of fixedly mapping the hole bit to the highest bit of the physical address lacks flexibility and has the problem that the access efficiency may not be optimal.
[0052] Among them, for the consideration of access efficiency, the rule of memory address mapping is: the address of memory particles with fast access speed is located at the position with high memory access frequency. Therefore, under normal circumstances, the address of memory particles with faster access speed will try to map to the low-order direction of the physical address, and the address of memory particles with slower access speed will try to map to the high-order direction of the physical address. Among them, for DRAM (Dynamic Random Access Memory) memory, the memory particle address generally includes bank address, row address, column address, etc. For HBM memory, the memory particle address also includes PC (Pseudo Channel) address. Memory address mapping is the mapping of bit allocation of bank address, row address, column address, etc. on the physical address. Among them, the memory chip includes multiple banks, each bank can be regarded as a larger storage body, and each bank includes multiple rows and multiple columns. Some memory chips (such as HBM) can also include multiple physical channels.
[0053] In the above Tables 2 and 3, "B0~B5" represents the bank address, "R0~R13" represents the row address, "C0~C4" represents the column address, "PC" represents the pseudo channel address, and "BL" is the abbreviation of "Burst Length", which represents the address of the smallest storage unit (cell) of the memory particle. The address of the smallest storage unit is not limited to the 5 bits shown in Tables 2 and 3. For example, it can also be 6 bits, 8 bits, etc. Among them, the bank address is used to select a specific bank, and in the selected bank, the row address is used to select a specific row (word line). Each row contains multiple storage units, similar to a row of a matrix. The column address is used to select a specific column (bit) in the selected row, thereby locating a specific storage unit. The PC address is used to select a specific channel among multiple channels (Channel) of the memory.
[0054] The implementation principle of S2 is further described below.
[0055] After receiving the memory access request, if there is a hole in the memory particle address, the memory controller determines whether the bit value corresponding to the hole in the target physical address needs to be transposed. If yes, S3 is executed, and if no, S5 is executed.
[0056] In one possible implementation, after receiving a memory access request, the memory controller can obtain the configuration in the register group to learn whether there is a hole bit in the memory particle address. When there is a hole bit in the memory particle address, execute: the above-mentioned judgment of whether the bit value corresponding to the hole bit in the target physical address needs to be transposed. If there is no hole bit in the memory particle address, directly execute S5.
[0057] Among them, before determining whether the bit value corresponding to the hole bit in the target physical address needs to be transposed, it is necessary to first obtain the bit value corresponding to the hole bit in the target physical address. In one possible implementation, the process of obtaining the bit value corresponding to the hole bit in the target physical address may include: obtaining the bit corresponding to the hole bit in the target physical address according to the mapping distribution of the hole bit on the physical address in the optimal address mapping table; obtaining the bit value corresponding to the bit of the hole bit in the target physical address, thereby obtaining the bit value corresponding to the hole bit in the target physical address (hereinafter referred to as the bit value of the hole bit). The number of bits of the physical address in the optimal address mapping table is consistent with the number of bits of the target physical address in the memory access request.
[0058] Taking the target physical address 31'b101 1111 1111 1111 1111 1111 1111 as an example, based on the mapping distribution of the hole bits on the physical address in the optimal address mapping table shown in Table 2, it can be seen that the hole bits B5 and B4 are mapped to bit16 and bit15 of the physical address, thereby obtaining that the bit values corresponding to bit16 and bit15 are 1 and 1.
[0059] In one implementation, when determining whether the bit value corresponding to the hole bit in the target physical address needs to be transposed, the process may include: determining whether the bit value corresponding to the hole bit in the target physical address is within a normal range; wherein, if the bit value corresponding to the hole bit in the target physical address is not within the normal range, it is determined that the bit value corresponding to the hole bit in the target physical address needs to be transposed; conversely, if the bit value corresponding to the hole bit in the target physical address is within the normal range, it is determined that the bit value corresponding to the hole bit in the target physical address needs to be transposed.
[0060] In one possible implementation, when judging whether the bit value corresponding to the hole bit in the target physical address is within the normal range, the bit value corresponding to the hole bit in the target physical address can be judged based on the bit value of the hole bit and the preset hole bit value. For example, if the bit value of the hole bit and the preset hole bit value satisfy a specific relationship, it is considered that the bit value corresponding to the hole bit in the target physical address is within the normal range, and the bit value corresponding to the hole bit in the target physical address does not need to be transposed. If the bit value of the hole bit and the preset hole bit value do not satisfy the specific relationship, it is considered that the bit value corresponding to the hole bit in the target physical address is not within the normal range, and the bit value corresponding to the hole bit in the target physical address needs to be transposed. In one implementation, the specific relationship may include a numerical value size relationship or a numerical value inclusion relationship, etc.
[0061] In some possible implementations, it may be possible to determine whether the bit value of the hole bit and the preset hole bit value satisfy a preset numerical value relationship to determine whether the bit value of the hole bit in the target physical address needs to be transposed. If the preset numerical value relationship is satisfied, no transposition is required. For example, the hole bit value includes the maximum value of the hole bit, and the process of determining whether the bit value of the hole bit in the target physical address is within a normal range may include: determining the hole value corresponding to the bit value of the hole bit, and determining whether the hole value is greater than the preset maximum value of the hole bit; wherein, if the hole value is greater than the maximum value of the hole bit, the bit value of the hole bit in the target physical address is not within the normal range, and the bit value of the hole bit in the target physical address needs to be transposed; otherwise, no transposition is required.
[0062] Taking the target physical address of 31'b101 1111 1111 1111 1111 1111 1111 1111 as an example, based on the mapping distribution of the hole bits on the physical address in the optimal address mapping table shown in Table 2, it can be seen that the hole bits B5 and B4 are mapped to bit16 and bit15 of the physical address, and the bits corresponding to the hole bits in the target physical address are obtained, that is, bit16 and bit15, and the corresponding bit value is 11. Taking B5 and B4 in the above example as an example, the maximum value of the hole bit is 2 (corresponding to 2'b10). Taking the target physical address of 31'b101 1111 1111 1111 1111 1111 1111 1111 as an example, the hole value corresponding to the bit value of bit16 and bit15 is 3 (corresponding to 2'b11). Since 3 is greater than the maximum value of the hole bit 2, it is necessary to perform bit conversion processing.
[0063] In some possible implementations, it can be determined whether the bit value of the hole bit and the preset hole bit value satisfy the numerical inclusion relationship to determine whether the bit value of the hole bit in the target physical address needs to be transposed. If it is included, no transposition is required. For example, if the hole bit value includes all the bit values that the hole bit can take, then the process of determining whether the bit value of the hole bit in the target physical address is within the normal range may include: determining whether the bit value of the hole bit can be found in all the bit values that the preset hole bit can take; wherein, if the bit value of the hole bit cannot be found in the hole bit value, then the bit value of the hole bit in the target physical address is not within the normal range, and the bit value of the hole bit in the target physical address needs to be transposed; otherwise, no transposition is required.
[0064] Taking B5 and B4 as an example, based on Table 1, all the bit values that B5 and B4 can take are 2'b00, 2'b01, and 2'b10. Taking the target physical address as 31'b101 1111 1111 1111111111 1111 1111 as an example, the bit values of bit16 and bit15 are 2'b11. Since 2'b11 cannot be found in all the bit values that the hole bit can take, the bit value corresponding to the hole bit in the target physical address needs to be transposed.
[0065] It should be noted that the number of bits of the hole bit in the memory particle address is usually greater than or equal to 2 bits, and the mapping distribution of multiple bits of the hole bit on the physical address may be discontinuous. When calculating the maximum value of the hole bit, the maximum value can be calculated according to the mapping distribution of multiple bits on the physical address, in order from high to low (not limited to the above decimal). Correspondingly, when determining the hole value corresponding to the bit value of the hole bit, the bit value of the hole bit is also arranged in order from high to low to calculate the hole value. Similarly, when obtaining all the bit values that the hole bit can take, multiple bits of the hole bit can also be arranged in order from high to low.
[0066] S3: Performing bit-swapping processing on the bit values corresponding to the hole bits in the target physical address to ensure that the target physical address after the bit-swapping processing can correctly access the memory.
[0067] When determining whether a bit value corresponding to a hole bit in a target physical address needs to be transposed, the bit value corresponding to the hole bit in the target physical address is transposed to ensure that the target physical address after the transposition processing can correctly access the memory.
[0068] According to the physical address addressing range of 1.5GB storage capacity: 0~31'b101 1111 111111111 11111111 1111, it can be seen that the highest two bits of the physical address can take 2'b10 at most, and the B5 and B4 addresses are mapped to the highest bits, which can just match each other. Therefore, in a possible implementation, the process of transposing the bit value corresponding to the hole bit in the target physical address includes: transposing the bit value corresponding to the hole bit in the target physical address with the high bit value in the target physical address, and obtaining the target physical address after transposition, wherein the number of high bits is consistent with the number of hole bits.
[0069] When there are multiple hole bits, during the bit swapping process, the highest bit among the multiple hole bits may be swapped with the bit value of the highest bit in the target physical address, the second highest bit among the multiple hole bits may be swapped with the bit value of the second highest bit in the target physical address, the third highest bit among the multiple hole bits may be swapped with the bit value of the third highest bit in the target physical address, and so on, until the bit values of all the hole bits are swapped with the bit values of the high bits in the target physical address.
[0070] Taking the target physical address 31'b101 1111 1111 1111 1111 1111 1111 1111 as an example, the bits corresponding to the hole bits B5 and B4 are bit16 and bit15 respectively. After swapping the bit values of bit16 and bit15 with the bit values of the high bits, i.e., bit31 and bit30, the new target physical address is 31'b111 1111 1111 1111 011111111 1111 1111.
[0071] Take the address mapping relationship with the best access efficiency of a 1.5GB, 48-bank memory particle as an example shown in Table 4. The shaded (or gray) part in Table 4 is the distribution of the hole bits in the address mapping table.
[0072] Table 4
[0073]
[0074] Based on Table 4, it can be seen that the hole bits B5 and B4 are located at bit 16 and bit 15, and correspondingly, the normal memory particle addresses R13 and R12 are located at the high bits bit 30 and bit 29. In order to better understand the changes before and after the bit value of the hole bit is swapped with the high bit value in the target physical address, the following is explained in conjunction with Table 5.
[0075] Table 5
[0076]
[0077] For the 1.5GB addressing space 0~31'b 101 1111 1111 1111 1111 1111 11111111, there are three expected binary values of B5 and B4: 00, 01, 10; there are four binary values of R13 and R12: 00, 01, 10, 11, and there are 12 address combinations in total. Combined with the changes in the memory granule addresses before and after the hole bit preprocessing shown in Table 5:
[0078] Before hole bit preprocessing, there are four binary combinations of physical addresses that can be addressed to bit16 and bit15 (B5 and B4): 00, 01, 10, and 11; there are three binary combinations of physical addresses that can be addressed to bit30 and bit29 (R13 and R12): 00, 01, and 10. There are 12 address combinations in total, among which B5 and B4 take the value 2'b11, and R13 and R12 cannot take the value 2'b11, which are all addressing results that do not meet expectations.
[0079] After the hole bit preprocessing, there are three binary addresses that can be addressed to bit16 and bit15 (B5 and B4): 00, 01, and 10; there are four binary addresses that can be addressed to bit30 and bit29 (R13 and R12): 00, 01, 10, and 11. There are 12 address combinations in total, all of which are in line with expectations. The gray (or shaded) part in Table 5 is the part that needs to be transposed.
[0080] S4: According to a preset optimal address mapping table, physically mapping the target after the transposition processing to a memory particle address.
[0081] After obtaining the target physical address after the transposition processing, the target after the transposition processing is physically mapped to the memory particle address according to the preset optimal address mapping table, and the memory is accessed based on the memory particle address.
[0082] Among them, the optimal address mapping table is the address mapping table with the best memory access efficiency. When establishing the address mapping relationship, the influence of the hole bit can be ignored. For the sake of access efficiency, the optimal address mapping table is established according to the rule that the memory particle address with faster access speed is mapped to the low-order direction of the physical address as much as possible, and the memory particle address with slower access speed is mapped to the high-order direction of the physical address as much as possible.
[0083] S5: According to the optimal address mapping table, physically map the target to a memory particle address.
[0084] The bit value corresponding to the hole bit in the target physical address does not need to be transposed. According to the optimal address mapping table, the target is physically mapped to the memory particle address, and the memory is accessed based on the memory particle address.
[0085] The present application embodiment also provides a memory controller (Memory Controller, MC), as shown below Figure 2 The memory controller provided in the embodiment of the present application is described. The memory controller includes: a hole bit preprocessing module and an address conversion module, and the address conversion module is connected to the hole bit preprocessing module. The present application preprocesses the hole bits in the memory particle address by adding a hole bit preprocessing module. For example, when the bit value of the hole bit is within the normal range, address mapping is performed normally; when the bit value of the hole bit exceeds the normal range, the hole bit and the highest bit are swapped in sequence, and then address mapping is performed, so as to solve the address hole problem while taking into account access efficiency.
[0086] Figure 1 S1 to S3 in the memory address mapping method shown can be implemented by connecting a hole bit preprocessing module, and S4 to S5 can be implemented by an address conversion module.
[0087] Among them, the hole bit preprocessing module is used to receive the target physical address to be accessed, wherein the target physical address is a memory address; if there is a hole bit in the memory particle address, it is determined whether the bit value corresponding to the hole bit in the target physical address needs to be transposed; if so, the bit value corresponding to the hole bit in the target physical address is transposed to ensure that the target physical address after the transposition can correctly access the memory.
[0088] The address conversion module is used to physically map the transposed target to the memory particle address according to the preset optimal address mapping table, and access the memory based on the memory particle address, wherein the optimal address mapping table is an address mapping table with the best memory access efficiency. The address conversion module is preset with an address mapping table, such as the address conversion module includes a register group for storing the address mapping table. When performing address conversion, address conversion needs to be performed according to the address mapping table.
[0089] In one implementation, the hole bit preprocessing module is further used to send the target physical address directly to the address conversion module when the answer is no; the address conversion module is further used to physically map the target to the memory particle address according to the optimal address mapping table, and access the memory based on the memory particle address.
[0090] The hole bit preprocessing module may include two functions: hole bit configuration and hole bit preprocessing. In one implementation, for example, the hole bit preprocessing module includes a register group and a hole bit preprocessing unit. The related functions of the hole bit configuration are implemented by configuring the register group, and the hole bit preprocessing function is implemented by the hole bit preprocessing unit.
[0091] The register group is used to store the mapping distribution of the hole bits in the optimal address mapping table on the physical address and the preset hole bit values.
[0092] The hole bit preprocessing unit is used to obtain the bit value of the hole bit corresponding to the target physical address according to the mapping distribution of the hole bit on the physical address in the optimal address mapping table stored in the register group; and judge whether the bit value of the hole bit corresponding to the hole bit in the target physical address needs to be transposed according to the bit value of the hole bit and the hole bit value stored in the register group. In addition, the hole bit preprocessing unit is also used to transpose the bit value corresponding to the hole bit in the target physical address.
[0093] The hole bit preprocessing unit, when judging whether the bit value corresponding to the hole bit in the target physical address needs to be transposed based on the bit value of the hole bit and the hole bit value stored in the register group, can judge whether the bit value corresponding to the hole bit in the target physical address is within a normal range based on the bit value of the hole bit and the preset hole bit value, so as to determine whether the bit value corresponding to the hole bit in the target physical address needs to be transposed.
[0094] In one implementation manner, the hole bit value includes the maximum value of the hole bit, and the hole bit preprocessing unit is specifically used to determine the hole value corresponding to the bit value of the hole bit, and judge whether the hole value is greater than the preset maximum value of the hole bit; wherein, if the hole value is greater than the maximum value of the hole bit, the bit value corresponding to the hole bit in the target physical address is not within the normal range, and the bit value corresponding to the hole bit in the target physical address needs to be transposed; otherwise, no transposition is required.
[0095] In one implementation manner, the hole bit value includes all bit values that the hole bit can take, and the hole bit preprocessing unit is specifically used to determine whether the bit value of the hole bit can be found in all bit values that the preset hole bit can take; wherein, if the bit value of the hole bit cannot be found in the hole bit value, the bit value corresponding to the hole bit in the target physical address is not within a normal range, and the bit value corresponding to the hole bit in the target physical address needs to be transposed; otherwise, no transposition is required.
[0096] The above-mentioned hole bit preprocessing unit can be implemented by using a logic circuit or some programmable devices.
[0097] In one implementation, the principle of the memory controller when performing address translation can be as follows: Figure 3 As shown in the figure, after obtaining the physical address from the MMU, the hole value is calculated according to the distribution of the configured hole bits on the physical address and the input physical address, and then it is determined whether the hole value is within the configured normal range. If it is not within the normal range, the hole bit and the highest bit of the physical address are swapped in turn to obtain a new physical address. If it is within the normal range, it is directly sent to the address conversion module. The address conversion module translates the physical address from the hole bit preprocessing module into the memory particle address according to the optimal address mapping table, thereby completing the address conversion.
[0098] The implementation principle and technical effects of the memory controller embodiment are the same as those of the aforementioned method embodiment. For the sake of brief description, for matters not mentioned in the memory controller embodiment, reference may be made to the corresponding contents in the aforementioned method embodiment.
[0099] The embodiment of the present application also provides a processor, which includes a memory management unit (MMU) and the above-mentioned memory controller, the MMU is connected to the memory controller, and the MMU accesses the memory through the memory controller. For example, the MMU can send a memory access request to the memory controller to access the memory. The processor can be various general-purpose processors, embedded processors, system-on-chip (SOC) mobile device processors, server processors, etc.
[0100] In one implementation, the processor may be a general-purpose processor including a central processing unit (CPU), a network processor (NP), a graphics processing unit (GPU), an accelerated processing unit (Accelerated Processing Unit), a multimedia application processor (MAP), a microprocessor, etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. Or the processor may also be any conventional processor, etc.
[0101] The application embodiment also provides an electronic device, which includes the above-mentioned processor and memory. The memory includes but is not limited to the above-mentioned DRAM memory and HBM memory. In addition, the memory can also be replaced with other memories with storage functions. The electronic devices provided in the embodiments of the present application include but are not limited to mobile phones, tablets, notebooks, computers, servers and other devices.
[0102] In one implementation, the structural block diagram of the electronic device may be as follows: Figure 4 As shown, it includes: a transceiver, a memory, a communication bus and a processor.
[0103] The transceiver, the memory, and the processor are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these elements can be electrically connected to each other through one or more communication buses or signal lines. Among them, the transceiver is used to send and receive data. The memory is used to store data, and the data may include a computer program, such as a computer program including at least one software function module that can be stored in the memory in the form of software or firmware (Firmware) or solidified in the operating system (Operating System, OS) of the electronic device. The processor is used to execute the software function module or computer program stored in the memory. For example, the processor is used to execute the above-mentioned memory address mapping method.
[0104] Among them, the memory can be, but is not limited to, random access memory (Random Access Memory, RAM), programmable read-only memory (Programmable Read-Only Memory, PROM), erasable read-only memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable read-only memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.
[0105] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.
[0106] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.
[0107] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
[0108] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A memory address mapping method, characterized in that: include: Receiving a target physical address to be accessed, wherein the target physical address is a memory address; If there is a hole in the memory particle address, determine whether the bit value corresponding to the hole in the target physical address needs to be transposed; When the answer is yes, transpose the bit value corresponding to the hole bit in the target physical address to ensure that the target physical address after the transposition process can correctly access the memory; According to a preset optimal address mapping table, the target after the transposition process is physically mapped to a memory particle address, wherein the memory particle address is used to access the memory, and the optimal address mapping table is an address mapping table with the best memory access efficiency.
2. The method according to claim 1, characterized in that Determining whether a bit value corresponding to a hole bit in the target physical address needs to be transposed includes: Determining whether a bit value corresponding to a hole bit in the target physical address is within a normal range; If the bit value corresponding to the hole bit in the target physical address is not within a normal range, it is determined that the bit value corresponding to the hole bit in the target physical address needs to be transposed.
3. The method according to claim 2, characterized in that Determining whether a bit value corresponding to a hole bit in the target physical address is within a normal range includes: Determine a hole value corresponding to the bit value of the hole bit; Determine whether the hole value is greater than a preset maximum value of the hole bit; If the hole value is greater than the maximum value of the hole bit, the bit value corresponding to the hole bit in the target physical address is not within a normal range.
4. The method according to claim 2, characterized in that: Determining whether a bit value corresponding to a hole bit in the target physical address is within a normal range includes: Determine whether the bit value of the hole bit can be found in all the preset bit values that the hole bit can take; If the bit value of the hole bit cannot be found in all the bit values that the hole bit can take, then the bit value corresponding to the hole bit in the target physical address is not within a normal range.
5. The method according to claim 1, characterized in that Obtaining a bit value corresponding to a hole bit in the target physical address includes: According to the mapping distribution of the hole bit in the optimal address mapping table on the physical address, obtaining the bit corresponding to the hole bit in the target physical address; Obtain a bit value corresponding to the bit of the hole bit in the target physical address.
6. The method according to claim 1, characterized in that Transposing the bit value corresponding to the hole bit in the target physical address includes: The bit value corresponding to the hole bit in the target physical address is transposed with the bit value of the high bit in the target physical address to obtain the target physical address after transposition, wherein the number of high bits is consistent with the number of hole bits.
7. The method according to claim 1, characterized in that The method further comprises: When the answer is no, the target is physically mapped to the memory particle address according to the optimal address mapping table.
8. A memory controller, characterized in that: include: A hole bit preprocessing module is used to receive a target physical address to be accessed, wherein the target physical address is a memory address; if there is a hole bit in the memory particle address, determine whether the bit value corresponding to the hole bit in the target physical address needs to be transposed; if yes, transpose the bit value corresponding to the hole bit in the target physical address to ensure that the target physical address after the transposition process can correctly access the memory; An address conversion module is connected to the hole bit preprocessing module, and the address conversion module is used to physically map the target after the transposition processing to the memory particle address according to a preset optimal address mapping table, wherein the optimal address mapping table is an address mapping table with the best memory access efficiency, and the memory particle address is used to access the memory.
9. The memory controller according to claim 8, characterized in that: The hole position preprocessing module comprises: A register group, used to store the mapping distribution of the hole bits in the optimal address mapping table on the physical address, and a preset hole bit value; A hole bit preprocessing unit is used to obtain the bit value corresponding to the hole bit in the target physical address according to the mapping distribution of the hole bit on the physical address in the optimal address mapping table stored in the register group, and to determine whether the bit value corresponding to the hole bit in the target physical address needs to be transposed according to the bit value of the hole bit and the hole bit value stored in the register group.
10. The memory controller according to claim 8, characterized in that: The hole bit preprocessing module is further configured to send the target physical address directly to the address conversion module when the answer is no; The address conversion module is further used to physically map the target to a memory particle address according to the optimal address mapping table.
11. A processor, characterized in that: include: An MMU and a memory controller according to any one of claims 8 to 10, wherein the MMU and the memory controller are connected, The MMU is used to send a memory access request to the memory controller.
12. An electronic device, characterized in that: include: A memory and a processor as claimed in claim 11, wherein the processor is connected to the memory.