MCU control circuit and MCU control method

Abstract

The invention discloses an MCU control circuit and an MCU control method, the MCU control circuit comprises a processor, a low power consumption control module, an analog peripheral controller and an analog peripheral, the processor is connected with the low power consumption control module and the analog peripheral controller, and the low power consumption control module and the analog peripheral controller are connected with the analog peripheral. According to the MCU control circuit and the MCU control method, the starting of the simulation module is put in the process that the processor quits the low-power-consumption mode, so that the processor of the simulation external MCU can be automatically closed and started when entering and quitting the low-power-consumption state, and the processor is awakened after the starting of the simulation module is stable, so that the starting time of the simulation module is shortened, and the starting time of the simulation module is shortened. The processor is controlled to quit the low-power-consumption mode, so that the processor and the simulation module can start to work synchronously, the complexity of software control is reduced, and system errors caused by the fact that the simulation peripheral starts to work before being started when the processor quits the low-power-consumption mode are reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to an MCU control circuit and an MCU control method. Background Art

[0002] MCU applications generally have very high requirements for power consumption, especially battery-powered applications, which require the MCU to have various low-power modes. When the MCU enters low-power mode, in order to achieve very low power consumption, unused analog peripherals will be turned off, and then the analog peripherals will be turned on after exiting the low-power mode.

[0003] The existing analog peripherals are controlled by software, some of which are turned off before entering the low power mode and enabled after exiting the low power mode. In this way, software participation is required before and after entering the low power mode and after exiting the low power mode, which occupies the processor CPU execution time; some are controlled by hardware, and the analog peripherals are automatically turned off when the processor CPU enters the low power mode, and automatically turned on when the processor CPU wakes up. However, general analog peripherals require a certain startup time when they are turned on. Therefore, when the processor CPU is already running, these peripherals have not yet started up, resulting in system errors.

[0004] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0005] The object of the present invention is to provide an MCU control circuit and an MCU control method, which can enable analog peripherals before a processor starts running to prevent system errors.

[0006] In order to achieve the above-mentioned object, a specific embodiment of the present invention provides an MCU control circuit, comprising: a processor, a low-power control module, an analog peripheral controller and an analog peripheral, wherein the processor is connected to the low-power control module and the analog peripheral controller, and the low-power control module and the analog peripheral controller are connected to the analog peripheral;

[0007] The processor is used to generate a characterization signal that characterizes the current mode of the processor, the analog peripheral controller is used to generate a second enable signal, the low-power control module receives the characterization signal and the first wake-up signal, the low-power control module obtains the current mode of the processor based on the characterization signal and generates a first enable signal to cooperate with the second enable signal to turn off the analog peripheral or generates a first enable signal based on the first wake-up signal to cooperate with the second enable signal to turn on the analog peripheral, and generates a second wake-up signal for controlling the processor to exit the low-power mode after turning on the analog peripheral.

[0008] In one or more embodiments of the present invention, the control circuit also includes a logic control unit, which is connected to the low power control module and the analog peripheral controller, and the logic control unit receives a first enable signal and a second enable signal to generate a third enable signal for turning off or turning on the analog peripheral based on the first enable signal and the second enable signal.

[0009] In one or more embodiments of the present invention, the low power consumption control module includes a state machine, a first enabling circuit, and a second enabling circuit;

[0010] The state machine is used to jump between different states and output corresponding state signals. The first enabling circuit is connected to the state machine and the processor. The first enabling circuit generates a first enabling signal based on the characterization signal and the corresponding state signal. The second enabling circuit generates a second wake-up signal based on the characterization signal, the time count signal and the corresponding state signal.

[0011] In one or more embodiments of the present invention, the state machine outputs a first state signal when jumping to the S_ENTER state, and the first enabling circuit generates a first enabling signal based on the characterization signal and the first state signal when the processor is in a low power consumption mode to cooperate with the second enabling signal to shut down the analog peripheral;

[0012] The state machine outputs a second state signal when jumping to the S_EXIT1 state, and the first enabling circuit generates a first enabling signal based on the second state signal to cooperate with the second enabling signal to start the analog peripheral;

[0013] The state machine outputs a third state signal when jumping to the S_EXIT2 state, and the second enabling circuit generates a second wake-up signal for controlling the processor to exit the low power consumption mode based on the time counting signal and the third state signal.

[0014] In one or more embodiments of the present invention, the low power consumption control module further includes a counter, which generates a time counting signal based on a preset time from when the analog peripheral is turned on to when the processor exits the low power consumption mode.

[0015] In one or more embodiments of the present invention, the first enabling circuit includes a first AND gate, a first NOT gate, a second AND gate, a first OR gate, a first clock gating unit and a first D flip-flop, wherein the first input end of the first AND gate is used to receive a characterization signal, the second input end of the first AND gate is used to receive a first state signal, the input end of the first NOT gate is connected to the output end of the first AND gate, the first input end of the second AND gate is used to receive a second state signal, the second input end of the second AND gate is connected to the output end of the first NOT gate, the D input end of the first D flip-flop is connected to the output end of the second AND gate, the first input end of the first OR gate is connected to the output end of the first AND gate, the second input end of the first OR gate is used to receive the second state signal, the input end of the first clock gating unit is used to receive a first clock signal, the control end of the first clock gating unit is connected to the output end of the first OR gate, the clock control end of the first D flip-flop is connected to the output end of the first clock gating unit, and the Q output end of the first D flip-flop is used to output a first enabling signal.

[0016] In one or more embodiments of the present invention, the second enabling circuit includes a fifth AND gate, a second clock gating unit and a second D flip-flop, the first input end of the fifth AND gate is used to receive a time count signal, the second input end of the fifth AND gate is used to receive a third state signal, the D input end of the second D flip-flop is connected to the output end of the fifth AND gate, the input end of the second clock gating unit is used to receive a second clock signal, the control end of the second clock gating unit is connected to the output end of the fifth AND gate, the clock control end of the second D flip-flop is connected to the output end of the second clock gating unit, and the output end of the second D flip-flop is used to output a second wake-up signal; or

[0017] The second enabling circuit includes a third AND gate, a second NOT gate, a fourth AND gate, a second OR gate, a fifth AND gate, a second clock gating unit and a second D flip-flop, wherein the first input end of the third AND gate is used to receive a characterization signal, the second input end of the third AND gate is used to receive a fourth state signal, the input end of the second NOT gate is connected to the output end of the third AND gate, the first input end of the fourth AND gate is connected to the output end of the second NOT gate, the first input end of the fifth AND gate is used to receive a time counting signal, the second input end of the fifth AND gate is used to receive a third state signal, the second input end of the fourth AND gate is connected to the output end of the fifth AND gate, the D input end of the second D flip-flop is connected to the output end of the fourth AND gate, the first input end of the second OR gate is connected to the input end of the fifth AND gate, the second input end of the second OR gate is connected to the output end of the third AND gate, the input end of the second clock gating unit is used to receive a second clock signal, the control end of the second clock gating unit is connected to the output end of the second OR gate, the clock control end of the second D flip-flop is connected to the output end of the second clock gating unit, and the output end of the second D flip-flop is used to output a second wake-up signal.

[0018] The present invention also discloses an MCU control method. Based on the MCU control circuit, the control method includes:

[0019] Before the processor exits the low power consumption mode, the low power consumption control module generates a first enable signal based on the first wake-up signal to cooperate with the second enable signal generated by the analog peripheral controller to start the analog peripheral;

[0020] After the analog peripheral is turned on, the low power consumption control module generates a second wake-up signal to control the processor to exit the low power consumption mode.

[0021] In one or more embodiments of the present invention, a state machine jumps between different states and outputs corresponding state signals to control the first enabling circuit to generate a first enabling signal in low power consumption mode, and to start the analog peripherals in conjunction with the second enabling signal, and to control the second enabling circuit to generate a second wake-up signal after the analog peripherals are turned on to control the processor to exit the low power consumption mode.

[0022] In one or more embodiments of the present invention, the control method further includes:

[0023] Control the processor to enter low power consumption mode;

[0024] The characterization signal generated after the processor enters the low power consumption mode controls the low power consumption control module to generate a first enable signal to cooperate with the second enable signal generated by the analog peripheral controller to shut down the analog peripheral.

[0025] Compared with the prior art, the MCU control circuit and MCU control method of the present invention place the activation of the analog module in the process of the processor exiting the low power consumption mode, so that the analog peripherals can be automatically turned off and on when the MCU processor enters and exits the low power consumption state, and after the analog module is turned on and stabilized, the processor is woken up again to control the processor to exit the low power consumption mode, so that the processor and the analog module can start working synchronously, reducing the complexity of software control and reducing system errors caused by the analog peripherals starting to work before the startup is completed when the processor exits the low power consumption mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 4 is a circuit diagram of an MCU control circuit in an embodiment.

[0028] Figure 2 FIG. 4 is a signal timing diagram of an MCU control circuit in an embodiment.

[0029] Figure 3 FIG. 4 is a state diagram of a state machine of an MCU control circuit in an embodiment.

[0030] Figure 4 FIG. 4 is a circuit schematic diagram of a first enabling circuit in an embodiment.

[0031] Figure 5 FIG. 4 is a circuit schematic diagram of a second enabling circuit in an embodiment.

[0032] Figure 6 FIG. 4 is a flow chart of an MCU control method in an embodiment. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0034] "Coupled" or "connected" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits. In addition, in the invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0035] In the detailed description of the specification, reference is made to the accompanying drawings forming a part thereof, wherein like reference numerals refer to like parts throughout, and wherein are shown by way of exemplary embodiments that may be implemented. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered in a limiting sense.

[0036] The various operations in the specification may be described in turn as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be order-dependent. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.

[0037] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0038] Various components and devices may be referred to or shown in the singular form herein (e.g., "transistor," "transistor," "switch," etc.), but this is merely for ease of discussion, and any element referred to in the singular form may include multiple such elements in accordance with the teachings herein.

[0039] The specification describes the use of the phrases "in one embodiment" or "in other embodiments" or "in some embodiments", which may each refer to one or more of the same or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in relation to the embodiments of the present disclosure are synonymous.

[0040] like Figure 1As shown, an MCU control circuit in an embodiment of the present invention includes: a processor, a low-power control module, an analog peripheral controller, a logic control unit and analog peripherals.

[0041] Specifically, the processor is connected to the low power consumption control module and the analog peripheral controller, and the low power consumption control module and the analog peripheral controller are connected to the analog peripheral via a logic control unit. In one embodiment, the logic control unit adopts an AND logic circuit.

[0042] In one embodiment, the processor is connected to the analog peripheral controller via a bus, the processor controls the analog peripheral controller by generating a bus control signal bus, and the analog peripheral controller generates a second enable signal func_aperi_en based on the bus control signal bus.

[0043] The processor generates a characterization signal sleeping for characterizing the current mode of the processor. In one embodiment, when the characterization signal sleeping is at a low level, the processor is in a normal working state, and when the characterization signal sleeping is at a high level, the processor is in a low power consumption mode. In other embodiments, the high and low levels of the characterization signal and the working mode of the processor can also be flexibly adjusted in combination with actual circuit conditions.

[0044] The low power control module receives a characterization signal sleeping and a first wake-up signal lpwakeup. The low power control module obtains the current mode of the processor based on the characterization signal sleeping and generates a first enable signal lp_aperi_en to cooperate with the second enable signal func_aperi_en to turn off the analog peripherals when the processor is in the low power mode (that is, the characterization signal sleeping is at a high level at this time); the low power control module generates a first enable signal lp_aperi_en based on the first wake-up signal lpwakeup to cooperate with the second enable signal func_aperi_en to turn on the analog peripherals when the processor is in the low power mode, and generates a second wake-up signal cpuwakeup for controlling the processor to exit the low power mode after turning on the analog peripherals.

[0045] In one embodiment, the logic control unit receives the first enable signal lp_aperi_en and the second enable signal func_aperi_en to perform an AND logic operation on the first enable signal lp_aperi_en and the second enable signal func_aperi_en to generate a third enable signal aperi_en for turning off or on the analog peripheral. The analog peripheral can only be turned on when the first enable signal lp_aperi_en and the second enable signal func_aperi_en are both at high levels.

[0046] like Figure 2As shown, at time T1, the characterization signal sleeping is at a low level, the processor is in a normal working state, the second enable signal func_aperi_en jumps to a high level, the first enable signal lp_aperi_en is at a high level, and the third enable signal aperi_en is also at a high level, thereby turning on the analog peripherals.

[0047] At time T2, the characterization signal sleeping starts to jump to a high level, and the surface processor starts to enter a low power consumption mode. Correspondingly, the first enable signal lp_aperi_en also jumps to a low level, thereby making the third enable signal aperi_en a low level, thereby shutting down the analog peripherals.

[0048] At time T3, the first wake-up signal lpwakeup jumps to a high level, and the analog peripherals are not turned on immediately. Instead, at time T4, the first enable signal lp_aperi_en jumps to a high level (the second enable signal func_aperi_en has been a high level since time T2), thereby causing the third enable signal aperi_en to also jump to a high level, thereby turning on the analog peripherals.

[0049] The analog peripherals are turned on from time T4, and then at time T5, the second wake-up signal cpuwakeup jumps to a high level (the high level is a valid signal of the second wake-up signal cpuwakeup), thereby waking up the processor and controlling the processor to exit the low power consumption mode and enter the normal working mode.

[0050] In one embodiment, the low power consumption control module includes a state machine, a counter, a first enabling circuit and a second enabling circuit.

[0051] The counter generates a time counting signal aperi_start_time based on a preset time from when the analog peripheral is turned on to when the processor exits the low power consumption mode. The time from time T4 to time T5 can be controlled by the counter.

[0052] The state machine is used to jump between different states and output corresponding state signals, such as Figure 3As shown, in one embodiment, the states of the state machine include S_RUN state, S_ENTER state, S_LP state, S_EXIT0 state, S_EXIT1 state and S_EXIT2 state, and the state machine jumps in these states in sequence. When the characterization signal sleeping flips to a high level (sleeping=1), the state machine jumps from the S_RUN state to the S_ENTER state, and when the state machine is in the S_RUN state, it indicates that the processor is in a normal working state; when the first wake-up signal lpwakeup flips to a high level (lpwakeup=1), the state machine jumps from the S_LP state to the S_EXIT0 state; when the time counting signal aperi_start_time flips to a high level (aperi_start_cnt=aperi_start_time, aperi_start_cnt is a counter), the state machine flips from the S_EXIT2 state to the S_RUN state.

[0053] In addition Figure 3 In the figure, enter_seq_done, enter_seq1_done and enter_seq2_done are represented as indication signals for completion of memory, power supply and clock, that is, when the indication signal enter_seq_done is high level (enter_seq_done=1), the indication signal enter_seq1_done is high level (enter_seq1_done=1) and the indication signal enter_seq2_done is high level (enter_seq2_done=1), it indicates that the memory, power supply and clock are established and can work normally, and the state machine also performs state jumps based on the indication signals. The establishment order of the memory, power supply and clock can be changed as needed, that is, the state machine performs state jumps based on each indication signal, which can correspond to different establishment orders of the memory, power supply and clock.

[0054] When the state machine jumps to each state, a corresponding state signal is generated. When the state machine jumps to the S_ENTER state, the state machine outputs the first state signal state1. When the processor is in low power consumption mode (sleeping=1), the first enabling circuit generates a first enabling signal lp_aperi_en based on the characterization signal sleeping and the first state signal state1 to cooperate with the second enabling signal func_aperi_en to shut down the analog peripherals.

[0055] The state machine outputs the second state signal state2 when jumping to the S_EXIT1 state. The first enabling circuit generates the first enabling signal lp_aperi_en based on the second state signal state2 to cooperate with the second enabling signal func_aperi_en to enable the analog peripheral.

[0056] The state machine outputs a third state signal state3 when jumping to the S_EXIT2 state, and the second enabling circuit generates a second wake-up signal cpuwakeup for controlling the processor to exit the low power consumption mode based on the time counting signal aperi_start_time and the third state signal.

[0057] The state machine outputs a fourth state signal state4 when jumping to the S_RUN state.

[0058] The first enabling circuit is connected to the state machine and the processor, and generates a first enabling signal lp_aperi_en based on the characterization signal sleeping and the corresponding state signal. The second enabling circuit generates a second wake-up signal cpuwakeup based on the characterization signal sleeping, the time counting signal aperi_start_time and the corresponding state signal.

[0059] like Figure 4 As shown, the first enabling circuit includes a first AND gate AND1, a first NOT gate A1, a second AND gate AND2, a first OR gate OR1, a first clock gating unit CKG1 and a first D flip-flop D1.

[0060] The first input end of the first AND gate AND1 is used to receive the characterization signal sleeping, the second input end of the first AND gate AND1 is used to receive the first state signal state1, the input end of the first NOT gate A1 is connected to the output end of the first AND gate AND1, the first input end of the second AND gate AND2 is used to receive the second state signal state2, the second input end of the second AND gate AND2 is connected to the output end of the first NOT gate A1, the D input end of the first D flip-flop D1 is connected to the output end of the second AND gate AND2, the first input end of the first OR gate OR1 is connected to the output end of the first AND gate AND1, the second input end of the first OR gate OR1 is used to receive the second state signal state2, the input end of the first clock gating unit CKG1 is used to receive the first clock signal clock1, the control end of the first clock gating unit CKG1 is connected to the output end of the first OR gate OR1, the clock control end of the first D flip-flop D1 is connected to the output end of the first clock gating unit CKG1, and the Q output end of the first D flip-flop D1 is used to output the first enable signal lp_aperi_en.

[0061] When the processor enters low power mode (sleeping = 1), the state machine jumps from the S_RUN state to the S_ENTER state (state1 = 1). At this time, other state signals can be considered to be low level (0), the output of the second AND gate AND2 is 0, the output of the first OR gate OR1 is 1, and the first enable signal lp_aperi_en output from the Q output terminal of the first D flip-flop D1 is low level, thereby turning off the analog peripherals. At this time, it is equivalent to Figure 3 The T2 moment in .

[0062] When the state machine jumps from the S_ENTER state to the S_LP state, it is equivalent to Figure 3 At time T3 in FIG. 1 , when the first wake-up signal lpwakeup turns to a high level, the state machine turns again from the S_LP state.

[0063] When the state machine jumps to the S_EXIT1 state (state2=1), the output of the second AND gate AND2 is 1, the output of the first OR gate OR1 is 1, and the first enable signal lp_aperi_en outputted from the Q output terminal of the first D flip-flop D1 is 1, thereby turning on the analog peripherals. Figure 3 The T4 moment in the game.

[0064] In other embodiments, the first wake-up signal lpwakeup being turned to a high level can be used as a condition for any state transition between the S_ENTER state and the S_EXIT2 state as needed.

[0065] like Figure 5As shown, the second enabling circuit includes a third AND gate AND3, a second NOT gate A2, a fourth AND gate AND4, a second OR gate OR2, a fifth AND gate AND5, a second clock gating unit CKG2, and a second D flip-flop D2. The first input end of the third AND gate AND3 is used to receive the characterization signal sleeping, the second input end of the third AND gate AND3 is used to receive the fourth state signal, the input end of the second NOT gate A2 is connected to the output end of the third AND gate AND3, the first input end of the fourth AND gate AND4 is connected to the output end of the second NOT gate A2, the first input end of the fifth AND gate AND5 is used to receive the time counting signal aperi_start_time, the second input end of the fifth AND gate AND5 is used to receive the third state signal, the second input end of the fourth AND gate AND4 is connected to the output end of the fifth AND gate AND5, and the second D flip-flop The D input end of the device D2 is connected to the output end of the fourth AND gate AND4, the first input end of the second OR gate OR2 is connected to the input end of the fifth AND gate AND5, the second input end of the second OR gate OR2 is connected to the output end of the third AND gate AND3, the input end of the second clock gating unit CKG2 is used to receive the second clock signal clock2, the control end of the second clock gating unit CKG2 is connected to the output end of the second OR gate OR2, the clock control end of the second D flip-flop D2 is connected to the output end of the second clock gating unit CKG2, and the output end of the second D flip-flop D2 is used to output the second wake-up signal cpuwakeup.

[0066] When the state machine is in the S_EXIT2 state (state3=1), and the counter aperi_start_cnt counts to a certain value and generates a time counting signal aperi_start_time (aperi_start_time=1), the fifth AND gate AND5 outputs 1, the fourth AND gate AND4 outputs 1 (sleeping=1, state4=0), the second OR gate OR2 outputs 1, and the second wake-up signal cpuwakeup outputted from the Q output terminal of the second D flip-flop D2 is 1, thereby waking up the processor and controlling the processor to exit the low power mode and enter the normal working mode. At this time, it is equivalent to Figure 3 At time T5 in the example, the count of the counter aperi_start_cnt can control how long it takes to wake up the processor after the analog peripherals are turned on, thereby ensuring that the processor is woken up after the analog peripherals are turned on and stabilized.

[0067] When the time counting signal aperi_start_time is at a high level, the state machine jumps from the S_EXIT2 state to the S_RUN state (state4=1, aperi_start_time=0, state3=0), and when the processor exits the low power mode (sleeping=0), the output of the fourth AND gate AND4 is 0, the output of the second OR gate OR2 is 0, and the second wake-up signal cpuwakeup output from the Q output end of the second D flip-flop D2 jumps to 0, thereby preventing the second wake-up signal cpuwakeup from being 1 all the time and being in the state of waking up the processor all the time, wasting resources.

[0068] like Figure 6 As shown, the present invention also discloses an MCU control method. Based on the above MCU control circuit, the control method includes:

[0069] The processor is controlled to enter the low power consumption mode. In one embodiment, a software program is used to control the processor to enter the low power consumption mode. In other embodiments, the processor can also be controlled to enter the low power consumption mode by a hardware structure.

[0070] The characterization signal sleeping generated after the processor enters the low power mode controls the low power control module to generate the first enable signal lp_aperi_en to cooperate with the second enable signal func_aperi_en generated by the analog peripheral controller to turn off the analog peripheral. That is, after the processor enters the low power mode, the characterization signal sleeping output by the processor is high level, and the low power control module generates a low level first enable signal lp_aperi_en based on the characterization signal sleeping, thereby cooperating with the second enable signal func_aperi_en to turn off the analog peripheral.

[0071] After the processor enters the low power consumption mode, the clock, the storage module and the power supply may be processed so that the clock, the storage module and the power supply enter the low power consumption mode in a required sequence.

[0072] In the process of waking up the processor, before the processor exits the low power mode, the low power control module generates a first enable signal lp_aperi_en based on the first wake-up signal lpwakeup to cooperate with the second enable signal func_aperi_en generated by the analog peripheral controller to turn on the analog peripheral. That is, when the processor is in the low power mode, the first wake-up signal lpwakeup will jump to a high level, indicating that the processor is to be woken up. Before waking up the processor, the low power control module generates a high-level first enable signal lp_aperi_en to cooperate with the high-level second enable signal func_aperi_en to turn on the analog peripheral.

[0073] Before the processor exits the low power consumption mode, the clock, the storage module, and the power supply may be processed so that the clock, the storage module, and the power supply exit the low power consumption mode in a required order.

[0074] After the analog peripherals are turned on, the low power control module generates a second wake-up signal cpuwakeup to control the processor to exit the low power mode. That is, after the analog peripherals are turned on and stabilized, the low power control module generates a high-level second wake-up signal cpuwakeup to wake up the processor, control the processor to exit the low power mode, and make the processor and the analog peripherals start working at the same time.

[0075] In one embodiment, the analog peripheral device may be an analog-to-digital converter ADC. In an application in which the analog-to-digital converter ADC regularly measures changes in external signals at regular intervals, the MCU may be awakened by a timer to perform measurements, and then enter a low-power state after the measurements are completed. After the MCU exits the low-power state and the processor is awakened, the analog-to-digital converter ADC may be directly triggered to convert and obtain measurement results through a program. After the program is processed, the MCU enters a low-power state, and the above-mentioned control circuit may automatically control the shutdown and enabling of the analog-to-digital converter ADC.

[0076] The state machine jumps between different states and outputs corresponding state signals to control the first enabling circuit to generate the first enabling signal lp_aperi_en in low power consumption mode, and cooperate with the second enabling signal func_aperi_en to turn on the analog peripherals, and after the analog peripherals are turned on, control the second enabling circuit to generate the second wake-up signal cpuwakeup to control the processor to exit the low power consumption mode.

[0077] In one embodiment, when the first enable signal lp_aperi_en is at a low level and when it is at a high level, and when the second wake-up signal cpuwakeup is at a high level, are mainly configured by the state signal generated by the state jump of the state machine, and the timing of each signal is configured by the state jump of the state machine. For details, please refer to the description of the circuit.

[0078] Those skilled in the art should know that, for the purpose of illustration in this application, each trigger signal is assigned a high level or low level state corresponding to a corresponding control state, but in other embodiments, when the logic circuit changes, the corresponding relationship between the level of the trigger signal and the control state will change accordingly. Technical solutions that use control signals with the same functions as those of this application to change the circuit state should fall within the scope of protection of this application, and should not be limited to the corresponding relationship between the level of a certain signal and the control state.

[0079] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0080] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. An MCU control circuit, characterized in that: include: A processor, a low-power control module, an analog peripheral controller and an analog peripheral, wherein the processor is connected to the low-power control module and the analog peripheral controller, and the low-power control module and the analog peripheral controller are connected to the analog peripheral; The processor is used to generate a characterization signal that characterizes the current mode of the processor, the analog peripheral controller is used to generate a second enable signal, the low-power control module receives the characterization signal and the first wake-up signal, the low-power control module obtains the current mode of the processor based on the characterization signal and generates a first enable signal to cooperate with the second enable signal to turn off the analog peripheral or generates a first enable signal based on the first wake-up signal to cooperate with the second enable signal to turn on the analog peripheral, and generates a second wake-up signal for controlling the processor to exit the low-power mode after turning on the analog peripheral.

2. The MCU control circuit according to claim 1, characterized in that: The control circuit also includes a logic control unit, which is connected to the low-power control module and the analog peripheral controller. The logic control unit receives a first enable signal and a second enable signal to generate a third enable signal for turning off or turning on the analog peripheral based on the first enable signal and the second enable signal.

3. The MCU control circuit according to claim 1, characterized in that: The low power consumption control module includes a state machine, a first enabling circuit and a second enabling circuit; The state machine is used to jump between different states and output corresponding state signals. The first enabling circuit is connected to the state machine and the processor. The first enabling circuit generates a first enabling signal based on the characterization signal and the corresponding state signal. The second enabling circuit generates a second wake-up signal based on the characterization signal, the time count signal and the corresponding state signal.

4. The MCU control circuit according to claim 3, characterized in that: The state machine outputs a first state signal when jumping to the S_ENTER state, and the first enabling circuit generates a first enabling signal based on the characterization signal and the first state signal when the processor is in a low power consumption mode to cooperate with the second enabling signal to shut down the analog peripheral; The state machine outputs a second state signal when jumping to the S_EXIT1 state, and the first enabling circuit generates a first enabling signal based on the second state signal to cooperate with the second enabling signal to start the analog peripheral; The state machine outputs a third state signal when jumping to the S_EXIT2 state, and the second enabling circuit generates a second wake-up signal for controlling the processor to exit the low power consumption mode based on the time counting signal and the third state signal.

5. The MCU control circuit according to claim 3, characterized in that: The low power consumption control module further includes a counter, which generates a time counting signal based on a preset time from when the analog peripheral is turned on to when the processor exits the low power consumption mode.

6. The MCU control circuit according to claim 3, characterized in that: The first enabling circuit includes a first AND gate, a first NOT gate, a second AND gate, a first OR gate, a first clock gating unit and a first D flip-flop, wherein the first input end of the first AND gate is used to receive a characterization signal, the second input end of the first AND gate is used to receive a first state signal, the input end of the first NOT gate is connected to the output end of the first AND gate, the first input end of the second AND gate is used to receive a second state signal, the second input end of the second AND gate is connected to the output end of the first NOT gate, the D input end of the first D flip-flop is connected to the output end of the second AND gate, the first input end of the first OR gate is connected to the output end of the first AND gate, the second input end of the first OR gate is used to receive the second state signal, the input end of the first clock gating unit is used to receive a first clock signal, the control end of the first clock gating unit is connected to the output end of the first OR gate, the clock control end of the first D flip-flop is connected to the output end of the first clock gating unit, and the Q output end of the first D flip-flop is used to output a first enabling signal.

7. The MCU control circuit according to claim 3, characterized in that: The second enabling circuit includes a fifth AND gate, a second clock gating unit, and a second D flip-flop, wherein the first input end of the fifth AND gate is used to receive a time counting signal, the second input end of the fifth AND gate is used to receive a third state signal, the D input end of the second D flip-flop is connected to the output end of the fifth AND gate, the input end of the second clock gating unit is used to receive a second clock signal, the control end of the second clock gating unit is connected to the output end of the fifth AND gate, the clock control end of the second D flip-flop is connected to the output end of the second clock gating unit, and the output end of the second D flip-flop is used to output a second wake-up signal; or The second enabling circuit includes a third AND gate, a second NOT gate, a fourth AND gate, a second OR gate, a fifth AND gate, a second clock gating unit and a second D flip-flop, wherein the first input end of the third AND gate is used to receive a characterization signal, the second input end of the third AND gate is used to receive a fourth state signal, the input end of the second NOT gate is connected to the output end of the third AND gate, the first input end of the fourth AND gate is connected to the output end of the second NOT gate, the first input end of the fifth AND gate is used to receive a time counting signal, the second input end of the fifth AND gate is used to receive a third state signal, the second input end of the fourth AND gate is connected to the output end of the fifth AND gate, the D input end of the second D flip-flop is connected to the output end of the fourth AND gate, the first input end of the second OR gate is connected to the input end of the fifth AND gate, the second input end of the second OR gate is connected to the output end of the third AND gate, the input end of the second clock gating unit is used to receive a second clock signal, the control end of the second clock gating unit is connected to the output end of the second OR gate, the clock control end of the second D flip-flop is connected to the output end of the second clock gating unit, and the output end of the second D flip-flop is used to output a second wake-up signal.

8. A MCU control method, characterized in that: Based on the MCU control circuit according to any one of claims 1 to 7, the control method comprises: Before the processor exits the low power consumption mode, the low power consumption control module generates a first enable signal based on the first wake-up signal to cooperate with the second enable signal generated by the analog peripheral controller to start the analog peripheral; After the analog peripheral is turned on, the low power consumption control module generates a second wake-up signal to control the processor to exit the low power consumption mode.

9. The MCU control method according to claim 8, characterized in that: The state machine jumps between different states and outputs corresponding state signals to control the first enabling circuit to generate a first enabling signal in low power consumption mode, and to start the analog peripherals in conjunction with the second enabling signal, and to control the second enabling circuit to generate a second wake-up signal after the analog peripherals are turned on to control the processor to exit the low power consumption mode.

10. The MCU control method according to claim 8, characterized in that: The control method further comprises: Control the processor to enter low power consumption mode; The characterization signal generated after the processor enters the low power consumption mode controls the low power consumption control module to generate a first enable signal to cooperate with the second enable signal generated by the analog peripheral controller to shut down the analog peripheral.

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