Hardware acceleration processing system and data exchange request sending method

Abstract

The embodiment of the invention provides a hardware acceleration processing system and a data exchange request sending method, the hardware acceleration processing system comprises: M first target engines used for sending a data exchange request to a bus interconnection structure, M being a positive integer; the bus interconnection structure is connected with the M first target engines and used for dispatching and sending data exchange requests sent by the M first target engines to N slave nodes, and N is a positive integer; and the N slave nodes are connected with the bus interconnection structure and are used for receiving a data exchange request sent by the bus interconnection structure and sending a data exchange result corresponding to the data exchange request to the M first target engines through the bus interconnection structure.

Description

Technical Field

[0001] The embodiments of the present application relate to the computer field, and in particular, to a hardware acceleration processing system and a method for sending a data exchange request. Background Art

[0002] In current high-performance storage systems, non-volatile memories (such as solid-state drives (SSDs)) communicate with the host through the PCI Express (PCIe) interface. NVMe (Non-Volatile Memory Express) is an optimized protocol designed to fully utilize the high-speed performance of SSDs, reduce latency, and increase data transfer rates. However, while achieving high-performance data transmission, the NVMe protocol places high demands on the host CPU. During the NVMe command processing process, the host needs to manage and convert the PRP (Physical Region Range), maintain the SQ (Submission Queue) and CQ (Completion Queue), and notify the disk controller to fetch instructions through the doorbell register, etc. This not only consumes precious CPU resources, but also limits the overall throughput and performance of the system.

[0003] Especially in large-scale system-on-chip (SoC), the increase in the number of NVMe engines is accompanied by higher bus access requirements. Since the traditional AXI bus arbitration mechanism uses polling or priority to allocate bus usage rights, when multiple Master components (such as various modules of the NVMe engine) compete for limited AXI bus resources at the same time, the bus access efficiency becomes low. Specifically, when each Master accesses different Slave components, it must wait for the previous bus access operation to complete before starting the next operation. This serial wait greatly affects the response speed and overall performance of the system. What's more, if the response time of some Slave components is much longer than that of other components, the performance of the overall system will be limited by the slowest component, forming the so-called "bottleneck effect".

[0004] This problem is particularly prominent in the specific implementation of the NVMe protocol, because NVMe command processing involves multiple stages, each of which requires frequent bus access, including data reading and writing, queue updating, interrupt processing, etc. Therefore, how to optimize the use of the AXI bus, improve the efficiency of NVMe command processing, and reduce the burden on the host CPU has become an urgent problem to be solved in the current technical field.

[0005] In the related art, since the AXI buses of different slaves (slave nodes) are intertwined, it is necessary to wait for a bus response to complete before responding to the next request, resulting in a technical problem that the overall slave response speed is too slow. No effective solution has been proposed yet. Summary of the invention

[0006] An embodiment of the present application provides a hardware acceleration processing system and a method for sending a data exchange request, so as to at least solve the problem in the related art that, because the AXI buses of different Slaves (slave nodes) are intertwined, it is necessary to wait for a bus response to be completed before responding to the next request, resulting in the overall Slave response speed being too slow.

[0007] According to one embodiment of the present application, a hardware acceleration processing system is provided, comprising: M first target engines, used to send data exchange requests to a bus interconnection structure, wherein M is a positive integer; the bus interconnection structure is connected to the M first target engines, and is used to schedule the data exchange requests sent by the M first target engines to be sent to N slave nodes, wherein N is a positive integer; the N slave nodes are connected to the bus interconnection structure, and are used to receive the data exchange requests sent by the bus interconnection structure, and send the data exchange results corresponding to the data exchange requests to the M first target engines through the bus interconnection structure.

[0008] In an exemplary embodiment, the second target engine among the M first target engines includes: T host nodes, used to send data exchange requests to the N slave nodes, wherein T is a positive integer; N first arbitration components, each first arbitration component is connected to t first host nodes, and the N first arbitration components are connected to the bus interconnection structure, each first arbitration component is used to arbitrate the sending order of the data exchange requests sent by the t first host nodes, and send the t data exchange requests to the first slave node in sequence through the bus interconnection structure according to the sending order, wherein the T host nodes include the t first host nodes, the N slave nodes include the first slave node, the data exchange objects of the t first host nodes are all the first slave nodes, and t is a positive integer.

[0009] In an exemplary embodiment, the bus interconnection structure includes: N second arbitration components, each second arbitration component is connected to a first arbitration component in m third target engines, and the N second arbitration components are connected to the N slave nodes in a one-to-one correspondence, and the target second arbitration component in the N second arbitration components is used to arbitrate the processing order of data exchange requests sent by m first arbitration components in the m third target engines according to the response time, and send the m data exchange requests to the second slave node connected to the target second arbitration component in sequence according to the processing order, wherein m is a positive integer, the M first target engines include the m third target engines, and the response time is the response time of the second slave node to the m data exchange requests.

[0010] In an exemplary embodiment, the target first arbitration component among the N first arbitration components is used to: receive t data exchange requests sent by the t first host nodes; arbitrate the sending order of the t data exchange requests through an arbitration algorithm to obtain the sending order; determine the second host node to which the data exchange request is currently to be sent according to the sending order, and send an authorization signal to the second host node, wherein the authorization signal is used to instruct the second host node to send the data exchange request; when it is determined that the high-level interface bus corresponding to the second host node is idle, send the authorization signal to the next first host node among the t first host nodes according to the sending order.

[0011] In an exemplary embodiment, the fourth target engine among the M first target engines comprises: T host nodes, used to send data exchange requests to the N slave nodes, wherein T is a positive integer; P third arbitration components, each third arbitration component is connected to I third host node, and the P third arbitration components are connected to P request initiation components in a one-to-one correspondence, and the target third arbitration component among the P third arbitration components is used to arbitrate the initiation order of I data exchange requests sent by the I third host node to obtain the initiation order, wherein P and I are both positive integers, the T host nodes include the I third host node, and the data exchange objects of the I third host node are all third slave nodes; the target request initiation component among the P request initiation components is connected to the N first arbitration components The fourth arbitration component in the bus interconnection structure is connected to send the I data exchange requests to the fourth arbitration component according to the initiation order, wherein the fourth arbitration component corresponds to the third slave node; the N first arbitration components, each of which is connected to p request initiating components and k fourth host nodes, and the N first arbitration components are connected to the bus interconnection structure, the fourth arbitration component is used to arbitrate the sending order of the p request initiating components and the k fourth host nodes to send the data exchange requests, and send p+k data exchange requests to the third slave node in sequence through the bus interconnection structure according to the sending order, wherein p and k are both positive integers, the P request initiating components include the p request initiating components, and the T host nodes include the k fourth host nodes.

[0012] In an exemplary embodiment, the T host nodes include: a task receiving processing module, which is used to receive the first task information sent by the task scheduling management engine, wherein the task scheduling management engine is used to manage the M first target engines; an address acquisition module, which is connected to the task receiving processing module, and is used to acquire the starting address information from the first task information, wherein the starting address information includes: the starting address information of the HPRP and the starting address information of the CPRP; a data handling module, which is connected to the address acquisition module, and is used to write the CPR data corresponding to the starting address information into the physical memory area; an SQE sending management module, which is connected to the data handling module, and is used to write the SQE command into the physical memory area; an SQE pointer management module, which is connected to the SQE sending management module, and is used to write the SQE pointer into the first register to instruct the first target engine to acquire the SQE command and the CPRP data in the physical memory area according to the SQE pointer, and generate a target command according to the SQE command and the CPRP data; a CQE receiving management module, which is connected to the PC le controller is connected to receive the command execution result of the target command, wherein the PCIe controller is used to execute the target command; a CQE pointer management module is connected to the CQE receiving management module, and is used to write the CQE pointer into the second register to indicate that the execution of the target command of the first target engine is completed.

[0013] In an exemplary embodiment, the data handling module includes: a data reading module, connected to the address acquisition module, for reading HPRP data according to the starting address information of the HPRP, and reading first CPRP data according to the starting address information of the CPRP; a data conversion module, connected to the data reading module, for converting the HPRP data into second CPRP data; a data writing module, connected to the address acquisition module and the data conversion module, for writing the first CPRP data and the second CPRP data into the physical memory area, wherein the CPRP data includes the first CPRP data and the second CPRP data.

[0014] According to another embodiment of the present application, a method for sending a data exchange request is provided, comprising: receiving data exchange requests sent by M first target engines, where M is a positive integer; scheduling the data exchange requests sent by the M first target engines to be sent to N slave nodes, where N is a positive integer; and sending data exchange results corresponding to the data exchange requests sent by the N slave nodes to the M first target engines.

[0015] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0016] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0017] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps of the method described in each embodiment of the present application are implemented.

[0018] Through the present application, during the operation of the M first target engines in the hardware acceleration processing system, data exchange requests will be sent to the bus interconnection structure, where M is a positive integer; the bus interconnection structure is connected to the M first target engines, and is used to schedule the data exchange requests sent by these first target engines to be sent to N slave nodes, where N is a positive integer; the slave nodes are connected to the bus interconnection structure, and are used to receive the data exchange requests sent by the bus interconnection structure, and send the corresponding data exchange results to the M first target engines through the bus interconnection structure; through the above system, a bus interconnection structure is introduced to complete the data exchange between multiple hosts and multiple slaves in multiple engines, thereby solving the problem in the related art that, because the AXI buses of different Slaves (slave nodes) are intertwined, it is necessary to wait for a bus response to be completed before responding to the next request, resulting in the overall Slave response speed being too slow. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a hardware structure block diagram of a computer terminal according to a method for sending a data exchange request in an embodiment of the present application;

[0020] Figure 2 is a structural block diagram of a hardware acceleration processing system according to an embodiment of the present application;

[0021] Figure 3 1 is a schematic diagram of the structure of an optional NVMe engine according to an embodiment of the present application (I);

[0022] Figure 4 This is a schematic diagram of an optional AXI arbitration process according to an embodiment of the present application (I);

[0023] Figure 5 This is a schematic diagram (II) of an optional AXI arbitration process according to an embodiment of the present application;

[0024] Figure 6 2 is a schematic diagram of the structure of an optional NVMe engine according to an embodiment of the present application (II);

[0025] Figure 7 is a schematic structural diagram of an optional NVMe hardware acceleration processing device according to an embodiment of the present application;

[0026] Figure 8 It is a structural schematic diagram of an optional NVMe engine according to an embodiment of the present application (III);

[0027] Fig. 9 It is a flowchart of a method for sending a data exchange request according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0030] The method embodiments provided in the embodiments of the present application can be executed in a computer terminal or a similar computing device. Taking running on a computer terminal as an example, Figure 1 FIG. 1 is a hardware structure block diagram of a computer terminal for sending a data exchange request according to an embodiment of the present application. Figure 1 As shown, the computer terminal may include one or more ( Figure 1 Only one is shown in the figure) processor 102 (processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the computer terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above-mentioned computer terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0031] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for sending a data exchange request in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory arranged relative to the processor 102 process, and these process memories may be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0032] The transmission device 106 is used to receive or send data through a network. The specific example of the above network may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0033] The following is an explanation of the technical terms that appear in this application:

[0034] NVMe (Non Volatile Memory Host Controller Interface Specification), or non-volatile memory host controller interface specification, is a logical device interface specification used to access non-volatile memory media attached through the PCI Express (PCIe) bus.

[0035] SSD (Solid State Drives): solid state drive;

[0036] AXI (Advanced eXtensible Interface) is a bus protocol;

[0037] PCIe (Peripheral Component Interconnect Express), a high-speed serial computer expansion bus standard.

[0038] PRP (physical region range) refers to the physical region page. PRP entry describes the starting address of a continuous physical memory. If you need to describe several discontinuous physical memories, you need several PRP entries; linking several PRP entries together forms a PRP list.

[0039] HPRP (Host PRP): Host PRP List;

[0040] CPRP (Client PRP): used to send the PRP List to the disk;

[0041] SQ (submission queue): submission queue;

[0042] SQE (submission queue entry): submission queue entry;

[0043] SQT (submission tail pointer): submission queue tail pointer;

[0044] CQ (completion queue): completion queue;

[0045] CQE (completion queue entry): completion queue entry;

[0046] CQH (completion queue header pointer): completion queue head pointer.

[0047] In this embodiment, a hardware acceleration processing system is provided. Figure 2 is a structural block diagram of a hardware acceleration processing system according to an embodiment of the present application, such as Figure 2 As shown, the system includes:

[0048] M first target engines 22, used to send data exchange requests to the bus interconnection structure 24, where M is a positive integer;

[0049] The bus interconnection structure 24 is connected to the M first target engines 22, and is used to schedule the data exchange requests sent by the M first target engines 22 to N slave nodes 26, where N is a positive integer;

[0050] The N slave nodes 26 are connected to the bus interconnection structure 24 , and are used to receive data exchange requests sent by the bus interconnection structure 24 , and send data exchange results corresponding to the data exchange requests to the M first target engines 22 through the bus interconnection structure 24 .

[0051] Through the above system, during the operation of the M first target engines in the hardware acceleration processing system, data exchange requests will be sent to the bus interconnection structure, where M is a positive integer; the bus interconnection structure is connected to the M first target engines, and is used to schedule the data exchange requests sent by these first target engines to be sent to N slave nodes, where N is a positive integer; the slave nodes are connected to the bus interconnection structure, and are used to receive the data exchange requests sent by the bus interconnection structure, and send the corresponding data exchange results to the M first target engines through the bus interconnection structure; through the above system, the bus interconnection structure is introduced to complete the data exchange between multiple hosts and multiple slaves in multiple engines, thereby solving the problem in the related art that, because the AXI buses of different Slaves (slave nodes) are intertwined, it is necessary to wait for a bus response to be completed before responding to the next request, resulting in the overall Slave response speed being too slow.

[0052] In an exemplary embodiment, the second target engine among the M first target engines includes: T host nodes, used to send data exchange requests to the N slave nodes, wherein T is a positive integer; N first arbitration components, each first arbitration component is connected to t first host nodes, and the N first arbitration components are connected to the bus interconnection structure, each first arbitration component is used to arbitrate the sending order of the data exchange requests sent by the t first host nodes, and send the t data exchange requests to the first slave node in sequence through the bus interconnection structure according to the sending order, wherein the T host nodes include the t first host nodes, the N slave nodes include the first slave node, the data exchange objects of the t first host nodes are all the first slave nodes, and t is a positive integer.

[0053] In an optional embodiment, the structure of the NVMe engine (i.e., the second target engine) is as follows: Figure 3 As shown, it includes: T host nodes and N first arbitration components, wherein each first arbitration component is connected to t first host nodes through an AXI bus, and the t first host nodes connected to each first arbitration component have the same object (i.e., the above-mentioned first slave node) to which the data exchange request is to be sent, and the first arbitration component is used to arbitrate the connected t first host nodes, determine the sending order of the data exchange requests sent by the t first host nodes, and then the first arbitration component controls the first host nodes to send the data exchange requests in sequence according to the sending order.

[0054] In this embodiment, according to the different targets accessed by different AXI buses, the bus topology structures inside and outside the IP are optimized respectively. At the IP level: a single AXI interface is expanded into multiple AXI interfaces with different targets at the IP port; inside the IP, the hardware modules (i.e., host nodes) with the same AXI bus access target are sent to different AXI interfaces through a target arbitration component (i.e., the first arbitration component).

[0055] This embodiment greatly improves the bus response speed of a single component and shortens the delay in the processing flow by setting multiple arbitration components.

[0056] Furthermore, the bus interconnection structure includes: N second arbitration components, each second arbitration component is connected to a first arbitration component in m third target engines, and the N second arbitration components are connected to the N slave nodes in a one-to-one correspondence, and the target second arbitration component in the N second arbitration components is used to arbitrate the processing order of data exchange requests sent by m first arbitration components in the m third target engines according to the response time, and send the m data exchange requests to the second slave node connected to the target second arbitration component in sequence according to the processing order, wherein m is a positive integer, the M first target engines include the m third target engines, and the response time is the response time of the second slave node to the m data exchange requests.

[0057] Each host node needs to access the storage space outside the engine through the bus, so it needs to arbitrate through the AXI arbitration component, first select an AXI from many AXI requests, and then distribute the selected AXI to the corresponding target to access the corresponding storage space. The current AXI arbitration process is as follows Figure 4 As shown in the figure, multiple Master components (components 1-n, i.e., host nodes) compete for an AXI bus, which is then distributed to different targets. There are as many arbitration participants as there are AXI access components, and the probability of each component obtaining arbitration rights is 1 / n. The overall arbitration time is long, and for multiple NVMe engines, the processing time of a single engine pipeline is severely limited by obtaining bus arbitration rights and the bus response time.

[0058] In order to solve this problem, a bus interconnection structure is introduced in this embodiment, and a new arbitration method is proposed based on the bus interconnection structure. The arbitration process is shown as follows: Figure 5 As shown, in this embodiment, the specific structure of the bus interconnection structure is as follows Figure 5As shown in the NOC in FIG, NOC includes multiple SWs (SW1-SWi, i.e., the N second arbitration components mentioned above). Taking SW1 as an example, it is connected to a first arbitration component of multiple NVMe engines (only one NVMe engine is shown in the figure, and other NVMe engines are shown as "other IP AXI interfaces"). The multiple arbitration components connected thereto all interact with Slave1 (the second slave node) for data. The function of the second arbitration component is: when SW1 receives data interaction requests sent by multiple NVMe engines, it arbitrates the processing order according to the response speed of Slave1 to these data interaction requests, so that multiple NVMe engines can complete the data interaction process in an orderly manner, avoiding the overall response speed of Slave being too slow.

[0059] Through this embodiment, at the system level, a bus interconnection structure (NOC) is introduced between the AXI master (host node) and the AXI slave (slave node) that exchange data through the bus, so as to complete the data exchange between multiple hosts and multiple slaves. The bus interconnection structure can realize functions such as clock domain, bit width and AXI protocol conversion between the master and slave. In the bus interconnection structure, different IPs accessing the same slave are through a Switch arbitration structure (i.e., the second arbitration component), and Figure 4 Compared with the process shown in the figure, the cross-waiting problem between the same AXI master accessing different AXI slaves due to different slave response delays can be avoided.

[0060] Furthermore, the target first arbitration component among the N first arbitration components is used to: receive t data exchange requests sent by the t first host nodes; arbitrate the sending order of the t data exchange requests through an arbitration algorithm to obtain the sending order; determine the second host node to which the data exchange request is currently to be sent according to the sending order, and send an authorization signal to the second host node, wherein the authorization signal is used to instruct the second host node to send the data exchange request; when it is determined that the high-level interface bus corresponding to the second host node is idle, send the authorization signal to the next first host node among the t first host nodes according to the sending order.

[0061] The arbitration process of the first arbitration component includes: receiving t data exchange requests sent by t first host nodes connected to the target first arbitration component, and then arbitrating the sending order of the t data exchange requests through an arbitration algorithm to obtain the sending order; then, according to the sending order, determining the second host node to send the data exchange request at the current moment, and sending an authorization signal to the second host node, the authorization signal is used to authorize the second host node to send the data exchange request to the bus interconnection structure; then, after determining that the AXI bus (i.e., the advanced interface bus) corresponding to the second host node is idle, determining that the second host node has completed sending, and sending the authorization signal to the next first host node among the t first host nodes in the sending order.

[0062] Optionally, the fourth target engine among the M first target engines includes: T host nodes, used to send data exchange requests to the N slave nodes, wherein T is a positive integer; P third arbitration components, each third arbitration component is connected to I third host node, and the P third arbitration components are connected to P request initiation components in a one-to-one correspondence, and the target third arbitration component among the P third arbitration components is used to arbitrate the initiation order of 1 data exchange request sent by the I third host node to obtain the initiation order, wherein P and I are both positive integers, the T host nodes include the I third host node, and the data exchange objects of the I third host node are all third slave nodes; the target request initiation component among the P request initiation components is connected to the fourth one of the N first arbitration components The arbitration component is connected to send the I data exchange requests to the fourth arbitration component according to the initiation order, wherein the fourth arbitration component corresponds to the third slave node; the N first arbitration components, each of which is connected to p request initiating components and k fourth host nodes, and the N first arbitration components are connected to the bus interconnection structure, the fourth arbitration component is used to arbitrate the sending order of the p request initiating components and the k fourth host nodes to send the data exchange requests, and send p+k of the data exchange requests to the third slave node through the bus interconnection structure in sequence according to the sending order, wherein p and k are both positive integers, the P request initiating components include the p request initiating components, and the T host nodes include the k fourth host nodes.

[0063] In another optional embodiment, the structure of the NVMe engine (i.e., the fourth target engine) is as follows: Figure 6 As shown, in this embodiment, a second optimization point of AXI bus arbitration is proposed. For the inside of IP, the access to AXI can be simplified by reducing the number of AXI buses, such as Figure 6As shown, the third host node 1 and the third host node 2 (I third host nodes) access the same Slave component (i.e., the third slave node). The operations that the third host node 1 and the third host node 2 need to initiate AXI read and write requests (i.e., data exchange requests) can be arbitrated first by the third arbitration component, and the arbitrated control and data information is stored in the cache. Then, the request initiating component uniformly initiates the AXI read and write request operations, and then the request initiating component and other fourth host nodes are arbitrated by the fourth arbitration component for the sending order.

[0064] Through this embodiment, compared with the third host node 1 and the third host node 2 completely independently initiating AXI operations, the use of cache resources can be reduced, and the processing logic resources for initiating AXI read and write operations can be saved. For engines with more AXI operations, some hardware resources can be saved.

[0065] Based on the above embodiments, from the perspective of resources, the above scheme for optimizing the bus arbitration mechanism can effectively reduce the overall usage of different component caches and the resources of the overall AXI logic, thereby reducing the area overhead of the system; and from the perspective of back-end synthesis, the optimization scheme significantly reduces the design complexity, and has obvious improvement effects on timing convergence and area optimization. Table 1 shows the comparison results of some key parameters before and after bus optimization and back-end synthesis. From Table 1, the following conclusions can be drawn: The bus optimization scheme proposed in this application has a very significant effect on reducing the overall area and optimizing the timing. The reduction in equivalent logic check time can also reflect the reduction in design complexity from the side.

[0066] Table 1

[0067]

[0068] As the performance of SSDs gradually increases, SSDs based on PCIe interfaces have gradually become the mainstream of development due to their high performance and low latency. As a new generation of interface transmission protocol, NVMe needs to perform certain IO operations. The typical operation process is as follows: Phase 1: The host sets the PRP in the command; the host writes the command to the SQ queue; the host notifies the NVMe SSD controller to fetch the instruction through the doorbell register; Phase 2: After receiving the notification, the NVMe SSD controller fetches the instruction from the SQ queue; the NVMe SSD controller performs the corresponding data read and write operations according to the instruction; after the NVMe SSD controller executes the instruction, it writes the instruction execution result to the CQ queue; the NVMe SSD controller interrupts and notifies the host to detect the feedback information in the CQ; Phase 3: After the host CQ instruction is executed, it notifies the doorbell register to reply to the NVMe SSD controller. In the above typical operation process, the host undertakes a lot of work, such as the conversion of PRP entry; the management and pointer update of SQ; the update of CQ queue pointer, etc.

[0069] In order to speed up the processing of NVMe disk commands and reduce the overhead of the host CPU, it is proposed in this embodiment to implement the above process through hardware to speed up the processing of NVMe commands, provide higher throughput and better performance. Therefore, the present application proposes an NVMe hardware acceleration processing device based on AXI bus operation, in which the NVMe hardware acceleration processing device completes the processing of NVMe commands through multiple host nodes (i.e., the above T host nodes), and these host nodes, during operation, all of which involve bus operations, need to send read and write requests (i.e., the above data exchange requests) to the AXI arbitration module (i.e., the above first arbitration module) for unified arbitration and send to the Slave.

[0070] The following describes multiple host nodes that complete the processing of NVMe commands in the NVMe hardware acceleration processing device in combination with some optional embodiments:

[0071] Optionally, the T host nodes include: a task receiving processing module, used to receive the first task information sent by the task scheduling management engine, wherein the task scheduling management engine is used to manage the M first target engines; an address acquisition module, connected to the task receiving processing module, used to obtain the starting address information from the first task information, wherein the starting address information includes: the starting address information of HPRP, the starting address information of CPRP; a data handling module, connected to the address acquisition module, used to write the CPR data corresponding to the starting address information into the physical memory area; an SQE sending management module, connected to the data handling module, used to write the SQE command into the physical memory area domain; an SQE pointer management module connected to the SQE sending management module, used to write the SQE pointer into the first register to instruct the first target engine to obtain the SQE command and the CPRP data in the physical memory area according to the SQE pointer, and generate a target command according to the SQE command and the CPRP data; a CQE receiving management module connected to the PCIe controller, used to receive the command execution result of the target command, wherein the PCIe controller is used to execute the target command; a CQE pointer management module connected to the CQE receiving management module, used to write the CQE pointer into the second register to indicate to the first target engine that the execution of the target command is completed.

[0072] Optionally, the data handling module includes: a data reading module, connected to the address acquisition module, and used to read HPRP data according to the starting address information of the HPRP, and read the first CPRP data according to the starting address information of the CPRP; a data conversion module, connected to the data reading module, and used to convert the HPRP data into second CPRP data; a data writing module, connected to the address acquisition module and the data conversion module, and used to write the first CPRP data and the second CPRP data into the physical memory area, wherein the CPRP data includes the first CPRP data and the second CPRP data.

[0073] like Figure 7As shown, the NVMe hardware acceleration processing device in the embodiment of the present application is composed of a multi-NVMe task scheduling management engine (i.e. the above-mentioned task scheduling management engine), an NVMe engine (i.e. the above-mentioned first target engine), a PCIe controller, and a disk, wherein NVMe is composed of a task receiving processing module, an HPRP address resolution module (corresponding to the above-mentioned address acquisition module), a CPRP address resolution module (corresponding to the above-mentioned address acquisition module), an HPRP data reading module (corresponding to the above-mentioned data reading module), a data conversion module, a CPRP data writing module (corresponding to the above-mentioned data writing module), an SQE sending management module, an SQT pointer management module (corresponding to the above-mentioned SQE pointer management module), a CQE receiving management module, a CQH pointer management module (corresponding to the above-mentioned CQE pointer management module), and a task response processing module.

[0074] Among them, the task receiving and processing module receives the original task information issued by the multi-NVMe task scheduling management.

[0075] The HPRP / CPRP address acquisition module obtains the starting addresses of HPRP and CPRP respectively through bus operations according to the system-level PRP list management policy.

[0076] The PRP data handling module (corresponding to the above-mentioned data handling module) involves the conversion from HPRP to CPRP, and completes the reading of HPRP data information and the writing of CPRP data information through bus operations.

[0077] SQE sending management module: through bus operations, writes SQE to the SQE address space accessible to the disk.

[0078] SQE pointer management module: writes SQT Doorbell into the disk Doorbell register (corresponding to the first register mentioned above) through bus operation.

[0079] CQE receiving management module: writes CQH Doorbell to the disk Doorbell space, notifies the disk that a new CQE has been processed, and the CQH pointer in the CQ queue can be updated accordingly.

[0080] For large-scale SOC systems, the management of PRP involves the joint operation of multiple hardware components. For example, there are special PRP management allocation hardware components, PRP list recovery management hardware components, management scheduling hardware components, etc. In order to facilitate the joint operation of multiple components, generally speaking, PRP will be stored in a public space, and multiple hardware components access the public space of PRP through the bus. Figure 7The NVMe hardware acceleration processing device in the bus operation needs to send the read and write requests to the AXI arbitration module for unified arbitration and send them to the AXI interface, such as Figure 8 As shown, Figure 8 The dotted line in the figure indicates that the corresponding component needs to initiate a bus operation (ie, a data exchange request).

[0081] The above embodiments are applicable to various chip designs that need to accelerate NVMe command data processing. From a performance perspective, the use of hardware solutions to implement NVMe command processing effectively reduces the host's involvement and reduces CPU overhead compared to software implementation.

[0082] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0083] In this embodiment, a method for sending a data exchange request is also provided, and the method is applied to the above bus interconnection structure. Fig. 9 is a flow chart of a method for sending a data exchange request according to an embodiment of the present application, such as Fig. 9 As shown, the method includes:

[0084] Step S902, receiving data exchange requests sent by M first target engines, where M is a positive integer;

[0085] Step S904, scheduling the data exchange requests sent by the M first target engines to be sent to N slave nodes, where N is a positive integer;

[0086] Step S906: Send the data exchange results corresponding to the data exchange requests sent by the N slave nodes to the M first target engines.

[0087] Through the above steps, the bus interconnection structure first receives the data exchange requests sent by the M first target engines; then the data exchange requests sent by the M first target engines are scheduled and sent to the N slave nodes; finally, the data exchange results corresponding to the data exchange requests sent by the N slave nodes are received, and forwarded to the M first target engines; thereby completing the sending process of the data exchange request; adopting the above scheme, the bus interconnection structure is introduced to complete the data exchange of multiple hosts to multiple slaves in multiple engines, thereby solving the problem in the related technology that, because the AXI buses of different Slaves (slave nodes) are intertwined, it is necessary to wait for a bus response to be completed before responding to the next request, resulting in the overall Slave response speed being too slow.

[0088] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0089] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0090] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0091] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0092] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0093] An embodiment of the present application further provides a computer program product, comprising a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program product, and when the computer program is executed by a processor, the steps of the method described in each embodiment of the present application are implemented.

[0094] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0095] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0096] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A hardware acceleration processing system, characterized in that: include: M first target engines, used to send data exchange requests to the bus interconnection structure, where M is a positive integer; The bus interconnection structure is connected to the M first target engines and is used to schedule and send the data exchange requests sent by the M first target engines to N slave nodes, where N is a positive integer; The N slave nodes are connected to the bus interconnection structure, and are used to receive data exchange requests sent by the bus interconnection structure, and send data exchange results corresponding to the data exchange requests to the M first target engines through the bus interconnection structure.

2. The hardware acceleration processing system according to claim 1, characterized in that: The second target engine among the M first target engines comprises: T host nodes, used to send data exchange requests to the N slave nodes, where T is a positive integer; N first arbitration components, each first arbitration component is connected to t first host nodes, and the N first arbitration components are connected to the bus interconnection structure, each first arbitration component is used to arbitrate the sending order of the t first host nodes to send data exchange requests, and send the t data exchange requests to the first slave node in sequence through the bus interconnection structure according to the sending order, wherein the T host nodes include the t first host nodes, the N slave nodes include the first slave node, the data exchange objects of the t first host nodes are all the first slave nodes, and t is a positive integer.

3. The hardware acceleration processing system according to claim 2, characterized in that: The bus interconnection structure comprises: N second arbitration components, each second arbitration component is connected to a first arbitration component in m third target engines, and the N second arbitration components are connected to the N slave nodes in a one-to-one correspondence, and the target second arbitration component in the N second arbitration components is used to arbitrate the processing order of data exchange requests sent by m first arbitration components in the m third target engines according to the response time, and send the m data exchange requests to the second slave node connected to the target second arbitration component in sequence according to the processing order, wherein m is a positive integer, the M first target engines include the m third target engines, and the response time is the response time of the second slave node to the m data exchange requests.

4. The hardware acceleration processing system according to claim 2, characterized in that: The target first arbitration component among the N first arbitration components is used for: Receiving t data exchange requests sent by the t first host nodes; Arbitrating the sending order of the t data exchange requests through an arbitration algorithm to obtain the sending order; Determine the second host node to which the data exchange request is currently to be sent according to the sending order, and send an authorization signal to the second host node, wherein the authorization signal is used to instruct the second host node to send the data exchange request; When it is determined that the advanced interface bus corresponding to the second host node is idle, the grant signal is sent to the next first host node among the t first host nodes according to the sending order.

5. The hardware acceleration processing system according to claim 1, characterized in that: The fourth target engine among the M first target engines comprises: T host nodes, used to send data exchange requests to the N slave nodes, where T is a positive integer; P third arbitration components, each of which is connected to I third host node, and the P third arbitration components are connected to P request initiation components in a one-to-one correspondence, and the target third arbitration component among the P third arbitration components is used to arbitrate the initiation order of I data exchange requests sent by the I third host node to obtain the initiation order, wherein P and I are both positive integers, the T host nodes include the I third host node, and the data exchange objects of the I third host node are all third slave nodes; A target request initiating component among the P request initiating components is connected to a fourth arbitration component among the N first arbitration components, and is used to send the one data exchange request to the fourth arbitration component according to the initiation order, wherein the fourth arbitration component corresponds to the third slave node; The N first arbitration components, each of which is connected to p request initiating components and k fourth host nodes, and the N first arbitration components are connected to the bus interconnection structure, the fourth arbitration component is used to arbitrate the sending order of the p request initiating components and the k fourth host nodes to send data exchange requests, and send p+k data exchange requests to the third slave node in sequence through the bus interconnection structure according to the sending order, wherein p and k are both positive integers, the P request initiating components include the p request initiating components, and the T host nodes include the k fourth host nodes.

6. The hardware acceleration processing system according to claim 2 or 5, characterized in that: The T host nodes include: A task receiving and processing module, used for receiving first task information sent by a task scheduling and management engine, wherein the task scheduling and management engine is used for managing the M first target engines; an address acquisition module, connected to the task receiving and processing module, and configured to acquire starting address information from the first task information, wherein the starting address information includes: starting address information of HPRP and starting address information of CPRP; A data handling module, connected to the address acquisition module, for writing the CPR data corresponding to the start address information into the physical memory area; An SQE sending management module, connected to the data handling module, for writing SQE commands into the physical memory area; an SQE pointer management module, connected to the SQE sending management module, and configured to write an SQE pointer into a first register to instruct the first target engine to obtain the SQE command and the CPRP data in the physical memory area according to the SQE pointer, and to generate a target command according to the SQE command and the CPRP data; A CQE receiving management module, connected to the PCIe controller, for receiving a command execution result of the target command, wherein the PCIe controller is used to execute the target command; A CQE pointer management module is connected to the CQE receiving management module and is used to write a CQE pointer into a second register to indicate that the execution of the target command by the first target engine is completed.

7. The hardware acceleration processing system according to claim 6, characterized in that: The data handling module comprises: a data reading module, connected to the address acquisition module, and configured to read the HPRP data according to the starting address information of the HPRP, and read the first CPRP data according to the starting address information of the CPRP; A data conversion module, together with the data reading module, is used to convert the HPRP data into second CPRP data; A data writing module is connected to the address acquisition module and the data conversion module, and is used to write the first CPRP data and the second CPRP data into the physical memory area, wherein the CPRP data includes the first CPRP data and the second CPRP data.

8. A method for sending a data exchange request, characterized in that: The bus interconnection structure applied to any one of claims 1 to 7, include: Receiving data exchange requests sent by M first target engines, where M is a positive integer; Scheduling the data exchange requests sent by the M first target engines to N slave nodes, where N is a positive integer; The data exchange results corresponding to the data exchange requests sent by the N slave nodes are sent to the M first target engines.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in claim 8 when executed by a processor.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to claim 8 are implemented.

Images