Data balance processing method, system, device and equipment and storage medium

Abstract

The invention provides a data balance processing method, system and device, equipment and a storage medium, relates to the technical field of computers, and aims to solve the problem of how to realize efficient data migration in a multi-engine multi-channel DMA (Direct Memory Access) and how to accelerate performance convergence during performance balance scene testing. The method comprises the steps that based on the number of engines of a direct memory access module, first equalization processing is conducted on data to be processed when the data are input into all the engines of the direct memory access module, and the first equalization processing is used for evenly distributing the data to be processed to all the engines; performing second equalization processing on the to-be-processed data allocated to the single engine when the to-be-processed data is input into each channel of the single engine, wherein the second equalization processing is used for uniformly allocating the data allocated to the single engine into each channel of the single engine; and transmitting the to-be-processed data to a data processing module connected with the direct memory access module through each channel of each engine of the direct memory access module.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a data balancing processing method, system, device, equipment and storage medium. Background Art

[0002] DMA (Direct Memory Access) technology is a technology that allows external devices (such as graphics cards, hard disks, etc.) to interact directly with the computer's main memory without the intervention of the central processing unit. Multi-engine multi-channel DMA is an extension of DMA technology, which allows multiple DMA engines to operate multiple channels simultaneously, thereby achieving parallel data transmission and processing, further improving data transmission efficiency.

[0003] The performance verification of multi-engine multi-channel DMA usually adopts the fork...join method of SV (SystemVerilog). However, when using the system function provided by SV to select random data, repeated selection of random numbers will occur, so some engines or some channels will be hit repeatedly multiple times, resulting in uneven distribution. This makes data transmission inefficient under the test of system performance balance scenario and cannot meet the expected goals of performance testing. Summary of the invention

[0004] Based on the above technical problems, the embodiments of the present application provide a data balancing processing method, system, device, equipment and storage medium, aiming to achieve efficient data movement in multi-engine multi-channel DMA and accelerate performance convergence during performance balancing scenario testing.

[0005] A first aspect of an embodiment of the present application provides a data balancing processing method, the method comprising:

[0006] Based on the number of engines of the direct memory access module, performing a first balancing process on the data to be processed when the data is input into each engine of the direct memory access module, wherein the first balancing process is used to evenly distribute the data to be processed to each engine;

[0007] Based on the number of channels in a single engine in each engine, a second balancing process is performed on the to-be-processed data allocated to the single engine when the data is input into each channel of the single engine, wherein the second balancing process is used to evenly distribute the data allocated to the single engine to each channel of the single engine;

[0008] The data to be processed is transmitted to a data processing module connected to the direct memory access module through each channel of each engine of the direct memory access module.

[0009] Optionally, based on the number of engines of the direct memory access module, performing first balancing processing on the data to be processed when inputting into each engine of the direct memory access module includes:

[0010] The data to be transmitted are grouped and processed according to the number of engines to obtain multiple groups of data matching the number of engines;

[0011] The multiple groups of data are randomly matched one by one with the engines of the direct memory access module.

[0012] Optionally, the method further comprises:

[0013] When a performance test instruction for a direct memory access module is detected, a random variable for engine input and a data length of the random variable are obtained;

[0014] Generate a random data set according to a bit width range that can be supported by the random variable data length, and cache the random data set into a first queue;

[0015] The data in the first queue are processed in a disorderly manner by calling the disorder function;

[0016] The data after disorder processing is grouped according to the number of engines to obtain multiple groups of data matching the number of engines;

[0017] The multiple groups of data are randomly matched one by one with the engines of the direct memory access module.

[0018] Optionally, the method further comprises:

[0019] When M performance test requests for the direct memory access module are detected, when the performance test request for the direct memory access module is detected, obtaining a random variable for engine input and a data length of the random variable;

[0020] Generate a random data set according to a bit width range that can be supported by the random variable data length, and cache the random data set into a first queue;

[0021] The data in the first queue are processed in a disorderly manner by calling the disorder function;

[0022] The data after disorder processing is grouped according to the number of engines to obtain multiple groups of data matching the number of engines;

[0023] The multiple groups of data are randomly matched M times one by one with each engine of the direct memory access module, so as to realize polling matching of the multiple groups of data to the M engines of the direct memory access module.

[0024] Optionally, the number of engines of the direct memory access module is N, and based on the number of channels in a single engine in each engine, a second balancing process is performed on the to-be-processed data allocated to the single engine when the data is input into each channel of the single engine, including:

[0025] Based on the number of channels in the Nth engine in each engine, add the channel identifier of each channel of the Nth engine to the second queue;

[0026] According to the number of channels of the Nth engine, the data to be processed allocated to the Nth engine is grouped and processed to obtain a plurality of data segments matching the number of channels;

[0027] The channel identifiers in the second queue are processed in a disordered manner by calling a disorder function;

[0028] The channel identifiers that have been processed out of order are randomly matched with the multiple data segments one by one.

[0029] A second aspect of an embodiment of the present application provides a data balancing processing system, the system comprising:

[0030] A direct memory access module, the direct memory access module includes a plurality of engines and each engine has a plurality of channels;

[0031] A data processing module connected to the direct memory access module;

[0032] A data balancing processing device, used to execute the data balancing processing method described in any one of claims 1-5, so as to transmit the data to be processed to the data processing module through each channel of each engine of the direct memory access module.

[0033] Optionally, the system further comprises:

[0034] An excitation source, used to generate random data and send the data to the data equalization processing device;

[0035] The data equalization processing device is further used to determine the random data as data to be processed.

[0036] Optionally, the system further comprises:

[0037] The test terminal is used to generate a performance test instruction for the direct memory access module and send it to the data balancing processing device.

[0038] A third aspect of an embodiment of the present application provides a data equalization processing device, the device comprising:

[0039] A first balancing processing module, configured to perform a first balancing process on the data to be processed when the data is input into each engine of the direct memory access module based on the number of engines of the direct memory access module, wherein the first balancing process is configured to evenly distribute the data to be processed to each engine;

[0040] a second balancing processing module, configured to perform a second balancing processing on the data to be processed allocated to the single engine when the data is input into each channel of the single engine based on the number of channels in the single engine in each engine, wherein the second balancing processing is used to evenly distribute the data allocated to the single engine to each channel of the single engine;

[0041] The transmission module is used to transmit the data to be processed to the data processing module connected to the direct memory access module through each channel of each engine of the direct memory access module.

[0042] A fourth aspect of an embodiment of the present application provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, the data equalization processing method of the first aspect of the embodiment of the present application is implemented.

[0043] A fifth aspect of an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the data balancing processing method of the first aspect of an embodiment of the present application is implemented.

[0044] Through the data balancing processing method of the embodiment of the present application, based on the number of engines of the direct memory access module, a first balancing process is performed on the data to be processed when it is input into each engine of the direct memory access module, and the first balancing process is used to evenly distribute the data to be processed to each engine; based on the number of channels in a single engine in each engine, a second balancing process is performed on the data to be processed allocated to the single engine when it is input into each channel of the single engine, and the second balancing process is used to evenly distribute the data allocated to the single engine to each channel of the single engine; and the data to be processed is transmitted to the data processing module connected to the direct memory access module through each channel of each engine of the direct memory access module.

[0045] In this embodiment, the present application performs the first balancing process when the data to be processed is input into multiple engines, so that each engine can jointly undertake the system data transmission task, thereby improving the engine utilization rate, and performs the second balancing process again when multiple channels are hit and selected in a single engine, so that each channel can share the data transmission task with each other, thereby improving the transmission efficiency. In the channel DMA performance test scenario, the data can be evenly distributed across each data channel for transmission, which can not only efficiently complete the data moving task, but also accelerate the performance convergence when the performance balancing scenario is tested. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0047] Figure 1 is a flowchart of the steps of a data balancing processing method proposed in an embodiment of the present application;

[0048] Figure 2 is a schematic diagram of a first equalization processing process of a data equalization processing method proposed in an embodiment of the present application;

[0049] Figure 3 It is a schematic diagram of a data balancing method according to an embodiment of the present application, in which a plurality of random variables are input to different engines after first balancing processing;

[0050] Figure 4 is a schematic diagram of a second equalization processing process of a data equalization processing method proposed in an embodiment of the present application;

[0051] Figure 5 It is a schematic diagram of the random data generation and balancing process of the data balancing method proposed in one embodiment of the present application;

[0052] Figure 6 It is a schematic diagram of a single Repeat channel hit distribution based on a random function of an SV system according to a data balancing processing method proposed in an embodiment of the present application;

[0053] Figure 7 It is a schematic diagram of the hit distribution of a single Repeat channel of the data balancing processing method proposed in an embodiment of the present application;

[0054] Figure 8 It is a schematic diagram of the channel hit distribution based on the SV system random function Repeat 10 times of the data balancing processing method proposed in one embodiment of the present application;

[0055] Fig. 9 It is a schematic diagram of the distribution of channel hits in Repeat 10 times of the data balancing processing method proposed in an embodiment of the present application;

[0056] Fig.10 is a schematic diagram of an electronic device in the present application. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0058] In the drawings, the size of the constituent elements, the thickness of the layer or the area may be exaggerated for the sake of clarity. Therefore, any implementation of the present disclosure is not necessarily limited to the size shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and any implementation of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0059] DMA (Direct Memory Access) technology, or direct memory access technology, is a technology that allows external devices (such as graphics cards, hard disks, etc.) to interact directly with the computer's main memory without the intervention of the central processing unit. This technology reduces the CPU's involvement in the data transfer process, thereby reducing the CPU's load and improving overall system performance.

[0060] Multi-engine multi-channel DMA is an extension of DMA technology, which allows multiple DMA engines to operate multiple channels at the same time, thereby realizing parallel transmission and processing of data. This technology further improves the efficiency of data transmission, enabling computer systems to better cope with scenarios such as large-scale data processing and multi-tasking. For this reason, multi-engine multi-channel DMA technology is also widely used in the field of chip design, and is used in many fields such as server products, storage products, and network switching products.

[0061] For chips involving multi-engine multi-channel DMA functions, from a verification perspective, we need to be concerned not only with whether the multi-engine multi-channel DMA function design can meet the architecture and design requirements, but more importantly, whether its performance meets the expectations of the architecture and design, that is, verify whether the DMA transmission speed meets the design requirements; verify whether there is a performance bottleneck when multiple DMA engines and channels work simultaneously.

[0062] The performance verification of multi-engine multi-channel DMA usually uses the fork...join method of SV (SystemVerilog) to start each engine in parallel, and the selection of each channel within a single engine is often randomly scheduled. For example, the system function provided by SV (for example: $urandom) can be used to achieve random selection within the specified channel range. Usually, when we use the system random function provided by SV to select random data, there will be repeated selection of random numbers in the process, so some engines or some channels will be repeatedly hit multiple times, resulting in uneven distribution. If we consider that some channels are hit more times and these channels may cause congestion due to network quality or other abnormalities during the actual data transmission process, the data transmission will become inefficient under the test of the system performance balance scenario, and the expected goals of the performance test cannot be met.

[0063] In the actual data transmission process, high-load data (i.e., the data transfer center carries a large amount of data transmission and processing tasks, and the traffic exceeds the network's processing capacity or bandwidth capacity) and unbalanced traffic distribution (i.e., data traffic is unevenly distributed in the transmission channel, some paths or devices may face overload, while other paths or devices are idle) are two important factors that cause data congestion and affect data transmission efficiency.

[0064] Please refer to Figure 1 , Figure 1 1 is a flowchart of the steps of the data balancing processing method proposed in one embodiment of the present application. Figure 1 As shown, the method may include steps S11 to S13:

[0065] Step S11: Based on the number of engines of the direct memory access module, a first balancing process is performed on the data to be processed when it is input into each engine of the direct memory access module, wherein the first balancing process is used to evenly distribute the data to be processed to each engine.

[0066] The number of engines included in the DMA (direct memory access) module is clarified. These engines are independent units in the DMA module responsible for data transmission and processing. When the data to be processed is input into each engine of the direct memory access module, a first balancing process is performed to evenly distribute the data to be processed to each engine. The data to be processed can be random data of a certain excitation source. By performing the first balancing process when the data to be processed is input into multiple engines, each engine can jointly undertake the system data transmission task, thereby improving the engine utilization rate.

[0067] Further, based on the number of engines of the direct memory access module, a first balancing process is performed on the data to be processed when it is input into each engine of the direct memory access module, including:

[0068] The data to be transmitted are grouped and processed according to the number of engines to obtain multiple groups of data matching the number of engines;

[0069] The multiple groups of data are randomly matched one by one with the engines of the direct memory access module.

[0070] Identify the number of engines in the DMA module, evaluate the total amount of data to be transmitted, and divide it into multiple groups of data according to the characteristics and processing requirements of the data. When grouping, try to ensure that the size of each group of data is similar so that the processing load of each engine can be balanced. Then randomly match the multiple groups of data with each engine of the DMA module one by one. Here, a random matching method can be used. After the matching is completed, each engine will get a group of data. By evenly grouping the data to be transmitted and randomly assigning it to each engine, it helps to improve engine utilization and overall data processing efficiency.

[0071] Further, when a performance test instruction for a direct memory access module is detected, a random variable for engine input and a data length of the random variable are obtained;

[0072] Generate a random data set according to a bit width range that can be supported by the random variable data length, and cache the random data set into a first queue;

[0073] The data in the first queue are processed in a disorderly manner by calling the disorder function;

[0074] The data after disorder processing is grouped according to the number of engines to obtain multiple groups of data matching the number of engines;

[0075] The multiple groups of data are randomly matched one by one with the engines of the direct memory access module.

[0076] like Figure 2 As shown, when a performance test instruction for a direct memory access module is detected, the random variable used for engine input and the data length of the random variable are obtained. Usually there are multiple random variables, for example: if the interface of the DMA module adopts the standard AXI protocol, the random variables that need to be considered include the data source address, the data destination address, and the data length, etc.

[0077] For each random variable, a corresponding data set is generated according to its bit width and data range. A random data set can be generated according to the bit width range supported by the random variable data length. For example, it is known that the bit width is [11:0] and cannot be 0, so a set of integers from 1 to 212-1 (i.e. 4095) is generated. In order to facilitate the next step of processing of the generated data, the random data set is cached in the first queue. A random data set can also be generated according to the bit width range supported by the data source address and the data destination address. For example, if the address bit width is 32 bits, a set of integers from 0 to 232-1 is generated (adjusted according to the actual address space of the system).

[0078] Shuffle processing is an optimization technique that allows tasks, data, or instructions to be processed without having to follow the original order, thereby improving efficiency and performance. Use the shuffle() function (such as random.shuffle() in Python) to shuffle the data in the first queue. This ensures that the order of the data is random during the subsequent grouping process, thereby increasing the complexity and authenticity of the test.

[0079] According to the number of engines, the out-of-order data is evenly divided into groups to obtain multiple groups of data that match the number of engines. The idea of ​​equal division is usually used, that is, the amount of data in each group is equal as much as possible. Assuming there are N engines, the modulus operation (%) can be used to achieve equal division.

[0080] Randomly match multiple sets of data with the engines of the direct memory access module one by one. Distribute the out-of-order data to multiple engines for processing, simulating some scenarios of parallel processing, which helps to evaluate the performance and stability of the DMA module in a parallel environment.

[0081] Further, when M performance test test requests for the direct memory access module are detected, when the performance test test request for the direct memory access module is detected, a random variable for engine input and a data length of the random variable are obtained;

[0082] Generate a random data set according to a bit width range that can be supported by the random variable data length, and cache the random data set into a first queue;

[0083] The data in the first queue are processed in a disorderly manner by calling the disorder function;

[0084] The data after disorder processing is grouped according to the number of engines to obtain multiple groups of data matching the number of engines;

[0085] The multiple groups of data are randomly matched M times one by one with each engine of the direct memory access module, so as to realize polling matching of the multiple groups of data to the M engines of the direct memory access module.

[0086] When M performance test requests for the direct memory access module are detected, the random variables for engine input and the data length of the random variables are obtained; a random data set is generated according to the bit width range supported by the random variable data length, and the random data set is cached in the first queue; the data in the first queue is processed in a disorderly manner by calling the disorder function; the disordered data is processed in groups according to the number of engines to obtain multiple groups of data matching the number of engines. After the grouping process, a random polling strategy can be used to input the grouped data into different engines to further achieve randomness. This means that in each iteration, a group of data can be randomly selected and sent to the corresponding engine. In a simple parallel processing scenario, the grouped data is usually directly assigned to the engine in sequence or according to a fixed strategy (such as a loop). Through the random polling strategy, it is ensured that each engine can receive the data and the data is distributed as evenly as possible, so as to comprehensively evaluate the performance of the DMA module in a parallel processing environment.

[0087] like Figure 3 As shown in the figure, if there are multiple random variables x, y, z, ..., the processing process for each variable is similar. First, a set of data supported by the current random variable bit width needs to be generated, and then the data set is equally divided according to the number of engines. After processing, the data interval matching the number of engines is obtained, and then it is sent to the engine entrance as input. Figure 3 The DUT is a data processing module connected to the direct memory access module, i.e., the device under test. Monitor and Checker jointly complete the functions of data task inspection and error correction. CR VIP provides the clock and reset signals necessary for the verification environment. AXIVIP0 / 1 is a VIP component authorized by a third party. Step S102: According to the analysis results, filter out at least one device driver from the original root file system to obtain a new root file system;

[0088] Step S12: Based on the number of channels in a single engine in each engine, a second balancing process is performed on the to-be-processed data allocated to the single engine when it is input into each channel of the single engine, wherein the second balancing process is used to evenly distribute the data allocated to the single engine to each channel of the single engine.

[0089] The number of channels in a single engine in each engine in the DMA module is clarified. According to the number of channels, the data to be processed allocated to the single engine is subjected to a second balancing process when it is input into each channel of the single engine, so as to evenly distribute the data allocated to the single engine to each channel of the single engine. This enables each channel to share the data transmission task with each other, thereby improving the transmission efficiency.

[0090] Furthermore, the number of engines of the direct memory access module is N, and based on the number of channels in a single engine in each engine, a second balancing process is performed on the to-be-processed data allocated to the single engine when it is input into each channel of the single engine, including:

[0091] Based on the number of channels in the Nth engine in each engine, add the channel identifier of each channel of the Nth engine to the second queue;

[0092] According to the number of channels of the Nth engine, the data to be processed allocated to the Nth engine is grouped and processed to obtain a plurality of data segments matching the number of channels;

[0093] The channel identifiers in the second queue are processed in a disordered manner by calling a disorder function;

[0094] The channel identifiers that have been processed out of order are randomly matched with the multiple data segments one by one.

[0095] The second balancing process for random data multi-channels of a single engine is divided into two stages. The first stage is mainly to shuffle the channels written into the channel queue, and then POP the channels one by one after the shuffle process to ensure that the channels of each POP are unique and different until the channel queue is empty; at the same time of each POP, the random data entering the engine is evenly distributed and traversed to each channel. In the second stage, based on the first stage, the selected / hit channels are used as the input of the DUT.

[0096] Specifically, Figure 4 As shown, in the first stage, the channel array is first defined and initialized. According to the hardware configuration or design requirements of the system, an array containing all available channels is defined and initialized. Each element of the array corresponds to the identifier or address of a channel. The channel array is pushed into the queue. According to the number of channels in the Nth engine in each engine, the channel identifiers of each channel of the Nth engine are added to the second queue. According to the number of channels of the Nth engine, the data to be processed allocated to the Nth engine are grouped and processed according to the idea of ​​equal distribution to obtain multiple data segments matching the number of channels. The number of channels in the queue is shuffled, and the channel identifiers in the second queue are shuffled by calling the shuffle function to ensure that random data can be evenly and randomly allocated to each channel. In the second stage, the selected / hit channel selection results are selected on the basis of the first stage. Each channel address popped out from the shuffle queue has been selected. The selected channel is used as the input of the DUT, indicating that the next write operation will be performed on this channel. Finally, the channel identifiers after shuffle processing are randomly matched with multiple data segments one by one.

[0097] Step S13: transmitting the data to be processed to the data processing module connected to the direct memory access module through each channel of each engine of the direct memory access module.

[0098] After completing the first and second equalization processing of data between the engine and the channel, the DMA module is started for data transmission. The DMA module uses its multiple engines and channels to transfer data from the source address to the target address of the data processing module connected to the DMA module in parallel. After two processings, the data is transmitted across various data channels, and the data movement task can be completed efficiently.

[0099] For ease of understanding, the embodiments of the present disclosure are described through specific application scenarios.

[0100] Assume that the random data of a stimulus source during the verification process is as follows Figure 5 As shown in FIG. 1 , it is assumed that the multi-engine multi-channel object has 4 engines (Engine0, Engine1, Engine2, Engine3) and each engine has 4 channels (CH0, CH1, CH2, CH3). Through the specific method of steps S11 to S12, Figure 5 It can be seen that the random data generated by a certain excitation source can not only be evenly and randomly distributed to the four engines, but also the random data entering the current engine during data transmission can be evenly distributed to each channel. In this way, each engine and channel can be fully utilized during data transmission. Without considering other network factors, this type of data distribution takes the shortest time and has the highest efficiency during transmission.

[0101] In addition, the channel hit distribution results of the traditional SV random function and the data balancing processing method of this application are compared. That is, in order to clearly present the distribution of random hit channels during multi-channel selection through the SV system random function (ie: $urandom) and the distribution of random hit channels during multi-channel selection proposed by the data balancing processing method of this application, tests were conducted based on two different methods.

[0102] In the test, it is assumed that the number of channels is 8, and the channel hit distribution test is performed for a single repeat and 10 repeats respectively. The test results of the two methods for a single repeat are as follows: Figure 6 and Figure 7 As shown, the results of Repeat 10 tests are as follows Figure 8 and Fig. 9 As shown. Figure 6 to Figure 9 It can be seen that the distribution of the hit channels based on the random function of the SV system is unbalanced due to the large number of repeated hits on some channels, while the data balancing processing based on this application makes the hit channel distribution balanced under the same test environment.

[0103] The data balancing processing method provided by the present invention can not only be applied to the verification of multi-engine multi-channel DMA performance balancing scenarios, but also can refer to the random stimulus balancing processing strategies and methods proposed in this patent in the functional verification stage to accelerate the collection of code coverage and data improvement.

[0104] In the disclosed embodiment, by performing the first balancing process when the data to be processed is input into multiple engines, each engine can jointly undertake the system data transmission task, thereby improving the engine utilization rate, and performing the second balancing process again when multiple channels in a single engine are hit and selected, so that each channel can share the data transmission task with each other, thereby improving the transmission efficiency. In the channel DMA performance test scenario, the data can be evenly distributed across each data channel for transmission, which can not only efficiently complete the data moving task, but also accelerate the performance convergence when the performance balancing scenario is tested.

[0105] Based on the same design concept, an embodiment of the present application provides a data balancing processing system. The system includes:

[0106] A direct memory access module, the direct memory access module includes a plurality of engines and each engine has a plurality of channels;

[0107] A data processing module connected to the direct memory access module;

[0108] A data balancing processing device, used to execute the data balancing processing method described in any one of claims 1-5, so as to transmit the data to be processed to the data processing module through each channel of each engine of the direct memory access module.

[0109] Optionally, the system further comprises:

[0110] An excitation source, used to generate random data and send the data to the data equalization processing device;

[0111] The data equalization processing device is further used to determine the random data as data to be processed.

[0112] Optionally, the system further comprises:

[0113] The test terminal is used to generate a performance test instruction for the direct memory access module and send it to the data balancing processing device.

[0114] Based on the same design concept, an embodiment of the present application provides a data balancing processing device. The device includes:

[0115] A first balancing processing module, configured to perform a first balancing process on the data to be processed when the data is input into each engine of the direct memory access module based on the number of engines of the direct memory access module, wherein the first balancing process is configured to evenly distribute the data to be processed to each engine;

[0116] a second balancing processing module, configured to perform a second balancing processing on the data to be processed allocated to the single engine when the data is input into each channel of the single engine based on the number of channels in the single engine in each engine, wherein the second balancing processing is used to evenly distribute the data allocated to the single engine to each channel of the single engine;

[0117] The transmission module is used to transmit the data to be processed to the data processing module connected to the direct memory access module through each channel of each engine of the direct memory access module.

[0118] Optionally, the first equalization processing module is specifically used to:

[0119] Based on the number of engines of the direct memory access module, performing first balancing processing on the data to be processed when the data is input into each engine of the direct memory access module includes:

[0120] The data to be transmitted are grouped and processed according to the number of engines to obtain multiple groups of data matching the number of engines;

[0121] The multiple groups of data are randomly matched one by one with the engines of the direct memory access module.

[0122] Optionally, the second equalization processing module is specifically used to:

[0123] The number of engines of the direct memory access module is N. Based on the number of channels in the Nth engine in each engine, the channel identifier of each channel of the Nth engine is added to the second queue; according to the number of channels of the Nth engine, the data to be processed allocated to the Nth engine is grouped and processed to obtain multiple data segments matching the number of channels; the channel identifiers in the second queue are shuffled by calling the shuffle function; and each channel identifier after shuffle is randomly matched with the multiple data segments one by one.

[0124] Optionally, the device further comprises:

[0125] The first processing module is used to obtain the random variables used for engine input and the data length of the random variables when a performance test instruction for the direct memory access module is detected; generate a random data set according to the bit width range supported by the random variable data length, and cache the random data set to the first queue; shuffle the data in the first queue by calling the shuffle function; group the shuffled data according to the number of engines to obtain multiple groups of data matching the number of engines; and randomly match the multiple groups of data with each engine of the direct memory access module one by one.

[0126] Optionally, the device further comprises:

[0127] The second processing module is used to obtain random variables used for engine input and the data length of the random variables when M performance test test requests for the direct memory access module are detected; generate a random data set according to the bit width range supported by the random variable data length, and cache the random data set to the first queue; shuffle the data in the first queue by calling the shuffle function; group the shuffled data according to the number of engines to obtain multiple groups of data matching the number of engines; randomly match the multiple groups of data with each engine of the direct memory access module M times one by one to achieve polling matching of the multiple groups of data to the M engines of the direct memory access module.

[0128] Based on the same design concept, another embodiment of the present application provides an electronic device, such as Fig.10 shown. Fig.10 1 is a schematic diagram of an electronic device shown in an embodiment of the present application. The electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the data equalization processing method described in any of the above embodiments of the present application when executing the computer program.

[0129] Based on the same design concept, another embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps in the data balancing processing method described in any of the above embodiments of the present application are implemented.

[0130] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0131] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0132] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present application may adopt the form of complete hardware embodiments, complete software embodiments, or embodiments in combination with software and hardware. Moreover, the embodiments of the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0133] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0134] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0135] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0136] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0137] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0138] The above is a detailed introduction to a data balancing processing method, system, device, equipment and storage medium provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A data balancing processing method, characterized in that: The method comprises: Based on the number of engines of the direct memory access module, performing a first balancing process on the data to be processed when the data is input into each engine of the direct memory access module, wherein the first balancing process is used to evenly distribute the data to be processed to each engine; Based on the number of channels in a single engine in each engine, a second balancing process is performed on the to-be-processed data allocated to the single engine when the data is input into each channel of the single engine, wherein the second balancing process is used to evenly distribute the data allocated to the single engine to each channel of the single engine; The data to be processed is transmitted to a data processing module connected to the direct memory access module through each channel of each engine of the direct memory access module.

2. A data equalization processing method according to claim 1, characterized in that: Based on the number of engines of the direct memory access module, performing first balancing processing on the data to be processed when the data is input into each engine of the direct memory access module includes: The data to be transmitted are grouped and processed according to the number of engines to obtain multiple groups of data matching the number of engines; The multiple groups of data are randomly matched one by one with the engines of the direct memory access module.

3. A data equalization processing method according to claim 1, characterized in that: The method further comprises: When a performance test instruction for a direct memory access module is detected, a random variable for engine input and a data length of the random variable are obtained; Generate a random data set according to a bit width range that can be supported by the random variable data length, and cache the random data set into a first queue; The data in the first queue are processed in a disorderly manner by calling the disorder function; The data after disorder processing is grouped according to the number of engines to obtain multiple groups of data matching the number of engines; The multiple groups of data are randomly matched one by one with the engines of the direct memory access module.

4. A data equalization processing method according to claim 1, characterized in that: The method further comprises: When M performance test test requests for the direct memory access module are detected, when the performance test test request for the direct memory access module is detected, obtaining a random variable for engine input and a data length of the random variable; Generate a random data set according to a bit width range that can be supported by the random variable data length, and cache the random data set into a first queue; The data in the first queue are processed in a disorderly manner by calling the disorder function; The data after disorder processing is grouped according to the number of engines to obtain multiple groups of data matching the number of engines; The multiple groups of data are randomly matched M times one by one with each engine of the direct memory access module, so as to realize polling matching of the multiple groups of data to the M engines of the direct memory access module.

5. A data equalization processing method according to any one of claims 1 to 4, characterized in that: The number of engines of the direct memory access module is N. Based on the number of channels in a single engine in each engine, a second balancing process is performed on the to-be-processed data allocated to the single engine when the data is input into each channel of the single engine, including: Based on the number of channels in the Nth engine in each engine, add the channel identifier of each channel of the Nth engine to the second queue; According to the number of channels of the Nth engine, the data to be processed allocated to the Nth engine is grouped and processed to obtain a plurality of data segments matching the number of channels; The channel identifiers in the second queue are processed in a disordered manner by calling a disorder function; The channel identifiers that have been processed out of order are randomly matched with the multiple data segments one by one.

6. A data balancing processing system, characterized in that: The system comprises: A direct memory access module, the direct memory access module includes a plurality of engines and each engine has a plurality of channels; A data processing module connected to the direct memory access module; A data balancing processing device, used to execute the data balancing processing method described in any one of claims 1-5, so as to transmit the data to be processed to the data processing module through each channel of each engine of the direct memory access module.

7. A data equalization processing system according to claim 6, characterized in that: The system further comprises: An excitation source, used to generate random data and send the data to the data equalization processing device; The data equalization processing device is further used to determine the random data as data to be processed.

8. A data equalization processing system according to claim 6 or 7, characterized in that: The system further comprises: The test terminal is used to generate a performance test instruction for the direct memory access module and send it to the data balancing processing device.

9. A data equalization processing device, characterized in that: The device comprises: A first balancing processing module, configured to perform a first balancing process on the data to be processed when the data is input into each engine of the direct memory access module based on the number of engines of the direct memory access module, wherein the first balancing process is configured to evenly distribute the data to be processed to each engine; a second balancing processing module, configured to perform a second balancing processing on the data to be processed allocated to the single engine when the data is input into each channel of the single engine based on the number of channels in the single engine in each engine, wherein the second balancing processing is used to evenly distribute the data allocated to the single engine to each channel of the single engine; The transmission module is used to transmit the data to be processed to the data processing module connected to the direct memory access module through each channel of each engine of the direct memory access module.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the computer program is executed by the processor, the data equalization processing method according to any one of claims 1 to 5 is implemented.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the data equalization processing method according to any one of claims 1 to 5 is implemented.

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