A method for managing out-of-order reception of RapidIO Message transactions based on FPGA

Abstract

The invention discloses a disordered receiving management method of RapidIO Message transactions based on FPGA, relates to the technical field of communication, and is used to improve the problem of data congestion caused by competition between source nodes. The method comprises the following steps: receiving a RapidIO transaction packet and transmitting it into a RapidIO driver module; in the RapidIO driver module, performing cross-clock domain processing on a RapidIO interface so that data transmission in different clock domains tends to be synchronized; caching the Message transaction packet after the cross-clock domain processing; performing protocol parsing on the Message transaction packet, obtaining framed data after the parsing of the Message transaction packet; outputting the parsed Message framed data; arbitrating an SRAM cache channel after caching the Message framed data, obtaining a matching SRAM cache channel, writing the Message framed data into a corresponding channel, mapping an SRAM cache address with a fragment offset of the Message frame, and writing the framed data into a corresponding space of the SRAM module, thereby completing automatic sorting of the Message frame and reducing the communication failure problem caused by disordered retransmission of the Message transaction packet caused by competition between source nodes.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and more specifically, to a method for managing out-of-order reception of RapidIOMessage transactions based on FPGA. Background Art

[0002] With the rapid development of information technology, embedded high-speed interconnection technology based on RapidIO has been widely used in many fields such as radar, communication, remote sensing, etc. As an open interconnection technology standard, RapidIO supports multiple transaction applications such as NWR, NREAD, SWR, DoorBell, Message, etc.

[0003] In the Message transaction application, the maximum single Message length supported by RapidIO is 4096 bytes, which can be divided into 16 packets for fragmented data transmission at most, with a maximum of 256 bytes per packet, and each packet is distinguished by the number of fragments and the fragment offset field. The RapidIO protocol allows the fragments of the Message transaction to be sent or received out of order. In a large RapidIO switching system, when sending Message transactions at high speed from multiple nodes to a single node, competition will occur between the source nodes, and the nodes that do not obtain the transmission right will experience data congestion, increasing the probability of disordered transmission. The destination node will also receive disordered Message transaction packets, which will cause communication failures if they cannot be sorted. Summary of the invention

[0004] In order to overcome the above defects of the prior art, an embodiment of the present invention provides an out-of-order reception management method for RapidIOMessage transactions based on FPGA, which solves the problems raised in the above background technology by simultaneously receiving and sorting Message data from multiple different source nodes.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A method for managing out-of-order reception of RapidIO Message transactions based on FPGA includes the following steps:

[0007] Step S1: Receive the RapidIO transaction packet and enter the RapidIO driver module, perform cross-clock processing on the RapidIO interface and cache the Message transaction packet;

[0008] Step S2: Perform protocol parsing on the message transaction packet, process the parsed message transaction data to obtain message frame data and trigger a message response request, and assemble and output the packet according to the message response request;

[0009] Step S3: arbitrate the SRAM cache channel and write the message frame data into the corresponding channel;

[0010] Step S4: Map the SRAM cache address to the fragment offset of the message frame one by one, write the frame data into the corresponding space of the SRAM module, and complete the automatic sorting of the message frame;

[0011] SRAM cache is a high-performance memory used for temporary storage of data; RapidIO is a high-performance serial communication protocol used in embedded systems and high-performance computing environments; Message transactions are message transactions; IP interface refers to the interface for data communication between devices and networks, and is used for information interaction operations.

[0012] In a preferred embodiment, the out-of-order reception management method of RapidIO Message transactions based on FPGA mainly includes three modules, namely, a RapidIO IP interface module, a RapidIO driver module and a multi-channel sorting module.

[0013] The RapidIO IP interface module is used to complete the underlying sending and receiving of RapidIO transaction packets;

[0014] The RapidIO driver module is used to complete the protocol parsing of the RapidIO transaction packet and respond to the request packet that requires a response;

[0015] The multi-channel sorting module is used to sort and combine the Message transaction data from different source nodes, and output the complete Message frame data after the sorting and combination are completed.

[0016] In a preferred embodiment, the RapidIO driver module includes three modules: an AXI FIFO buffer module, a Message request transaction parsing module, and a Message response transaction packaging module;

[0017] The RapidIO driver module performs protocol analysis on the received Message transaction and responds to the Message request transaction.

[0018] The AXI FIFO buffer module is used for cross-clock domain processing of the RapidIO interface and for caching message transaction packets.

[0019] The message request transaction parsing module is used to perform protocol parsing on the message request transaction and output message framing parameters;

[0020] The message response transaction package module is used to respond to the message request transaction and package and send it according to the message response frame format.

[0021] In a preferred embodiment, in step S1, the AXI FIFO buffer module performs cross-clock domain processing on the RapidIO interface in the following specific steps:

[0022] Identify clock domains: obtain data and frequency of each clock domain, and determine the data and interfaces transmitted across clock domains;

[0023] Cross-clock domain: Use AXI FIFO with asynchronous and independent clock to achieve data and clock interface connection between different clock domains. At the same time, use double-edge triggers at the receiving end to capture data and reduce the occurrence rate of timing problems in data sampling.

[0024] Design data transmission protocol: determine the header and payload of the data packet, and control the data sending and receiving process through the existing state machine;

[0025] Data synchronization: Use synchronizers to ensure that received data is stable in the new clock domain;

[0026] Data caching: Caches data packets in the new clock domain.

[0027] In a preferred embodiment, in step S2, the message request transaction parsing module performs protocol parsing on the message transaction packet and processes the parsed message transaction data. The specific steps are as follows:

[0028] Get RapidIO transaction packets: read the original RapidIO transaction packets through the Serial RapidIO Gen2 IP interface;

[0029] Extract header information; parse payload: extract payload data based on header information;

[0030] Verification processing: Check the tail information to ensure that there are no errors in the RapidIO transaction packet during transmission;

[0031] Framing processing: Process the parsed Message transaction data to obtain framing parameters, including:

[0032] msg_id, msg_len, msg_seg, msg_data, msg_data_val, and msg_data_last are respectively the Message source ID, the number of Message fragments, the Message fragment offset, the Message data, the Message data validity, and the Message data end flag.

[0033] In a preferred embodiment, in step S2, each framing parameter corresponds to the framing data in the Message transaction packet, and triggers a Message response request after framing processing;

[0034] After receiving the Message response request, the Message response transaction packet assembly module generates the corresponding Message response transaction packet and sends it to the AXI FIFO buffer module. The AXI FIFO buffer module buffers the Message response transaction packet, processes it across clock domains, and then outputs it to the Serial RapidIO Gen2 IP interface for sending.

[0035] In a preferred embodiment, in step S3, the multi-channel sorting module includes a FIFO buffer module, a channel arbitration module, an SRAM buffer control module, an SRAM buffer module and a Message output control module;

[0036] The FIFO buffer module is used to buffer message frames;

[0037] The channel arbitration module is used to arbitrate the SRAM cache channel and enter the message frame data into the corresponding SRAM cache channel for arbitration. The arbitration steps are as follows:

[0038] When new Message frame data is received, the occupy_st register of the SRAM cache module is polled. If the msg_id of the Message frame is equal to the occupy_id in the occupied SRAM cache module, the Message frame data is written to the corresponding SRAM cache channel; otherwise, a new SRAM cache channel is applied, and the msg_id of the Message frame is assigned to the occupy_id of the SRAM, and the Message frame data is written to the new cache channel.

[0039] In a preferred embodiment, in step S4, the SRAM cache control module is used to write the message frame data of the same Message source ID to the corresponding address of the SRAM module, and allocate multiple parameters for the state management of the SRAM module, including:

[0040] occupy_id, occupy_st, msg_rlen, msg_rdata, msg_rcnt, which are SRAM occupation ID, SRAM occupation status, Message complete frame actual length, Message complete frame data and Message complete frame fragment count respectively;

[0041] occupy_id is used to query whether the message frame data from the same source node is written into the corresponding channel;

[0042] occupy_st is used to query the current occupied state of SRAM and mark the idle state as occupied_st[1:0]=2'b00;

[0043] Mark the occupied state as occupied_st[1:0]=2'b01;

[0044] Mark the packet completion status as occupy_st[1:0]=2'b10;

[0045] Mark the Message output status as occupied_st[1:0]=2'b11;

[0046] msg_rcnt is used to count the complete message frame fragments. Every time a message frame is written, the count value of msg_rcnt is increased by 1.

[0047] In a preferred embodiment, in step S4, when the Message framing storage is completed, the msg_rcnt value used for the Message framing statistical count is increased by 1, and when it is detected that the Message framing statistical count msg_rcnt is equal to the number of fragments msg_len of the Message framing, the SRAM occupancy state is set to occupied_st[1:0]=2'b10, and the Message complete frame is waited for to be output. After the output is completed, the Message complete frame is output, the framing statistical count msg_rcnt is cleared, and the SRAM occupancy state is set to occupied_st[1:0]=2'b00;

[0048] If the occupied SRAM cache channel does not complete the packet sorting within the preset specified time, when a timeout interrupt is generated, the message frame statistics count msg_rcnt is cleared and the SRAM occupation state is set to occupied_st[1:0]=2'b00.

[0049] The technical effects and advantages of the out-of-order reception management method of RapidIO Message transactions based on FPGA of the present invention are as follows:

[0050] The present invention receives a RapidIO transaction packet and transmits it to a RapidIO driver module. In the RapidIO driver module, cross-clock domain processing is performed on the RapidIO interface so that data transmission in different clock domains tends to be synchronized. After the cross-clock domain processing, the Message transaction packet is cached, the protocol is parsed on the Message transaction packet, frame data after the parsing of the Message transaction packet is obtained, the parsed Message frame data is output, and after the Message frame data is cached, an SRAM cache channel is arbitrated to obtain a matching SRAM cache channel, the Message frame data is written into a corresponding channel, the SRAM cache address is mapped with the fragment offset of the Message frame, and the frame data is written into the corresponding space of the SRAM module, thereby completing the automatic sorting of the Message frame and reducing the communication failure problem caused by the disordered retransmission of the Message transaction packet caused by the competition between the source nodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 The present invention is a schematic diagram of an out-of-order reception management method of RapidIO Message transactions based on FPGA.

[0052] Figure 2 The present invention is an FPGA logic function block diagram of an FPGA-based RapidIO Message transaction out-of-order reception management method.

[0053] Figure 3 A RapidIO driver module diagram of an FPGA-based RapidIO Message transaction out-of-order reception management method of the present invention is shown in FIG.

[0054] Figure 4 This is a multi-channel sorting module diagram of an FPGA-based RapidIO Message transaction out-of-order receiving management method of the present invention.

[0055] Figure 5 The present invention is a channel arbitration flow chart of a method for managing out-of-order reception of RapidIO Message transactions based on FPGA.

[0056] Figure 6 The present invention is a schematic diagram of the SRAM sharding sorting principle of an FPGA-based RapidIO Message transaction out-of-order receiving management method.

[0057] Figure 7 The present invention is a flow chart of SRAM slicing and packaging of an out-of-order receiving management method of RapidIO Message transactions based on FPGA. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0059] The present invention receives a RapidIO transaction packet and transmits it to a RapidIO driver module. In the RapidIO driver module, cross-clock domain processing is performed on the RapidIO interface so that data transmission in different clock domains tends to be synchronized. After the cross-clock domain processing, the Message transaction packet is cached, the protocol is parsed on the Message transaction packet, frame data after the parsing of the Message transaction packet is obtained, the parsed Message frame data is output, and after the Message frame data is cached, an SRAM cache channel is arbitrated to obtain a matching SRAM cache channel, the Message frame data is written into a corresponding channel, the SRAM cache address is mapped with the fragment offset of the Message frame, and the frame data is written into the corresponding space of the SRAM module, thereby completing the automatic sorting of the Message frame and reducing the communication failure problem caused by the disordered retransmission of the Message transaction packet caused by the competition between the source nodes.

[0060] Embodiment, a method for managing out-of-order reception of RapidIO Message transactions based on FPGA, such as Figure 1 As shown, the following steps are included:

[0061] Step S1: Receive the RapidIO transaction packet and enter the RapidIO driver module, perform cross-clock processing on the RapidIO interface and cache the Message transaction packet;

[0062] Step S2: Perform protocol parsing on the message transaction packet, process the parsed message transaction data to obtain message frame data and trigger a message response request, and assemble and output the packet according to the message response request;

[0063] Step S3: arbitrate the SRAM cache channel and write the message frame data into the corresponding channel;

[0064] Step S4: Map the SRAM cache address to the fragment offset of the message frame one by one, write the frame data into the corresponding space of the SRAM module, and complete the automatic sorting of the message frame.

[0065] The specific implementation is as follows:

[0066] The out-of-order reception management method of RapidIO Message transactions based on FPGA mainly includes three modules: Figure 2 As shown, they are RapidIO IP interface module, RapidIO driver module and multi-channel sorting module.

[0067] The RapidIO IP interface module is mainly used to complete the underlying sending and receiving of RapidIO transaction packets;

[0068] The RapidIO driver module is used to complete the protocol parsing of the RapidIO transaction packet and respond to the request packet that requires a response;

[0069] The multi-channel sorting module is used to sort and combine the Message transaction data from different source nodes, and output the complete Message frame data after the sorting and combination are completed.

[0070] It should be noted that FPGA is an integrated circuit that users can configure after manufacturing to achieve highly flexible digital circuit design. RapidIO is a high-performance serial communication protocol used in embedded systems and high-performance computing environments. Message transactions are message transactions. IP interface refers to the interface for data communication between devices and networks, which is used for information interaction operations.

[0071] In step S1, when receiving a RapidIO transaction packet, the interaction of the RapidIO transaction packet is realized by calling the Serial RapidIO Gen2IP inside the FPGA, that is, receiving the RapidIO transaction packet or transmitting the processed data file.

[0072] The RapidIO driver module mainly includes three modules: AXI FIFO buffer module, Message request transaction parsing module and Message response transaction packaging module. Figure 3 As shown, the RapidIO driver module performs protocol parsing on the received Message transaction and responds to the Message request transaction.

[0073] The AXI FIFO buffer module is used for cross-clock domain processing of the RapidIO interface and caches the Message transaction packets. The Message request transaction parsing module is used to perform protocol parsing on the Message request transaction and output the Message framing parameters. The Message response transaction packet assembly module is used to respond to the Message request transaction and assemble and send the packet according to the Message response frame format.

[0074] The specific steps for the AXI FIFO buffer module to process the RapidIO interface across clock domains are as follows:

[0075] Identify clock domains: obtain the data and frequency of each clock domain, and determine the data and interfaces that need to be transmitted across clock domains, namely the message transaction packet and Serial RapidIO Gen2 IP interface in this example;

[0076] Cross-clock domain: Use AXI FIFO with asynchronous and independent clock to achieve data and clock interface connection between different clock domains. At the same time, use double-edge triggers at the receiving end to capture data and reduce the occurrence rate of timing problems in data sampling.

[0077] Design data transmission protocol: determine the header and payload of the data packet, and control the data sending and receiving process through the existing state machine;

[0078] Data synchronization: Use synchronizers to ensure that received data is stable in the new clock domain;

[0079] Data caching: Caches data packets in the new clock domain.

[0080] It should be noted that the clock domain refers to the circuit part driven by a specific clock signal in digital circuit design. The circuits in each clock domain work synchronously in the same clock cycle, but different clock domains may operate at different clock frequencies and phases, resulting in data inconsistency or loss, which requires cross-clock domain processing; the synchronizer used in data synchronization is not unique, for example, a dual D flip-flop synchronizer is used for data synchronization.

[0081] In step S2, after the AXI FIFO buffer module performs cross-clock domain processing on the RapidIO interface, the Message request transaction parsing module performs protocol parsing on the Message transaction packet and processes the parsed Message transaction data. The specific steps are as follows:

[0082] Get RapidIO transaction packets: read the original RapidIO transaction packets through Serial RapidIO Gen2 IP;

[0083] Extract header information: parse the transaction packet header, extract key fields, determine the transaction packet type, and after determining it is a Message transaction packet, understand the length of the payload;

[0084] Parsing the payload: Extracting the payload data based on the header message;

[0085] Verification processing: Check the tail information to ensure that there are no errors in the RapidIO transaction packet during transmission;

[0086] Framing processing: Process the parsed Message transaction to obtain framing parameters, including:

[0087] msg_id, msg_len, msg_seg, msg_data, msg_data_val, msg_data_last, which are Message source ID, number of Message fragments, Message fragment offset, Message data, Message data validity, and Message data end flag respectively;

[0088] Each framing parameter corresponds to the corresponding framing data in the Message transaction packet, and triggers a Message response request after framing processing.

[0089] After receiving the Message response request, the Message response transaction packet assembly module generates the corresponding Message response transaction packet and sends it to the AXI FIFO buffer module. The AXI FIFO buffer module buffers the Message response transaction packet, processes it across clock domains, and then outputs it to the Serial RapidIO Gen2 IP interface for sending.

[0090] It should be noted that the Serial RapidIO Gen2 IP is a preset IP interface in this example, which is used to exchange RapidIO transaction packets. The parsing algorithm and the verification algorithm are not unique. For example, the parsing algorithm can use recursive downward parsing, and the verification algorithm can use cyclic redundancy checking.

[0091] In step S3, the multi-channel sorting module includes a FIFO buffer module, a channel arbitration module, an SRAM buffer control module, an SRAM buffer module and a Message output control module. Figure 4 As shown, the multi-channel sorting module sorts and combines the Message transaction data of different source nodes, that is, sorts the Message frame data output by the RapidIO driver module according to the frame parameters and then merges and outputs the complete Message frame data.

[0092] The FIFO buffer module is used to buffer message frames;

[0093] The channel arbitration module is used to arbitrate the SRAM cache channel and enter the message frame data into the corresponding SRAM cache channel for arbitration. The process relationship is as follows: Figure 5 As shown, the arbitration steps are as follows:

[0094] When new Message frame data is received, the occupy_st register of the SRAM cache module is polled. If the msg_id of the Message frame is equal to the occupy_id in the occupied SRAM cache module, the Message frame data is written to the corresponding SRAM cache channel; otherwise, a new SRAM cache channel is applied, and the msg_id of the Message frame is assigned to the occupy_id of the SRAM, and the Message frame data is written to the new cache channel.

[0095] The SRAM cache control module is used to write the message frame data of the same Message source ID to the corresponding address of the SRAM module, and allocate multiple parameters for the status management of the SRAM module, such as Figure 6 As shown, including:

[0096] occupy_id, occupy_st, msg_rlen, msg_rdata, and msg_rcnt are respectively SRAM occupation ID, SRAM occupation status, actual length of the Message complete frame, Message complete frame data, and Message complete frame fragment count.

[0097] occupy_id is used to query whether the message frame data from the same source node is written into the corresponding channel;

[0098] occupy_st is used to query the current occupied state of SRAM, mark the idle state as occupied_st[1:0]=2'b00; mark the occupied state as occupied_st[1:0]=2'b01; mark the packet completion state as occupied_st[1:0]=2'b10; mark the Message output state as occupied_st[1:0]=2'b11;

[0099] msg_rcnt is used to count the complete message frame fragments. Every time a message frame is written, the count value of msg_rcnt is increased by 1.

[0100] The SRAM cache channel is arbitrated through the channel arbitration module to ensure that the Message frame data from the same source ID is written into the same SRAM cache channel, reducing resource competition conflicts and reasonably avoiding competition and conflicts for shared resources when multiple Message transactions access the SRAM cache at the same time. Using msg_rcnt to count the Message complete frame fragments to determine the occupancy of the Message transaction can improve concurrency performance and lay an auxiliary foundation for the subsequent addition of high-priority transaction processing. When the fragment offset is set, when the data to be transmitted exceeds the capacity of a single Message transaction, the data can be divided into multiple "fragments" for transmission. The fragment offset is used to identify the relative position of each fragment in the entire data for fragment transmission, which increases the inclusiveness of data transmission.

[0101] It should be noted that SRAM cache is a high-performance memory used to temporarily store data and accelerate data access and processing. Figure 6 The two variables sram_addr[11:8] and sram_addr[7:0] represent the address bus of SRAM, [11:8] represents the high 4-bit address; [7:0] represents the low 8-bit address, together they constitute the complete address of SRAM; sram_wdata variable represents the SRAM data written; sram_wen variable represents the write enable signal of SRAM, which is used to control the write operation of SRAM; sram_rdata variable represents the data read from SRAM.

[0102] In step S4, the SRAM cache address is mapped to the fragment offset of the message frame, and the frame data is written into the corresponding space of the SRAM module to complete the automatic sorting of the message frame. Figure 7 As shown, the SRAM cache module is used to cache the complete message frame. Since the maximum length of a single message supported by RapidIO is 4096 bytes, it can be divided into 16 packets at most for fragmented data transmission. The maximum length of each packet is 256 bytes, and 4096 cache spaces are opened for the SRAM cache. The address addressing range is sram_waddr[11:0]: 0x000~0xFFF. The high 4-bit address sram_waddr[11:8] of the SRAM cache is mapped one by one with the fragment offset msg_seg[3:0] of the frame, that is, the SRAM cache is divided into 16 cache spaces with a length of 256 bytes. In the process of storing the message frame, the frame data is written into the corresponding space of the SRAM module through the fragment offset, thereby completing the automatic sorting function of the message frame;

[0103] When the Message frame storage is completed, the msg_rcnt value used for the Message frame statistics count is increased by 1. When it is detected that the Message frame statistics count msg_rcnt is equal to the number of fragments msg_len of the Message frame, the SRAM occupancy status is set to occupied_st[1:0]=2'b10, that is, the SRAM occupancy status is set to the packet assembly completion status, waiting for the Message complete frame to be output. After the output is completed, the Message complete frame, the frame statistics count msg_rcnt is cleared, and the SRAM occupancy status is set to occupied_st[1:0]=2'b00, that is, the SRAM occupancy status is set to the idle state.

[0104] If the occupied SRAM cache channel does not complete the packet sorting within the preset specified time, when a timeout interrupt is generated, the message frame statistics count msg_rcnt is cleared and the SRAM occupation state is set to occupied_st[1:0]=2'b00.

[0105] The Message output control module is used to output a complete Message frame after the SRAM module completes the packet assembly. By polling the SRAM status occupy_st of each channel, when it is detected that the SRAM is in the packet assembly completion state, the Message data in the SRAM module is displayed and output. The output message complete frame includes:

[0106] Msg_rid, msg_rlen, msg_rdata, msg_rdv, msg_rsof, and msg_reof are respectively the Message receiving source ID, the Message receiving length, the Message receiving data, the Message receiving data validity, the Message receiving data start flag, and the Message receiving data end flag.

[0107] It should be noted that the fragment offset refers to the starting position or relative position of different fragments in the entire data stream when the data is divided into multiple fragments for transmission. It is used to identify the position field of a specific fragment in the entire data block. Through the fragment offset, the position of the fragment in the entire data stream is used to correctly reassemble the original data. For large-scale RapidIO switching systems, the RapidIO driver module and the multi-channel sorting module are used to reduce the communication failure caused by the disordered retransmission of Message transaction packets due to competition between source nodes, and expand the subsequent application scenario analysis of the RapidIO bus in embedded systems.

[0108] The above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented by software, the above embodiments may be implemented in whole or in part in the form of a computer program product.

[0109] Those of ordinary skill in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application of the technical solution and the invention constraints. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0110] In addition, each functional module in each embodiment of the present application may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.

[0111] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0112] Finally: The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for managing out-of-order reception of RapidIO Message transactions based on FPGA, characterized in that: The following steps are included: Step S1: Receive the RapidIO transaction packet and enter the RapidIO driver module, perform cross-clock processing on the RapidIO interface and cache the Message transaction packet; Step S2: Perform protocol parsing on the message transaction packet, perform frame processing on the parsed message transaction data to obtain message frame data and trigger a message response request, and perform packet output according to the message response request; Step S3: arbitrate the SRAM cache channel and write the message frame data into the corresponding channel; Step S4: Map the SRAM cache address to the fragment offset of the message frame one by one, write the frame data into the corresponding space of the SRAM module, and complete the automatic sorting of the message frame; SRAM cache is a high-performance memory used to temporarily store data; RapidIO is a high-performance serial communication protocol used in embedded systems and high-performance computing environments; Message transactions are message transactions; IP interface refers to the interface for data communication between devices and networks, used for information interaction operations; The out-of-order receiving management method of RapidIO Message transactions based on FPGA includes three modules, namely RapidIO IP interface module, RapidIO driver module and multi-channel sorting module; The RapidIO IP interface module is used to complete the underlying sending and receiving of RapidIO transaction packets; The RapidIO driver module is used to complete the protocol parsing of the RapidIO transaction packet and respond to the request packet that requires a response; The multi-channel sorting module is used to sort and combine the message transaction data from different source nodes, and output the complete message frame data after the sorting and combination is completed; In step S3, the multi-channel sorting module includes a FIFO buffer module, a channel arbitration module, an SRAM buffer control module, an SRAM buffer module and a Message output control module; The FIFO buffer module is used to buffer message frames; The channel arbitration module is used to arbitrate the SRAM cache channel and enter the message frame data into the corresponding SRAM cache channel for arbitration. The arbitration steps are as follows: When new message frame data is received, the occupy_st register of the SRAM cache module is polled. If the msg_id and occupy_id of the message frame in the occupied SRAM and cache module are equal, the message frame data is written into the corresponding SRAM cache channel; otherwise, a new SRAM cache channel is applied, and the msg_id of the message frame is assigned to the occupy_id of the SRAM, and the message frame data is written into the new cache channel; In step S4, the SRAM cache control module is used to write the message frame data of the same Message source ID to the corresponding address of the SRAM module, and allocate multiple parameters for the state management of the SRAM module, including: occupy_id, occupy_st, msg_rlen, msg_rdata, msg_rcnt, which are SRAM occupation ID, SRAM occupation status, Message complete frame actual length, Message complete frame data and Message complete frame fragment count respectively; occupy_id is used to query whether the message frame data from the same source node is written into the corresponding channel; occupy_st is used to query the current occupied state of SRAM and mark the idle state as occupied_st[1:0]=2'b00; Mark the occupied state as occupied_st[1:0]=2'b01; Mark the packet completion status as occupy_st[1:0]=2'b10; Mark the Message output status as occupied_st[1:0]=2'b11; When msg_rcnt is working, it counts the complete message frame fragments. Every time a message frame is written, the count value of msg_rcnt is increased by 1.

2. The method for managing out-of-order reception of RapidIO Message transactions based on FPGA according to claim 1, characterized in that: The RapidIO driver module contains three modules: AXI FIFO buffer module, Message request transaction parsing module and Message response transaction packaging module; The RapidIO driver module performs protocol analysis on the received Message transaction and responds to the Message request transaction. The AXI FIFO buffer module is used for cross-clock domain processing of the RapidIO interface and for caching message transaction packets. The message request transaction parsing module is used to perform protocol parsing on the message request transaction and output message framing parameters; The message response transaction package module is used to respond to the message request transaction and package and send it according to the message response frame format.

3. The method for managing out-of-order reception of RapidIO Message transactions based on FPGA according to claim 2, characterized in that: In step S1, the AXI FIFO buffer module performs cross-clock domain processing on the RapidIO interface. The specific steps are as follows: Identify clock domains: obtain the source, frequency, and phase of each clock domain, and determine the data and interfaces transmitted across clock domains; Cross-clock domain: Use AXI FIFO buffer to buffer data, and use double-edge triggers to capture data at the receiving end to reduce the occurrence of timing problems in data sampling; Design data transmission protocol: determine the header and payload of the data packet, and control the data sending and receiving process through the existing state machine; Data synchronization: Use synchronizers to ensure that received data is stable in the new clock domain; Data caching: Caches data packets in the new clock domain.

4. The method for managing out-of-order reception of RapidIO Message transactions based on FPGA according to claim 2, characterized in that: In step S2, the message request transaction parsing module performs protocol parsing on the message transaction packet and performs framing processing on the parsed message transaction data. The specific steps are as follows: Get RapidIO transaction packets: read the original RapidIO transaction packets through the Serial RapidIO Gen2 IP interface; Extract header information; parse payload: extract payload data based on header information; Verification processing: Check the tail information to ensure that there are no errors in the RapidIO transaction packet during transmission; Framing: Framing the message transaction package to obtain framing parameters, including: msg_id, msg_len, msg_seg, msg_data, msg_data_val, and msg_data_last are respectively the Message source ID, the number of Message fragments, the Message fragment offset, the Message data, the Message data validity, and the Message data end flag.

5. The method for managing out-of-order reception of RapidIO Message transactions based on FPGA according to claim 4, characterized in that: In step S2, each framing parameter corresponds to the framing data in the Message transaction packet, and triggers a Message response request after framing processing; The Message response transaction packet assembly module converts the Message request transaction packet after framing into a Message response transaction packet and transmits it back to the AXI FIFO buffer module. The AXI FIFO buffer module caches the framing parameters and the Message response transaction packet and outputs the Message response transaction packet.

6. The method for managing out-of-order reception of RapidIO Message transactions based on FPGA according to claim 1, characterized in that: In step S4, when the Message frame storage is completed, the msg_rcnt value used for the Message frame statistics count is increased by 1. When it is detected that the Message frame statistics count msg_rcnt is equal to the number of fragments msg_len of the Message frame, the SRAM occupancy state is set to occupied_st[1:0]=2'b10, and the Message complete frame is waited for to be output. After the output is completed, the Message complete frame is cleared, and the SRAM occupancy state is set to occupied_st[1:0]=2'b00; If the occupied SRAM cache channel does not complete the packet sorting within the preset specified time, when a timeout interrupt is generated, the message frame statistics count msg_rcnt is cleared and the SRAM occupation state is set to occupied_st[1:0]=2'b00.

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