Token indicating completion of data storage

Abstract

The invention relates to a token indicating completion of data storage. Systems, devices, and methods related to a token indicating completion of data storage to memory are described. An exemplary method may include storing, by a first page in a first row of a memory cell array, a plurality of data values in response to receiving a first command from a host, wherein the first command is associated with an open transaction token; and receiving a second command from the host to store a plurality of data values by a second page in the first row. The method may further include sending a security token to the host to indicate completion of storage of the plurality of data values by the second page in the first row.

Description

[0001] Divisional Application Information

[0002] This application is a divisional application of an invention patent application with an application date of October 15, 2020, application number "202011104668.2", and invention name "Token indicating completion of data storage". Technical Field

[0003] The present disclosure relates generally to semiconductor memories and methods, and more particularly to tokens that indicate completion of data storage to the memory. Background Art

[0004] Memory devices are typically provided as internal, semiconductor, integrated circuit and / or external removable devices in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data, and may include random access memory (RAM), dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory can maintain stored data when not powered on, and may include NAND flash memory, NOR flash memory, phase change random access memory (PCRAM), resistive random access memory (RRAM) and magnetic random access memory (MRAM), etc.

[0005] Memory storage devices may be combined together to form a solid state drive (SSD). An SSD, embedded multimedia card (eMMC) memory, or universal flash storage (UFS) memory may include non-volatile memory (e.g., NAND flash memory, NOR flash memory, and / or wireless memory), and / or may include volatile memory (e.g., DRAM and / or SRAM) and various other types of non-volatile and volatile memory. For example, a flash memory device may include memory cells that store data in a charge storage structure (e.g., a floating gate or a charge trap), and may be used as non-volatile memory for a wide range of electronic applications. A flash memory device may use a single transistor memory cell that allows for high memory density, high reliability, and low power consumption.

[0006] Improving memory storage devices may include reducing power consumption, increasing reliability of data retention, preventing potential modification of data values ​​due to interruptions in energy supply, and / or reducing manufacturing costs, among other things. Summary of the invention

[0007] One aspect of the present disclosure relates to a method of storing data, comprising: storing multiple data values ​​by a first page in a first row of a memory cell array in response to receiving a first command from a host, wherein the first command is associated with an open transaction token; receiving a second command from the host to store multiple data values ​​by a second page in the first row; and sending a security token to the host to indicate completion of storage of the multiple data values ​​by the second page in the first row.

[0008] Another aspect of the present disclosure relates to a data storage device, comprising: a multi-layer memory cell array, wherein the corresponding cells are each configured to store a plurality of data values ​​corresponding to a corresponding plurality of lower pages in a first row, and to store data values ​​corresponding to an upper page in the first row; and a controller coupled to the array, wherein the controller is configured to: direct programming of the upper page in the first row in response to receiving a first command containing a plurality of data values ​​to be stored by the upper page, wherein the first command is associated with a first open transaction token; direct programming of a specific lower page in the plurality of lower pages in the first row in response to receiving a second command containing a plurality of data values ​​to be stored by the specific lower page; and output a security token to indicate completion of programming of the specific lower page in the plurality of lower pages in the first row.

[0009] Yet another aspect of the present disclosure relates to a system for storing data, comprising: a host configured to generate a command for storing a data value; and a memory device coupled to the host, wherein the memory device comprises: an array of memory cells, wherein the respective cells are each configured to store a data value corresponding to a first page of a particular row, and to store a data value corresponding to a second page of a particular row; and a controller coupled to the array, wherein the controller is configured to: direct programming of the first page in a first row in response to receiving a first command from the host containing a plurality of data values ​​to be stored by the first page, wherein the first command is associated with a first open transaction token; direct programming of a second page in the first row in response to receiving a second command from the host containing a plurality of data values ​​to be stored by the second page; and send a security token to the host to indicate completion of programming of the second page in the first row, wherein the security token is associated with an indicator of a logical location of each of the data values ​​stored by the first page and the second page; wherein the security token sent to the host cancels the first open transaction token and indicates that the programming of the second page in the first row has been completed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A block diagram of an exemplary computing system according to one embodiment of the present disclosure is shown.

[0011] Figure 2 A diagram showing a portion of an exemplary memory array according to one embodiment of the present disclosure.

[0012] Figure 3A is a schematic diagram of a portion of an exemplary non-volatile memory array according to one embodiment of the present disclosure.

[0013] Figure 3B is a schematic diagram of a portion of an exemplary nonvolatile memory array of four levels of nonvolatile memory cells according to one embodiment of the present disclosure.

[0014] Figure 4 A table showing tokens that may be used by a host and a memory device according to one embodiment of the present disclosure.

[0015] Figure 5 An exemplary sequence of a host and a memory device using a token according to one embodiment of the present disclosure is shown.

[0016] Figure 6 is a flow chart of an exemplary method for using a token to indicate completion of storing data to a memory according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0017] Various types of memory devices may have conductive paths to enable access to various components. The conductive paths may include electrodes, access lines (e.g., word lines), and sense lines (e.g., bit lines), as well as other possible conductive paths. Components accessible via conductive paths may include control circuitry, sense amplifiers, memory cells, transistors, and memory storage nodes (e.g., floating gates, capacitors, etc.), as well as other possible components powered by an energy source (e.g., an electrical power source).

[0018] For example, a memory cell in a flash array architecture (NAND or NOR) can be programmed (e.g., as a result of a write operation) to a desired state. Charge can be placed on or removed from a floating gate or charge trap of a memory cell to cause the cell to enter a variety of data value storage states. A single-level cell (SLC) can represent two binary states (e.g., 1 or 0). A flash memory cell can also store more than two binary states (e.g., 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 0000, 1000, 1010, 0010, 0110, and 1110 for a four-level memory cell). This cell may be referred to as a multi-state memory cell, a multi-bit cell, or a multi-level cell (MLC). MLCs can allow the manufacture of higher density memories without increasing the number of memory cells because each cell can represent more than one bit. MLCs can have more than one programming state. For example, a quad level cell capable of storing four bits may have fifteen programmed states and one erased state.

[0019] The memory cells in an SLC flash array can each have only two potential charge levels. The two potential charge levels can correspond to two binary states. The charge level (e.g., data value) of a nonvolatile memory cell programmed to one of these binary states can be relatively stable even when the SLC flash array is turned off and / or the power supply from the energy source is interrupted. In contrast, the memory cells in an MLC flash array can each have more than two potential charge levels. The number of potential charge levels can correspond to the two binary states of each layer of memory cells in the MLC flash array, and can be calculated exponentially using 2 as the base and the number of layers as the exponent. For example, the number of potential charge levels for a two-layer MLC is 2. 2 =4, the number of potential charge levels of a three-layer MLC is 2 3 =8, the number of potential charge levels for a four-layer MLC is 2 4 =16, and so on.

[0020] Thus, for example, for a two-layer MLC, the potential charge level may have one erased state and three programming states with gradually increasing charge, while for a four-layer MLC, the potential charge level may have one erased state and fifteen programming states with gradually increasing charge. The charge level (e.g., data value) of a nonvolatile MLC programmed to one of these multiple binary states may be relatively unstable (e.g., compared to an SLC) in a transition state where one or more layers remain unprogrammed. For example, when the upper and / or lower layers of the MLC remain unprogrammed, the transition state may allow the voltage level corresponding to a particular data value to be shifted at a programming level. An interruption in the power supply from the energy source to the MLC may prevent the upper and / or lower layers of the MLC from being programmed, which may result in instability of the previously programmed charge level corresponding to the data value. MLC memory stores multiple bits on each cell by using a different threshold level for each state stored. The difference between adjacent threshold voltage distributions may be small compared to SLC memory. Thus, the effects of a power outage preventing programming of upper and / or lower layers of the MLC may increase the probability of unintended modification (eg, loss, corruption, etc.) of previously programmed data values.

[0021] For example, a row of MLCs in a NAND array may be formed of a series of nonvolatile MLCs (e.g., 4,096 memory cells, 8,192 memory cells, 16,384 memory cells, etc.) each having multiple layers for storing potential charge levels corresponding to the multiple bits storable on each cell. In a row of two-layer MLCs, the first layer in each MLC may be collectively referred to as a first page (e.g., an upper page) for storing a data value corresponding to a first bit, and the second layer in each MLC may be collectively referred to as a second page (e.g., a lower page) for storing a data value corresponding to a second bit.

[0022] A host may be coupled to a memory device including an array of MLCs. The host may be configured to send data (e.g., data values) to the memory device and / or the array of MLCs for storage at a particular logical location (e.g., corresponding to a particular physical address of an MLC and / or page in the array). The host may be configured to monitor the stability or instability (e.g., security) of data intended to be programmed (e.g., written) to the MLCs of the array. For example, when a power outage prevents programming of a second page (e.g., an upper page and / or a lower page) of the MLCs due to, for example, a potential shift in voltage levels in a transition state, the security of the data stored in the first page may be compromised. Thus, monitoring by the host whether programming of the second page has been completed after programming of the first page may indicate whether an intervening power outage has occurred.

[0023] If such a power outage (or other event that prevents programming) has not occurred and / or the first and second pages have already been programmed, the host can determine the security of the data on the first page (and the second page) based on the data being securely stored by the intended MLCs and / or pages of the array. Such a determination can cause the host to subsequently send additional data to the memory device for storage in the MLC array, as described herein.

[0024] As described herein, the determination of such a power outage can prevent the host from sending data to the memory device again for storage in the MLC array. For example, when it has been determined that a power outage (or another event) has occurred to prevent programming of the second page, the host can determine that the data of the first page is not safely stored, and the host can delay (e.g., stop) sending additional data. The host can send the previously sent data and additional data again after restoring the power supply, and / or can guide the memory device to recover the previously sent data from a backup data storage component (e.g., a backup memory page of the SLC, a capacitor, etc.). In an embodiment in which there are backup data storage components, these components can be used to store data (associated with commands) when the data is provided to the memory device so that the stored data values ​​can be recovered for programming of the MLC memory. This recovery of data values ​​from the backup data storage component (e.g., after restoring the power supply) can be performed in the case where the input of commands and / or data from the host was previously interrupted.

[0025] In contrast, in various embodiments of the present disclosure, based on the use of tokens to indicate completion of data storage to the MLC memory (as described herein), a storage device including the MLC memory (e.g., as shown at 100 and 110, respectively, and in conjunction with Figure 1 A computing system configured as described herein (described herein) so as not to include a backup data storage component (e.g., spare memory). The tokens described herein can be used to indicate (e.g., ensure) that data corresponding to a command from a host has not only been programmed (e.g., written) to the appropriate location (layer in the MLC memory), but has also been programmed securely. The computing system so configured can save bandwidth and / or increase endurance by reducing unnecessary attempts and / or repeated attempts at data programming, such as after a power outage. In addition to not including a backup data storage component, saving bandwidth and / or increasing endurance may also help reduce manufacturing and / or operating costs.

[0026] The present disclosure includes systems, devices, and methods related to tokens indicating completion of data storage to a memory. An example of the method described herein includes: storing a plurality of data values ​​by a first page in a first row of a memory cell array in response to receiving a first command from a host, wherein the first command is associated with an open transaction token; and receiving a second command from the host to store a plurality of data values ​​by a second page in the first row. The method may further include: sending a security token to the host to indicate completion of storage of the plurality of data values ​​by the second page in the first row.

[0027] In the following detailed description of the present disclosure, reference is made to the accompanying drawings which form a part of the present disclosure and in which is shown by way of illustration how one or more embodiments of the present disclosure may be practiced. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the embodiments of the present disclosure, and it is to be understood that other embodiments may be utilized and process, electrical and / or structural changes may be made without departing from the scope of the present disclosure.

[0028] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number of the figure and the remaining digits identify an element or component in the figure. Similar elements or components between different figures may be identified by using similar numerals. For example, 104 may be Figure 1 Elements are marked with "04" in the Figure 5 In some examples, multiple similar but functionally and / or structurally distinguishable elements or components in the same figure or in different figures may be sequentially labeled with the same element number (e.g., Figure 2 In addition, the labels "B", "M", "N", "R", and "S" used herein, particularly with respect to the reference numerals in the accompanying drawings, are intended to indicate that one or more of the specific features so labeled can be included in embodiments of the present disclosure.

[0029] Figure 1 1 shows a block diagram of a computing system 100 according to an embodiment of the present disclosure. Figure 1As shown in , computing system 100 may include a device in the form of a host 102 and a memory device 104. As used herein, a "device" may refer to, but is not limited to, any of a variety of structures or combinations of structures (such as, for example, a circuit or circuit system, one or more dies, one or more modules, one or more devices, or one or more systems). Computing system 100 may include an energy source 101 (e.g., a battery, a capacitor, a power outlet, etc.). Host 102 and memory device 104 may be coupled to energy source 101 to provide energy (e.g., electricity) to host 102 and memory device 104. In various embodiments, host 102 and memory device 104 may be coupled to different energy sources.

[0030] Host 102 may include memory such as RAM (not shown to avoid obscuring embodiments of the present disclosure) and memory access devices such as processor 114. Processor 114 may represent one or more processors, such as a parallel processing system, one or more coprocessors, etc. Exemplary hosts may include laptop computers, personal computers, digital cameras, digital recording and playback devices, mobile devices (e.g., smart phones, tablets, etc.), personal digital assistants (PDAs), memory card readers, interface hubs, etc.

[0031] like Figure 1 As shown in , the host 102 may include a file register (e.g., as shown at register 111) to store an indicator of a logical location of a data value stored by the memory 110 of the memory device 104 in response to a command (CMD) sent by the host 102 to the controller 108 of the memory device 104. The host 102 may further include a first token component 107-1 (as will be further described herein) to serve as a source of token sources that can be used to monitor the completion of data storage (e.g., creation, storage, update, etc.). The completion of data storage may indicate that the corresponding data value is protected from accidental modification (e.g., security) due to, for example, an interruption of energy supplied to the memory device 104 before the data storage is completed.

[0032] like Figure 1 As shown in FIG. 1 , the host 102 may include a controller 116 coupled directly or indirectly to the processor 114, the file register 111, and the first token component 107-1. The host 102 may further include an interface 118 coupled directly or indirectly to the controller 116, the file register 111, and the first token component 107-1. Although not shown in FIG. Figure 1 1 so as not to obscure the embodiments of the present disclosure, but the host 102 may also include and / or be configured to implement an application that uses a driver (e.g., a Universal Flash Storage (UFS) driver) to communicate with the memory device 104. The driver may manage the controller 116 through a UFS host controller interface (not shown).

[0033] like Figure 1 As shown in , the memory device 104 can include an interface 106 directly or indirectly coupled to a controller 108, a second token component 107-2, and a memory 110. The controller 108 can be coupled to the memory 110 and the second token component 107-2. As will be further described herein, the second token component 107-2 can be used as a source of tokens that can be combined with tokens from the first token component 107-1 to monitor the completion of data storage (e.g., creation, storage, update, etc.).

[0034] In various embodiments, the memory device 104 may be a UFS memory device. The UFS memory device may be, for example, a memory card (full size or micro size), an embedded bootable mass storage device, or an IO device. Although not shown to avoid obscuring the embodiments of the present disclosure, the UFS device may also include multiple logical units (LUs) and a device manager. The device manager may perform device-level functions such as power management and monitoring; the LU may perform functions such as writing data to or reading data from the memory 110; and the file register 111 may store relevant information. In addition, although in Figure 1 One memory 110 is shown in FIG. 1 , but embodiments of the present disclosure are not limited thereto (eg, the memory device 104 may include more than one memory coupled to the controller 108 ).

[0035] Interfaces 106 and 118 may be used to communicate information (e.g., data) between host 102 and memory device 104. For example, interfaces 106 and 118 may provide an interface for passing control, addresses, information (e.g., data), tokens, indicators, and other signals between memory device 104 and host 102.

[0036] In a number of embodiments, interfaces 106 and 118 may be physical interfaces, such as standardized physical interfaces. For example, when memory device 104 is used for information storage in computing system 100, interfaces 106 and 118 may be UFS interfaces, serial advanced technology attachment (SATA) physical interfaces, peripheral component interconnect fast (PCIe) physical interfaces, or universal serial bus (USB) physical interfaces, as well as other physical connectors and / or interfaces. For example, when interfaces 106 and 118 are UFS interfaces, interfaces 106 and 118 may include a UFS interconnect (UIC) layer between host 102 and memory device 104 including MIPI UniPro and MIPI M-PHY. The physical layer M-PHY may be a differential dual simplex PHY including TX and RX pairs. In these embodiments, memory device 104 may receive energy from host 102 and / or communicate information with host 102 via a wired connection to host 102 (e.g., host 102 and memory device 104 may be coupled via a wired connection).

[0037] The controller 108 may communicate with the memory 110 to sense (e.g., read), program (e.g., write), and / or erase information, among other operations. The controller 108 may include, for example, control circuitry and / or logic (e.g., hardware and / or firmware). The controller 108 may be included on the same physical device (e.g., the same die) as the memory 110, or may be included on a different physical device that is communicatively coupled to the physical device that includes the memory 110. In various embodiments, components of the controller 108 may be spread across multiple physical devices (e.g., some components on the same die as the memory 110, and some components on different dies, modules, or boards).

[0038] The memory 110 may include, for example, one or more non-volatile memory arrays (e.g., it may include one or more non-volatile memory cells). For example, the memory 110 may be a flash memory having a NAND architecture. Examples of the memory 110 will be further described herein (e.g., in conjunction with Figure 2 and 3A -3B). However, embodiments of the present disclosure are not limited to a particular type of memory or memory device. For example, in various embodiments, memory 110 may be NOR, SRAM, DRAM, RRAM, FeRAM, and / or PCRAM, as well as other types of volatile and non-volatile memory.

[0039] In a NAND architecture, the control gates of a "row" of memory cells may be coupled to an access (e.g., word) line, while the memory cells may be coupled in a "string" of source-to-drain series between select gate source transistors and select gate drain transistors. The string may be connected to a data sense (e.g., bit) line through the select gate drain transistors. The use of the terms "row" and "string" does not imply a linear or orthogonal arrangement of the memory cells. As will be appreciated by one of ordinary skill in the art, the manner in which the memory cells are connected to the bit lines and source lines depends on whether the array is a NAND architecture, a NOR architecture, or some other memory array architecture.

[0040] One or more memory arrays of memory 110 may include one or more memory cells that may be grouped. As used herein, a group may include one or more memory cells, such as a page, a block, a plane, a die, an entire array, or other group of memory cells. For example, some memory arrays may include one or more pages of memory cells that constitute a block of memory cells. One or more blocks may be included in a plane of memory cells, and one or more planes of memory cells may be included on a die. For example, a 128GB memory device may contain 4320 bytes of information per page, 128 pages per block, 2048 blocks per plane, and 16 planes per device.

[0041] Figure 1 The embodiments shown in the drawings may include additional circuitry, which is not shown to avoid obscuring the embodiments of the present disclosure. For example, memory 110 may include address circuitry to latch address signals provided on an input / output (I / O) connector via I / O circuitry. The address signals may be received and decoded by a row decoder and a column decoder to access memory 110 (e.g., one or more arrays of memory 110).

[0042] Complementary to the use of tokens as described herein to indicate completion of data storage (which is used to protect against potential interruptions in energy supplied from energy source 101), host 102 (e.g., processor 114 and / or controller 116) can determine energy information of memory device 104 (e.g., memory 110) and provide the energy information to memory device 104 (e.g., controller 108). For example, host 102 can process information including characteristics (e.g., type) of its energy source 101 (e.g., whether its battery is removable or non-removable), charge level, capacity (e.g., charge storage capacity), characteristics of system 100 and its user activity (e.g., rate of system power consumption due to, for example, a display being turned on or off), whether the energy source is currently charging, whether the energy currently being supplied to memory device 104 is unlimited (e.g., because host 102 is plugged into an outlet), and / or the age of its energy source. The host 102 may use this processing information to determine whether it is necessary for the memory device 104 to perform a power loss protection operation (e.g., a sudden power failure recovery operation) to protect data that has been programmed and / or is being programmed to the memory 110 from the sudden and / or unexpected energy loss, and / or to determine whether a sufficient amount of energy is available from its energy source 101 to maintain normal operation. The host 102 may then provide this determination to the memory device 104, for example, using a single data bit.

[0043] Figure 2 A diagram showing a portion of an exemplary memory array 220 according to one embodiment of the present disclosure. In various embodiments, the memory array 220 may be a memory array previously described in conjunction with Figure 1 Memory 110 described. In addition, although not in Figure 2 2 , but memory array 220 may be located on a particular semiconductor die along with various peripheral circuitry associated with its operation.

[0044] like Figure 2 As shown in , the memory array 220 may include one or more physical blocks 224-0 (block 0), 224-1 (block 1), ..., 224-B (block B) of memory cells. The memory cells may include SLC and / or MLC, such as, for example, two-level cells, three-level / triple level cells (TLC), and / or four-level / quadruple level cells (QLC), among other possibilities. For example, the number of physical blocks in the memory array 220 may be 128 blocks, 512 blocks, or 1,024 blocks, but embodiments are not limited to a specific power of two or any specific number of physical blocks in the memory array 220.

[0045] One or more physical blocks of memory cells (e.g., blocks 224-0, 224-1, ..., 224-B) may be included in a memory cell plane, and one or more memory cell planes may be included on a die. Figure 2 In the example shown in FIG. 1 , each physical block 224-0, 224-1, ..., 224-B may be part of a single die. That is, Figure 2 The portion of memory array 220 shown in FIG. 2 may be a die of memory cells.

[0046] like Figure 2 As shown in , each physical block 224-0, 224-1, ..., 224-B includes one or more physical rows (e.g., 221-0, 221-1, ..., 221-R) of memory cells coupled to access lines (e.g., word lines). The number of rows (e.g., word lines) in each physical block can be 32, but embodiments are not limited to a specific number of rows 221, 221-1, ..., 221-R per physical block. In addition, although not shown in Figure 2 , but the memory cells may be coupled to sense lines (eg, bit lines, data lines, and / or digit lines).

[0047] In various embodiments, each row 221-0, 221-1, ..., 221-R may include one or more memory cell pages (e.g., physical pages). A physical page refers to a programmed and / or sensed cell (e.g., one or more memory cells that are programmed and / or sensed together as a functional group). Figure 2 In the embodiment shown in , each row 221-0, 221-1, ..., 221-R appears to show a physical page of memory cells; however, the embodiments of the present disclosure are not limited thereto. For example, in multiple embodiments, each row may include multiple physical pages of memory cells (e.g., one or more even pages of memory cells coupled to even bit lines, and one or more odd pages of memory cells coupled to odd bit lines). In addition, for embodiments including MLCs, a row (physical page) of memory cells may store multiple pages (e.g., logical pages) of data. For example, a row of a two-layer MLC may store data of an upper page and data of a lower page, and each cell in the physical page stores one or more bits of data pointing to the upper page and one or more bits of data pointing to the lower page.

[0048] like Figure 2As shown in , a physical page of a memory cell may include one or more physical sectors 222-0, 222-1, ..., 222-S (e.g., a subset of memory cells). Each physical sector 222-0, 222-1, ..., 222-S of a cell may store data of one or more logical sectors (e.g., data words). In addition, the data of each logical sector may correspond to a portion of the data of a particular page. For example, the data of a first logical sector stored in a particular physical sector may correspond to a logical sector corresponding to the data of a first page, and the data of a second logical sector stored in a particular physical sector may correspond to the data of a second page. Each physical sector 222-0, 222-1, ..., 222-S may store system and / or user data and / or may include overhead data, such as error correction code (ECC) data and logical block address (LBA) data.

[0049] Other configurations of physical blocks 224-0, 224-1, ..., 224-B, rows 221-0, 221-1, ..., 221-R, sectors 222-0, 222-1, ..., 222-S, and pages are possible. For example, rows 221-0, 221-1, ..., 221-R of physical blocks 224-0, 224-1, ..., 224-B may each store data corresponding to a single logical sector, which may contain, for example, more or less than 512 bytes of data.

[0050] Figure 3A is a schematic diagram of a portion of an exemplary non-volatile memory array 325 according to one embodiment of the present disclosure. Figure 3A The embodiment of the present invention shows a NAND architecture non-volatile memory; however, the embodiments described herein are not limited to this example. In various embodiments, the memory array 325 may be a memory array previously combined with a memory array 325. Figure 1 and 2 The memory 110 and / or 220 described above. Figure 3A As shown in FIG. 3 , the memory array 325 includes access lines (word lines) 326-1, ..., 326-N and intersecting sense lines (bit lines) 327-1, ..., 327-M. For ease of addressing in a digital environment, the number of word lines 326-1, ..., 326-N and the number of bit lines 327-1, ..., 327-M are each a power of two (e.g., 256 word lines multiplied by 4,096 bit lines).

[0051] The memory array 325 includes NAND strings 329-1, ..., 329-M. Each NAND string 329-1, ..., 329-M includes nonvolatile memory cells 328-1, ..., 328-N, each located at the intersection of a word line 326-1, ..., 326-N and a local bit line 327-1, ..., 327-M. The nonvolatile memory cells 328-1, ..., 328-N of each NAND string 329-1, ..., 329-M are connected in series source to drain between a source select gate (SGS) 330 (e.g., a field effect transistor (FET)) and a drain select gate (SGD) 334 (e.g., a FET). The source select gate 330 is located at the intersection of the local bit line 327 - 1 and the source select line 331 , and the drain select gate 334 is located at the intersection of the local bit line 327 - 1 and the drain select line 333 .

[0052] like Figure 3A , the source of the source select gate 330 can be connected to the common source line 332. The drain of the source select gate 330 can be connected to the source of the memory cell 328-1 of the corresponding NAND string 329-1. The drain of the drain select gate 334 can be connected to the local bit line 327-1 of the corresponding NAND string 329-1 at the drain contact 335. The source of the drain select gate 334 can be connected to the drain of the last memory cell 328-N (e.g., a floating gate transistor) of the corresponding NAND string 329-1.

[0053] In various embodiments, the construction of the nonvolatile memory cells 328-1, ..., 328-N may include a source, a drain, a floating gate or a charge storage layer, and a control gate. The nonvolatile memory cells 328-1, ..., 328-N have their control gates coupled to corresponding word lines 326-1, ..., 326-N. The columns of nonvolatile memory cells 328-1, ..., 328-N constitute NAND strings 329-1, ..., 329-M, which may be coupled to given local bit lines 327-1, ..., 327-M, respectively. The rows of nonvolatile memory cells are typically coupled to given word lines 326-1, ..., 326-N.

[0054] Figure 3B FIG. 3 is a schematic diagram of a portion of an example of a NAND array 340 of four layers of memory cells according to one embodiment of the present disclosure. In various embodiments, the NAND array 340 may be a previously combined Figure 1 , 2 and memories 110, 220 and / or 325 described in 3A.

[0055] Figure 3BOne embodiment of a NAND array 340 of four-bit nonvolatile memory cells is shown, where the four bits correspond to the combination of Figure 3B Four layers 343, 344, 345 and 346 of each MLC 342 are depicted. Figure 3B The bit lines BL0 327-1 and BL1 327-2 shown in FIG. Figure 3A , 327-M. In various embodiments, bit lines BL0 327-1 and BL1 327-2 may represent even and odd bit lines corresponding to respective programming sequences.

[0056] for Figure 3B For each MLC 342 shown in FIG. 1 , the lower left numeral 343 is intended to represent the programming data of the first lower page (LP1), the upper left numeral 344 is intended to represent the programming data of the second lower page (LP2), the upper right page 345 is intended to represent the programming data of the third lower page (LP3), and the lower right page 346 is intended to represent the programming data of the upper page (UP). This description is intended to enable different program states in the MLC to be distinguished, and is not intended to be limited to a particular physical structure or sequence of floating gates in the MLC, nor to the order in which they are programmed. For example, of the four pages, the upper page may be the first page to be programmed or the last page to be programmed (e.g., depending on the preferences of the programming design and the terminology to be applied to each layer and other considerations).

[0057] Figure 3B The embodiment shows starting with a first word line (WL1) 326-1 adjacent to an SGS line 331 of a NAND array 340, and alternating between programming of a first lower page 343, a second lower page 344, and a third lower page 345 and an upper page 346 of an MLC 342 associated with even BL0 327-1 and odd BL1 327-2 between a plurality of secondary adjacent word lines (e.g., WL1 326-1, WL2 326-2, ..., WLN 326-N).

[0058] Figure 3BThe embodiment shown in may indicate that the first lower page (LP1) at 343-0 of MLC 342-0 is first programmed on even BL0 327-1, and the first lower page (LP1) at 343-1 of MLC 342-1 is programmed on odd BL1 327-2 associated with the first word line (WL1) at 326-1. The embodiment may indicate that LP1 343-2 of MLC 342-2 is next programmed on even BL0 327-1, and LP1 343-3 of MLC 342-3 is programmed on odd BL1 327-2 associated with the second WL2 at 326-2. The embodiment may indicate that LP1 343-4 of MLC 342-4 is programmed next on even BL0 327-1, and LP1 343-5 of MLC 342-5 is programmed on odd BL1 327-2 associated with the third WL3 at 326-3. In various embodiments, this programming sequence may continue until MLC 342-N-1 associated with the last WLN at 326-N and the first lower page of 342-N have been programmed.

[0059] In various embodiments, a similar sequence may then be performed to program a second lower page (LP2) at 344-0, 344-1, etc. of the MLCs 342-0, ..., 342-N associated with WLs 326-1, ..., 326-N. A sequence may then be performed to program a third lower page (LP3) at 345-0, 345-1, etc. of the MLCs 342-0, ..., 342-N associated with WLs 326-1, ..., 326-N. Programming of each layer of MLCs 342-0, ..., 342-N may then be completed with a sequence of programming upper pages (UP) at 346-0, 346-1, etc. of the MLCs 342-0, ..., 342-N associated with WLs 326-1, ..., 326-N.

[0060] In a controller of a memory device (e.g., in conjunction with Figure 1 The controller 108 of the memory device 104 shown and described) receives data from a host (e.g., in conjunction with Figure 1There may be a significant delay between the host 102 (shown and described) receiving a command to program the MLCs 342 in the NAND array 340 and the completion of programming each of the different (e.g., paired) layers in a particular MLC 342. An interruption in energy (e.g., power) may occur in the delay between programming of the lower page of one or more MLCs and programming of the upper page of one or more MLCs, such that at least some of the upper pages may not have been programmed prior to the interruption, even though some of the paired lower pages have been programmed. Therefore, the probability of accidental modification of the data value stored by the lower page is increased due to the data value not being programmed in the paired upper page relative to the paired upper page being successfully programmed. The use of tokens as described herein to indicate completion of data storage to memory is intended to reduce the probability of such accidental modification of the data value stored by the lower page.

[0061] Figure 4 A table of tokens 450 that can be used by a host and a storage device according to one embodiment of the present disclosure is shown. For each type of token, the tokens 450 in the table are listed with a name 451, a source 453, and a description 455. The source 453 is intended to indicate the source of the creation, storage, update, etc. of a particular token that can be used to monitor the completion of data storage.

[0062] In association with a first command to program at least a plurality of first pages of a corresponding number of rows of a memory cell array (e.g., to write / store data values ​​therein), an open transaction token 456 may be originated from a host (e.g., using a host (e.g., Figure 1 102 in FIG. 107 ). The closing transaction token 457 may also originate from the host (e.g., created, stored, and / or updated using the first token component 107-1). In various embodiments, the opening transaction token 456 and / or the closing transaction token 457 may be created, stored, and / or updated in the first token component 107-1 and / or the file register (e.g., Figure 1 Stored and / or updated in register 111) shown on host 102 in.

[0063] In various embodiments, the memory device (e.g., the controller 108 of the memory device 104 and / or firmware (not shown) coupled to the memory device / controller) may send an indicator to the host (e.g., as shown at 571 and in conjunction with Figure 5 Description) to indicate the completion of the first command to program at least the number of first pages of the corresponding number of rows. The indicator can be sent to the file register (e.g., Figure 1 In various embodiments, the memory device may be connected to the host computer via an interface (e.g., a register 111 shown on the host computer 102 in FIG. 1 ) of the memory device. Figure 1In various embodiments, the indicator may then be sent (e.g., by Figure 1 The indicator may enable verification of the closing transaction token 457 to indicate successful completion of the first command to program the first page.

[0064] The security token 458 may be derived from a memory device (e.g., using a memory device (such as in Figure 1 104 in FIG. 106 ). A security token 458 may be sent by a memory device (e.g., by a controller and / or firmware) to a host to indicate completion of a second command to program a plurality of second pages associated with the plurality of first pages encapsulated by an open transaction token 456 and a close transaction token 457. “Encapsulated” by an open transaction token 456 and a close transaction token 457 is intended to mean that a plurality of first pages of a corresponding plurality of MLCs directed to be programmed with the first command associated with the open transaction token have been successfully programmed, as indicated by sending an indicator to verify the corresponding close transaction token 457. The open transaction token 456 and the close transaction token 457 may each correspond to one or more first pages of a corresponding number of rows, for example, as shown in FIG. Figure 5 564-1 and CMD 2 at 564-2 are shown for commands (CMD) 1 at 564-1 and CMD 2 at 564-2 associated with the first open transaction token 556-1 and the first closed transaction token 557-1. Figure 5 The plurality of first pages (eg, Figure 5 The plurality of second pages associated with (eg, in pairs of) CMD 569-1 and 569-2 are second pages 569-5 and 569-6 associated with CMD 564-5 and CMD 564-6, respectively.

[0065] The associated security token 458 (e.g., Figure 5 The issuance of the associated security token 458 may also indicate that no intervening power outage has occurred. In various embodiments, the receipt of the security token 458 (e.g., by a power supply) may indicate that the programming of the second page of the pair (e.g., pages 569-5 and 569-6) has been successfully completed after the programming of the first page (e.g., pages 569-1 and 569-2). The issuance of the associated security token 458 may also indicate that no intervening power outage has occurred. In various embodiments, the receipt of the security token 458 (e.g., by a power supply) may indicate that the programming of the second page of the pair (e.g., pages 569-5 and 569-6) has been successfully completed after the programming of the first page (e.g., pages 569-1 and 569-2). Figure 11) on the host 102 shown in the file register 111 may cause the open transaction token 456 (eg, the first open transaction token 556-1) to be cancelled by indicating successful completion of the storage of the plurality of data values ​​by the second page (eg, pages 569-5 and 569-6).

[0066] Figure 5 An exemplary sequence 560 of using a token by a host 502 and a memory device 504 is shown according to one embodiment of the present disclosure. Figure 4 The token 450 shown and described may correspond to a Figure 5 The token shown and described (eg, the same as) is shown and described. The transaction token and indicator under the host 502 and memory device 504 header are in Figure 5 The positioning in is intended to indicate each of their sources (e.g., as shown at 453 and in conjunction with Figure 4 describe).

[0067] Figure 5 The exemplary sequence 560 shown in FIG. 5 shows the host 502 issuing CMD1 at 564-1 and CMD2 at 564-2 associated with the first open transaction token 556-1. The two commands in the subsequence of the exemplary sequence 560 each contain a data value to be programmed to a particular page 569 of the MLC array. In addition to instructions as to which row, column, page, etc. of the array to be programmed, each command may contain a plurality of data values ​​to be programmed that may correspond to a plurality of MLCs in a row of the array. Different layers (e.g., in combination) of the plurality of MLCs in the row may be programmed to a plurality of MLCs in the row. Figure 3B Each of the four layers of MLC 342 shown and described may be collectively referred to as page 569, such that Figure 3B The rows associated with WL1 326-1, WL2 326-2, ..., WLN 326-N shown in FIG. 326-1 may each have four pages 569 (e.g., LP1 343, LP2 344, LP3 345, and UP 346) for storing a plurality of data values ​​corresponding to the plurality of MLCs in the row. For clarity, Figure 5 The exemplary sequence 560 in is shown as having two pages 569 (eg, an upper page and a lower page) corresponding to two layers in the MLCs in each row; however, embodiments are not limited to two pages per row and / or two layers in each MLC.

[0068] The two commands 564-1 and 564-2 associated with the first open transaction token 556-1 may be sent consecutively (e.g., in two consecutive cycles of the host 502) to the memory device 504 to be programmed (e.g., written) to the appropriate pages 569 (e.g., as indicated by Figure 11 and 564-2). Consistent with the instructions contained in the two commands 564-1 and 564-2, upper page 1 at 569-1 (e.g., belonging to the MLC in row 1) can be programmed with data values ​​in response to CMD1, and upper page 2 at 569-2 (e.g., belonging to the MLC in row 2) can be programmed with data values ​​in response to CMD2. After completing programming of upper page 1 at 569-1 and upper page 2 at 569-2, the memory device 504 (e.g., its controller and / or firmware) can be configured to output 562 an indicator 571-1 to the host 502 that CMD1 and CMD2 are completed.

[0069] Indicator 571-1 is provided by host 502 (e.g., by Figure 1 The controller 116, the first token component 107-1, and / or the file register 111 shown in FIG. 10A receives a first closing transaction token 557-1 stored by the host (e.g., in the file register 111 or in the first token component 107-1) that corresponds to the first opening transaction token 556-1 and can verify the first closing transaction token 557-1. The verification of the first closing transaction token 557-1 can be used to indicate the completion of programming of the upper page 1 at 569-1 and the upper page 2 at 569-2 associated with CMD1 564-1 and CMD2 564-2.

[0070] The subsequence of the exemplary sequence 560 associated with the open transaction token 556 is not limited to only including two commands 564 (e.g., CMD1 564-1 and CMD2 564-2) sent consecutively from the host 502 to the memory device 504. The subsequence associated with the open transaction token 556 is also not limited to programming only one layer and / or type of page 569 of the MLC (e.g., upper page 1 at 569-1 and upper page 2 at 569-2).

[0071] For example, Figure 5 The second open transaction token 556-2 is shown to be associated with CMD3 at 564-3, CMD4 at 564-4, CMD5 at 564-5, CMD6 at 564-6, CMD7 at 564-7, and CMD8 at 564-8. Consistent with the instructions contained in these six commands 564-3, ..., 564-8, upper page 3 at 569-3 (e.g., belonging to the MLC in row 3) can be programmed with a data value in response to CMD3, and upper page 4 at 569-4 (e.g., belonging to the MLC in row 4) can be programmed with a data value in response to CMD4.

[0072] like Figure 5As shown in , a subsequence of the exemplary sequence 560 may include commands directed toward programming of different types of pages 569 associated with the same open transaction token 556. For example, not only is programming of upper pages 3 and 4 associated with open transaction token 556-2, but also associated with open transaction token 556-2 is lower page 1 at 569-5 (e.g., belonging to MLCs in row 1), which may be programmed with data values ​​in response to CMD5; lower page 2 at 569-6 (e.g., belonging to MLCs in row 2), which may be programmed with data values ​​in response to CMD6; lower page 3 at 569-7 (e.g., belonging to MLCs in row 3), which may be programmed with data values ​​in response to CMD7; and lower page 4 at 569-8 (e.g., belonging to MLCs in row 4), which may be programmed with data values ​​in response to CMD8.

[0073] After completing programming of Lower Page 1 at 569-5 and Lower Page 2 at 569-6, the memory device 504 can be configured to output 562 a first security token 558-1 to the host 502 to indicate completion of programming of the data values ​​associated with CMD5 and CMD6. Completion of programming also indicates that no interruption of power (or other event that prevents programming) has occurred between programming of Upper Page 1 at 569-1 and Upper Page 2 at 569-2 associated with CMD1 564-1 and CMD2 564-2, and Lower Page 1 at 569-5 and Lower Page 2 at 569-6, a pair associated with CMD5 564-5 and CMD6 564-6. In addition, the first security token 558-1 can also indicate that based on the programming of the lower page 1 at the pair 569-5 and the lower page 2 at 569-6 in the first and second rows has been completed, the probability of accidental modification of the upper page 1 at the pair 569-1 and the upper page 2 at 569-2 in the corresponding first and second rows is reduced (e.g., relatively safe).

[0074] Included in the subsequence associated with the second open transaction token 556-2, the exemplary sequence 560 can continue to program the lower page 3 at 569-7 (e.g., belonging to the MLC in row 3) with a data value in response to CMD7 564-7 and program the lower page 4 at 569-8 (e.g., belonging to the MLC in row 4) with a data value in response to CMD8 564-8. After completing programming of the lower page 3 at 569-7 and the lower page 4 at 569-8, the memory device 504 can be configured to output 562 an indicator 571-2 to the host 502 that CMD3, CMD4, CMD5, CMD6, CMD7, and CMD8 are completed.

[0075] The indicator 571-2 is received by the host 502 to verify the second closing transaction token 557-2 stored by the host (e.g., in the file register 111 or in the first token component 107-1) corresponding to the second opening transaction token 566-2. The verification of the second closing transaction token 557-2 can be used to indicate the completion of programming of the upper page 3 at 569-3 and the upper page 4 at 569-4 associated with CMD3 564-3 and CMD4 564-4. The verification of the second closing transaction token 557-2 can also be used to indicate the completion of programming of the lower page 1 at 569-5, the lower page 2 at 569-6, the lower page 3 at 569-7, and the lower page 4 at 569-8 associated with CMD5 564-5, CMD6 564-6, CMD7 564-7, and CMD8 564-8, respectively. Alternatively or additionally, after programming of Upper Page 4 is completed, an indicator 571 may be output 562 to the host 502 to indicate completion of programming of Upper Page 3 and Upper Page 4 corresponding to CMD3 564-3 and CMD3 564-3.

[0076] After completing programming of lower page 4 at 569-8, the memory device 504 can be configured to output 562 a second security token 558-2 to the host 502 to indicate completion of programming of the data values ​​associated with CMD7 564-7 and CMD8 564-8. Completion of programming also indicates that no interruption of power (or other event that prevents programming) has occurred between programming of upper page 3 at 569-3 and upper page 4 at 569-4 associated with CMD3 564-3 and CMD4 564-4, and lower page 3 at 569-7 and lower page 4 at 569-8, the pairs associated with CMD7 564-7 and CMD8 564-8. In addition, the second security token 558-2 may also indicate that, based on the completion of programming of the lower page 3 at the pair 569-7 and the lower page 4 at the pair 569-8 in the third and fourth rows, the probability of accidental modification of the upper page 3 at the pair 569-3 and the upper page 4 at the pair 569-4 of the corresponding third and fourth rows is reduced (e.g., relatively safe). Therefore, the memory device 504 (e.g., the controller 108) may be configured to delay the output of the security token applicable to the completion of the particular command until the plurality of additional commands are completed, so that the security token indicates the completion of the programming associated with the particular command and the additional commands.

[0077] In various embodiments, receipt of a security token 558 by the host 502 may result in cancellation of a corresponding open transaction token 556 (e.g., and a corresponding close transaction token 557) in the file register 111. For example, receipt of a first security token 558-1 may result in cancellation of a first open transaction token 556-1, and receipt of a second security token 558-2 may result in cancellation of a second open transaction token 556-2. The file register 111 may store an indicator of the logical location of the data value securely stored by the corresponding row and the upper and lower pages in response to receipt of the corresponding security token.

[0078] Thus, the memory device (e.g., as shown at 104 and in conjunction with Figure 1 110 and may be combined with the MLC array in the memory. In various embodiments, the array may be a NAND array of non-volatile MLCs arranged in rows. Figure 1 The described embodiment, shown at 220 and combined Figure 2 The described embodiment, shown at 325 and combined Figure 3A The embodiments described and / or shown at 340 and combined Figure 3B The described embodiments, as well as other possible embodiments of memory consistent with the present disclosure, are consistently formed into arrays.

[0079] The MLCs 342 in the array may each be configured to store a plurality of data values ​​corresponding to a corresponding number of lower pages and to store data values ​​corresponding to the upper pages of the first row. Figure 3BIn the first row (e.g., WL1 326-1) of the NAND array 340 of four layers (e.g., four bits) of non-volatile memory cells shown in FIG, MLC 342-0 may include LP1 343-0, LP2 344-0, LP3 345-0, and UP 346-0. Similarly, MLC 342-1 of the first row may include LP1 343-1, LP2 344-1, LP3 345-1, and UP 346-1. The first row may include any number of four-layer MLCs (e.g., 1,024, 2,048, 4,096, 8,192, or 16,384, and other possible numbers of memory cells that are not equal to a power of 2). The total number of lower page layers LP1 343-0, LP1 343-1, etc. corresponding to the number of MLCs 342 (e.g., 342-0, 342-1, etc.) in the first row 326-1 may be referred to as the first page of the first row 326-1. The total number of lower page layers LP2 344-0, LP2 344-1, etc. corresponding to the number of MLCs 342 in the first row 326-1 may be referred to as the second page of the first row 326-1. Similarly, the total number of lower page layers LP3 345-0, LP2 345-1, etc. corresponding to the number of MLCs 342 in the first row 326-1 may be referred to as the third page of the first row 326-1. The total number of upper page layers UP346-0, LP2 346-1, etc. corresponding to the number of MLCs 342 in the first row 326-1 may be referred to as the fourth page of the first row 326-1. The four pages of LP1 343 , LP2 344 , LP3 345 , and UP 346 of the MLC 342 used in each row 326 - 2 , 326 - 3 , . . . , 326 -N may be similarly formed.

[0080] Various embodiments may have less than four layers (e.g., two or three layers) in each MLC 342, or may have more than four layers (e.g., five or more layers) in each MLC 342, such that the number of pages in each row may correspond to the number of layers. In addition, the numbering of the pages may be reversed. For example, the lower page layer LP1 343-0, LP1 343-1, etc. may be referred to as the fourth page of the first row 326-1, and the upper page layer UP 346-0, LP2 346-1, etc. may be referred to as the first page of the first row 326-1. For example, for a two-layer MLC, the lower page layer may be referred to as the first page, and the upper page layer may be referred to as the second page, or vice versa.

[0081] A controller (eg, as shown at 108 and in conjunction with Figure 1 Description) can be coupled to the MLC array. In various embodiments, the controller can be configured to respond to a request to be received by the previous page (e.g., shown in 569-1 and in conjunction with Figure 5The first command (eg, shown at 564-1 and in conjunction with the first command of the plurality of data values ​​stored in the description on page 1) Figure 5 The first command may be received with a first open transaction token (e.g., as shown at 456 and 556-1, respectively, and in conjunction with Figure 4 and Figure 5 Description) is associated.

[0082] The controller may be further configured to respond to a second command (eg, as shown at 564-5 and in conjunction with the Figure 5 The reception of CMD5 described above guides the programming of a specific lower page (eg, the second page of a two-layer MLC or the fourth page of a four-layer MLC) among the multiple lower pages. Figure 5 In the example shown in , the specific next page in the next page can be the next page 1 shown at 569-5. The controller can be further configured to guide the first security token (e.g., as shown at 458 and 558-1 respectively and in combination Figure 4 and Figure 5 Description) to indicate completion of programming of a particular lower page among the plurality of lower pages in the first row.

[0083] The first security token may cause cancellation of the first open transaction token and may indicate that programming of a specific lower page in the lower pages in the first row has been completed. For example, in response to receiving the security token by the host 502, the completion of programming of the specific lower page in the lower pages in the first row is confirmed, and the first open transaction token is cancelled. The first security token may further indicate that programming of the upper page in the first row was completed before programming of the specific lower page in the lower pages was completed. The first security token may further indicate that the probability of accidental modification of the data value programmed in the upper page is reduced due to the completion of programming of the data value in the specific lower page in the lower pages in the first row. The reduced probability may be relative to the probability of accidental modification of the data value in the case where the specific lower page in the lower pages remains unprogrammed. In response to the specific lower page in the lower pages not remaining unprogrammed, for example, by an interruption of energy (e.g., electricity) supplied to the memory device containing the array after programming of the upper page, the first security token may be output to indicate that the interruption of energy has not occurred before programming of the specific lower page in the lower pages is completed.

[0084] In various embodiments, the first command (eg, shown at 564-1 and in conjunction with Figure 5The CMD1 described above may be followed by a third command (e.g., CMD2 shown at 564-2) to direct programming of an upper page in the second row (e.g., upper page 2 shown at 569-1). Both the first command and the third command may be associated with a second open transaction token (e.g., which may be the same as the first open transaction token shown at 556-1). The controller of the memory device may be further configured to output an indicator (e.g., as shown at 571-1) in response to completion of programming of the upper page in the first row and the upper page in the second row (e.g., upper pages 569-1 and 569-2).

[0085] The third command (e.g., CMD2 shown at 564-2) may be followed by a fourth command (e.g., CMD6 shown at 564-6) to direct programming of a specific lower page among the plurality of lower pages in the second row (e.g., lower page 2 shown at 569-6). The controller may be further configured to direct output of the first security token (e.g., shown at 558-1) to indicate completion of programming of a specific lower page among the plurality of lower pages in the first row (e.g., lower page 569-5) and programming of a specific lower page among the plurality of lower pages in the second row (e.g., lower page 569-6). Receipt of the first security token 558-1 may result in cancellation of the second open transaction token (e.g., the first open transaction token shown at 556-1). The first security token 558-1 can also indicate that programming of particular lower pages (e.g., lower pages 569-5 and 569-6) in the first and second rows has been completed and that the probability of accidental modification of data values ​​programmed in upper pages (e.g., upper pages 569-1 and 569-2) in the first and second rows has been reduced.

[0086] A computing system (eg, as shown at 100 and in conjunction with Figure 1 1) may include a host (e.g., as shown at 102) configured to generate a command for storing a data value. The computing system 100 may further include a memory device (e.g., as shown at 104) coupled to the host 102. The memory device 104 may include an array of MLCs (e.g., as shown at 110, 220, 325, and 340). Each MLC may be configured to store a data value corresponding to a first page in a particular row (e.g., upper page 1 at 569-1) and store a data value corresponding to a second page in a particular row (e.g., lower page 1 at 569-5). The total number of MLCs in the first row may correspond to a respective number of data values ​​to be stored by each of the first page and the second page.

[0087] A controller (e.g., as shown at 108) can be coupled to the array. The controller can be configured to direct programming of a first page in a first row (e.g., upper page 1 at 569-1) in response to receiving a first command (e.g., CMD1 at 564-1) from a host containing a plurality of data values ​​to be stored by the first page. The first command can be associated with a first open transaction token (e.g., shown at 556-1). The open transaction token can originate from the host in association with a command to program at least a plurality of first pages of a corresponding number of rows of the array. For example, Figure 5 The first open transaction token 556-1 shown in FIG. 5 is associated with CMD1 564-1 and CMD2 564-2 for programming of upper page 1 569-1 in row 1 and upper page 2 569-1 in row 2, respectively. Figure 5 The second open transaction token 556-2 shown in FIG. 5 is associated with CMD3 564-3 and CMD4 564-4 for programming of upper page 1 569-3 in row 3 and upper page 4 569-4 in row 4, respectively. In addition, the second open transaction token 556-2 may be associated with CMD5 569-5 for programming of lower page 1 569-5 in row 1, CMD6 569-6 for programming of lower page 2 569-6 in row 2, CMD7 569-7 for programming of lower page 3 569-7 in row 3, and CMD8 569-8 for programming of lower page 4 569-8 in row 4.

[0088] The controller may be further configured to direct programming of a second page in the first row (e.g., next page 1 at 569-5) in response to receiving a second command (e.g., CMD5 at 564-5) from the host containing a plurality of data values ​​to be stored by the second page. The controller may be further configured to direct sending a first security token (e.g., shown at 558-1) to the host to indicate completion of programming of the second page in the first row. The first security token may be sent to the host (e.g., by the controller) to indicate completion of a second command (e.g., CMD5 at 564-5 and CMD6 at 564-6) to program a plurality of second pages (e.g., 569-5 and 569-6) associated with the plurality of first pages (e.g., pages 569-1 and 569-2) encapsulated by a first open transaction token (e.g., shown at 556-1) and a first close transaction token (e.g., shown at 557-1).

[0089] The first security token can be associated with (e.g., include) an indicator of the logical location of each data value stored by the first page and the second page in the array. The security token sent to the host can indicate that programming of the second page in the first row is complete. The security token sent to the host can also cause the cancellation of the first open transaction token.

[0090] Indicators (e.g., as shown at 571-1 and / or 571-2) may be sent (or directed to be sent) by the controller to the host to indicate completion of a first command to program at least the plurality of first pages of a corresponding number of rows. For example, indicator 571-1 may indicate completion of CMD1 564-1 and CMD2 564-2 associated with the first open transaction token 556-1 to program upper page 1 569-1 and upper page 2 569-2, respectively. In various embodiments, indicator 571-2 may indicate completion of CMD3 564-3 and CMD4 564-4 associated with the second open transaction token 556-2 to program upper page 3 569-3 and upper page 4 569-4, respectively. Alternatively, indicator 571-2 may indicate completion of CMD 3-8 to program upper pages 3 and 4 in addition to lower pages 1-4 associated with the second open transaction token 556-2. The indicator 571-1 may verify a first closed transaction token 557-1 corresponding to the first open transaction token 556-1, and the indicator 571-2 may verify a second closed transaction token 557-2 stored by the host corresponding to the second open transaction token 556-2.

[0091] As described herein, a security token (e.g., a first security token shown at 558-1) can indicate that a probability of accidental modification of a data value programmed in a first page (e.g., page 569-1) is reduced due to an interruption in energy (e.g., power) supplied to a memory device relative to a second page (e.g., paired page 569-5) remaining unprogrammed. For example, receiving a security token by a host can indicate that a probability of accidental modification of a data value programmed in the first page is reduced due to completing programming of the data value in the second page in the first row relative to the second page remaining unprogrammed.

[0092] The first command (e.g., CMD1 at 564-1 for programming upper page 1 in row 1) may be followed by a third command (e.g., CMD2 at 564-2 for programming upper page 2 in row 2) to direct programming of the first page in the second row. The first and third commands may be associated with a second open transaction token (e.g., the first open transaction token shown at 556-1). The third command may be followed by a fourth command (e.g., CMD6 at 564-6) to direct programming of the second page in the second row (e.g., lower page 2 at 569-6). The controller may be further configured to send a first security token 558-1 of CMD1 564-1 and CMD2 564-2 to the host to indicate completion of programming of the second page in the first row and programming of the second page in the second row (e.g., lower pages 569-5 and 569-6).

[0093] In response to receiving the first security token 558-1 by the host, the second open transaction token may be cancelled (e.g., as shown at 556-1). In response to receiving the first security token 558-1, the file register of the host (e.g., shown at 111) may be directed (e.g., by the controller 118) to store an indicator of the logical location of the data values ​​stored by the first page and the second page in each of the respective first and second rows. The storage of the indicator of the logical location of each data value in the first page by the file register may indicate that the probability of accidental modification of the data value in the first page is reduced due to the interruption of the energy supplied to the memory device.

[0094] Receipt of the security token may indicate to the host that the data value has been stored by the non-volatile MLC corresponding to the first page and the second page, and that the stored data value is protected from accidental modification due to the interruption of energy supplied to the memory device. Conversely, the absence of (e.g., not receiving) the security token may indicate to the host that at least the second page of the MLC has not yet stored the data value. Thus, the host may be configured to determine that no additional commands for storing the data value will be sent to the memory device. The host may further be configured to delay sending the command for storing the data value to the memory device until energy supplied to the memory device is restored (e.g., by the host 102 being configured to monitor characteristics of the energy source 101, as described elsewhere herein).

[0095] Figure 6 680 is a flowchart of an exemplary method 680 for using a token to indicate completion of data storage to a memory according to multiple embodiments of the present disclosure. The method 680 can be performed by a processing logic that can include hardware and / or firmware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. Unless explicitly stated, the elements of the methods described herein are not limited to a specific order or sequence. In addition, multiple method embodiments or elements thereof described herein can be performed at the same or substantially the same time point.

[0096] In various embodiments, method 680 may be performed using controller 108 of memory device 104 and / or controller 116 of host 102 (e.g., in combination with memory 110 and / or processor 114), as shown and in conjunction with Figure 1Description. The operations described herein (e.g., storing, sending, canceling, recording, canceling, detecting, etc.) performed by the memory device 104 and / or the host 102 using circuit systems, memories, controllers, and / or processors associated therewith are implemented by executing instructions stored on a computer-readable medium (CRM). In various embodiments, the CRM may be stored on tangible hardware, firmware, and / or software, which may be part of, directly coupled to, and / or indirectly coupled to (e.g., operably coupled to) the controllers, memories, and / or processors of the memory device 104 and the host 102. For example, the controller 108 and / or memory 110 of the memory device 104 may include a CRM (which includes instructions executable to direct the generation and / or output of the token 107-2 (e.g., via the interface 106)), or be operably coupled to it. The controller 116 and / or processor 114 of the host 102 may include, or be operably coupled to, a CRM including instructions executable to direct receipt of the token 107-2 (e.g., via the interface 118). In various embodiments, the CRM may further include instructions executable by the controller 116 to direct the token 107-2 (e.g., as shown at 458 and in conjunction with Figure 4 Instructions for use of a security token).

[0097] At block 681, method 680 may include storing a plurality of data values ​​(eg, as shown and in conjunction with FIG. 1 ) by a first page in a first row of a memory cell array in response to receiving a first command from a host. Figure 3B and 5 and described elsewhere herein). The first command may be associated with an open transaction token (e.g., as shown and in conjunction with Figure 4 and 5 and described elsewhere herein). At block 683, method 680 may include: receiving a second command from the host to store a plurality of data values ​​from a second page in the first row (eg, as shown and in conjunction with Figure 3B and 5 At block 685, method 680 may include sending a security token to the host to indicate completion of storage of the plurality of data values ​​by the second page in the first row (eg, as shown and in conjunction with Figure 4 and 5 and described elsewhere in this article).

[0098] In various embodiments, method 680 may further include: canceling (e.g., by the host) the open transaction token in response to receiving the security token to indicate completion of the storage of the plurality of data values ​​by the second page (e.g., as shown and in conjunction with Figure 4 and 5and described elsewhere herein). The method 680 may further include conditionally recording (e.g., by the host) completion of storage of the plurality of data values ​​by the first and second pages in the first row in response to matching the open transaction token with the received security token. For example, a particular open transaction token (e.g., Figure 5 The method 680 may further include: detecting, based on a mismatch between the open transaction token and the received security token, an interruption in energy (e.g., power) supplied to the array (e.g., by the host). The method 680 may further include: the security token indicating that a probability of accidental modification of a data value stored by the first page relative to the data value not being stored by the second page is reduced due to the interruption in energy supplied to the array.

[0099] The method 680 may further include: based on the determination that the open transaction token does not match the received security token, delaying (e.g., by the host) sending a command to store a data value to a memory device including a memory cell array (e.g., as shown and in conjunction with Figure 5 and described elsewhere herein). The method 680 may further include: the memory device does not include a backup data storage component because the sending of the command to store the data value is delayed. For example, in various embodiments, the system 100 and / or the memory device 104 may not include a backup data storage component because the system (e.g., the host 102) may be configured to delay sending a command to store the data value to the memory device in response to not receiving a security token as described herein (e.g., until energy supplied to the memory device is restored). Therefore, since the command to store the data value is not received by the memory device when, for example, power supply from the energy source is interrupted, potential use of the data value stored by the backup data storage component may be reduced (e.g., eliminated).

[0100] In the above detailed description of the present disclosure, reference is made to the accompanying drawings that form a part of the present disclosure, and in which one or more embodiments of the present disclosure are shown by way of illustration how they may be practiced. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the embodiments of the present disclosure, and it is understood that other embodiments may be utilized and process, electrical and / or structural changes may be made without departing from the scope of the present disclosure. In addition, the structural features shown in the accompanying drawings are intended to indicate the relative positioning of the structural features in one or more embodiments, and are not necessarily drawn to scale relative to other structural features in the accompanying drawings or otherwise.

[0101] It should be understood that the terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting. Unless the context clearly dictates otherwise, as used herein, the singular forms "a / an" and "the" include singular and plural referents, as do "plurality," "at least one," and "one or more" (e.g., a plurality of memory arrays may refer to one or more memory arrays), while "plurality" is intended to refer to more than one such thing. In addition, throughout this application, the words "can / may" are used in a permissive sense (i.e., it is possible, able to) rather than a mandatory sense (i.e., must). The term "includes" and its derivatives mean "including but not limited to." The term "coupled / coupling" refers to physically connecting directly or indirectly to access and / or move (transmit) instructions (e.g., control signals, address signals, etc.) and data (depending on the context).

[0102] Although exemplary embodiments including various combinations and configurations of energy sources, hosts, memory devices, controllers, memory arrays, MLCs, tokens, token components, indicators, file registers, and other materials and / or components associated with tokens indicating completion of data storage to memory have been shown and described herein, embodiments of the present disclosure are not limited to those combinations explicitly recited herein. Other combinations and configurations of energy sources, hosts, memory devices, controllers, memory arrays, MLCs, tokens, token components, indicators, and / or file registers associated with tokens indicating completion of data storage to memory other than those disclosed herein are explicitly included within the scope of the present disclosure.

[0103] Although specific embodiments have been shown and described herein, it will be understood by those of ordinary skill in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover adaptations or modifications of one or more embodiments of the present disclosure. It should be understood that the above description is provided in an illustrative manner and is not restrictive. By reading the above description, the combination of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art. The scope of one or more embodiments of the present disclosure includes other applications using the above structures and processes. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the attached claims and the equivalence of the full scope enjoyed by these claims.

[0104] In the foregoing detailed description, some features are grouped together in a single embodiment for the purpose of simplifying the disclosure. This method of disclosure should not be interpreted as reflecting the following intention: the disclosed embodiments of the present disclosure must use more features than the features explicitly recited in each claim. On the contrary, as reflected in the following claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the following claims are hereby incorporated into the detailed description, with each claim independently serving as a separate embodiment.

Claims

1. An apparatus for indicating completion of data storage, comprising: a memory cell array; a controller coupled to the array, wherein the controller is configured to: In response to storing a second number of data values ​​to populate each page of a first row of the array, a security token associated with a first number of data values ​​stored by a first page of the first row of the array is output.

2. The apparatus of claim 1, wherein the controller is configured to: The first number of data values ​​is stored by the first page in the first row of the memory cell array in response to receiving a first command from a host, wherein the first command is associated with a first open transaction token.

3. The apparatus of claim 2, wherein the controller is configured to: In response to receiving a second command from the host, a third number of data values ​​is stored by a second page in the first row of the memory cell array, wherein the second command is associated with a second open transaction token.

4. The apparatus of claim 2, wherein the controller is configured to: An indicator of completion of programming of the first page in the first row of the array is output to verify a first closing transaction token corresponding to the first opening transaction token.

5. The apparatus of claim 3, wherein the controller is configured to: An indicator of completion of programming of the second page in the first row is output to verify a second closing transaction token corresponding to the second opening transaction token.

6. The apparatus of claim 3, wherein the controller is configured to: Resuming in response to receiving a third command from the host, storing the second number of data values ​​to populate each page of the first row of the array.

7. An apparatus for indicating completion of data storage, comprising: a memory cell array; a controller coupled to the array, wherein the controller is configured to: A security token associated with a first number of data values ​​stored by a first page of a first row of the array is output to indicate that a power interruption has not occurred prior to the completion of programming data values ​​to each page of the first row of the array.

8. The apparatus of claim 7, wherein the memory cell array is a non-volatile multi-level memory cell (NAND) array, and wherein each cell is configured to store a plurality of data values ​​corresponding to a respective plurality of lower pages, and to store data values ​​corresponding to an upper page in the first row.

9. The apparatus of claim 8 , wherein the security token further indicates that a probability of accidental modification of a programmed data value in the first page in the first row is reduced due to completion of the programming of the particular one of the plurality of lower pages in the first row relative to the particular one of the plurality of lower pages remaining unprogrammed.

10. The apparatus of claim 9, wherein the security token further indicates that the programming of the upper page in the first row is completed prior to the completion of the programming of the particular one of the lower pages.

11. An apparatus according to any one of claims 7-10, wherein the controller is further configured to delay output of the security token applicable to completion of a particular command until a plurality of additional commands are completed so that the security token indicates completion of programming associated with the particular command and the additional commands.

12. A system for indicating completion of data storage, comprising: a host configured to generate a command for storing a data value; and a memory device coupled to the host, wherein the memory device comprises: a memory cell array; and a controller coupled to the array, wherein the controller is configured to: A security token is sent to the host to indicate completion of programming of a second page in a first row of the array, wherein the security token sent to the host cancels a first open transaction token associated with a first command to program a plurality of data values ​​stored by a first page in the first row of the array.

13. The system of claim 12, wherein the host is configured to monitor stability of the plurality of data values ​​stored in the first page in the first row of the memory array using the security token.

14. The system of claim 12, wherein the host is configured to determine whether an intervening power outage occurred between programming the plurality of data values ​​to the first page of the array and programming the second page in a first row of the array.

15. The system of claim 12, wherein the host is configured to determine, based on receiving the security token, whether an interruption of power to the memory device occurred between programming the plurality of data values ​​to the first page of the array and programming the second page in the first row of the array.

16. The system of any of claims 12-15, wherein the host is configured to delay sending further commands until the security token is received by the host.

17. A system according to any one of claims 12-15, wherein the host is configured to resend previously sent data after power to the memory device is restored in response to an interruption of the power occurring before a security token is received by the host, the security token canceling an open transaction token associated with a previous transmission of the previously sent data.

18. The system of any one of claims 12-15, wherein the host is configured to direct the memory device to recover previously sent data from a backup page of the memory array in response to an interruption of the power occurring before a security token is received by the host, the security token canceling an open transaction token associated with a previous transmission of the previously sent data.

19. The system of any one of claims 12-15, wherein the host is configured to: The completion of the programming of the plurality of data values ​​by the first page and the second page in the first row is recorded conditionally in response to matching the first open transaction token with a received security token.

20. The system of any of claims 12-15, wherein a file register of the host stores an indicator of a logical location of the data values ​​stored by the first page and the second page in response to receiving the security token.

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