A processing method for accelerating simulation verification

Abstract

The present application relates to the field of simulation verification technology, and in particular to a method for accelerating simulation verification. The method comprises: obtaining a phase list phase corresponding to the task phase when performing simulation verification on the design to be tested; initializing k to 1; performing phase verification on the design to be tested k During the corresponding simulation verification process, the sequencer can send a new request to the design under test before the uvc receives the historical response returned by the design under test; if the uvc does not receive the phase returned by the design under test k The corresponding last request response, then wait until uvc receives the phase returned by the design under test k The response to the last request; if uvc receives the phase returned by the design under test k The response to the last request, and k

Description

Technical Field

[0001] The present invention relates to the technical field of simulation verification, and in particular to a processing method for accelerating simulation verification. Background Art

[0002] UVM is the abbreviation of Universal Verification Methodology, which refers to the universal verification methodology. Phase mechanism is the core concept of UVM, which is used to organize and control the execution order of each component in the verification environment. The Phase mechanism divides Phase into two categories, one is function phase, i.e., function phase; the other is task phase, i.e., task phase. In the prior art, when using UVM to simulate and verify the design under test, it is often necessary to wait for the response of a request to be returned before issuing the next request, resulting in a long time spent on the simulation and verification of the design under test. How to reduce the time for simulation and verification of the design under test, and thus improve the efficiency of simulation and verification of the design under test, is a problem that needs to be solved urgently. Summary of the invention

[0003] The present invention aims to provide a processing method for accelerating simulation verification, so as to reduce the time of simulation verification for the design to be tested, thereby improving the efficiency of simulation verification for the design to be tested.

[0004] According to the present invention, a processing method for accelerating simulation verification is provided, the method comprising the following steps:

[0005] S100, obtain the phase list phase corresponding to the task phase when simulating and verifying the design to be tested, phase = (phase1, phase2, ..., phase i ,…,phase n ), phase i is the i-th stage corresponding to the task stage when the design under test is simulated and verified, the value range of i is 1 to n, and n is the number of stages corresponding to the task stage when the design under test is simulated and verified.

[0006] S200: Initialize a first variable k to 1.

[0007] S300, phase the design under test k The corresponding simulation verification is carried out in the phase of the design under test. kDuring the corresponding simulation verification process, the sequencer can send a new request to the design under test before the uvc receives the historical response returned by the design under test; the historical response is the response to the request previously sent by the sequencer to the design under test; the sequencer is used to control whether each request generated by the sequence for generating requests is sent to the design under test.

[0008] S400, if the uvc does not receive the phase k corresponding to the response of the last request, then wait until the uvc receives the phase k corresponding to the response of the last request; if the uvc receives the phase k corresponding to the response of the last request, and k < n, then update k to k + 1, repeat S300 until k = n; the uvc is a verification component for simulating and verifying the design under test.

[0009] The present invention has at least the following beneficial effects compared with the prior art:

[0010] In the task stage of simulating and verifying the design under test, the present invention performs the corresponding stage simulation verification on the design under test in the order of the stages in the stage list. When the simulation verification of a stage is completed, it is judged whether the uvc receives the response of the last request of this stage returned by the design under test. If received, the simulation verification of the next stage is entered; moreover, during the simulation verification process of each stage, the sequencer can send a new request to the design under test before the uvc receives the historical response returned by the design under test, rather than waiting until the uvc receives the historical response returned by the design under test and then sending a new request to the design under test. Thus, the time for waiting for the historical response corresponding to the historical request to return can be saved, the simulation verification duration of each stage can be saved, and further the total duration of the task stage when simulating and verifying the design under test can be reduced, the time for simulating and verifying the design under test can be reduced, and further the efficiency of simulating and verifying the design under test can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0012] Figure 1 It is a flowchart of the processing method for accelerating simulation verification provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0014] According to this embodiment, Figure 1 As shown, a processing method for accelerating simulation verification is provided, and the method comprises the following steps:

[0015] S100, obtain the phase list phase corresponding to the task phase when simulating and verifying the design to be tested, phase = (phase1, phase2, ..., phase i ,…,phase n ), phase i is the i-th stage corresponding to the task stage when the design under test is simulated and verified, the value range of i is 1 to n, and n is the number of stages corresponding to the task stage when the design under test is simulated and verified.

[0016] As a specific implementation method, n=7, phase=(phase1, phase2, phase3, phase4, phase5, phase6, phase7), phase1, phase2, phase3, phase4, phase5, phase6 and phase7 are respectively: pre reset phase, reset phase, post reset phase, preconfigure phase, configure phase, post configure phase and pre main phase.

[0017] S200: Initialize a first variable k to 1.

[0018] S300, phase the design under test k The corresponding simulation verification is carried out in the phase of the design under test. k During the corresponding simulation verification process, the sequencer can issue a new request to the design under test before the uvc receives the historical response returned by the design under test; the historical response is the response to the request previously issued by the sequencer to the design under test; the sequencer is used to control whether each request generated by the sequence used to generate the request is issued to the design under test.

[0019] In this embodiment, the new request is a request that has not yet been issued to the design under test.

[0020] As a preferred specific implementation, S300 includes:

[0021] S310, obtain the request list req to be processed by the sequencer, req=(req1, req2,…, req a ,…,req A ), req a is the ath request to be processed by the sequencer. The value of a ranges from 1 to A, and A is the number of requests to be processed by the sequencer. a Corresponds to an order-preserving tag.

[0022] In this embodiment, the sequencer is used to control whether each request generated by the sequence for generating requests is issued to the design to be tested. Each request generated by the sequence for generating requests is first sent to the sequencer, and the sequencer determines the order in which each request is issued to the design to be tested. The requests included in req are generated by different sequences.

[0023] In this embodiment, req a The corresponding sequence preservation tag value is the first preset value or the second preset value. a When the value of the corresponding sequence-preserving tag is the preset first value, req a Need to preserve order; when req a When the value of the corresponding sequence preservation tag is the preset second value, req a As a specific implementation, the first preset value is 1, and the second preset value is 0.

[0024] S320, obtain the priority list prio of the requests to be processed by the sequencer, prio=(prio1,prio2,…,prio a ,…,prio A ), prio a For req a priority.

[0025] In this embodiment, each req a Corresponding to a priority prio a The larger the priority value, the higher the corresponding request a The higher the priority.

[0026] In this embodiment, each req a Corresponding prio ais a known value.

[0027] S330, get the highest priority prio among the prios a .

[0028] S340: If the order preservation tag of req' indicates that order preservation is required, then proceed to S350; req' is the prio with the highest priority among the prios. a Corresponding req a .

[0029] As a specific implementation, when req a When the value of the corresponding sequence-preserving tag is the preset first value, req a Need to preserve order; when req a When the value of the corresponding sequence preservation tag is the preset second value, req a No order preservation is required.

[0030] S350, obtain sequence', where sequence' is the sequence that generates req' in the sequence list sequence, sequence=(sequence1, sequence2, ..., sequence j ,…,sequence m ), sequence j is the j-th sequence used to generate requests when simulating and verifying the design under test, where j ranges from 1 to m, and m is the number of sequences used to generate requests when simulating and verifying the design under test.

[0031] In this embodiment, when the number of sequences used to generate requests during simulation verification of the design under test is m, the sequencer is used to control whether the requests generated by the m sequences are issued to the design under test.

[0032] S360: If the number of requests generated by sequence' in req is greater than or equal to ε, obtain the first request list freq, where freq=(req',freq2,…,freq b ,…,freq ε ),freq b is the request with the bth highest priority generated by sequence' in req, where b ranges from 2 to ε; ε is the preset number of requests.

[0033] In this embodiment, ε is an empirical value, corresponding to the number of requests that the sequencer usually sends to the design under test within a preset sequence preservation time period; optionally, ε is 3 or 4 or 5.

[0034] In this embodiment, the first highest priority is the highest priority, the second highest priority is the second highest priority, and so on.

[0035] S370, if any of freq b If the order preservation tags all indicate that order preservation is not required, the requests in freq are sorted from req' to freq ε The order is sent to the design under test in sequence, and each freq b There is no need to wait for the response of the previously issued request. ε Requests for generating other sequences in sequence except sequence' are sent to the design under test only after the request is sent to the design under test.

[0036] In this embodiment, when freq ε After sending it to the design under test, update the sequencer's list of requests to be processed, and then refer to S341-S347 for similar processing.

[0037] Based on S350-S370, the order preservation tag in req' can indicate that order preservation is required and any freq in freq new,b The order preservation labels all indicate that requests can be issued quickly when order preservation is not required, which improves the efficiency of simulation verification. The registers corresponding to the requests that need order preservation will not be affected by other sequences. While improving the efficiency of simulation verification, the accuracy of simulation verification results is also guaranteed.

[0038] In this embodiment, S370 further includes: if there is an order preservation tag in the freq indicating that the freq needs to be order preserved b , then enter S380.

[0039] S380: The last order preservation tag in freq indicates the freq that needs to be preserved. b The corresponding value of b is determined as the target request number num.

[0040] In this embodiment, if the last order preservation tag in freq indicates the freq that needs to be preserved b If it is freq2, then num=2; if the last order-preserving label in freq indicates the freq that needs to be ordered b If it is freq3, then num=3; if the last order-preserving label in freq indicates the freq that needs to be ordered b for freq ε , then num=ε.

[0041] S381, if the number qua of requests generated by sequence’ in the second list is greater than or equal to num-1, then append the first num-1 requests with the highest priority generated by sequence’ from the second list to freq, and the appended freq is freq’, freq’=(req’, freq2, …, freq b , …, freq ε , greq1, greq2, …, greq e , …, greq num-1 ); greq e is the request with the e-th highest priority appended to freq in the second list, and the value range of e is from 1 to num-1. The second list is the list composed of requests in req except those in freq.

[0042] S382, if the order-preserving tags of any greq e in freq’ all indicate that order preservation is not required, then send the requests in freq’ to the design under test in the order from req’ to greq num-1 , and do not wait for the response of the previously sent request when sending each request in freq’. After sending greq num-1 to the design under test, send the requests generated by other sequences in sequence except sequence’ to the design under test.

[0043] In this embodiment, after sending greq num-1 to the design under test, update the request list to be processed by the sequencer, and then perform similar processing with reference to S341-S347.

[0044] Based on S380-S382, it is possible to quickly send requests when the order-preserving tag of req’ indicates that order preservation is required, there is an order-preserving tag in freq indicating that order preservation is required, qua≥num-1, and the order-preserving tags of any greq new,b in freq’ all indicate that order preservation is not required, improving the efficiency of simulation verification. Moreover, the registers corresponding to the requests that require order preservation will not be affected by other sequences, ensuring the accuracy of the simulation verification results while improving the efficiency of simulation verification. e In this embodiment, S381 further includes: if qua < num-1, then go to S383.

[0045] In this embodiment, S381 further includes: if qua < num-1, then go to S383.

[0046] S383. Append the top qua requests generated by sequence’ with the highest priority from the second list to freq. The appended freq is nreq, and nreq = (req’, freq2, …, freq b , …, freq ε , greq1, greq2, …, greq c , …, greq qua ); greq c is the request appended to freq with the c-th highest priority, and the value range of c is from 1 to qua.

[0047] S384. If the ordering tags of any greq in nreq c indicate that ordering is not required, then send the requests in nreq to the design under test in the order from req’ to greq qua without waiting for the response of the previously sent requests. After a specified time, send the requests generated by other sequences in sequence except sequence’ to the design under test. The specified time is the time that is a preset ordering period away from the target time and after the target time. The target time is the time when the last freq in freq whose ordering tag indicates that ordering is required is sent to the design under test. b

[0048] In this embodiment, the preset ordering period is an empirical value.

[0049] In this embodiment, after the specified time, update the request list to be processed by the sequencer, and then perform similar processing with reference to S341 - S347.

[0050] Based on S383 - S384, it is possible to quickly send requests when the ordering tag of req’ indicates that ordering is required, there is a freq in freq new,b whose ordering tag indicates that ordering is required, and qua < num - 1, improving the efficiency of simulation verification. Moreover, the registers corresponding to the requests that require ordering will not be affected by other sequences, ensuring the accuracy of the simulation verification results while improving the efficiency of simulation verification.

[0051] In this embodiment, if there is a greq in nreq c whose ordering tag indicates that ordering is required, then send the requests in nreq to the design under test in the order from req’ to greq qua ​The order of nreq is issued to the design under test, and each request in nreq is issued without waiting for the response of the previously issued request. The requests generated by other sequences in sequence except sequence' are issued to the design under test after the first time. The first time is the time that is separated from the second time by a preset sequence preservation time period and is after the second time. The second time is the time that the last sequence preservation tag in nreq indicates that the greq that needs to be preserved is c The time at which the design under test is issued.

[0052] S382 also includes: if there is an order preservation tag in freq' indicating that the order preservation is required e , then enter S385.

[0053] S385, the last order-preserving label in freq' indicates the greq that needs to be preserved in order e The corresponding value of e is determined to be the specified request quantity β.

[0054] S386: If the number of requests generated by sequence' in the third list is greater than or equal to β, then the first β requests generated by sequence' and having the highest priority are added to freq' from the third list, and the added freq' is freq + ,freq + =(req',freq2,…,freq b ,…,freq ε ,greq1,greq2,…,greq e ,…,greq num-1 ,hreq1,hreq2,…,hreq t ,…,hreq β ); hreq t The third list is appended to freq + And the request with the tth highest priority, the value range of t is 1 to β, and the third list is a list composed of the requests in req except the requests in freq'.

[0055] S387, if freq + Any hreq t If the order preservation tags of freq + The request follows the sequence from req' to hreq β The order of hreq is issued to the design under test, and each request in freq' is issued without waiting for the response of the previously issued request. β Requests for generating other sequences in sequence except sequence' are sent to the design under test only after the request is sent to the design under test.

[0056] In this embodiment, when hreq β After sending it to the design under test, update the sequencer's list of requests to be processed, and then refer to S341-S347 for similar processing.

[0057] Based on S385-S387, the order preservation tag in req' can indicate that order preservation is required and freq exists in freq new,b The order-preserving tag indicates that the order needs to be preserved, qua ≥ num-1, and greq exists in freq' e The order preservation label indicates that the request can be issued quickly when the order preservation is required, which improves the efficiency of simulation verification. The registers corresponding to the requests that need to be ordered will not be affected by other sequences. The accuracy of the simulation verification results is guaranteed while improving the efficiency of simulation verification.

[0058] In this embodiment, if freq + hreq exists in t If the sequence preservation tags all indicate that sequence preservation is required, similar processing is performed with reference to S385-S387, which will not be repeated here.

[0059] In this embodiment, S340 further includes: if the sequence preservation tag of req' indicates that sequence preservation is not required, then sending req' to the design under test and entering S341.

[0060] S341, obtain the updated sequencer request list req to be processed new ,req new =(req new,1 ,req new,2 ,…,req new,r ,…,req new,R ), req new,r is the rth request to be processed by the updated sequencer, where r ranges from 1 to R, and R is the number of requests to be processed by the updated sequencer; each req new,r Corresponds to an order-preserving tag.

[0061] In this embodiment, if no new request is generated in each sequence during the process of sending req' to the design under test, then the updated sequencer request list to be processed req new Delete the list after req' in req; if a new request is generated by the sequence during the process of sending req' to the design under test, then the updated sequencer's list of pending requests req new Delete the list after req' in req and append the list after the new request.

[0062] S342, obtaining the updated priority list prio of the sequencer's pending requests new , prio new =(prio new,1 ,prio new,2 ,…,prio new,r ,…,prio new,R ), prio new,r For req new,r priority.

[0063] S343, get prio new The highest priority prio new,r .

[0064] S344, if req' new If the sequence preservation tag indicates that sequence preservation is required, then enter S345; req' new For prio new The highest priority prio new,r Corresponding req new,r .

[0065] S345, get sequence' new , sequence' new Generate req' for the sequence list sequence new sequence.

[0066] S346, if req new In sequence' new If the number of generated requests is greater than or equal to ε, then get the updated first request list freq new ,freq new =(req' new ,freq new,2 ,…,freq new,b ,…,freq new,ε ),freq new,b For req new In sequence' new The request generated with the bth highest priority.

[0067] S347, if freq new Any freq new,b If the order preservation tags of freq new Request in accordance with req' new to freq new,ε The order is sent to the design under test, and when the freqnew For each request, there is no need to wait for the response of the previously issued request. After freq is sent to the design under test, requests generated by sequences other than sequence’ in the sequence are sent to the design under test. new,ε new

[0068] Based on S341 - S347, when the in - order tag of req’ indicates that in - order is not required and the in - order tags of any freq in freq new new,b both indicate that in - order is not required, fast request issuance can be achieved, improving the efficiency of simulation verification. Moreover, the registers corresponding to requests that require in - order are not affected by other sequences, ensuring the accuracy of the simulation verification results while improving the efficiency of simulation verification.

[0069] In this embodiment, if there is a freq in freq new new,b whose in - order tag indicates that in - order is required, similar processing is performed with reference to S380 - S382, which will not be elaborated here.

[0070] S400, if the uvc does not receive the response of the last request corresponding to the phase k returned by the design under test, it waits until the uvc receives the response of the last request corresponding to the phase k returned by the design under test; if the uvc receives the response of the last request corresponding to the phase k returned by the design under test and k < n, then k is updated to k + 1, and S300 is repeated until k = n; the uvc is a verification component for simulating and verifying the design under test.

[0071] In this embodiment, when the uvc receives the response of the last request corresponding to the phase k returned by the design under test, that is, during the process of simulating and verifying the design under test for the phase k corresponding, the responses of all requests sent to the design under test have been returned.

[0072] Those skilled in the art know that any verification component for simulating and verifying the design under test in the prior art falls within the protection scope of the present invention.

[0073] In the task stage of simulating and verifying the design under test, the present embodiment performs simulation verification on the corresponding stage of the design under test in the order of the stages in the stage list. When the simulation verification of one stage is completed, it is determined whether the UVC has received the response to the last request of the stage returned by the design under test. If it has been received, the simulation verification of the next stage is entered. Moreover, in the process of simulation verification of each stage, the sequencer can issue a new request to the design under test before the UVC receives the historical response returned by the design under test, instead of waiting for the UVC to receive the historical response returned by the design under test and then issuing a new request to the design under test. As a result, the time for waiting for the return of the historical response corresponding to the historical request can be saved, and the duration of the simulation verification of each stage can be saved, thereby reducing the total duration of the task stage when simulating and verifying the design under test, reducing the time for simulating and verifying the design under test, and thereby improving the efficiency of simulating and verifying the design under test.

[0074] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A processing method for accelerating simulation verification, characterized in that: The method includes the following steps: S100, obtain the phase list phase corresponding to the task phase when simulating and verifying the design to be tested, phase = (phase1, phase2, ..., phase i ,…,phase n ), phase i is the i-th stage corresponding to the task stage when the design under test is simulated and verified, the value range of i is 1 to n, and n is the number of stages corresponding to the task stage when the design under test is simulated and verified; S200, initialize the first variable k to 1; S300, phase the design under test k The corresponding simulation verification is carried out in the phase of the design under test. k In the corresponding simulation verification process, the sequencer can issue a new request to the design under test before the uvc receives the historical response returned by the design under test; the historical response is the response to the request previously issued by the sequencer to the design under test; the sequencer is used to control whether each request generated by the sequence for generating the request is issued to the design under test; S400, if the uvc does not receive the phase k corresponding to the response of the last request, then wait until the uvc receives the phase k corresponding to the response of the last request; if the uvc receives the phase k corresponding to the response of the last request, and k < n, then update k to k + 1, repeat S300 until k = n; the uvc is a verification component for simulating and verifying the design under test.

2. The processing method for accelerated simulation verification according to claim 1, characterized in that: S300 includes: S310, obtain the request list req to be processed by the sequencer, req=(req1, req2,…, req a ,…,req A ), req a is the ath request to be processed by the sequencer. The value of a ranges from 1 to A, and A is the number of requests to be processed by the sequencer. a Corresponding to an order-preserving label; S320, obtain the priority list prio of the requests to be processed by the sequencer, prio=(prio1, prio2, ..., prio a ,…,prio A ), prio a For req a Priority; S330, get the highest priority prio among the prios a ; S340: If the order preservation tag of req' indicates that order preservation is required, then proceed to S350; req' is the prio with the highest priority among the prios. a Corresponding req a ; S350, obtain sequence', where sequence' is the sequence that generates req' in the sequence list sequence, sequence=(sequence1, sequence2, ..., sequence j ,…,sequence m ), sequence j is the jth sequence used to generate requests when simulating and verifying the design under test, where j ranges from 1 to m, and m is the number of sequences used to generate requests when simulating and verifying the design under test; S360: If the number of requests generated by sequence' in req is greater than or equal to ε, obtain the first request list freq, where freq=(req',freq2,…,freq b ,…,freq ε ),freq b is the request with the highest priority b generated by sequence' in req, where b ranges from 2 to ε; ε is the preset number of requests; S370, if any of freq b If the order preservation tags all indicate that order preservation is not required, the requests in freq are sorted from req' to freq ε The order is sent to the design under test in sequence, and each freq b There is no need to wait for the response of the previously issued request. ε Requests for generating other sequences in sequence except sequence' are sent to the design under test only after the request is sent to the design under test.

3. The processing method for accelerated simulation verification according to claim 2, characterized in that: S370 also includes: if there is an order preservation tag in the freq indicating that the freq needs to be order preserved b , then enter S380; S380: The last order preservation tag in freq indicates the freq that needs to be preserved. b The corresponding value of b is determined as the target request number num; S381, if the number of requests qua generated by sequence' in the second list is greater than or equal to num-1, then append the first num-1 requests generated by sequence' and having the highest priority from the second list to freq, and obtain the appended freq as freq', freq'=(req',freq2,…,freq b ,…,freq ε ,greq1,greq2,…,greq e ,…,greq num-1 );greq e is the request in the second list that is appended to freq and has the highest priority e, where the value of e ranges from 1 to num-1, and the second list is a list consisting of the requests in req except the requests in freq; S382, if any greq in freq' e If the order preservation tags of all the requests in freq' indicate that order preservation is not required, the requests in freq' are sorted from req' to greq num-1 The order of freq' is issued to the design under test, and each request in freq' is issued without waiting for the response of the previously issued request. num-1 Requests for generating other sequences in sequence except sequence' are sent to the design under test only after the request is sent to the design under test.

4. The processing method for accelerated simulation verification according to claim 2, characterized in that: S340 further includes: if the in-order tag of req' indicates that in-order is not required, then after sending req' to the design under test, enter S341; S341, obtain the updated sequencer request list req to be processed new ,req new =(req new,1 ,req new,2 ,…,req new,r ,…,req new,R ), req new,r is the rth request to be processed by the updated sequencer, where r ranges from 1 to R, and R is the number of requests to be processed by the updated sequencer; each req new,r Corresponding to an order-preserving label; S342, obtaining the updated priority list prio of the sequencer's pending requests new , prio new =(prio new,1 ,prio new,2 ,…,prio new,r ,…,prio new,R ), prio new,r For req new,r Priority; S343, get prio new The highest priority prio new,r ; S344, if req' new If the sequence preservation tag indicates that sequence preservation is required, then enter S345; req' new For prio new The highest priority prio new,r Corresponding req new,r ; S345, get sequence' new , sequence' new Generate req' for the sequence list sequence new sequence; S346, if req new In sequence' new If the number of generated requests is greater than or equal to ε, then get the updated first request list freq new ,freq new =(req' new ,freq new,2 ,…,freq new,b ,…,freq new,ε ),freq new,b For req new In sequence' new The generated request with the highest priority b; S347, if freq new Any freq new,b If the order preservation tags of freq new Request in accordance with req' new to freq new,ε The order is sent to the design under test, and when the freq new Each request in the process does not need to wait for the response of the previous request. new,ε After the design under test is issued, the sequence is issued to the design under test except sequence' new Requests generated by sequences other than .

5. The processing method for accelerated simulation verification according to claim 3, characterized in that: S381 further includes: if qua < num - 1, then enter S383; S383, append the first qua requests with the highest priority generated by sequence' from the second list to freq, and obtain the appended freq as nreq, nreq=(req',freq2,…,freq b ,…,freq ε ,greq1,greq2,…,greq c ,…,greq qua );greq c The request with the cth highest priority is appended to freq, where the value of c ranges from 1 to qua. S384, if any greq in nreq c If the order preservation tags of all the requests in nreq indicate that order preservation is not required, the requests in nreq are sorted from req' to greq qua The order of nreq is issued to the design under test in sequence, and each request in nreq is issued without waiting for the response of the previously issued request. The requests generated by other sequences in sequence except sequence' are issued to the design under test after the specified time. The specified time is the time after the target time and the preset sequence preservation time period. The target time is the freq that the last sequence preservation tag in freq indicates needs to be preserved. b The time at which the design under test is issued.

6. The processing method for accelerated simulation verification according to claim 3, characterized in that: S382 also includes: if there is an order preservation tag in freq' indicating that the order preservation is required e , then enter S385; S385, the last order-preserving label in freq' indicates the greq that needs to be preserved in order e The corresponding value of e is determined to be the specified number of requests β; S386: If the number of requests generated by sequence' in the third list is greater than or equal to β, then the first β requests generated by sequence' and having the highest priority are added to freq' from the third list, and the added freq' is freq + ,freq + =(req',freq2,…,freq b ,…,freq ε ,greq1,greq2,…,greq e ,…,greq num-1 ,hreq1,hreq2,…,hreq t ,…,hreq β ); hreq t The third list is appended to freq + The request with the tth highest priority, t ranges from 1 to β, and the third list is a list consisting of the requests in req except the requests in freq'; S387, if freq + Any hreq t If the order preservation tags of freq + The request follows the sequence from req' to hreq β The order of hreq is issued to the design under test, and each request in freq' is issued without waiting for the response of the previously issued request. β Requests for generating other sequences in sequence except sequence' are sent to the design under test only after the request is sent to the design under test.

7. The processing method for accelerated simulation verification according to claim 2, characterized in that: req a The corresponding sequence preservation tag value is the first preset value or the second preset value. a When the value of the corresponding sequence-preserving tag is the preset first value, req a Need to preserve order; when req a When the value of the corresponding sequence preservation tag is the preset second value, req a No order preservation is required.

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