Verilog-based phase-locked loop circuit output signal frequency control method and system

Abstract

The invention discloses a Verilog-based phase-locked loop circuit output signal frequency control method and system, and relates to the technical field of electric digital data processing, and the method comprises the steps: monitoring an output signal of a phase frequency detector in real time, and recording the output signal data of the phase frequency detector; calculating a frequency difference value according to the output signal data of the phase frequency detector; adjusting the control voltage of the voltage-controlled oscillator according to the frequency difference value; and the output signal frequency of the voltage-controlled oscillator is fed back to the phase frequency detector. According to the invention, by monitoring the output signal of the phase frequency detector, the trigger time and the trigger times of the rising edge and the falling edge are obtained in real time for frequency difference calculation, and the control voltage of the voltage-controlled oscillator is adjusted based on the frequency difference, so that the control of the output signal frequency of the phase-locked loop circuit is realized; the process does not need to depend on the Cadence environment to accurately set variables and make waveforms, and the output signal frequency of the phase-locked loop circuit is controlled in the Verilog environment.

Description

Technical Field

[0001] The present invention relates to the technical field of electrical digital data processing, and in particular to a method and system for controlling the frequency of an output signal of a phase-locked loop circuit based on Verilog. Background Art

[0002] The phase-locked loop circuit is an electronic circuit used to control and adjust the frequency and phase. Its core function is to lock the frequency and phase of the output signal to the reference signal. Even if the frequency of the reference signal changes, the phase-locked loop circuit can adjust the output signal to synchronize with the reference signal. When designing and verifying the phase-locked loop circuit, it is usually described in a language related to Verilog-A. Verilog-A describes the phase-locked loop circuit by accurately setting variables such as voltage and current and making waveforms through functions. In this process, Verilog-A needs to rely on Cadence, an automated tool, and cannot implement the frequency modulation function of the phase-locked loop circuit without the Cadence environment, resulting in inconvenience in the design of the phase-locked loop circuit. Therefore, there is an urgent need for a method to implement the frequency modulation function of the phase-locked loop circuit without the Cadence environment and using pure digital logic. Summary of the invention

[0003] The purpose of the present invention is to provide a method and system for controlling the frequency of a phase-locked loop circuit output signal based on Verilog. The present invention monitors the output signal of a frequency detector and phase detector, obtains the trigger time of the rising edge and the falling edge and the trigger number of the rising edge and the falling edge in real time, calculates the frequency difference, and adjusts the control voltage of a voltage-controlled oscillator based on the frequency difference, thereby realizing the control of the frequency of the output signal of the phase-locked loop circuit. The whole process does not need to rely on the precise setting of variables and the production of waveforms in the Cadence environment, and realizes the control of the output signal frequency of the phase-locked loop circuit in the Verilog environment.

[0004] The purpose of the present invention is achieved by the following technical means: In a first aspect, the present invention provides a method for controlling the frequency of an output signal of a phase-locked loop circuit based on Verilog, comprising: Monitor the output signal of the frequency detector and phase detector in real time and record the output signal data of the frequency detector and phase detector; Calculating the frequency difference according to the output signal data of the frequency and phase detector; adjusting a control voltage of a voltage-controlled oscillator according to the frequency difference; Feeding the output signal frequency of the voltage-controlled oscillator back to the frequency and phase detector; Among them, the output signal data includes the up signal rising edge trigger time, the up signal falling edge trigger time, the up signal rising edge trigger times, the up signal falling edge trigger times, the dn signal rising edge trigger time, the dn signal falling edge trigger time, the dn signal rising edge trigger times and the dn signal falling edge trigger times.

[0005] Preferably, the real-time monitoring of the output signal of the phase frequency detector and recording the output signal data of the phase frequency detector include: Obtain and monitor the up signal and dn signal of the frequency detector and phase detector; Record the time when the up signal rises to obtain the trigger time of the up signal rising edge; Record the time when the up signal falls, and obtain the trigger time of the falling edge of the up signal; Record the number of times the up signal rises to obtain the number of times the up signal rises; Record the number of times the up signal falls, and obtain the number of times the up signal falls; Record the time of the rising moment of the dn signal to obtain the rising edge trigger time of the dn signal; Record the time when the dn signal falls, and obtain the trigger time of the falling edge of the dn signal; Record the number of rising moments of the dn signal to obtain the number of rising edge triggering times of the dn signal; The number of times the dn signal falls is recorded to obtain the number of times the dn signal falls.

[0006] Preferably, the calculating the frequency difference according to the output signal data of the frequency detector and phase detector comprises: When the number of times the up signal rising edge is triggered is equal to the number of times the up signal falling edge is triggered, obtaining the up signal rising edge trigger time and the up signal falling edge trigger time; The up signal frequency difference is obtained by subtracting the up signal rising edge trigger time from the up signal falling edge trigger time.

[0007] Preferably, the calculating the frequency difference according to the output signal data of the frequency detector and phase detector comprises: When the number of times the dn signal is triggered by the rising edge is equal to the number of times the dn signal is triggered by the falling edge, acquiring the dn signal rising edge trigger time and the dn signal falling edge trigger time; The dn signal frequency difference is obtained by subtracting the dn signal rising edge trigger time from the dn signal falling edge trigger time.

[0008] Preferably, adjusting the control voltage of the voltage-controlled oscillator according to the frequency difference includes: According to the frequency difference, adjusting the control voltage frequency; Recalculating the frequency coefficient according to the control voltage frequency; The control voltage phase is adjusted according to the frequency coefficient.

[0009] Preferably, adjusting the control voltage frequency according to the frequency difference includes: Inputting the up signal frequency difference into a charge pump, and the charge pump increases the control voltage frequency by the up signal frequency difference; Or, the dn signal frequency difference is input into a charge pump, and when the dn signal frequency difference is smaller than the control voltage frequency, the charge pump reduces the control voltage frequency by the dn signal frequency difference.

[0010] Preferably, adjusting the control voltage phase according to the frequency coefficient includes: Obtain and monitor the minimum clock signal; When the minimum clock signal changes, record the number of changes; When the number of changes is equal to the frequency coefficient, an inversion operation is performed on the phase of the output signal and the number of changes is cleared.

[0011] Preferably, before the real-time monitoring of the output signal of the phase frequency detector and recording the output signal data of the phase frequency detector, the method further comprises: Get reset signal data; When the reset signal data is at a first level, stopping controlling the output signal frequency; When the reset signal data is at the second level, the output signal frequency starts to be controlled, and an initial control voltage frequency and an initial frequency coefficient are set; The first level is a low level, and the second level is a high level.

[0012] Preferably, the step of feeding back the frequency of the output signal of the voltage-controlled oscillator to the frequency and phase detector comprises: Dividing the frequency of the output signal of the voltage-controlled oscillator to obtain a divided output signal frequency; The frequency of the frequency-divided output signal is fed back to the frequency detector and phase detector.

[0013] In a second aspect, the present invention provides a Verilog-based phase-locked loop circuit output signal frequency control system, which is applied to the above-mentioned Verilog-based phase-locked loop circuit output signal frequency control method, comprising: A data acquisition module, used for real-time monitoring of the output signal of the frequency detector and phase detector and recording the output signal data of the frequency detector and phase detector; A data processing module, used for calculating the frequency difference according to the output signal data of the frequency and phase detector; An output control module, used for adjusting a control voltage of a voltage-controlled oscillator according to the frequency difference; A frequency feedback module, used for feeding back the output signal frequency of the voltage-controlled oscillator to the frequency and phase detector; Among them, the output signal data includes the up signal rising edge trigger time, the up signal falling edge trigger time, the up signal rising edge trigger times, the up signal falling edge trigger times, the dn signal rising edge trigger time, the dn signal falling edge trigger time, the dn signal rising edge trigger times and the dn signal falling edge trigger times.

[0014] Compared with the prior art, the present invention has the following beneficial effects: The present invention monitors the output signal of the frequency detector and phase detector, obtains the trigger time of the rising edge and the falling edge and the trigger number of the rising edge and the falling edge in real time to calculate the frequency difference, and adjusts the control voltage of the voltage-controlled oscillator based on the frequency difference, thereby realizing the control of the output signal frequency of the phase-locked loop circuit. The whole process does not need to rely on the precise setting of variables and the production of waveforms in the Cadence environment, and realizes the control of the output signal frequency of the phase-locked loop circuit in the Verilog environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0017] Figure 1 A flowchart of a method for controlling the frequency of a phase-locked loop circuit output signal based on Verilog provided in this embodiment; Figure 2 A schematic diagram of the process of step S1 provided in this embodiment; Figure 3 A schematic diagram of the process of step S2 provided in this embodiment; Figure 4 A schematic diagram of the process of step S2 provided in this embodiment; Figure 5 A schematic diagram of the process of step S3 provided in this embodiment; Figure 6A schematic diagram of the process of step S33 provided in this embodiment; Figure 7 A schematic diagram of the process flow of the steps before step S1 provided in this embodiment; Figure 8 A schematic diagram of the process of step S4 provided in this embodiment; Fig. 9 A schematic diagram of the structure of a Verilog-based phase-locked loop circuit output signal frequency control system provided in this embodiment; Fig.10 A schematic diagram of the structure of an electronic device provided in this embodiment. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0020] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0021] The present invention monitors the output signal of the frequency detector and phase detector, obtains the trigger time of the rising edge and the falling edge and the trigger number of the rising edge and the falling edge in real time, calculates the frequency difference, and adjusts the control voltage of the voltage-controlled oscillator based on the frequency difference, thereby realizing the control of the output signal frequency of the phase-locked loop circuit. The whole process does not need to rely on the precise setting of variables and the production of waveforms in the Cadence environment, and realizes the control of the output signal frequency of the phase-locked loop circuit in Verilog.

[0022] The present invention provides a method for controlling the frequency of a phase-locked loop circuit output signal based on Verilog, such as Figure 1 As shown, the following steps are included: S1, real-time monitoring of the output signal of the phase frequency detector and recording the output signal data of the phase frequency detector; S2, calculating the frequency difference according to the output signal data of the frequency and phase detector; S3, adjusting the control voltage of the voltage-controlled oscillator according to the frequency difference; S4, feeding back the output signal frequency of the voltage-controlled oscillator to the frequency and phase detector; Among them, the output signal data includes the up signal rising edge trigger time, the up signal falling edge trigger time, the up signal rising edge trigger times, the up signal falling edge trigger times, the dn signal rising edge trigger time, the dn signal falling edge trigger time, the dn signal rising edge trigger times and the dn signal falling edge trigger times.

[0023] It should be noted that the output signal of the frequency detector is divided into an up signal and a dn signal. When the frequency detector detects that the frequency of the output signal of the phase-locked loop circuit is lower than the frequency of the reference signal, the up signal will be output, indicating that the frequency of the output signal of the phase-locked loop circuit needs to be increased. When the frequency detector detects that the frequency of the output signal of the phase-locked loop circuit is higher than the frequency of the reference signal, the dn signal will be output, indicating that the frequency of the output signal of the phase-locked loop circuit needs to be reduced. The overall working process of the phase-locked loop circuit is that the frequency detector obtains the frequency of the reference clock signal and the output signal of the phase-locked loop signal and compares them, and outputs an error signal according to the error of the two signal frequencies. This error signal is input into the charge pump, and the charge pump adjusts the input voltage of the voltage-controlled oscillator according to the error signal. Different input voltages will cause different resonant frequencies generated in the voltage-controlled oscillator, thereby adjusting the frequency of the output signal. The control of this process requires setting the components and node current and voltage of each device, and this embodiment adjusts the control voltage of the voltage-controlled oscillator by obtaining the output signal data of the frequency detector and calculating the frequency difference.

[0024] In this embodiment, the output signal of the frequency detector is monitored, the trigger time of the rising edge and the falling edge and the trigger number of the rising edge and the falling edge are obtained in real time to calculate the frequency difference, and the control voltage of the voltage-controlled oscillator is adjusted based on the frequency difference, thereby achieving control of the output signal frequency of the phase-locked loop circuit. The entire process does not need to rely on the precise setting of variables and the production of waveforms in the Cadence environment, and the output signal frequency of the phase-locked loop circuit can be controlled in the Verilog environment.

[0025] In some embodiments, Figure 2As shown, step S1, real-time monitoring of the output signal of the phase frequency detector and recording the output signal data of the phase frequency detector, includes the following steps: S11, obtaining and monitoring the up signal and dn signal of the frequency and phase detector; S12, record the time of the up signal rising moment to obtain the up signal rising edge trigger time; S13, record the time when the up signal falls, and obtain the trigger time of the falling edge of the up signal; S14, record the number of times the up signal rises, and obtain the number of times the up signal rises; S15, record the number of times the up signal falls, and obtain the number of times the up signal falls; S16, recording the time of the rising moment of the dn signal to obtain the rising edge trigger time of the dn signal; S17, record the time when the dn signal falls, and obtain the trigger time of the falling edge of the dn signal; S18, recording the number of rising moments of the dn signal to obtain the number of rising edge triggering times of the dn signal; S19, record the number of times the dn signal falls, and obtain the number of times the dn signal falls.

[0026] It should be noted that the process of monitoring the output signal of the frequency detector is to monitor the two output signals separately. When the signal changes, the time of the current change is obtained, and it is determined whether the signal belongs to the up signal or the dn signal and the value of the signal. If the signal change belongs to the up signal and is high level, the up signal rising edge trigger time is obtained, and this signal change is recorded as the first trigger of the up signal rising edge. When the up signal rising edge is monitored again, the time of the current change is recorded as the up signal rising edge trigger time, and this signal change is recorded as the second trigger of the up signal rising edge. Other trigger times and trigger times are deduced by analogy to obtain the output signal data of the frequency detector.

[0027] In some embodiments, Figure 3 As shown, step S2, calculating the frequency difference according to the output signal data of the frequency detector and phase detector, includes the following steps: S21, when the number of up signal rising edge triggering times is equal to the number of up signal falling edge triggering times, obtaining the up signal rising edge triggering time and the up signal falling edge triggering time; S22, subtract the up signal rising edge trigger time from the up signal falling edge trigger time to obtain the up signal frequency difference.

[0028] It should be noted that the up signal of the frequency detector is monitored in real time, and the above steps are performed every time the up signal changes. When the rising edge trigger number is equal to the falling edge trigger number, it is explained as the rising edge and falling edge of the same waveform, and the falling edge trigger time is subtracted from the rising edge trigger time to obtain the high level time. The time step of this embodiment is set to 1, so the high level time can be considered as the frequency difference, that is, the frequency value that the output signal needs to increase.

[0029] In some embodiments, Figure 4 As shown, step S2, calculating the frequency difference according to the output signal data of the frequency detector and phase detector, includes the following steps: S23, when the number of dn signal rising edge triggering times is equal to the number of dn signal falling edge triggering times, obtaining the dn signal rising edge triggering time and the dn signal falling edge triggering time; S24, subtract the rising edge trigger time of the dn signal from the falling edge trigger time of the dn signal to obtain a frequency difference of the dn signal.

[0030] It should be noted that the DN signal of the frequency detector is monitored in real time, and the above steps are performed each time the DN signal is monitored to change. When the rising edge trigger number is equal to the falling edge trigger number, it is indicated that it is the rising edge and falling edge of the same waveform, and the falling edge trigger time is subtracted from the rising edge trigger time to obtain the high level time. The time step of this embodiment is set to 1, so the high level time can be considered as the frequency difference, that is, the frequency value that the output signal needs to be reduced.

[0031] In some embodiments, Figure 5 As shown, step S3, adjusting the control voltage of the voltage-controlled oscillator according to the frequency difference, includes the following steps: S31, adjusting the control voltage frequency according to the frequency difference; S32, recalculating the frequency coefficient according to the control voltage frequency; S33, adjusting the control voltage phase according to the frequency coefficient.

[0032] It should be noted that the frequency coefficient is calculated based on the control voltage frequency, and changes with the change of the control voltage frequency of the voltage-controlled oscillator. Its function is to provide a time reference for phase inversion.

[0033] In some embodiments, step S31, adjusting the control voltage frequency according to the frequency difference, includes the following steps: S311, inputting the up signal frequency difference into the charge pump, and the charge pump increases the control voltage frequency by the up signal frequency difference; Or, S312, inputting the dn signal frequency difference into the charge pump, when the dn signal frequency difference is smaller than the control voltage frequency, the charge pump reduces the control voltage frequency by the dn signal frequency difference.

[0034] It should be noted that the up signal frequency difference is the frequency value that needs to be increased. When the up signal frequency difference is not zero, that is, the rising edge and falling edge of the same waveform of the up signal are detected to calculate the up signal frequency difference, the control voltage frequency is increased by the up signal frequency difference through the charge pump. The dn signal frequency difference is the frequency value that needs to be reduced. When the dn signal frequency difference is not zero and the dn signal frequency difference is less than the control voltage frequency, that is, the rising edge and falling edge of the same waveform of the dn signal are detected to calculate the dn signal frequency difference and the control voltage frequency is not reduced to zero, the control voltage frequency is reduced by the dn signal frequency difference through the charge pump.

[0035] In some embodiments, Figure 6 As shown, step S33, adjusting the control voltage phase according to the frequency coefficient, includes the following steps: S331, obtaining and monitoring a minimum clock signal; S332, when the minimum clock signal changes, record the number of changes; S333, when the number of changes is equal to the frequency coefficient, the output signal phase is inverted and the number of changes is cleared.

[0036] It should be noted that the minimum clock signal is monitored in real time, and the above steps are executed every time the minimum clock signal changes. When the minimum clock signal passes the number of frequency coefficients, the output signal of the phase-locked loop circuit is inverted to achieve an oscillation effect.

[0037] In some embodiments, Figure 7 As shown, before step S1, real-time monitoring of the output signal of the phase frequency detector and recording the output signal data of the phase frequency detector, the following steps are also included: S01, obtaining reset signal data; S02, when the reset signal data is at the first level, stop controlling the output signal frequency; S03, when the reset signal data is at the second level, start to control the output signal frequency, and set the initial control voltage frequency and the initial frequency coefficient; The first level is a low level, and the second level is a high level.

[0038] It should be noted that the phase-locked loop circuit may be unstable or in the process of resetting, and the output signal frequency obtained at this time is not accurate. Therefore, by obtaining the input reset signal data, when the reset signal data is at the first level, the output signal and the control voltage are controlled to 0, and when the reset signal is at the second level, the control voltage frequency is initialized and the frequency coefficient is calculated. The initial control voltage frequency of this embodiment is set to 0.5 times the positive phase signal value of the reference clock signal.

[0039] In some embodiments, Figure 8 As shown, step S4, feeding back the output signal frequency of the voltage-controlled oscillator to the frequency detector and phase detector, includes the following steps: S41, dividing the frequency of the output signal of the voltage-controlled oscillator to obtain a divided output signal frequency; S42, feeding back the frequency of the divided output signal to the frequency detector and phase detector.

[0040] The present invention provides a Verilog-based phase-locked loop circuit output signal frequency control system, which is applied to the above-mentioned Verilog-based phase-locked loop circuit output signal frequency control method, such as Fig. 9 As shown, including: A data acquisition module, used for real-time monitoring of the output signal of the frequency detector and phase detector and recording the output signal data of the frequency detector and phase detector; A data processing module, used for calculating the frequency difference according to the output signal data of the frequency and phase detector; An output control module, used for adjusting the control voltage of the voltage-controlled oscillator according to the frequency difference; A frequency feedback module, used for feeding back the output signal frequency of the voltage-controlled oscillator to the frequency and phase detector; Among them, the output signal data includes the up signal rising edge trigger time, the up signal falling edge trigger time, the up signal rising edge trigger times, the up signal falling edge trigger times, the dn signal rising edge trigger time, the dn signal falling edge trigger time, the dn signal rising edge trigger times and the dn signal falling edge trigger times.

[0041] In this embodiment, the output signal of the frequency detector is monitored, the trigger time of the rising edge and the falling edge and the trigger times of the rising edge and the falling edge are obtained in real time to calculate the frequency difference, and the control voltage of the voltage-controlled oscillator is adjusted based on the frequency difference, so as to control the frequency of the output signal of the phase-locked loop circuit. The whole process does not need to rely on the precise setting of variables and the production of waveforms in the Cadence environment, and the output signal frequency of the phase-locked loop circuit is controlled in the Verilog environment. It should be understood that the disclosed system can be implemented in other ways. For example, the system embodiments described above are merely schematic. For example, the division of the above modules is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, each functional module can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules.

[0042] The present invention provides an electronic device 2, such as Fig.10 As shown, a processor 21 and a memory 22, the memory 22 is used to store computer program codes, the computer program codes include computer instructions, when the processor 21 executes the computer instructions, the electronic device executes the above-mentioned method for controlling the frequency of the output signal of a phase-locked loop circuit based on Verilog.

[0043] The electronic device 2 includes a processor 21, a memory 22, an output device 23, and an input device 24. The processor 21, the memory 22, the output device 23, and the input device 24 are coupled via a connector, and the connector includes various interfaces, transmission lines, or buses, etc., which are not limited in the embodiments of the present invention. It should be understood that in various embodiments of the present invention, coupling refers to mutual connection in a specific manner, including direct connection or indirect connection through other devices, for example, through various interfaces, transmission lines, buses, etc.

[0044] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group consisting of multiple GPUs, and the multiple processors are coupled to each other via one or more buses. Optionally, the processor 21 may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0045] The memory 22 can be used to store computer program instructions and various computer program codes including program codes for executing the scheme of the present invention. Optionally, the memory 22 includes but is not limited to random access memory (RAM), read-only memory (ROM), erasable programmable read only memory (EPROM), or portable read only memory (CD-ROM), and the memory 22 is used for related instructions and data.

[0046] The input device 24 is used to input data and / or signals, and the output device 23 is used to output data and / or signals. The output device 23 and the input device 24 can be independent devices or an integrated device.

[0047] The present invention provides a computer-readable storage medium, in which a computer program is stored. The computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes the above-mentioned Verilog-based phase-locked loop circuit output signal frequency control method.

[0048] The above are only specific embodiments of the present invention, which enable those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for controlling the frequency of an output signal of a phase-locked loop circuit based on Verilog, characterized in that: include: Monitor the output signal of the frequency detector and phase detector in real time and record the output signal data of the frequency detector and phase detector; Calculating the frequency difference according to the output signal data of the frequency and phase detector; adjusting a control voltage of a voltage-controlled oscillator according to the frequency difference; Feeding the output signal frequency of the voltage-controlled oscillator back to the frequency and phase detector; Wherein, the output signal data includes the up signal rising edge trigger time, the up signal falling edge trigger time, the up signal rising edge trigger times, the up signal falling edge trigger times, the dn signal rising edge trigger time, the dn signal falling edge trigger time, the dn signal rising edge trigger times and the dn signal falling edge trigger times; The step of adjusting the control voltage of the voltage controlled oscillator according to the frequency difference comprises: According to the frequency difference, adjusting the control voltage frequency; Recalculating the frequency coefficient according to the control voltage frequency; According to the frequency coefficient, adjusting the control voltage phase; The step of adjusting the control voltage frequency according to the frequency difference comprises: Inputting the up signal frequency difference into a charge pump, and the charge pump increases the control voltage frequency by the up signal frequency difference; Or, inputting the dn signal frequency difference into a charge pump, and when the dn signal frequency difference is less than the control voltage frequency, the charge pump reduces the control voltage frequency by the dn signal frequency difference; The step of adjusting the control voltage phase according to the frequency coefficient includes: Obtain and monitor the minimum clock signal; When the minimum clock signal changes, record the number of changes; When the number of changes is equal to the frequency coefficient, an inversion operation is performed on the phase of the output signal and the number of changes is cleared.

2. The method for controlling the frequency of a phase-locked loop circuit output signal based on Verilog according to claim 1, characterized in that: The real-time monitoring of the output signal of the phase frequency detector and the recording of the output signal data of the phase frequency detector include: Obtain and monitor the up signal and dn signal of the frequency detector and phase detector; Record the time when the up signal rises to obtain the trigger time of the rising edge of the up signal; Record the time when the up signal falls, and obtain the trigger time of the falling edge of the up signal; Record the number of times the up signal rises, and obtain the number of times the up signal rises; Record the number of times the up signal falls, and obtain the number of times the up signal falls; Record the time of the dn signal rising moment to obtain the dn signal rising edge trigger time; Record the time when the dn signal falls, and obtain the trigger time of the falling edge of the dn signal; Record the number of rising moments of the dn signal to obtain the number of rising edge triggering times of the dn signal; The number of times the dn signal falls is recorded to obtain the number of times the dn signal falls.

3. The method for controlling the frequency of a phase-locked loop circuit output signal based on Verilog according to claim 1, characterized in that: The step of calculating the frequency difference according to the output signal data of the frequency detector and phase detector comprises: When the number of times the up signal rising edge is triggered is equal to the number of times the up signal falling edge is triggered, obtaining the up signal rising edge trigger time and the up signal falling edge trigger time; The up signal frequency difference is obtained by subtracting the up signal rising edge trigger time from the up signal falling edge trigger time.

4. The method for controlling the frequency of a phase-locked loop circuit output signal based on Verilog according to claim 1, characterized in that: The step of calculating the frequency difference according to the output signal data of the frequency detector and phase detector comprises: When the number of times the dn signal is triggered by the rising edge is equal to the number of times the dn signal is triggered by the falling edge, acquiring the dn signal rising edge trigger time and the dn signal falling edge trigger time; The dn signal frequency difference is obtained by subtracting the dn signal rising edge trigger time from the dn signal falling edge trigger time.

5. The method for controlling the frequency of a phase-locked loop circuit output signal based on Verilog according to claim 1, characterized in that: Before the real-time monitoring of the output signal of the phase frequency detector and the recording of the output signal data of the phase frequency detector, the method further comprises: Get reset signal data; When the reset signal data is at a first level, stopping controlling the output signal frequency; When the reset signal data is at the second level, the output signal frequency starts to be controlled, and an initial control voltage frequency and an initial frequency coefficient are set; The first level is a low level, and the second level is a high level.

6. The method for controlling the frequency of a phase-locked loop circuit output signal based on Verilog according to claim 1, characterized in that: Feeding back the frequency of the output signal of the voltage-controlled oscillator to the frequency and phase detector comprises: Dividing the frequency of the output signal of the voltage-controlled oscillator to obtain a divided output signal frequency; The frequency of the frequency-divided output signal is fed back to the frequency detector and phase detector.

7. A Verilog-based phase-locked loop circuit output signal frequency control system, used to execute a Verilog-based phase-locked loop circuit output signal frequency control method as claimed in any one of claims 1 to 6, characterized in that: include: A data acquisition module, used for real-time monitoring of the output signal of the frequency detector and phase detector and recording the output signal data of the frequency detector and phase detector; A data processing module, used for calculating the frequency difference according to the output signal data of the frequency and phase detector; An output control module, used for adjusting a control voltage of a voltage-controlled oscillator according to the frequency difference; A frequency feedback module, used for feeding back the output signal frequency of the voltage-controlled oscillator to the frequency and phase detector; Among them, the output signal data includes the up signal rising edge trigger time, the up signal falling edge trigger time, the up signal rising edge trigger times, the up signal falling edge trigger times, the dn signal rising edge trigger time, the dn signal falling edge trigger time, the dn signal rising edge trigger times and the dn signal falling edge trigger times.

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