Layout design violation detection method and device, equipment and storage medium

Abstract

The invention provides a violation detection method and device for layout design, equipment and a storage medium, and relates to the technical field of integrated circuit design automation, according to the algorithm, a truncation mode is generated through a preprocessing stage, a to-be-processed interval is determined in the legalization process, violation detection is carried out through a three-pointer algorithm, and the truncation mode and the truncation interval are different. The method comprises the following steps of: respectively representing the arrangement of lattice point types in the layout and a to-be-processed interval, generating a truncation mode, searching the to-be-processed interval, identifying violation through multi-round scanning, and judging the legality of unit positions until all units are legalized, so that the violation condition in the layout can be effectively identified, and the efficiency and the accuracy of design verification are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design automation, and in particular to a layout design violation detection method, device, equipment and storage medium. Background Art

[0002] In advanced integrated circuit nodes (22nm and below), self-aligned dual patterning confinement is a key technology to reduce feature size under limited lithography resolution. However, in this technology, if the distance between two patterns is smaller than the lithography resolution, they cannot be manufactured on the same mask.

[0003] Currently, in order to adapt to the self-aligned dual imaging technology, it is usually adopted in the standard cell library design stage to adjust the geometry of the standard cell routing to reduce the conflict between different cells under certain placement conditions (related to cell spacing and cell direction). However, this solution requires more frequent updates and maintenance of the standard cell library to ensure that all possible placement conditions are taken into account, and has poor flexibility.

[0004] In addition, during the wiring stage, some technicians also consider self-aligned double imaging constraints in advance to avoid manufacturability problems caused by double imaging after the chip layout is completed. However, the wiring stage belongs to the later stage of the design, and there is less room for adjustment during the wiring stage. Considering constraints in complex wiring will also face more modification complexity.

[0005] Therefore, in the integrated circuit design automation process, especially in the layout design violation detection method related process, how to quickly identify and flexibly solve potential placement problems in the early stage of the design process is a crucial issue. Summary of the invention

[0006] In view of this, the embodiments of the present application provide a layout design violation detection method, device, equipment and storage medium. By considering the optimal insertion of the filling unit in advance in the legalization stage, a legal filling unit insertion plan can be guaranteed when the unit is not fixed, and potential placement problems can be solved more flexibly. In addition, in the preprocessing stage, truncation mode rules are generated according to the constraints to limit the length of the interval for a single judgment. The three-pointer algorithm is used in the judgment process to quickly identify and judge the illegal interval. The embodiments of the present application provide the following technical solutions:

[0007] On the one hand, an embodiment of the present application provides a layout design violation detection method, comprising the following steps:

[0008] Obtaining constraint conditions, generating truncation mode rules based on the constraint conditions, obtaining a circuit design layout, and selecting a number of units to be processed and a number of positions to be placed;

[0009] Selecting a current processing unit from the units to be processed, selecting a current placement position from the positions to be placed, and generating a to-be-processed interval for the current processing unit at the current placement position based on the truncation pattern rule;

[0010] Perform multiple rounds of scanning on the waiting interval using a three-pointer algorithm to determine the violation, and when the violation is identified or the waiting interval is scanned, stop scanning the three-pointer algorithm and return the scanning judgment result at the current placement position;

[0011] Based on the scanning result, the placement legality of the current processing unit is judged, and if the placement legality is met, the next unit to be processed is processed; after all the units to be processed are processed, a legalized circuit design layout result is returned.

[0012] Furthermore, the constraint conditions include a minimum width constraint within a row and a minimum spacing constraint within a row.

[0013] Furthermore, the truncation pattern rule is that there is a truncation interval, so that the distribution design of the grid filling type on the first side of the truncation interval will not cause a violation of the distribution design on the second side.

[0014] Furthermore, a first truncation interval and a second truncation interval satisfying the truncation pattern rule are searched laterally along the current processing unit, and the grid points between the first truncation interval and the second truncation interval constitute the interval to be processed.

[0015] Furthermore, in each round of scanning of the three-pointer algorithm, three pointers move synchronously, and the violation is determined by the length of the pointer interval.

[0016] Furthermore, if a violation is found in this round of scanning, the scanning is stopped and the violation result at the current placement position is returned; if no violation is found in this round of scanning, the next round of scanning is performed until the interval to be processed is scanned and the compliance result at the current placement position is returned.

[0017] Furthermore, when the placement legality is not met, the next placement position among the positions to be placed is selected as the current placement position for the scanning judgment; when the placement legality is met, the next processing unit among the units to be processed is selected as the current processing unit for the scanning judgment until the units to be processed are judged.

[0018] On the other hand, an embodiment of the present application provides a layout design violation detection device, comprising:

[0019] A preprocessing module is used to obtain constraint conditions, generate truncation mode rules based on the constraint conditions, obtain a circuit design layout, and select a number of units to be processed and a number of positions to be placed;

[0020] An interval divider, used for selecting a current processing unit from the units to be processed, selecting a current placement position from the positions to be placed, and generating an interval to be processed for the current processing unit at the current placement position based on the truncation pattern rule;

[0021] A violation identifier, used for performing multiple rounds of scanning on the to-be-processed interval using a three-pointer algorithm to determine a violation, and stopping the scanning of the three-pointer algorithm upon identifying the violation or after scanning the to-be-processed interval, and returning a scanning determination result at the current placement position;

[0022] The legalization engine is used to determine the placement legality of the current processing unit based on the scanning result, and process the next unit to be processed if the placement legality is satisfied; after processing all the units to be processed, return the legalized circuit design layout result.

[0023] On the other hand, an embodiment of the present application provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the layout design violation detection method as described in any one of the above items when executing the computer program.

[0024] On the other hand, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps of the layout design violation detection method as described in any one of the above items are implemented.

[0025] Compared with the prior art, the at least one technical solution adopted in the embodiment of the present application can achieve the following beneficial effects:

[0026] 1. The violation detection method of the present application considers the optimal insertion of the filling unit in advance during the legalization stage, and can ensure that there is a legal filling unit insertion plan when the unit is not fixed, so as to solve potential placement problems more flexibly in the early stage of layout optimization and reduce the need for subsequent modifications and re-layout; by solving the filling problem in advance, the subsequent design iteration and verification process is smoother, the number of iterations in the design cycle is reduced, and multiple modifications caused by filling problems are avoided, thereby enhancing the stability of the design. Since there is no need to modify the standard cell library, the overall design cycle can be shortened and the design cost can be reduced.

[0027] 2. When processing large data sets, such as a large number of grid points in a semiconductor layout, the violation detection method of the present application generates truncation pattern rules based on constraint conditions in the preprocessing stage to limit the length of a single judgment interval. The three-pointer algorithm is used in the violation judgment process, which can complete more operations and checks in a single traversal. It has higher efficiency than the traditional two-pointer method and can quickly identify and judge the violation interval. In addition, the three-pointer algorithm can also handle multiple conditions and complex constraints more flexibly. In the real-time or near real-time layout design and verification process, it can simultaneously track the distribution of pruned layers and non-pruned layers, as well as their relationship with design rules, quickly identify violations, and adjust the design in time to reduce subsequent modifications and improvements.

[0028] 3. The violation detection method of the present application does not rely on a predefined standard cell library, and can dynamically adjust the insertion position and type of the filling cell according to the specific chip design and layout conditions, so that it can better adapt to various design requirements, such as processing irregularly shaped areas or coping with changing layout constraints. According to the actual layout conditions and cell spacing, the optimal filling cell insertion scheme can be accurately identified, thereby minimizing the number of violations of the filling cell and enhancing the robustness and adaptability of the detection method. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 is a step diagram of a violation detection method provided by an embodiment of the present invention;

[0031] Figure 2 is a schematic diagram of the relationship between intervals to be processed provided by an embodiment of the present invention;

[0032] Figure 3 It is a schematic diagram of the principle of a three-pointer algorithm provided by an embodiment of the present invention;

[0033] Figure 4 It is a schematic diagram of a violation detection device provided by an embodiment of the present invention.

[0034] In the figure: 11, first truncation interval, 12, second truncation interval, 13, current processing unit, 14, interval to be processed, 21, first scanning interval (point), 22, second scanning interval (point), 301, preprocessing module, 302, interval divider, 303, violation identifier, 304, legalization engine. DETAILED DESCRIPTION

[0035] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work belong to the scope of protection of the present invention.

[0037] It should be noted that the terms "first", "second", etc. in the specification, claims and drawings of the present invention are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0038] A layout design violation detection method, device, equipment and storage medium provided by the embodiment of the present application can be applied to the scenario of violation detection in the integrated circuit design automation process. Wherein double imaging refers to a unit being mapped by multiple chip elements, resulting in manufacturability problems. Under advanced integrated circuit process nodes (7nm process and below), given the self-aligned dual imaging (SADP) constraints in the layout stage and the circuit layout to be legalized, the present invention detects in advance whether there is a violation of the self-aligned dual imaging constraints by moving the pointer and considering the subsequent filling unit insertion, so that a legal solution can be obtained in the subsequent filler unit insertion stage, and ensures that the final derived design meets the manufacturability requirements of the corresponding process.

[0039] In semiconductor manufacturing, the minimum width and minimum spacing within a row are part of the self-aligned dual imaging constraints. These rules ensure that the size of circuit elements and the distance between them meet the accuracy requirements of the process to ensure the quality of the layout.

[0040] The minimum width requirement ensures that the wires or patterns in the trimmed and non-trim layers can be clearly defined and will not be broken or shorted during the manufacturing process due to being too thin. This width is usually related to the size of the process node. As the technology node shrinks, the minimum width will also decrease accordingly. The minimum spacing requirement ensures that the distance between the trimmed and non-trim layers is large enough to prevent interference between circuit elements, such as capacitive coupling or electromigration. This spacing also decreases as the technology node shrinks, but must be kept within a safe range to ensure the reliability of the circuit.

[0041] Among the studies published so far, some of the work has studied the ion implantation layer legalization problem considering only the minimum width constraint within a row and the minimum spacing constraint within a row, which is similar to the self-aligned dual imaging constraint considered in the present invention. However, the main solutions studied include lateral movement of a single unit, expansion of a single unit width, clustering of multiple units, etc. Such solutions cannot guarantee complete identification and resolution of self-aligned dual imaging violations. In addition, in actual industrial problems, the minimum width restriction of the filler unit must also be considered.

[0042] Therefore, on the one hand, the embodiment of the present application provides a layout design violation detection method, such as Figure 1 As shown in the step diagram, a violation detection method provided by an embodiment of the present invention includes the following steps:

[0043] S1: Obtain constraint conditions, generate truncation pattern rules based on the constraint conditions, obtain the circuit design layout, select several units to be processed and several positions to be placed;

[0044] Specifically, the constraints are to determine the constraints that need to be met in the circuit design, such as size constraints, rule constraints, interconnection constraints, etc. It provides the necessary constraints and design rules for the subsequent circuit design to ensure the standardization and accuracy of the circuit design. According to the constraints obtained, the rules on how to handle different situations in the circuit design are formulated, such as how to handle different types of positions in the circuit, how to handle different types of connections, etc., to carry out the circuit layout in an orderly manner and optimize the processing flow.

[0045] S2: Select the current processing unit 13 from the units to be processed, select the current placement position from the positions to be placed, and generate a to-be-processed interval 14 for the current processing unit 13 at the current placement position based on the truncation pattern rule;

[0046] Specifically, selecting units and positions refers to organizing the various components and placement positions in the circuit design for subsequent placement and detection operations, so that the circuit design process can be carried out more efficiently and avoid repeated operations and errors. According to the truncation mode rule, the processing range of the current processing unit 13 at the current placement position, that is, the processing interval 14, is determined, and the layout is efficiently detected to see if it violates the rules, thereby improving the detection efficiency and providing necessary information for subsequent scanning judgment.

[0047] S3: Use the three-pointer algorithm to perform multiple rounds of scanning on the processing interval 14 to determine violations, check whether the current processing unit 13 meets the constraints at the current placement position, efficiently detect whether the layout violates the rules, improve detection efficiency, and identify potential violations at the same time, effectively ensure the legality and correctness of the circuit design, and avoid errors and defects; when a violation is identified or the scanning of the processing interval 14 is completed, stop the scanning of the three-pointer algorithm, return the scanning judgment result at the current placement position, and promptly feedback the layout problem to avoid invalid calculations.

[0048] S4: Determine the placement legality of the current processing unit 13 based on the scanning result. If the placement legality is met, process the next unit to be processed to ensure that the layout of each unit complies with the rules and gradually optimize the entire circuit design. After processing all units to be processed, return the legalized circuit design layout.

[0049] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0050] In some embodiments, the constraint condition includes a minimum width constraint within a row and a minimum spacing constraint within a row. The truncation pattern rule is that there is a truncation interval, so that the distribution design of the grid filling type on the first side of the truncation interval does not cause a distribution design violation on the second side.

[0051] Specifically, if Figure 2As shown in the schematic diagram of the relationship between the intervals to be processed 14 provided by one embodiment of the present invention, the truncation mode rule is that at a truncation interval, the circuit design layout is virtually divided into two parts, left and right, and the internal changes of any part only affect the part itself, and will not affect the violation of the other part. Each grid point in the layout can be divided into three types: empty, trimmed layer and non-truncation layer according to the cell filling situation and the type of filling. The truncation mode is the arrangement of several grid point types. For example, the distribution of trimmed layers and non-truncation layers on the left side of the truncation mode will not affect the violation on the right side of the truncation mode. Similarly, the distribution on the right side will not affect the left side of the truncation mode. Therefore, the truncation mode can effectively solve the cascading effects of violations caused by filler cells. It should be understood that the integrity of the truncation mode only affects the running time and does not affect the violation judgment. In the case of not generating a truncation interval, the violation judgment can also be correctly performed, but the running time will be greatly increased. According to the minimum width and minimum spacing requirements of the self-aligned dual imaging constraints, different arrangements of different lengths can be generated as stage patterns.

[0052] Furthermore, the first truncation interval 11 and the second truncation interval 12 satisfying the truncation pattern rule are searched laterally along the current processing unit 13 , and the grid points between the first truncation interval 11 and the second truncation interval 12 constitute the to-be-processed interval 14 .

[0053] Specifically, according to the location of the current processing unit 13, the search is performed on the left and right sides of the unit according to the distribution of the trimmed layer and the non-trimmed layer of the layout until the truncation pattern is identified respectively and then the search stops. The interval between the truncation patterns searched on the left and right sides is the interval to be processed 14. The judgment of the truncation interval is related to the constraint conditions. For example, when the minimum width within a row is 4 grid points and the minimum spacing constraint within a row is 5 grid points, the three typical stage modes are: (1) 9 space points; (2) 4 trimmed layer grid points + 5 non-trimmed layer grid points; (3) 5 non-trimmed layer grid points + 4 trimmed layer grid points. That is, the minimum width of a trimming type is 4, and the minimum spacing constraint between the same trimming types is 5. In addition, considering the space points in the layout stage, there are also grid point combinations such as 3 non-trimmed layer grid points + 4 space points + 2 trimmed layer grid points.

[0054] Therefore, the truncation interval can be derived by formula: let the minimum width constraint within a row be W, the minimum spacing constraint within a row be S, and the truncation mode is generally expressed as follows: (1) {i trimmed layer grid points + (W + Sij) space points + j non-trunked layer grid points | 0≤i≤W, 0≤j≤S}; (2) {j non-trunked layer grid points + (W + Sij) space points + i trimmed layer grid points | 0≤i≤W, 0≤j≤S}. Through formula derivation, the boundary of the truncation interval can be accurately defined to ensure that the constraints of advanced process nodes such as self-aligned dual imaging (SADP) are met in layout design. In addition, it is integrated into automated design tools to improve the efficiency of the design process, reduce manual intervention, and reduce human errors. It should be understood that the formula here is designed based on SADP. Different similar formulas can also be applied to meet the automated design of multiple constraints to improve design reusability.

[0055] Furthermore, in each round of scanning, the three pointers of the three-pointer algorithm move synchronously, and the violation is determined by the length of the pointer interval.

[0056] Specifically, if Figure 3 As shown in the schematic diagram of the principle of the three-pointer algorithm provided by an embodiment of the present invention, the three-pointer algorithm initializes and sets three pointers before scanning, which are called left, mid and right respectively. Left and right are used to mark the start and end positions of a single round of judgment intervals in the interval to be processed 14, while mid is used to scan between left and right, and the position will be adjusted according to the limit of the minimum width of the filler unit. The grid points pointed to by the pointers left and mid and the grid points between them constitute a first scanning interval (point) 21, and the grid points pointed to by the pointers mid and right and the grid points between them constitute a second scanning interval (point) 22. The first scanning interval (point) 21 only contains space or one type of pruning layer, and the second scanning interval (point) 22 corresponds to another type of pruning layer.

[0057] Furthermore, if a violation is found in this round of scanning, the scanning is stopped and the violation result at the current placement position is returned; if no violation is found in this round of scanning, the next round of scanning is performed until the pending interval 14 is scanned and the compliance result at the current placement position is returned.

[0058] Specifically, after the pointer is initialized, the interval 14 to be processed is scanned and identified. The algorithm starts from the left and scans to the right until it reaches the right. In each round of scanning, the algorithm compares the length of the first scanning interval (point) 21, the length of the second scanning interval (point) 22, and whether there is a minimum filler unit width violation in the two intervals to determine whether there is a violation in the single-round judgment interval. If a violation is found during the scanning process, the algorithm will record the location and type of the violation. Then, the algorithm will repeat the above steps and continue to scan the next single-round judgment interval until all possible grid point intervals in the interval 14 to be processed are scanned. For each identified violation in the interval 14 to be processed, the algorithm will determine whether it is necessary to adjust the layout of the unit or take other measures to eliminate the violation based on the type and location of the violation. All identified violations and processing suggestions in the interval 14 to be processed are fed back to the legalization engine 304 for subsequent layout adjustments.

[0059] Furthermore, when the placement legality is not satisfied, the next placement position among the positions to be placed is selected as the current placement position for scanning and judgment until a legal placement position is found; when the placement legality is satisfied, the next processing unit among the units to be processed is selected as the current processing unit 13 for scanning and judgment until all the units to be processed are judged. It should be understood that any legalization engine 304 that can provide a candidate position sequence can be combined with the violation detection method of the present application.

[0060] On the other hand, the present application embodiment provides a layout design violation detection device, such as Figure 4 A violation detection device provided by an embodiment of the present invention is shown in a schematic diagram, comprising:

[0061] The preprocessing module 301 is used to obtain constraint conditions, generate truncation pattern rules based on the constraint conditions, obtain the circuit design layout, and select a number of units to be processed and a number of positions to be placed; the preprocessing module 301 outputs truncation pattern data and layer distribution information of the layout for use by the interval divider 302, which is usually implemented on the CPU or GPU as part of the design software, and can be parallelized through FPGA to improve efficiency;

[0062] The interval divider 302 is used to select the current processing unit 13 from the units to be processed, select the current placement position from the positions to be placed, and generate a to-be-processed interval 14 for the current processing unit 13 at the current placement position based on the truncation pattern rule; the interval divider 302 outputs the definition of the to-be-processed interval 14 and passes it to the violation identifier 303, which can be integrated on the hardware platform of the legalization engine 304, using a dedicated processor or a programmable logic device (such as FPGA) to achieve fast search and interval determination.

[0063] The violation identifier 303 is used to use the three-pointer algorithm to perform multiple rounds of scanning on the processing interval 14 to determine the violation situation. When a violation situation is identified or the scanning of the processing interval 14 is completed, the scanning of the three-pointer algorithm is stopped, and the scanning judgment result at the current placement position is returned; the violation identifier 303 outputs the violation identification result to inform the legalization engine 304 whether there is a violation. The three-pointer algorithm can be executed in parallel and is suitable for implementation in a GPU or a distributed processing system to accelerate the scanning process.

[0064] The legalization engine 304 is used to determine the placement legality of the current processing unit 13 based on the scanning results, and process the next unit to be processed if the placement legality is satisfied; after processing all the units to be processed, return the legalized circuit design layout result; the legalization engine 304 controls the entire legalization process, including unit placement, calling the interval divider 302 and the violation identifier 303, and adjusting the unit position according to feedback, and is usually implemented on a high-performance server, which may include multiple CPU cores and caches to handle complex design tasks.

[0065] It should be understood that in actual hardware implementation, these components may be integrated on a unified hardware platform or distributed among multiple devices, depending on the specific design process, performance requirements and cost considerations.

[0066] Furthermore, the constraints in the preprocessing module 301 include a minimum width constraint within a line and a minimum spacing constraint within a line.

[0067] Furthermore, the truncation pattern rule in the preprocessing module 301 is that there is a truncation interval, so that the distribution design of the grid filling type on the first side of the truncation interval will not cause a violation of the distribution design on the second side.

[0068] Furthermore, the interval divider 302 searches laterally along the current processing unit 13 to the first truncation interval 11 and the second truncation interval 12 that satisfy the truncation pattern rule, and the grid points between the first truncation interval 11 and the second truncation interval 12 constitute the to-be-processed interval 14 .

[0069] Furthermore, in each round of scanning, the three pointers of the three-pointer algorithm in the violation identifier 303 move synchronously, and the violation is determined by the length of the pointer interval.

[0070] Furthermore, if the violation identifier 303 finds a violation in this round of scanning, it stops scanning and returns the violation result at the current placement position; if no violation is found in this round of scanning, the next round of scanning is performed until the processing interval 14 is scanned and the compliance result at the current placement position is returned.

[0071] Furthermore, when the placement legality is not satisfied, the legalization engine 304 selects the next placement position among the positions to be placed as the current placement position for scanning and judgment; when the placement legality is satisfied, the legalization engine 304 selects the next processing unit among the units to be processed as the current processing unit 13 for scanning and judgment until all the units to be processed are judged.

[0072] On the other hand, an embodiment of the present application provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the steps of a layout design violation detection method as described above are implemented.

[0073] On the other hand, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps of the layout design violation detection method as described above are implemented.

[0074] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and the relevant parts can be referred to the partial description of the previous embodiments.

[0075] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A layout design violation detection method, characterized in that: The following steps are involved: Obtaining constraint conditions, generating truncation mode rules based on the constraint conditions, obtaining a circuit design layout, and selecting a number of units to be processed and a number of positions to be placed; Selecting a current processing unit from the units to be processed, selecting a current placement position from the positions to be placed, and generating a to-be-processed interval for the current processing unit at the current placement position based on the truncation pattern rule; Perform multiple rounds of scanning on the waiting interval using a three-pointer algorithm to determine the violation, and when the violation is identified or the waiting interval is scanned, stop scanning the three-pointer algorithm and return the scanning judgment result at the current placement position; Determine the legality of placement of the current processing unit based on the scanning result, and if the legality of placement is met, process the next unit to be processed; After all the units to be processed are processed, a legalized circuit design layout result is returned.

2. The layout design violation detection method according to claim 1, characterized in that: The constraint conditions include a minimum width constraint within a row and a minimum spacing constraint within a row.

3. The layout design violation detection method according to claim 1, characterized in that: The truncation pattern rule is that there is a truncation interval, so that the distribution design of the grid filling type on the first side of the truncation interval will not cause a violation of the distribution design on the second side.

4. The layout design violation detection method according to claim 3, characterized in that: A first truncation interval and a second truncation interval satisfying the truncation pattern rule are searched laterally along the current processing unit, and the grid points between the first truncation interval and the second truncation interval constitute the interval to be processed.

5. The layout design violation detection method according to claim 1, characterized in that: In each round of scanning of the three-pointer algorithm, the three pointers move synchronously, and the violation is determined by the length of the pointer interval.

6. The layout design violation detection method according to claim 5, characterized in that: If a violation is found in this round of scanning, the scanning is stopped and the violation result at the current placement position is returned; if no violation is found in this round of scanning, the next round of scanning is performed until the to-be-processed interval is scanned and the compliance result at the current placement position is returned.

7. The layout design violation detection method according to claim 1, characterized in that: When the placement legality is not met, the next placement position among the positions to be placed is selected as the current placement position for the scanning judgment; when the placement legality is met, the next processing unit among the units to be processed is selected as the current processing unit for the scanning judgment until the units to be processed are judged.

8. A layout design violation detection device, characterized in that: include: A preprocessing module is used to obtain constraint conditions, generate truncation mode rules based on the constraint conditions, obtain a circuit design layout, and select a number of units to be processed and a number of positions to be placed; An interval divider, used for selecting a current processing unit from the units to be processed, selecting a current placement position from the positions to be placed, and generating an interval to be processed for the current processing unit at the current placement position based on the truncation pattern rule; A violation identifier, used for performing multiple rounds of scanning on the to-be-processed interval using a three-pointer algorithm to determine a violation, and stopping the scanning of the three-pointer algorithm upon identifying the violation or after scanning the to-be-processed interval, and returning a scanning determination result at the current placement position; A legalization engine, used for judging the legality of placement of the current processing unit based on the scanning result, and processing the next unit to be processed if the legality of placement is met; After all the units to be processed are processed, a legalized circuit design layout result is returned.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the layout design violation detection method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the layout design violation detection method according to any one of claims 1 to 7 are implemented.

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