A memristor-based brain-inspired neuromorphic circuit architecture

Abstract

The present invention discloses a memristor-based brain-like neural morphology circuit architecture, which includes a number of operational amplifiers, a number of resistors, and a number of brain-like neural network circuit system units with a row-column structure; the brain-like neural network circuit system units include a voltage source, a memristor, and an NMOS transistor; the voltage source is used to provide input for the brain-like neural morphology circuit architecture; the NMOS transistor is used to regulate the positive and negative of the synaptic weight represented by the memristor; the last row of brain-like neural network circuit system units of the brain-like neural morphology circuit architecture is connected to an arithmetic unit and a resistor, and resistors are connected between the operational amplifiers. The present invention better exhibits the electrical behavior of the metal oxide memristor through an improved memristor model. Compared with other traditional architectures, the brain-like neural morphology circuit architecture built based on this memristor model greatly reduces the scale of the circuit architecture, reduces the energy consumption of system operation, and greatly reduces the cost problem in terms of entity.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronic devices, and relates to metal oxide memristor model simulation and neuromorphic circuits. In particular, it relates to a neuromorphic circuit architecture based on memristors. Background Art

[0002] Artificial neural networks are inspired by the electrochemical communication between human brain nerve cells and other biological nervous systems. Their applications have revealed power efficiency and good application prospects in very low-power consumption and mobile electronic solutions and devices. The memristor predicted by Leon Chua is a two-port electronic passive device that can store the charge passing through its structure. Its conductance value is adjusted by applying electrical signals such as electrical pulses or sinusoidal voltages. Therefore, the memristor-based neuromorphic integration chips can perform complex calculations quickly and efficiently with minimal power consumption. Some electronic synapses based on a single memristor element and MOS transistors only ensure positive weight values. More complex circuit diagrams use multiple memristors and many operational amplifiers for each synapse to work together to simulate positive, negative, and zero synaptic weight values, but this increases the area and power consumption of the neural network simulation circuit. Therefore, the present invention proposes a neuromorphic circuit architecture based on memristors to simulate neural network weights and implement the forward propagation of neural networks. Summary of the Invention

[0003] To solve the above technical problems, the present invention proposes a neuromorphic circuit architecture based on memristors to solve the problems existing in the above prior art.

[0004] To achieve the above object, the present invention provides a neuromorphic circuit architecture based on memristors, including a plurality of operational amplifiers, a plurality of resistors, and a plurality of neuromorphic neural network circuit system units having a row-column structure; the neuromorphic neural network circuit system unit includes a voltage source, a memristor, and an NMOS transistor; the memristor has a threshold voltage and an initial resistance value.

[0005] The voltage source is used to provide an input for the neuromorphic circuit architecture.

[0006] The NMOS transistor is used to regulate the positive and negative of the synaptic weight represented by the memristor.

[0007] The last row of the neuromorphic neural network circuit system units of the neuromorphic circuit architecture is connected to an arithmetic unit and a resistor, and resistors are connected between the operational amplifiers.

[0008] Optionally, the number of rows and columns of the neuromorphic neural network circuit system units in the neuromorphic circuit architecture is the same as the size of the output layer of the simulated neural network.

[0009] Optionally, the brain-inspired neural network circuit system unit includes two voltage sources, a memristor, and two NMOS transistors;

[0010] The TE terminal of the memristor is connected to the output terminal of a single voltage source, the BE terminal of the memristor is respectively connected to the sources of the two NMOS transistors, and the gates of the two NMOS transistors are connected to the other voltage source.

[0011] Optionally, the drains of the two NMOS transistors are respectively connected to the drains of different NMOS transistors in the next row of the brain-inspired neural network circuit system unit, and the last row of the brain-inspired neural network circuit system unit is connected to an arithmetic unit and a resistor.

[0012] Optionally, the operational amplifier is divided into a positive weight amplifier and a negative weight amplifier. The inverting input terminal of the positive weight amplifier is connected to the drain of the NMOS transistor that controls the positive weight of the memristor, and the inverting input terminal of the negative weight amplifier is connected to the drain of the NMOS transistor that controls the negative weight of the memristor. The positive and negative power supply input terminals of the positive weight amplifier are respectively connected in phase to the positive pole of the voltage source and the negative pole of the other voltage source. The positive and negative power supply input terminals of the negative weight amplifier are respectively connected in phase to the positive pole of the voltage source and the negative pole of the other voltage source, and the two voltage sources are in a connection relationship.

[0013] Optionally, in the single column of the brain-inspired neural morphology circuit architecture, a resistor is connected between the output terminal of the positive weight amplifier and the inverting input terminal of the negative weight amplifier; a resistor is connected between the inverting input terminal of the positive weight amplifier and the output terminal of the positive weight amplifier; the non-inverting input terminal of the positive weight amplifier is connected to the non-inverting input terminal of the negative weight amplifier; a resistor is connected between the inverting input terminal of the negative weight amplifier and the output terminal of the negative weight amplifier.

[0014] Optionally, the NMOS transistors are all NMOS transistors with an internal resistance of 1 ohm.

[0015] Optionally, the memristors in each row of the brain-inspired neural network circuit system unit are connected to the same voltage source.

[0016] Optionally, a mathematical model of the memristor is obtained based on two key equations, and the key equations are as follows:

[0017] i = v·[R ON x + R OFF (1 - x)] -1

[0018] x = k·sin 2 (πx)·v m ·stp(|v| - v thr )

[0019] The first equation is the i-v relationship, and the second equation is the relationship between the time derivative of the state variable x and the memristor current i. Here, i is the memristor current, k is a constant depending on the physical parameters of the memristor nanostructure, m is an odd integer exponent, v is the input voltage, and R on is the on-resistance state of the memristor, and R off is the on-resistance state of the memristor.

[0020] Compared with the prior art, the present invention has the following advantages and technical effects:

[0021] The improved memristor model of the present invention better exhibits the electrical behavior of metal-oxide memristors. Compared with other traditional memristor-based memory and computing integrated architectures that rely on two memristors as a differential pair to simulate the positive and negative values of synaptic weights, the circuit architecture scale of the proposed memristor-based neural morphology circuit architecture is greatly reduced, the energy consumption of system operation is decreased, and the physical cost problem is significantly reduced, providing a new idea for memory and computing integrated chips in terms of energy conservation and area reduction. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings forming a part of this application are used to provide a further understanding of this application. The schematic embodiments and descriptions thereof of this application are used to explain this application and do not constitute an improper limitation to this application. In the drawings:

[0023] Figure 1 is the test I-V curve of a memristor model according to an embodiment of the present invention;

[0024] Figure 2 is the single-row system unit architecture diagram of a memristor-based neural morphology circuit according to an embodiment of the present invention;

[0025] Figure 3 is the overall architecture diagram of a memristor-based neural network circuit according to an embodiment of the present invention;

[0026] Figure 4 is the output electrical signal diagram of a memristor-based neural morphology circuit according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other. The following will refer to the drawings and combine the embodiments to detail this application.

[0028] It should be noted that the steps shown in the flowchart of the drawings can be executed in a computer system such as a set of computer-executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0029] Example 1

[0030] As Figures 1-4 shown, in this embodiment, a memristor-based neuromorphic circuit architecture is provided, including:

[0031] To better construct a brain-like neural network circuit model, the memristor model should have the following characteristics: simple operation, high working speed, good accuracy, and allow precise and detailed fine-tuning processes. The process of simulating a neural network with a memristor array circuit is mainly divided into two stages: weight input and matrix operation of forward propagation. Since both of these processes require electrical signal input, the memristor model needs to modulate its conductance according to its electrical characteristic curve to change its conductance during the weight input stage, and needs to act as a stable resistor device to perform matrix operations during the forward propagation stage. Therefore, a threshold voltage V thr and an initial resistance value m0 are added to the memristor model code. In this model, the threshold voltage is set to 3V. During the conductance modulation stage, an input voltage greater than 3V is used to modulate the conductance to the corresponding weight according to the electrical curve of the memristor. During the forward propagation process, the resistance value shown by the memristor model needs to stably show the conductance value modulated in the previous stage.

[0032] The mathematical model of the memristor model is based on the following two key equations.

[0033] i = v·[R ON x + R OFF (1 - x)] -1

[0034] x = k·sin 2 (πx)·v m ·stp(|v| - v thr )

[0035] The first relationship provides the i-v relationship, and the second relationship connects the time derivative of the state variable x and the memristor current i (or the memristor voltage v). Among them, k is a constant depending on the physical parameters of the memristor nanostructure, and m is an odd and integer exponent. In addition, an initial resistance value R init is set in the source code. This memristor model has a simple mathematical structure, and the applied Hann window function has nothing to do with the terminal state problem. The resistance of the memristor has two limit values, usually denoted as R on (on-resistance state) and R off (off-resistance state). If the input voltage v is lower than the activation threshold voltage V thr, which is the time derivative of the state variable. When x = dx / dt = 0, the memristor behaves as a simple linear resistor device with a constant conductance. This operating mode is used to complete the training process and adjust the function of the metal-oxide memristor in the neural network after establishing the synaptic weights.

[0036] Among them, the threshold voltage V thr is set to 3, the on-resistance R on is set to 10, the off-resistance R off is set to 16K, the constant k is set to 10, the exponent m is set to 3, and the initial resistance value m0 is set to 300.

[0037] The classification neural network in this embodiment is a binary classification neural network, and the classification content is vehicles and pedestrians. The constructed brain-inspired neural network circuit simulates the output layer of the binary classification neural network.

[0038] Based on the above content, the brain-inspired neural network circuit system unit for simulating the output layer of the binary classification neural network is constructed as follows:

[0039] Step 1: Use a voltage source as the input section of the neural network. The magnitude of the output voltage of the voltage source represents the input data in the neural network, and its numerical value is scaled down to the range of 0 to 3 by the input end of the neural network.

[0040] Step 2: The output end of the voltage source is directly connected in series with the TE end (i.e., the top electrode) of a single memristor. After the input voltage of the voltage source is input, the resistance value of the memristor represents the synaptic weight in the neural network. The input voltage of the voltage source is subjected to Ohm's law operation with the conductance value of the memristor, that is, a multiplication operation, and the signal output from the BE end (i.e., the bottom electrode) of the memristor is the output signal of the multiplication operation.

[0041] Step 3: The BE end of the memristor is connected in parallel with the source electrodes of two MOS transistors. The two MOS transistors in the circuit system unit are respectively used to control the positive and negative of the synaptic weight represented by the memristor. Only one MOS transistor's stack electrode is turned on during operation to control the positive and negative of the synaptic weight of the memristor.

[0042] Step 4: The two MOS transistors are respectively connected to the inverting input ends of two amplifiers. The amplifier connected to the drain of the MOS transistor that controls the memristor weight to be positive is the positive weight amplifier of the system unit, and the other is called the negative weight amplifier. Both of these amplifiers are respectively connected to a resistor with a resistance value of 1K ohm. After the output end of the positive weight amplifier is connected in series with a resistor with a resistance value of 100 ohm, it is connected to the inverting input end of the negative weight amplifier. The output of the negative inverting amplifier is the output of the neural network system unit.

[0043] A brain-inspired neural circuit architecture based on memristors in this embodiment is as Figure 3As shown, it includes several operational amplifiers, several resistors, and several brain-inspired neural network circuit system units with a row-column structure; the brain-inspired neural network circuit system units include a voltage source, a memristor, and an NMOS transistor;

[0044] The voltage source is used to provide input for the brain-inspired neuromorphic circuit architecture;

[0045] The NMOS transistor is used to regulate the positive and negative of the synaptic weight represented by the memristor;

[0046] The last row of brain-inspired neural network circuit system units in the brain-inspired neuromorphic circuit architecture is connected to an arithmetic unit and a resistor, and resistors are connected between the operational amplifiers.

[0047] Preferably, the number of rows and columns of the brain-inspired neural network circuit system units in the brain-inspired neuromorphic circuit architecture is the same as the size of the output layer of the simulated neural network.

[0048] Preferably, the brain-inspired neural network circuit system unit includes two voltage sources, a memristor, and two NMOS transistors;

[0049] The TE terminal of the memristor is connected to the output terminal of a single voltage source, the BE terminal of the memristor is respectively connected to the source electrodes of the two NMOS transistors, and the gate electrodes of the two NMOS transistors are connected to another voltage source.

[0050] Preferably, the drain electrodes of the two NMOS transistors are respectively connected to the drain electrodes of different NMOS transistors in the next row of brain-inspired neural network circuit system units, and the last row of brain-inspired neural network circuit system units is connected to an arithmetic unit and a resistor.

[0051] Specifically, for the brain-inspired neural network circuit system unit, see Figure 2 , the TE terminal of the memristor U1 is connected to the output terminal of the voltage source V1, the BE terminal of the memristor U1 is respectively connected to the source electrodes of the NMOS transistor M1 and the NMOS transistor M2, and the gate electrodes of the two NMOS transistors are connected to the voltage source V15. The memristors in each row of brain-inspired neural network circuit system units are connected to the same voltage source.

[0052] As Figure 3 shown, the drain electrodes of the NMOS transistor M1 and the NMOS transistor M2 are respectively connected to the drain electrodes of the NMOS transistor M5 and the NMOS transistor M6 in the next row of brain-inspired neural network circuit system units.

[0053] Preferably, the operational amplifier is divided into a positive weight amplifier and a negative weight amplifier. The inverting input terminal of the positive weight amplifier is connected to the drain of the NMOS transistor that controls the positive weight of the memristor, and the inverting input terminal of the negative weight amplifier is connected to the drain of the NMOS transistor that controls the negative weight of the memristor. The positive and negative power input terminals of the positive weight amplifier are connected in phase with the positive pole of the voltage source and the negative pole of another voltage source respectively, and the positive and negative power input terminals of the negative weight amplifier are connected in phase with the positive pole of the voltage source and the negative pole of another voltage source respectively. The two voltage sources are in a connected relationship.

[0054] Preferably, in the single column of the neuromorphic circuit architecture, a resistor is connected between the output terminal of the positive weight amplifier and the inverting input terminal of the negative weight amplifier; a resistor is connected between the inverting input terminal and the output terminal of the positive weight amplifier; the non-inverting input terminal of the positive weight amplifier is connected to the non-inverting input terminal of the negative weight amplifier; a resistor is connected between the inverting input terminal and the output terminal of the negative weight amplifier.

[0055] Specifically, the structure of the last row of the neuromorphic neural network circuit system unit, the operational amplifier and the resistor can be seen in Figure 3 ,

[0056] The operational amplifier is divided into a positive weight amplifier U25 and a negative weight amplifier U26. The inverting input terminal of the positive weight amplifier U25 is connected to the drain of the NMOS transistor M45 that controls the positive weight of the memristor, and the inverting input terminal of the negative weight amplifier U26 is connected to the drain of the NMOS transistor M46 that controls the negative weight of the memristor. The positive and negative power input terminals of the positive weight amplifier U25 are connected in phase with the positive pole of the voltage source V14 and the negative pole of another voltage source V38 respectively, and the positive and negative power input terminals of the negative weight amplifier U26 are connected in phase with the positive pole of the voltage source V14 and the negative pole of another voltage source V38 respectively. The two voltage sources are connected with positive and negative poles.

[0057] In the single column of the neuromorphic circuit architecture, a resistor R1 is connected between the output terminal of the positive weight amplifier U25 and the inverting input terminal of the negative weight amplifier U26; a resistor R2 is connected between the inverting input terminal and the output terminal of the positive weight amplifier U25; the non-inverting input terminal of the positive weight amplifier U25 is connected to the non-inverting input terminal of the negative weight amplifier U26; a resistor R3 is connected between the inverting input terminal and the output terminal of the negative weight amplifier.

[0058] Preferably, all NMOS transistors are NMOS transistors with an internal resistance of 1 ohm.

[0059] In this embodiment, the output layer of the binary classification neural network has a size of 500*2. Therefore, the circuit proposed by the present invention is built by the system units in the above steps one, two, and three according to the scale of 500 rows and 2 columns. The drains of the MOS transistors of the system units in each row are connected to the drains of the MOS transistors of the system units in the next row. At the drains of the two groups of MOS transistors in the last row, they are built according to the above step four. The outputs of its two negative weight amplifiers respectively represent the people and vehicles in the classification content, and the output values are the outputs of the brain-inspired circuit simulating the binary classification neural network for this category.

[0060] When the brain-inspired circuit architecture simulates the classification neural network, first use pictures of people and vehicles as the input of the classification neural network on a computer, and output the values of 500 input units and 1000 weights of the output layer of the neural network. Then, in the memristor modulation stage, according to the Figure 1 I-V curve of the memristor model as shown, use the sinusoidal voltage output by the voltage source to modulate the conductance of the memristor model, and modulate all the memristor conductances to the 1000 weights output from the neural network in advance. Then, in the forward propagation stage, first scale down the true values of the input units obtained by testing to the interval 0-3 in proportion, and use them as the output voltage values of 500 voltage sources in the circuit architecture in turn. In the circuit operation stage, the 500 voltage sources are simultaneously input into the memristor array to perform matrix addition operations relying on Ohm's law and Kirchhoff's law. Finally, electrical signals are obtained at the two output ports of the circuit architecture, as shown in Figure 4 shown. The person or vehicle represented by the output port with the larger of the two electrical signals is used as the classification result of the neuromorphic circuit architecture.

[0061] The above is only the preferred specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in this application should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. A brain-like neuromorphic circuit architecture based on memristors, characterized in that: It includes several operational amplifiers, several resistors, and several brain-like neural network circuit system units with row and column structures; the brain-like neural network circuit system units include a voltage source, a memristor, and an NMOS tube; the memristor has a threshold voltage and an initial resistance value; The voltage source is used to provide input for the brain-like neuromorphic circuit architecture; The NMOS tube is used to control the positive or negative value of the synaptic weight represented by the memristor; The last row of brain-like neural network circuit system units in the brain-like neuromorphic circuit architecture is connected with an operator and a resistor, and resistors are connected between operational amplifiers; The brain-like neural network circuit system unit includes two voltage sources, a memristor, and two NMOS tubes; The TE end of the memristor is connected to the output end of a single voltage source, the BE end of the memristor is connected to the sources of two NMOS tubes respectively, and the gates of the two NMOS tubes are connected to another voltage source; The drains of the two NMOS tubes are respectively connected to the drains of different NMOS tubes in the next row of brain-like neural network circuit system units, and the last row of brain-like neural network circuit system units is connected to an operator and a resistor; The operational amplifier is divided into a positive weight amplifier and a negative weight amplifier, the inverting input terminal of the positive weight amplifier is connected to the drain of the NMOS tube that controls the memristor weight to be positive, the inverting input terminal of the negative weight amplifier is connected to the drain of the NMOS tube that controls the memristor weight to be negative, the positive and negative power supply input terminals of the positive weight amplifier are respectively connected in phase with the positive pole of the voltage source and the negative pole of another voltage source, the positive and negative power supply input terminals of the negative weight amplifier are respectively connected in phase with the positive pole of the voltage source and the negative pole of another voltage source, and the two voltage sources are in a connection relationship; The memristors in each row of brain-like neural network circuit system units are connected to the same voltage source.

2. The memristor-based brain-like neuromorphic circuit architecture according to claim 1, characterized in that: The number of rows and columns of brain-like neural network circuit system units in the brain-like neuromorphic circuit architecture are the same as the size of the output layer of the simulated neural network.

3. The memristor-based brain-like neuromorphic circuit architecture according to claim 1, characterized in that: In a single row of the brain-like neuromorphic circuit architecture, a resistor is connected between the output of the positive weight amplifier and the inverting input of the negative weight amplifier; a resistor is connected between the inverting input of the positive weight amplifier and the output of the positive weight amplifier; the positive input of the positive weight amplifier is connected to the positive input of the negative weight amplifier; A resistor is connected between the inverting input terminal of the negative weight amplifier and the output terminal of the negative weight amplifier.

4. The memristor-based brain-like neuromorphic circuit architecture according to claim 1, characterized in that: The NMOS tubes are all NMOS tubes with an internal resistance of 1 ohm.

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