A RISC-V-based AI processor design method for small convolution kernel acceleration

Abstract

The application relates to the technical field of RISC-V instruction set processor, in particular to a RISC-V-based AI processor design method for small convolution kernel acceleration, the acceleration requirement of a 3*3 convolution kernel in a convolutional neural network (CNN), the open architecture RV32I of RISC-V is selected as a basis, the core architecture of the AI processor is defined, and the core architecture comprises a calculation unit, a register stack and a control unit, so that the processing of the small convolution kernel is optimized; the design and implementation of a vector arithmetic logic unit (VALU) and a convolution operation unit (CUU); the VALU has parallel computing capacity and can execute addition, subtraction and multiplication vector operations to support instruction set extension; the convolution operation unit CUU processes 3*3 convolution operation and contains special hardware logic to execute element-by-element multiplication and accumulation operation, so that the convolution calculation process is accelerated.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of RISC-V instruction set processors, in particular to a RISC-V-based AI processing machine design method for small convolution kernel acceleration. BACKGROUND

[0002] RISC-V is a brand new, simple and open free instruction set architecture, which was invented by Professor Krste Asanovic, Andrew Waterman and Yunsup Lee of the University of California, Berkeley, USA in 2010, and has received strong support from David Patterson, a computer architecture expert. As a new generation of reduced instruction set, RISC-V has a short development history, but it has obvious advantages in data transmission volume and transmission speed, as well as simplicity, running efficiency, cost and flexibility. RISC-V is highly expected in the AIoT era and has become one of the instruction architectures for AI processing machine design.

[0003] The processor design of RISC-V adopts Harvard structure as its memory architecture. Harvard structure is a computer memory design that separates program instruction storage and data storage. In Harvard structure, program memory and data memory are two independent memories with independent address space and data bus.

[0004] Although traditional CPUs can be used to perform various computing tasks, AI CPUs have higher efficiency and performance when processing AI-related computing tasks. In the AI field, CPUs are mainly responsible for some general computing tasks in data preprocessing, model training and inference processes. Since AI tasks usually need to process a large amount of data, AI CPUs usually have multiple cores and threads, which can handle multiple tasks simultaneously to improve overall performance. However, for more complex AI tasks such as training and inference of deep learning models, more powerful computing power is usually required. In this case, special hardware such as graphics processing units (GPUs), tensor processing units (TPUs) and neural network processors (NPUs) are usually used to accelerate AI computing. These processors have higher parallel processing capabilities and optimized AI algorithms, which can significantly improve the efficiency of AI task execution.

[0005] FPGA technology and related development platforms greatly reduce the cost of processing machine design, and can obtain specific experimental data in the research stage before tape-out. The application completes the design of the processing machine with acceleration effect for specific AI algorithms on the Cyclone III chip in combination with the Quartus II development environment, through the hardware description language and the circuit design from the gate level to the RTL level. SUMMARY

[0006] The application aims to provide a RISC-V-based AI processor design method for small convolution kernel acceleration, which significantly improves the operation efficiency when processing 3*3 convolution kernel through the design of special vector instructions and convolution operation instructions. The implementation of vector register stack and vector arithmetic logic unit (VALU) enables parallel computation of multiple data elements, reduces the number of instructions and data transmission delay, and speeds up the execution of convolution operation.

[0007] To achieve the above technical purposes and effects, the application is implemented by the following technical solutions:

[0008] A RISC-V-based AI processor design method for small convolution kernel acceleration, comprising the following steps:

[0009] S1: Determine the acceleration requirement of 3*3 convolution kernel in convolutional neural network (CNN), select RISC-V open architecture RV32I as the basis, define the core architecture of AI processor, including calculation unit, register stack and control unit, to optimize the processing of small convolution kernel.

[0010] S2: Design the vector register stack, the actual capacity includes 32 96-bit registers; the register stack ensures efficient data loading and storage during convolution operation through supporting fast parallel data access. When designing the register stack, its layout needs to be optimized to support the operation process of 3*3 convolution well, focusing on reducing data transmission delay and improving the parallelism and efficiency of overall calculation;

[0011] S3: Introduce vector instructions and convolution operation instructions to enhance the computing power of the processor; including vector addition, subtraction and multiplication operations, and a special instruction format is designed for convolution operation to ensure the simplicity of programming and the efficiency of execution. In addition, the new instructions are coded and designed to ensure their compatibility with existing RISC-V instructions, and the extension of the instruction set is realized by allocating specific opcode and function bits to the extended instructions.

[0012] S4: Design and implementation of vector arithmetic logic unit (VALU) and convolution operation unit (CUU); VALU has parallel computing capability and can perform addition, subtraction and multiplication vector operations to support instruction set extension; convolution operation unit CUU processes 3*3 convolution operation, which contains special hardware logic to perform element-wise multiplication and accumulation operation to speed up the convolution calculation process.

[0013] S5: Design a control unit for parsing and executing the extended instructions, ensuring that the control signals are accurately dispatched to operate VALU and CUU; ensuring that the data transmission between the register file, VALU, and CUU has sufficient bandwidth and low latency when executing the extended instructions, to avoid performance bottlenecks and improve overall efficiency.

[0014] S6: Perform functional simulation and verification of the new processor design through simulation tools, ensuring that each hardware unit and new instruction can correctly operate in various scenarios. Write comprehensive test cases to verify the correctness and performance of the new design, evaluate the speed and efficiency improvement when performing 3x3 convolution calculation, and find out the improvements compared to the traditional design and make corresponding optimization adjustments.

[0015] S7: In the optimization and iteration phase, further optimize the hardware design and instruction set based on simulation and verification results; to ensure high efficiency and reliability when processing deep learning and image processing tasks, and finally achieve the best performance.

[0016] Further, the step S2 specifically includes:

[0017] Design a 32-element 96-bit vector register file to store enough convolution kernel data and intermediate operation results. Each vector register is composed of multiple elements for parallel operation. According to the encoding format of RISC-V vector instructions, the size of the vector register is determined to be 32, and the register addresses from top to bottom are v1, v2, v3…v32. When processing three-dimensional vectors, the depth of each vector register is set to 3, storing the x, y, z direction vector components respectively; each register should support fast read-write operation to meet the parallel computing requirements. Optimize the register layout to support the data flow requirements of 3x3 convolution operation, facilitating parallel loading, calculation and storage of data.

[0018] Further, the step S3 specifically includes:

[0019] Extend the RISC-V instruction set, add vector addition, subtraction and multiplication (dot product) instructions to support common vector operations. Design special instructions for convolution operations to simplify programming complexity and accelerate execution efficiency.

[0020] Code design for new instructions to ensure compatibility with existing RISC-V instructions. Assign specific `opcode` and `func3` fields to each type of instruction.

[0021] Vector addition instruction: `opcode` is 1010111, `func3` is 000. Perform element-wise addition operation on corresponding components of two vectors, and store the result in the target register.

[0022] Vector subtraction instruction: opcode is 1010111, func3 is 001. Implements element-wise subtraction of two vectors, result stored in destination register.

[0023] Vector multiplication (dot product) instruction: opcode is 1010111, func3 is 100. Compute dot product of two vectors, output a scalar, suitable for deep learning and graphics processing;

[0024] Convolution operation instruction: opcode is 1010111, func3 is 010; compute convolution of two 3x3 arrays, output a scalar, suitable for deep learning and graphics processing.

[0025] Further, the step S4 specifically comprises:

[0026] Implement VALU to handle parallel vector operations. VALU performs specified addition, subtraction, multiplication operations by receiving operands of vector registers, and quickly returns results. Design the logic of the arithmetic unit to fully utilize hardware parallelism to speed up operations.

[0027] Design and implement convolution operation unit, including input data buffer and convolution kernel buffer, for storing and processing 3x3 convolution data. Ensure that CUU can efficiently perform element-wise multiplication and summation operations and send results to registers.

[0028] Further, the step S5 specifically comprises:

[0029] Design vector instruction control unit responsible for parsing and managing the execution of vector instructions, scheduling control signals to drive VALU and register heap operations, ensuring efficient parallel execution of vector instructions. Define control logic to coordinate the execution order and data flow of extended instructions. Optimize data path design to support high-bandwidth data transmission and minimize latency. Ensure smooth data flow between register heap, VALU and CUU, without bottlenecks.

[0030] Convolution unit has convolution kernel buffer and input data buffer, dedicated to store matrices to be processed and convolution kernel weights. Through instruction decoding, determine data flow to VALU or dot product operator. Convolution operation unit parallel processing allows multiple data windows to be processed in parallel, element-wise multiplication and summation with convolution kernel, and the final result is stored in a dedicated buffer.

[0031] Further, the step S6 specifically comprises:

[0032] The Quartus II simulation tool is used to verify the functionality by observing the output waveforms and expected results. The correctness of vector instructions and convolution operations is emphasized. Extensive test cases are written to ensure that the new instructions and hardware units perform consistently in various scenarios. The performance of the AI processor is compared with traditional RISC-V architectures to evaluate the acceleration effect when performing 3x3 convolution kernel calculations. Performance bottlenecks are identified through test results, and corresponding adjustments and optimizations are made.

[0033] Further, the step S7 specifically comprises:

[0034] Based on simulation and test feedback, the hardware design and instruction set are adjusted to further improve computing performance and efficiency. Through multiple iterations, the AI processor ensures high performance and reliability in deep learning and image processing applications.

[0035] The beneficial effects of the present application are:

[0036] The present application enhances the computing power of the processor when performing convolution operations by introducing special vector instructions and convolution operation instructions. Traditional CPUs usually need to complete multiplication and accumulation operations through multiple loops and multiple instructions when performing convolution operations in convolutional neural networks (CNN). Its efficiency is limited by instruction set redundancy and data transmission delay. The technical solution of the present application designs a special vector register stack and a vector arithmetic logic unit (VALU) to achieve high-efficiency parallel computing capability, which can process multiple data elements simultaneously. Vector instructions such as addition, subtraction and dot product can be executed directly at the hardware level, reducing the number of instructions and improving execution speed and overall operation efficiency. Using vector registers, convolution operation data can be loaded, stored and calculated in parallel, significantly reducing data transmission delay and execution time.

[0037] The present application realizes efficient use of resources through optimization of hardware design. The design of the vector register stack supports fast parallel data access and operation, effectively reducing register read-write delay and improving parallelism and efficiency of computation. In convolution operations, specific hardware logic (convolution operation unit CUU) can handle 3x3 convolution operations, avoiding repeated calls to general-purpose computing units and power consumption. In addition, the convolution unit is connected to the register stack through a high-bandwidth internal bus to ensure smooth data transmission and reduce memory access frequency, thereby further reducing system power consumption. This optimized design is particularly beneficial for power-constrained embedded devices, making the processor suitable for application in edge computing and AIoT devices.

[0038] In deep learning tasks, especially in image recognition, small convolution kernels (such as 3x3) improve the efficiency of model training due to their small parameter quantity. Smaller parameter quantity means lower model complexity, easier convergence during training, and less risk of overfitting. The present invention designs a special instruction for 3x3 convolution kernels, significantly accelerating the execution of this convolution kernel while maintaining high non-linear expression capability, enabling the extraction of more complex features. In addition, through the stacking of multiple layers of small convolution kernels, local and global features are extracted layer by layer, and the generalization ability of the model is also improved. This enhanced feature expression capability is derived from more efficient hardware implementation, so that the speed improvement of convolution operation directly translates into better feature extraction effect.

[0039] The present invention fully considers the compatibility with the existing RISC-V instruction set when designing new instructions, by allocating specific opcode and func fields for extended instructions, ensuring seamless integration of new and old instructions. This compatibility not only protects existing software assets, but also facilitates the integration and promotion of new instructions. At the same time, the openness and modular design of the RISC-V instruction set make future instruction expansion and hardware improvement more flexible and cost-effective. During the functional simulation and testing process of the processor, implementation and verification on the FPGA platform further reduce design risks and development costs, laying the foundation for large-scale deployment of new technologies in diversified AI applications.

[0040] Of course, implementing any product of the present invention does not necessarily require achieving all the advantages described above at the same time. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings needed to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention, and other drawings can also be obtained by those skilled in the art without creative labor.

[0042] Figure 1 RISC-V structure schematic diagram before expansion;

[0043] Figure 2 (a) is a vector register stack schematic diagram; (b) is a vector register schematic diagram;

[0044] Figure 3 RISC-V structure schematic diagram before expansion;

[0045] Figure 4 RISC-V-based AI processor schematic diagram for small convolution kernel acceleration;

[0046] Figure 5 RISC-V-based computer RTL circuit diagram for accelerating AI;

[0047] Figure 6 For RISC-V-based accelerated AI processors;

[0048] Figure 7 For simulation results, show the schematic diagram. DETAILED DESCRIPTION

[0049] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0050] Embodiment 1

[0051] The design method of the RISC-V-based AI processor for small convolution kernel acceleration described in this embodiment includes the following steps:

[0052] S1: Determine the acceleration requirement of 3x3 convolution kernel in convolutional neural network (CNN), select the open architecture RV32I of RISC-V as the basis, define the core architecture of the AI processor, including the calculation unit, the register file and the control unit, to optimize the processing of small convolution kernel.

[0053] S2: Design the vector register file, the actual capacity includes 32 96-bit registers; the register file ensures that data can be loaded and stored in an efficient way during the convolution operation process by supporting fast parallel data access. When designing the register file, its layout needs to be optimized to support the operation process of 3x3 convolution well, focusing on reducing data transmission delay and improving the parallelism and efficiency of overall calculation;

[0054] S3: Introduce vector instructions and convolution operation instructions to enhance the computing power of the processor; including vector addition, subtraction and multiplication operations, and a special instruction format is designed for convolution operation to ensure the simplicity of programming and the efficiency of execution. In addition, the encoding design of these new instructions ensures the compatibility with the existing RISC-V instructions, and the expansion of the instruction set is realized by allocating specific opcode and function bits to the extended instructions.

[0055] S4: Design and implementation of vector arithmetic logic unit (VALU) and convolution operation unit (CUU); VALU has parallel computing capability and can perform addition, subtraction and multiplication vector operations to support instruction set extension; convolution operation unit CUU processes 3x3 convolution operation, which contains special hardware logic to perform element-wise multiplication and accumulation operation, thereby accelerating the convolution calculation process.

[0056] S5: Design a control unit for parsing and executing the extended instructions, ensuring that the control signals accurately schedule the operations of VALU and CUU; and ensuring that the data transfer between the register file, VALU, and CUU has sufficient bandwidth and low latency when executing the extended instructions, to avoid performance bottlenecks and improve overall efficiency.

[0057] S6: Perform functional simulation and verification of the new processor design using simulation tools, to ensure that each hardware unit and the new instructions can correctly operate in various scenarios. Write comprehensive test cases to verify the correctness and performance of the new design, evaluate the speed and efficiency improvement when performing 3x3 convolution calculations, and find improvements compared to traditional designs and make corresponding optimization adjustments.

[0058] S7: In the optimization and iteration phase, further optimize the hardware design and instruction set based on simulation and verification results; to ensure high efficiency and reliability when processing deep learning and image processing tasks, and finally achieve the best performance

[0059] In this embodiment, the step S2 specifically comprises:

[0060] A 32-element 96-bit vector register file is designed to store enough convolution kernel data and intermediate operation results. Each vector register is composed of multiple elements for parallel operation. According to the encoding format of RISC-V vector instructions, the size of the vector register is determined to be 32, and the register addresses from top to bottom are v1, v2, v3…v32. When processing three-dimensional vectors, the depth of each vector register is set to 3, storing the x, y, z direction vector components respectively; each register should support fast read-write operation to meet the parallel computing requirements. The register layout is optimized to support the data flow requirements of 3x3 convolution operations, facilitating parallel loading, calculation, and storage of data. The specific register layout is shown in Figure 3 .

[0061] In this embodiment, the step S3 specifically comprises:

[0062] The RISC-V instruction set is extended to add vector addition, subtraction, and multiplication (dot product) instructions to support common vector operations. Special instructions are designed for convolution operations to simplify programming complexity and accelerate execution efficiency.

[0063] The new instructions are coded and designed to ensure compatibility with existing RISC-V instructions. Each type of instruction is assigned a specific `opcode` and `func3` field.

[0064] Vector addition instruction: `opcode` is 1010111 and `func3` is 000. Perform element-wise addition operation on corresponding components of two vectors, and store the result in the target register.

[0065] Vector subtraction instructions: `opcode` is 1010111, `func3` is 001. This performs element-wise subtraction of two vectors, storing the result in the destination register.

[0066] Vector multiplication (dot product) instructions: `opcode` is 1010111, `func3` is 100. Calculates the dot product of two vectors and outputs a scalar, suitable for deep learning and graphics processing.

[0067] Convolution operation instructions: `opcode` is 1010111, `func3` is 010; calculates the convolution of two 3×3 arrays and outputs a scalar, suitable for deep learning and graphics processing.

[0068] In this embodiment, step S4 specifically includes:

[0069] Implement a VALU to handle parallel vector operations. The VALU receives operands from the vector register to perform specified addition, subtraction, or multiplication operations and quickly returns the results. Design the logic of the arithmetic unit to fully utilize hardware parallelism and accelerate computation.

[0070] Design and implement a convolution operation unit, including an input data buffer and a convolution kernel buffer, for storing and processing 3×3 convolution data. Ensure that the CUU can efficiently perform element-wise multiplication and summation operations and send the results to registers.

[0071] In this embodiment, step S5 specifically includes:

[0072] The vector instruction control unit (CUU) is designed to parse and manage the execution of vector instructions, scheduling control signals to drive VALU and register file operations, ensuring efficient parallel execution of vector instructions. Control logic is defined to coordinate the execution order of extended instructions and data flow. The data path design is optimized to support high-bandwidth data transmission and minimize latency. Smooth data flow between the register file, VALU, and CUU is ensured without bottlenecks.

[0073] The convolution unit has a kernel buffer and an input data buffer, dedicated to storing the matrix to be processed and the kernel weights. Instruction decoding determines whether the data flows to the VALU or dot product operator. Parallel processing of the convolution unit allows multiple data windows to be processed in parallel, performing element-wise multiplication and summation with the convolution kernel, with the final result stored in a dedicated buffer.

[0074] In this embodiment, step S6 specifically includes:

[0075] The Quartus II simulation tool is used to verify the functionality by observing the output waveforms and expected results. The correctness of vector instructions and convolution operations is emphasized. Extensive test cases are written to ensure that the new instructions and hardware units perform consistently in various scenarios. The performance of the AI processor is compared with traditional RISC-V architectures to evaluate the acceleration effect when executing 3x3 convolution kernel calculations. Performance bottlenecks are identified through test results, and corresponding adjustments and optimizations are made.

[0076] In this embodiment, the step S7 specifically comprises:

[0077] Based on the simulation and test feedback, the hardware design and instruction set are adjusted to further improve the computing performance and efficiency. Through multiple iterations, the AI processor ensures high performance and reliability in deep learning and image processing applications.

[0078] Embodiment 2

[0079] AI processor design for small convolution kernel acceleration

[0080] Instruction extension based on RV32I basic instruction architecture

[0081] Among common artificial intelligence algorithms, the convolutional neural network (CNN) is widely used. Due to its wide range of applications, it is widely used in image recognition and other deep learning scenarios. At the same time, this algorithm also has the problem of huge computing power consumption that many artificial intelligence algorithms have. There can be multiple convolution layers in the training process, and each convolution layer needs to use convolution kernels for convolution operation. Taking a 3x3 convolution kernel as an example, the calculation formula is:

[0082]

[0083] As can be seen from the above formula, the convolution operation mainly includes vector dot product operation composed of multiplication and addition. Taking a 3x3 convolution kernel as an example, 9 multiplication and 8 addition operations are needed to obtain one component result of the output matrix. Therefore, the convolutional neural network algorithm implemented using any high-level language needs to use vector multiplication and vector addition operations frequently. This inevitably poses a great challenge to the performance of the processor, so GPUs are often needed to assist ordinary CPUs in the running environment. Designing an AI processor to provide instruction-level support for specific operations will greatly alleviate the pressure on CPUs from artificial intelligence algorithms. On the basis of completing the basic instruction set, the CPU needs to extend vector instructions and convolution operation instructions to support Formula 1, which can fundamentally speed up the execution speed of the convolutional neural network algorithm.

[0084] The RV32I basic instruction architecture includes six common 32-bit instructions: R, I, S, B, U, and J. Based on the acceleration requirements of convolution kernels, combined with the widely used RISC-V instruction set, a basic processing machine structure is constructed, as shown in the schematic diagram:

[0085] Small convolution kernel selection

[0086] Common convolution kernel sizes include 1x1, 3x3, 5x5, and 7x7. Sometimes, 11x11 is also seen. If we extract features in the convolution layer, we choose the most commonly used 3x3 convolution kernel as the target for AI processor acceleration, and the reasons are as follows:

[0087] (1) Fewer parameters: Two 3x3 convolution kernels and one 5x5 convolution kernel have the same receptive field. Three 3x3 convolution kernels and one 7x7 convolution kernel have the same receptive field (the receptive field is the number of features that can be extracted from the surrounding neighbors). Assuming that the input and output channels are C, the required parameters for a 7x7 convolution kernel are calculated as follows:

[0088] 7x7xCxC = 49C 2 (2)

[0089] The required parameters for a 3x3 convolution kernel are calculated as follows:

[0090] 3x3xCxC + 3x3xCxC + 3x3xCxC = 27C 2 (3)

[0091] As can be seen, with the same receptive field, three 3x3 convolutions require much fewer parameters than one 7x7 convolution, which undoubtedly reduces the complexity of the model and speeds up the training. When training a model, the smaller the number of parameters, the easier it is for the model to converge and the less likely it is to overfit. Therefore, a 3x3 convolution kernel can effectively reduce the number of model parameters and improve the training efficiency and generalization ability of the model. Moreover, although the receptive fields are the same, the nonlinearity of the 3x3 convolution is higher and can represent more complex functions.

[0092] (2) Better feature extraction capability: A 3x3 convolution kernel has better feature extraction capability than a 5x5 convolution kernel. In a convolutional neural network, a smaller convolution kernel can extract more fine-grained features. For example, in an image recognition task, a 3x3 convolution kernel can capture information from 8 pixel points around a pixel point, while a 5x5 convolution kernel can only capture information from 16 pixel points. Therefore, using a 3x3 convolution kernel can better capture local features in the input data, thereby improving the accuracy of the model.

[0093] (3) It can improve the computational efficiency. In the convolutional neural network, the convolution operation is one of the most computationally intensive operations. Using a 3x3 convolution kernel can improve the computational efficiency, thereby speeding up the training and inference of the model. For example, when training the model using GPU, using a 3x3 convolution kernel can reduce the amount of data transmission, thereby improving the computational efficiency.

[0094] (4) Better model generalization ability. In the convolutional neural network, the generalization ability of the model refers to the adaptability of the model to unknown data. The 3x3 convolution kernel can gradually extract the local features and global features in the image through the multi-layer convolution superposition method.

[0095] Implementation of small convolution kernel acceleration processor

[0096] I. Design and implementation of vector register stack

[0097] With 3x3 convolution kernel as the acceleration design target, it is necessary to design the instruction of performing dot product and the corresponding special register and operator. Vector register will be a necessary choice. In view of the demand of providing 3x3 matrix at the same time, a register stack capable of accommodating large-scale vectors is designed, as shown in Figure 2 , and the circuit design schematic diagram is as shown in Figure 3 . The actual capacity of the vector register stack is 32 vector registers, and each vector register can store 96 bits.

[0098] II. Vector extension instruction set

[0099] Neural network convolution operation mainly involves the operation of vector and matrix data. In addition to designing independent operation instructions, the processor also designs and supports part of vector extension operations, mainly including three vector instructions of addition, subtraction and multiplication. The specific techniques include:

[0100] 1. Vector register, used for storing and operating vector data. Each vector register is composed of multiple elements for parallel operation. According to the coding format of RISC-V vector instruction, the capacity of vector register is determined to be 32, and the register addresses from top to bottom are v1, v2, v3…v32. When processing three-dimensional vectors, the depth of each vector register is set to 3, which stores the x, y and z direction vector components respectively.

[0101] 2. Vector arithmetic logic unit, which can perform vector operations including vector addition, vector subtraction and vector dot product; VALU supports parallel computing, that is, it can process multiple elements in the vector at the same time, improving the computing speed and efficiency. VALU receives vector operands from vector registers, performs the operations specified by the instructions, and returns the results to the vector registers.

[0102] 3. Vector instruction control unit, used for parsing and managing the execution of vector instructions; specially processing vector instructions, generating and scheduling control signals to drive the operation of VALU and vector register file; ensuring efficient execution of vector instructions in parallel mode.

[0103] The vector instruction format is designed as follows:

[0104]

[0105] The specific encoding is as follows:

[0106] 1. 32-bit vector addition instruction:

[0107] The vector addition instruction is used for element-wise addition of each component of two vectors, that is, vector registers A and B store vectors (A1, A2, A3) and (B1, B2, B3) respectively, then the vector addition instruction calculates (A1+B1, A2+B2, A3+B3) and stores the result in the target vector register; the instruction supports parallel processing of data to improve calculation speed. The instruction format is designed as follows:

[0108]

[0109] 2. 32-bit vector subtraction instruction:

[0110] The vector subtraction instruction is used for element-wise subtraction of each component of two vectors, that is, vector registers A and B store vectors (A1, A2, A3) and (B1, B2, B3) respectively, then the vector subtraction instruction calculates (A1-B1, A2-B2, A3-B3) and stores the result in the target vector register; the instruction also supports parallel processing of data to improve calculation efficiency. The instruction format is designed as follows:

[0111]

[0112] 3. 32-bit vector multiplication instruction:

[0113] The vector multiplication here refers to the dot product or scalar product of vectors. The vector dot product operation instruction is used to calculate the dot product of two vectors. The dot product operation multiplies the corresponding components of two vectors and sums them up, resulting in a scalar value. That is, vector registers A and B store vectors (A1, A2, A3) and (B1, B2, B3) respectively, then the vector dot product instruction calculates A1*B1+A2*B2+A3*B3 and stores the result in a scalar register; used for machine learning and graphics processing. The instruction format is designed as follows:

[0114]

[0115] From the above machine instruction format, it can be seen that the OP code 01010111 is all related to vector operation instructions, and the specific instruction decoding control is determined by the func3 field. (Note: the all-0 part is a three-operand, which can be replaced by a register address according to the needs of the instruction in actual application.)

[0116] The func3 code is 000 for vector addition;

[0117] The func3 code is 001 for vector subtraction;

[0118] The func3 code is 100 for vector multiplication;

[0119] The vector operation unit VALU, the relationship with the instruction bus, the data bus and other components can be seen from Figure 4 .

[0120] Three, the design and implementation of dot product instruction

[0121] The 3x3 convolution kernel and the convolution data involved in the design of the processor are input in the form of an array corresponding to the matrix. At the same time, in order to avoid interference with other instructions and to improve the operation rate to a certain extent, a large enough buffer is created to store the results of the convolution operation. In order to reduce redundancy, the vector register stack is shared with VALU, and through instruction decoding and other control methods, it is determined whether the current data is sent to VALU or the dot product operation unit. Since the convolution instruction is independent of other instructions, but in order to integrate with the whole machine, it is coded by borrowing the encoding format of the vector instruction. The 32-bit instruction is as follows.

[0122]

[0123] The convolution operation unit is used for convolution operation in deep learning; it includes a convolution kernel buffer (for storing convolution kernel weights), an input data buffer (for storing data to be processed), and an operation logic for performing convolution operations; the convolution operation unit can process multiple data windows in parallel, multiply each element with the convolution kernel, and sum the results, which are stored in the buffer. The unit is designed to accelerate the forward propagation calculation in convolutional neural networks.

[0124] Four, the implementation and testing of the AI processing machine

[0125] 1. Implementation of the processor

[0126] By combining the basic RV32I instruction set, the processor designed for convolution kernel acceleration can also process normal programs and scalar operations. The processor containing multiple operation units is designed. The processor can complete a 3x3 convolution kernel calculation with one machine instruction, achieving the goal of maximizing the acceleration of small-scale convolution operations.

[0127] For the convolution kernel greater than 3*3, since the processing machine supports vector instructions, the convolution operation can be translated into vector multiplication and vector addition instructions at the machine instruction level through compilation to achieve the purpose of maximum acceleration. Compared with the traditional CPU, the loop multiplication and addition are performed by each component, which can also achieve the purpose of greatly speeding up.

[0128] The overall design of the AI processing machine is shown in Figure 4 , and the test program can be executed.

[0129] The instruction memory, data memory and AI processing machine are integrated to complete the overall design, and the RTL diagram is shown in Figure 5 .

[0130] The detailed implementation circuit diagram of the processing machine is shown in the accompanying Figure 6 ;

[0131] Embodiment 3

[0132] Test method

[0133] The simulation tool of the quartus ii platform is used for simulation, and the correctness of the results is judged by observing the output results of the waveform diagram and combining the expected results.

[0134] The simulation results are shown, and it can be seen from the figure that when the funct is the corresponding instruction function code, the corresponding instruction operation is executed, such as Figure 7 .

[0135] The calculation results of the vector instruction, the elements of the two vectors are (9, 8, 7), (1, 2, 3), and the convolution kernel weight is a 3*3 matrix of all 1s. The data to be convolved is a 3*3 matrix of all 1s:

[0136] · Vector addition: when the function code funct is [0], the vector addition operation is executed, and the elements of the two vectors are added to output a new vector (result_x, result_y, result_z) = (10, 10, 10).

[0137] · Vector subtraction: when the function code funct is [1], the vector subtraction operation is executed, and the elements of the two vectors are subtracted to output a new vector (result_x, result_y, result_z) = (8, 6, 4).

[0138] · Vector multiplication (dot product): when the function code funct is [4], the vector dot product operation is executed, and the elements of the two vectors are multiplied and added to output a scalar data reslut = 2E (hexadecimal representation).

[0139] • Convolution operation: when the function code funct is [2], the convolution operation is performed, and two matrices are operated according to the convolution formula, and a scalar data conv_result = 9 is output.

[0140] (2) Acceleration effect comparison

[0141] Since the convolution operation is generally decomposed into multiplication and addition during the compilation phase, taking the vector addition with the worst acceleration ratio and the convolution operation with the largest acceleration ratio as examples, the program code amount running on the acceleration AI processor and the conventional RISC-V architecture processor is compared.

[0142]

[0143]

[0144] If the RISC-V vector addition instruction is used, only one instruction is needed, which is "vadd vd, vs2, vs1". The vector in the vs1 register is added to the vector in the vs2 register, and the result is sent to the vd register. Since RISC-V supports parallel operation of data, the three elements of the vector do not need to be input in a loop and traversed element by element for addition as in assembly. In this regard, the RISC-V vector instruction saves operation time and improves operation efficiency. At the same time, it also saves hardware resources and effectively avoids resource waste.

[0145] The preferred embodiments of the application disclosed above are only used to help explain the application. The preferred embodiments do not describe all the details and do not limit the application to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of the specification. The specification selects and describes these embodiments in order to better explain the principles and practical applications of the application, so that those skilled in the art can well understand and utilize the application. The application is limited only by the claims and their full scope and equivalents.

Claims

1. A RISC-V-based AI processor design method for accelerating small convolutional kernels, characterized in that, Includes the following steps: S1: Determine the acceleration requirements for 3×3 convolutional kernels in convolutional neural networks, select the RISC-V open architecture RV32I as the basis, and define the core architecture of the AI ​​processor, including computing units, register files and control units, to optimize the processing of small convolutional kernels. S2: Design a vector register file with an actual capacity of 32 96-bit registers. The register file ensures efficient loading and storage of data during convolution operations by supporting fast parallel data access. When designing the register file, its layout needs to be optimized to support the 3×3 convolution operation process well. The focus is on reducing data transmission latency and improving the overall parallelism and efficiency of the computation. S3: Introduces vector instructions and convolution operation instructions to enhance the processor's computing power; includes vector addition, subtraction and multiplication operations, and designs a special instruction format for convolution operations to ensure programming simplicity and execution efficiency; in addition, the encoding design of these new instructions ensures their compatibility with existing RISC-V instructions, and the instruction set is expanded by allocating specific opcodes and function bits to the extended instructions. S4: Design and implementation of the vector arithmetic logic unit (VALU) and convolution operation unit (CUU); the VALU has parallel computing capabilities and can perform addition, subtraction, and multiplication vector operations to support instruction set expansion; the CUU processes 3×3 convolution operations and includes dedicated hardware logic to perform element-wise multiplication and accumulation operations, thereby accelerating the convolution calculation process. S5: Designed to parse and execute extended instructions, ensuring that control signals accurately schedule the operation of VALU and CUU; ensuring that data transfer between register file, VALU and CUU has sufficient bandwidth and low latency when executing extended instructions, in order to avoid performance bottlenecks and improve overall efficiency; S6: Perform functional simulation and verification of the new processor design using simulation tools to ensure that each hardware unit and new instruction can run correctly in various scenarios; write comprehensive test cases to verify the correctness and performance of the new design, evaluate its speed and efficiency improvement when performing 3×3 convolution calculations, identify improvements compared to traditional designs, and make corresponding optimizations and adjustments. S7: During the optimization and iteration phase, the hardware design and instruction set are further optimized based on the simulation and verification results; To ensure efficiency and reliability when handling deep learning and image processing tasks, ultimately achieving optimal performance.

2. The RISC-V-based AI processor design method for acceleration with small convolutional kernels as described in claim 1, characterized in that: Step S2 specifically includes: Design a file containing 32 96-bit vector registers to support the storage of sufficient convolution kernel data and intermediate operation results. Each vector register consists of multiple elements for parallel operation. The capacity of the vector registers is determined to be 32 based on the encoding format of RISC-V vector instructions, with register addresses from top to bottom as v1, v2, v3…v32. When processing three-dimensional vectors, the depth of each vector register is set to 3, storing the vector components in the x, y, and z directions respectively. Each register should support fast read and write operations to meet the requirements of parallel computing. Optimize the register layout to support the data flow requirements of 3×3 convolution operations, facilitating parallel loading, computation, and storage of data.

3. The RISC-V-based AI processor design method for accelerating small convolutional kernels as described in claim 1, characterized in that: Step S3 specifically includes: The RISC-V instruction set is extended to include vector addition, subtraction, and multiplication instructions to support common vector operations; special instructions are designed for convolution operations to simplify programming complexity and accelerate execution efficiency. The new instructions are coded to ensure compatibility with existing RISC-V instructions; specific `opcode` and `func3` fields are assigned to each type of instruction; Vector addition instruction: `opcode` is 1010111, `func3` is 000; performs element-wise addition on corresponding components of two vectors, and stores the result in the destination register; Vector subtraction instruction: `opcode` is 1010111, `func3` is 001; performs element-wise subtraction of two vectors, and stores the result in the destination register; Vector multiplication instructions: `opcode` is 1010111, `func3` is 100; calculates the dot product of two vectors and outputs a scalar, suitable for deep learning and graphics processing; Convolution operation instructions: `opcode` is 1010111, `func3` is 010; calculates the convolution of two 3×3 arrays and outputs a scalar, suitable for deep learning and graphics processing.

4. The RISC-V-based AI processor design method for acceleration with small convolutional kernels as described in claim 1, characterized in that: Step S4 specifically includes: Implement VALUs to handle parallel vector operations; VALUs execute specified addition, subtraction, and multiplication operations by receiving operands from vector registers and quickly return the results; design the logic of the arithmetic unit to fully utilize hardware parallelism and accelerate computation; Design and implement a convolution operation unit, including an input data buffer and a convolution kernel buffer, for storing and processing 3×3 convolution data; ensure that the CUU can efficiently perform element-wise multiplication and summation operations and send the results to registers.

5. The RISC-V-based AI processor design method for acceleration with small convolutional kernels as described in claim 1, characterized in that: Step S5 specifically includes: The vector instruction control unit is designed to parse and manage the execution of vector instructions, schedule control signals to drive VALU and register file operations, and ensure that vector instructions can be executed efficiently in parallel; the control logic is defined to coordinate the execution order of extended instructions and data flow; the data path design is optimized to support high-bandwidth data transmission and minimize waiting time; and the smooth data flow between the register file, VALU, and CUU is ensured without bottlenecks. The convolution unit has a kernel buffer and an input data buffer, which are dedicated to storing the matrix to be processed and the kernel weights; the data flow to the VALU or dot product operator is determined by instruction decoding; the parallel processing of the convolution unit allows multiple data windows to be processed in parallel, performing element-wise multiplication and summation with the convolution kernel, and the final result is stored in a dedicated buffer.

6. The RISC-V-based AI processor design method for accelerating small convolutional kernels as described in claim 1, characterized in that: Step S6 specifically includes: Using the Quartus II simulation tool, functional verification was performed by observing the output waveforms and expected results; the correctness of vector instructions and convolution operations was verified with a focus on the verification; extensive test cases were written to ensure that the new instructions and hardware units performed consistently in various scenarios; the computing performance of the AI ​​processor was compared with that of the traditional RISC-V architecture to evaluate its acceleration effect when performing 3×3 convolution kernel calculations; performance bottlenecks were identified through test results and corresponding adjustments and optimizations were made.

7. The RISC-V-based AI processor design method for acceleration with small convolutional kernels as described in claim 1, characterized in that: Step S7 specifically includes: Based on simulation and testing feedback, the hardware design and instruction set were adjusted to further improve computing performance and efficiency; through multiple iterations, the high efficiency and reliability of the AI ​​processor in deep learning and image processing applications were ensured.

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