Display device

Abstract

A display device includes a display panel including pixels. The pixel includes: a light emitting element; a first capacitor connected between the first node and a voltage line; a first transistor connected to the first node, a voltage line, and a second node; the second transistor is connected between the first node and a third node, and the second transistor is used for receiving a first scanning signal; the third transistor is connected between the second node and a third node, and the third transistor is used for receiving a second scanning signal; a second capacitor connected between the third node and the fourth node; the fourth transistor is connected between the fourth node and the data line, and the fourth transistor is used for receiving a third scanning signal; and a fifth transistor connected between the second node and the light emitting element, and configured to receive the first emission control signal.

Description

Technical Field

[0001] Embodiments of the present disclosure described herein relate to a display device, and more particularly, to a display device having uniform light emitting characteristics. Background Art

[0002] Among the display devices, a light emitting display device displays an image by using a light emitting diode that generates light through recombination of electrons and holes. The light emitting display device is driven with low power while providing a fast response speed.

[0003] The light-emitting display device includes pixels connected to data lines and scan lines. Each of the pixels generally includes a light-emitting diode and a circuit unit for controlling the amount of current flowing to the light-emitting diode. In response to a data signal, the circuit unit can control the amount of current flowing from a terminal to which a first driving voltage is applied via the light-emitting diode to a terminal to which a second driving voltage is applied. In this case, light of a predetermined brightness is generated to correspond to the amount of current flowing through the light-emitting diode. Summary of the invention

[0004] Embodiments of the present disclosure provide a display device having improved display quality by employing pixels having uniform light emitting characteristics even when an operating frequency varies.

[0005] According to an embodiment, a display device includes a display panel, and the display panel includes a pixel. The pixel includes: a light-emitting element; a first capacitor connected between a first node and a voltage line; a first transistor connected to the first node, the voltage line, and a second node; a second transistor connected between the first node and a third node, and the second transistor is used to receive a first scan signal; a third transistor connected between the second node and the third node, and the third transistor is used to receive a second scan signal; a second capacitor connected between the third node and a fourth node; a fourth transistor connected between the fourth node and a data line, and the fourth transistor is used to receive a third scan signal; and a fifth transistor connected between the second node and the light-emitting element, and the fifth transistor is used to receive a first emission control signal.

[0006] According to an embodiment, a display device includes a display panel, and the display panel includes a pixel. The pixel includes: a light emitting element; a first capacitor connected between a first node and a voltage line; a first transistor connected to the first node, the voltage line, and a second node; a second transistor connected between the first node and a third node and used to receive a first scan signal; a third transistor connected between the second node and the third node and used to receive a second scan signal; a second capacitor connected between the third node and a fourth node; a fourth transistor connected between the fourth node and a data line and used to receive a third scan signal; and a shift compensation transistor connected between the second node and a reference voltage line and used to receive a shift scan signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0008] Figure 1 is a block diagram of a display device according to an embodiment of the present disclosure.

[0009] Figure 2 is a circuit diagram of a pixel according to an embodiment of the present disclosure.

[0010] Figure 3A and Figure 3B is a timing diagram for describing the operation of a display device according to an embodiment of the present disclosure.

[0011] Figure 4A and Figure 4B is a diagram for describing an operation of a pixel during a first period according to an embodiment of the present disclosure.

[0012] Figure 5A and Figure 5B is a diagram for describing an operation of a pixel during a second period according to an embodiment of the present disclosure.

[0013] Fig. 6A and Figure 6B is a diagram for describing an operation of a pixel during a third period according to an embodiment of the present disclosure.

[0014] Figure 6C is a diagram for describing a current deviation compensation process according to an embodiment of the present disclosure.

[0015] Fig. 7A and Figure 7B is a diagram for describing an operation of a pixel during a fourth period according to an embodiment of the present disclosure.

[0016] Fig. 8A and Figure 8Bis a diagram for describing an operation of a pixel during a fifth period according to an embodiment of the present disclosure.

[0017] Fig.9A and Fig. 9B is a diagram for describing an operation of maintaining a frame according to an embodiment of the present disclosure.

[0018] Fig. 10A is a circuit diagram of a pixel according to another embodiment of the present disclosure.

[0019] Fig. 10B and Fig. 10C is a diagram for describing an operation of a pixel during a sixth period according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] In this specification, the statement that a first component (or region, layer, part, portion, etc.) is "on" a second component, "connected to" a second component, or "coupled to" a second component means that the first component is directly on, directly connected to, or directly coupled to the second component, or that a third component is between the first and second components.

[0021] The same reference numerals represent the same components. Moreover, in the drawings, the thickness, proportion and size of the components are exaggerated for the effectiveness of the description of the technical content. The expression "and / or" includes one or more combinations that the related components can define.

[0022] Although the terms "first", "second", etc. can be used to describe various components, the components should not be interpreted as being limited by these terms. These terms are only used to distinguish one component from another component. For example, without departing from the scope and spirit of the present disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. The articles "a", "a", and "the" are singular when they have a single referent, but in the specification, the use of the singular form should not exclude the presence of more than one referent.

[0023] Furthermore, the terms "below," "beneath," "on," "over," etc. are used to describe the relationship of components shown in the drawings. These terms are relative and are described with reference to the directions shown in the drawings.

[0024] It will be understood that the terms "include", "comprising", "having", etc. indicate the presence of the features, numbers, steps, operations, elements or components or a combination thereof described in the specification, but do not exclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, elements or components or a combination thereof.

[0025] Unless otherwise defined, all terms (including technical terms and scientific terms) used in the specification have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. In addition, unless explicitly defined herein, terms (such as those defined in general dictionaries) should be interpreted as having the same meaning as they have in the context of the relevant technology, and should not be interpreted in an idealized or overly formalized sense.

[0026] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0027] Figure 1 is a block diagram of a display device according to an embodiment of the present disclosure.

[0028] Reference Figure 1 The display device DD may be a device that is activated according to an electrical signal to display an image. The display device DD may be applied to an electronic device such as a smart watch, a computer (such as a tablet personal computer (PC) or a notebook computer), or a smart TV.

[0029] The display device DD includes a display panel DP and a panel driver PDD driving the display panel DP. As an example of the present disclosure, the panel driver PDD may include a driving controller 100, a data driving circuit 200, a scan driving circuit 300, an emission driving circuit 350, and a voltage generator 400.

[0030] The driving controller 100 receives the image signal RGB and the control signal CTRL. The driving controller 100 generates the image data DATA by converting the data format of the image signal RGB to be suitable for the interface specification of the data driving circuit 200. The driving controller 100 outputs the scanning control signal SCS, the data control signal DCS and the emission driving signal ECS.

[0031] The data driving circuit 200 receives a data control signal DCS and image data DATA from the driving controller 100. The data driving circuit 200 converts the image data DATA into a data signal and outputs the data signal to a plurality of data lines DL1, DL2, ... and DLm (m is a positive integer) to be described later. The data signal refers to an analog voltage corresponding to the grayscale value of the image data DATA.

[0032] The voltage generator 400 generates voltages to operate the display panel DP. In an embodiment of the present disclosure, the voltage generator 400 generates a first driving voltage ELVDD, a second driving voltage ELVSS, and a reference voltage VREF. The reference voltage VREF may have a voltage level lower than that of the first driving voltage ELVDD.

[0033] The display panel DP includes scan lines SCL0, SCL1, SCL2, ..., SCLn and SCLn+1 and SWL1 to SWLn, emission control lines EML0 to EMLn, data lines DL1 to DLm and pixels PX. A display area DA and a non-display area NDA are defined in the display panel DP. Scan lines SCL0 to SCLn+1 and SWL1 to SWLn, emission control lines EML0 to EMLn, data lines DL1 to DLm and pixels PX may be disposed in the display area DA. Scan lines SCL0 to SCLn+1 and SWL1 to SWLn extend in a first direction DR1 and are arranged spaced apart from each other in a second direction DR2. Emission control lines EML0 to EMLn extend in a first direction DR1 and are arranged spaced apart from each other in a second direction DR2. Data lines DL1 to DLm extend in a second direction DR2 and are arranged spaced apart from each other in a first direction DR1.

[0034] As an example of the present disclosure, the scan lines SCL0 to SCLn+1 and SWL1 to SWLn may include compensation scan lines SCL0 to SCLn+1 and write scan lines SWL1 to SWLn. However, the present disclosure is not limited thereto, and the display panel DP may further include other scan lines in another embodiment.

[0035] The scan driving circuit 300 and the emission driving circuit 350 may be disposed in the non-display area NDA of the display panel DP. As an example of the present disclosure, the scan driving circuit 300 is positioned adjacent to one side of the display area DA, and the emission driving circuit 350 is positioned adjacent to the other side of the display area DA opposite to the one side. Figure 1 In the example shown in , the scan driving circuit 300 and the emission driving circuit 350 are respectively positioned on opposite sides of the display area DA, but the present disclosure is not limited thereto. For another example, each of the scan driving circuit 300 and the emission driving circuit 350 may be positioned adjacent to one of the one side and the other side of the display panel DP. In an embodiment, the scan driving circuit 300 and the emission driving circuit 350 may be integrated into one circuit.

[0036] A plurality of pixels PX may be positioned in a display area DA of a display panel DP. The plurality of pixels PX are electrically connected to compensation scan lines SCL0 to SCLn+1, write scan lines SWL1 to SWLn, emission control lines EML0 to EMLn, and data lines DL1 to DLm (n is a positive integer or 0). Each of the plurality of pixels PX may be electrically connected to at least one compensation scan line, at least one write scan line, and at least one emission control line. In an embodiment, for example, Figure 1As shown in , the first row of pixels can be connected to a dummy compensation scan line SCL0, a first compensation scan line SCL1, a second compensation scan line SCL2, a first write scan line SWL1, a dummy emission control line EML0, and a first emission control line EML1. In addition, the second row of pixels can be connected to a first compensation scan line SCL1, a second compensation scan line SCL2, a third compensation scan line, a second write scan line SWL2, a first emission control line EML1, and a second emission control line EML2. However, the number of scan lines connected to each of the pixels and the number of emission control lines connected to each of the pixels are not limited thereto. For another example, the number of scan lines and the number of emission control lines can be changed.

[0037] Each of the plurality of pixels PX includes a light emitting element ED (see Figure 2 ) and a pixel circuit unit PXC for controlling the emission of the light emitting element ED (see Figure 2 ). The pixel circuit unit PXC may include one or more transistors and one or more capacitors. The scan driving circuit 300 and the emission driving circuit 350 may be directly disposed in the non-display area NDA of the display panel DP through the same process as the transistors of the pixel circuit unit PXC.

[0038] Each of the plurality of pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, and a reference voltage VREF from the voltage generator 400 .

[0039] The scan driving circuit 300 receives a scan control signal SCS from the driving controller 100. The scan driving circuit 300 may output a compensation scan signal and a write scan signal to the compensation scan lines SCL0 to SCLn+1 and the write scan lines SWL1 to SWLn, respectively, in response to the scan control signal SCS. The emission driving circuit 350 may output an emission control signal to the emission control lines EML0 to EMLn in response to an emission driving signal ECS from the driving controller 100.

[0040] The driving controller 100 according to an embodiment of the present disclosure may determine an operating frequency, and may control the data driving circuit 200, the scan driving circuit 300, and the emission driving circuit 350 according to the determined operating frequency. As an example of the present disclosure, the emission driving circuit 350 may operate at a frequency higher than or equal to that of the scan driving circuit 300.

[0041] Figure 2 is a circuit diagram of a pixel according to an embodiment of the present disclosure.

[0042] Figure 2 shows the connection to Figure 1The equivalent circuit diagram of the pixel PXij shown in FIG. 1 shows the i-th data line DLi (i is a positive integer less than or equal to m) among the data lines DL1 to DLm, the (j-1)th compensation scan line SCLj-1 (j is a positive integer less than or equal to n) among the compensation scan lines SCL0 to SCLn+1, the j-th compensation scan line SCLj and the (j+1)th compensation scan line SCLj+1, the j-th write scan line SWLj among the write scan lines SWL1 to SWLn, and the (j-1)th emission control line EMLj-1 and the j-th emission control line EMLj among the emission control lines EML0 to EMLn. Because Figure 1 Each of the plurality of pixels PX shown in FIG. Figure 2 The circuit configuration of the pixel PXij shown in FIG. 1 is the same as the circuit configuration, so a detailed description of the remaining pixels PX is omitted.

[0043] Reference Figure 2 , also refer to Figure 1 , the pixel PXij according to the embodiment includes a pixel circuit unit PXC and a light emitting element ED. In the embodiment of the present disclosure, the pixel circuit unit PXC may include eight transistors and two capacitors. Hereinafter, the eight transistors are respectively referred to as "a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8". The two capacitors are respectively referred to as "a first capacitor C1 and a second capacitor C2".

[0044] In an embodiment, each of the first to eighth transistors T1 to T8 is a P-type transistor having a low temperature polysilicon ("LTPS") semiconductor layer. Alternatively, each of the first to eighth transistors T1 to T8 may be an N-type transistor. In addition, at least one of the first to eighth transistors T1 to T8 may be an N-type transistor, and the other transistors may be a P-type transistor. Alternatively, at least one of the first to eighth transistors T1 to T8 may be a transistor having an oxide semiconductor layer. In an embodiment, for example, some of the first to eighth transistors T1 to T8 may be oxide semiconductor transistors, and the other transistors may be LTPS transistors.

[0045] The circuit configuration of the pixel PXij according to the embodiment of the present disclosure is not limited to Figure 2 The circuit configuration shown in . Figure 2 The pixel PXij shown in FIG. 1 is merely an example, and the circuit configuration of the pixel PXij may be modified and implemented.

[0046] The jth compensation scan line SCLj and the jth write scan line SWLj supply the jth compensation scan signal SCj and the jth write scan signal SWj to the pixel PXij, respectively. The (j-1)th compensation scan line SCLj-1 and the (j+1)th compensation scan line SCLj+1 supply the (j-1)th compensation scan signal SCj-1 and the (j+1)th compensation scan signal SCj+1 to the pixel PXij, respectively. In addition, the (j-1)th emission control line EMLj-1 and the jth emission control line EMLj supply the (j-1)th emission control signal EMj-1 and the jth emission control signal EMj to the pixel PXij, respectively. The i-th data line DLi transmits the i-th data voltage Vdata to the pixel PXij. The i-th data voltage Vdata may have a value similar to that input to the display device DD (see Figure 1 )’s image signal RGB corresponding to the voltage level.

[0047] The pixel PXij can be connected to a first voltage line VL1, a second voltage line VL2, and a reference voltage line VL3. Figure 1 The first driving voltage ELVDD supplied from the voltage generator 400 shown in FIG. 1 is transferred to the pixel PXij. The second voltage line VL2 transfers the second driving voltage ELVSS supplied from the voltage generator 400 to the pixel PXij. The reference voltage line VL3 can transfer the reference voltage VREF supplied from the voltage generator 400 to the pixel PXij.

[0048] The first capacitor C1 is connected between the first node NA and a first voltage line VL1 for receiving the first driving voltage ELVDD.

[0049] The first transistor T1 may be connected to a first node NA, a first voltage line VL1, and a second node NB, and may be operated according to a potential difference between the first node NA and the second node NB. The first transistor T1 includes a first electrode connected to the first voltage line VL1, a second electrode connected to the second node NB, and a gate electrode connected to the first node NA. The first transistor T1 operates according to the potential of the first node NA, and electrically connects the second node NB and the first voltage line VL1.

[0050] The second transistor T2 is connected between the first node NA and the third node NC, and receives the first scan signal. The second transistor T2 includes a first electrode connected to the third node NC, a second electrode connected to the first node NA, and a gate electrode for receiving the first scan signal. As an example of the present disclosure, the second transistor T2 can be connected to the j-th compensation scan line SCLj to receive the j-th compensation scan signal SCj as a "first scan signal". The second transistor T2 is turned on in response to the first scan signal and controls the potential of the gate electrode of the first transistor T1.

[0051] The third transistor T3 is connected between the second node NB and the third node NC and receives the second scan signal. The third transistor T3 includes a first electrode connected to the second node NB, a second electrode connected to the third node NC, and a gate electrode for receiving the second scan signal. As an example of the present disclosure, the third transistor T3 is connected to the (j+1)th compensation scan line SCLj+1 to receive the (j+1)th compensation scan signal SCj+1 as a "second scan signal". The third transistor T3 is turned on in response to the second scan signal to transfer the signal output from the second electrode of the first transistor T1 to the third node NC. As an example of the present disclosure, the first scan signal may be a signal activated before the second scan signal.

[0052] The fourth transistor T4 is connected between the fourth node ND and the i-th data line DLi, and receives the third scan signal. The fourth transistor T4 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the fourth node ND, and a gate electrode for receiving the third scan signal. As an example of the present disclosure, the fourth transistor T4 is connected to the j-th write scan line SWLj to receive the j-th write scan signal SWj as a "third scan signal". The fourth transistor T4 can be turned on in response to the third scan signal to output the i-th data voltage Vdata supplied through the i-th data line DLi to the fourth node ND.

[0053] The second capacitor C2 may be connected between the third node NC and the fourth node ND.

[0054] The fifth transistor T5 is connected between the second node NB and the light emitting element ED, and receives the first emission control signal. The fifth transistor T5 includes a first electrode connected to the second node NB, a second electrode connected to the anode of the light emitting element ED, and a gate electrode for receiving the first emission control signal. The fifth transistor T5 can be connected to the (j-1)th emission control line EMLj-1 to receive the (j-1)th emission control signal EMj-1 as the "first emission control signal". The fifth transistor T5 electrically connects the second node NB and the anode of the light emitting element ED in response to the first emission control signal.

[0055] The sixth transistor T6 is connected between the reference voltage line VL3 supplied with the reference voltage VREF and the third node NC, and receives the second emission control signal. The sixth transistor T6 includes a first electrode connected to the third node NC, a second electrode connected to the reference voltage line VL3, and a gate electrode for receiving the second emission control signal. As an example of the present disclosure, the sixth transistor T6 can be connected to the j-th emission control line EMLj, and can receive the j-th emission control signal EMj as the "second emission control signal". The sixth transistor T6 electrically connects the third node NC and the reference voltage line VL3 in response to the second emission control signal.

[0056] The seventh transistor T7 is connected between the reference voltage line VL3 and the fourth node ND, and receives the fourth scan signal. The seventh transistor T7 includes a first electrode connected to the fourth node ND, a second electrode connected to the reference voltage line VL3, and a gate electrode for receiving the fourth scan signal. As an example of the present disclosure, the seventh transistor T7 can be connected to the (j-1)th compensation scan line SCLj-1, and can receive the (j-1)th compensation scan signal SCj-1 as a "fourth scan signal". The seventh transistor T7 electrically connects the fourth node ND and the reference voltage line VL3 in response to the fourth scan signal. As an example of the present disclosure, the fourth scan signal can be a signal activated before the first scan signal and the second scan signal.

[0057] The eighth transistor T8 is connected between the reference voltage line VL3 and the light emitting element ED, and receives the fifth scan signal. The eighth transistor T8 includes a first electrode connected to the anode of the light emitting element ED, a second electrode connected to the reference voltage line VL3, and a gate electrode for receiving the fifth scan signal. As an example of the present disclosure, the eighth transistor T8 can be connected to the j-th write scan line SWLj, and can receive the j-th write scan signal SWj as the fifth scan signal. The eighth transistor T8 electrically connects the anode of the light emitting element ED and the reference voltage line VL3 in response to the fifth scan signal. As an example of the present disclosure, the fifth scan signal can be the same signal as the third scan signal.

[0058] The light emitting element ED is connected between the second voltage line VL2 for receiving the second driving voltage ELVSS and the fifth transistor T5. The anode of the light emitting element ED is connected to the second electrode of the fifth transistor T5. The cathode of the light emitting element ED is connected to the second voltage line VL2.

[0059] Figure 3A and Figure 3B is a timing diagram for describing the operation of a display device according to an embodiment of the present disclosure. Figure 3A is a timing diagram for describing that a display device operates at a first operating frequency according to an embodiment of the present disclosure. Figure 3Bis a timing diagram for describing that a display device operates at a second operating frequency according to an embodiment of the present disclosure.

[0060] Reference Figures 1 to 3A , the operating frequency of the display device DD may be changed. In an embodiment of the present disclosure, the first operating frequency may be the highest operating frequency at which the display device DD can operate. In an embodiment, for example, the first operating frequency may be 360 ​​Hz. The first operating frequency may be referred to as a “reference frequency” or a “maximum frequency”.

[0061] When the display device DD operates at the first operating frequency, the scan driving circuit 300 may sequentially activate the compensation scan signals SC1, SCj, and SCn and the write scan signals SW1, SWj, and SWn to be at a low level during each of the plurality of first frames F1. During each of the plurality of first frames F1, the emission driving circuit 350 may sequentially disable the first emission control signals EM1, EMj, and EMn to be at a high level. Figure 3A It is shown that the activation level of the compensation scan signals SC1, SCj and SCn, the write scan signals SW1, SWj and SWn, and the first emission control signals EM1, EMj and EMn is a low level, and the deactivation level of the compensation scan signals SC1, SCj and SCn, the write scan signals SW1, SWj and SWn, and the first emission control signals EM1, EMj and EMn is a high level, but the present disclosure is not limited thereto. For another example, when Figure 2 When the first to eighth transistors T1 to T8 shown in are N-type transistors, the activation levels of the compensation scan signals SC1, SCj and SCn, the write scan signals SW1, SWj and SWn, and the first emission control signals EM1, EMj and EMn may be high levels, and the deactivation levels of the compensation scan signals SC1, SCj and SCn, the write scan signals SW1, SWj and SWn, and the first emission control signals EM1, EMj and EMn may be low levels.

[0062] When the first operating frequency is the maximum frequency, each first frame F1 may include only the first write frame WF1. In this case, the duration of the first write frame WF1 may be equal to the duration of each first frame F1.

[0063] Reference Figures 1 to 3B , the display device DD may operate at a second operating frequency lower than the first operating frequency. As an example of the present disclosure, the second operating frequency is 90 Hz, but the second operating frequency is not limited thereto. The operating frequency of the display device DD may be changed in various ways. In an embodiment, the operating frequency of the display device DD may be determined according to the characteristics of the image signal RGB (e.g., a video or a still image).

[0064] When the display device DD operates at a second operating frequency lower than the first operating frequency, the duration of each second frame F2 may be greater than Figure 3A As an example of the present disclosure, the duration of each second frame F2 may be four times the duration of each first frame F1. Each of the second frames F2 may include a second write frame WF2 and hold frames HF1, HF2, and HF3. The second write frame WF2 may have the same Figure 3A The duration of the first write frame WF1 shown in is the same duration.

[0065] During the second write frame WF2, the scan driving circuit 300 may sequentially activate the compensation scan signals SC1, SCj, and SCn and the write scan signals SW1, SWj, and SWn to be at an active level (e.g., a low level). During the second write frame WF2, the emission driving circuit 350 may sequentially disable the first emission control signals EM1, EMj, and EMn to be at a disable level (e.g., a high level).

[0066] During the holding frames HF1, HF2 and HF3, the scan driving circuit 300 maintains the compensation scan signals SC1, SCj and SCn at a disabled level (e.g., a high level). However, during the holding frames HF1, HF2 and HF3, the scan driving circuit 300 may sequentially activate the write scan signals SW1, SWj and SWn. In addition, during the holding frames HF1, HF2 and HF3, the emission driving circuit 350 may sequentially disable the first emission control signals EM1, EMj and EMn to be at a disabled level (e.g., a high level). That is, even when the operating frequency of the display device DD is changed to the second operating frequency, the write scan signals SW1, SWj and SWn and the first emission control signals EM1, EMj and EMn may still be output at the maximum frequency (i.e., the first operating frequency). Figure 3B An embodiment in which three holding frames HF1, HF2, and HF3 are included in the second frame F2 is shown, but the present disclosure is not limited thereto. For another example, the number of holding frames included in the second frame F2 may vary according to the size of the second operating frequency.

[0067] Meanwhile, during the holding frames HF1, HF2, and HF3, the i-th data voltage Vdata may be held as a bias voltage Vb. The bias voltage Vb may be a voltage maintained at a constant voltage level during the holding frames HF1, HF2, and HF3. As an example of the present disclosure, the bias voltage Vb may have a voltage level corresponding to a black grayscale, but is not limited thereto.

[0068] Figure 4A and Figure 4Bis a diagram for describing an operation of a pixel during a first period according to an embodiment of the present disclosure. Figure 5A and Figure 5B is a diagram for describing an operation of a pixel during a second period according to an embodiment of the present disclosure. Fig. 6A and Figure 6B is a diagram for describing an operation of a pixel during a third period according to an embodiment of the present disclosure. Figure 6C is a diagram for describing a current deviation compensation process according to an embodiment of the present disclosure. Fig. 7A and Figure 7B is a diagram for describing an operation of a pixel during a fourth period according to an embodiment of the present disclosure. Fig. 8A and Figure 8B is a diagram for describing an operation of a pixel during a fifth period according to an embodiment of the present disclosure.

[0069] Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B It explains Figure 3B The operation of the pixel PXij during the second writing frame WF2 and the first holding frame HF1 is shown in FIG. However, the operation of the pixel PXij can be equally implemented during the first writing frame WF1. Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B , the second write frame WF2 includes a first period Ti, a second period Tc, a third period Tw, and a fourth period Te, and the first hold frame HF1 includes a fifth period Tr.

[0070] Reference Figure 4A and Figure 4B During the first period Ti of the second write frame WF2, each of the (j-1)th compensation scan signal SCj-1 (i.e., the fourth scan signal), the jth compensation scan signal SCj (i.e., the first scan signal), and the jth emission control signal EMj (i.e., the second emission control signal) has an activation level. Therefore, during the first period Ti, the seventh transistor T7 is turned on in response to the (j-1)th compensation scan signal SCj-1, the second transistor T2 is turned on in response to the jth compensation scan signal SCj, and the sixth transistor T6 is turned on in response to the jth emission control signal EMj.

[0071] The reference voltage VREF is applied to the fourth node ND through the turned-on seventh transistor T7, and is applied to the first node NA and the third node NC through the turned-on second transistor T2 and the sixth transistor T6. Therefore, during the first period Ti, the first node NA, the third node NC, and the fourth node ND may be initialized to the reference voltage VREF. That is, the first period Ti may be an initialization period in which the first node NA, the third node NC, and the fourth node ND are initialized to the reference voltage VREF.

[0072] During the first period Ti of the second write frame WF2, each of the (j+1)th compensation scan signal SCj+1 (i.e., the second scan signal), the jth write scan signal SWj (i.e., the third scan signal and the fifth scan signal), and the (j-1)th emission control signal EMj-1 (i.e., the first emission control signal) has a disable level. Therefore, during the first period Ti, the third transistor T3 is turned off in response to the (j+1)th compensation scan signal SCj+1, the fourth transistor T4 and the eighth transistor T8 are turned off in response to the jth write scan signal SWj, and the fifth transistor T5 is turned off in response to the (j-1)th emission control signal EMj-1. In this way, since the third transistor T3 is turned off during the first period Ti, a constant current path from the first voltage line VL1 to the reference voltage line VL3 can be prevented from being formed, thereby reducing power consumption.

[0073] Reference Figure 5A and Figure 5B , the second period Tc occurs after the first period Ti. During the second period Tc of the second write frame WF2, each of the (j-1)th compensation scan signal SCj-1 (i.e., the fourth scan signal), the jth compensation scan signal SCj (i.e., the first scan signal) and the (j+1)th compensation scan signal SCj+1 (i.e., the second scan signal) has an activation level. Therefore, the second transistor T2, the third transistor T3 and the seventh transistor T7 are turned on during the second period Tc. The first drive voltage ELVDD supplied by the first voltage line VL1 is applied to the first node NA via the turned-on first transistor T1, the second transistor T2 and the third transistor T3. During the second period Tc, the first node NA may have a potential "ELVDD-Vth". Here, "Vth" may be a threshold voltage of the first transistor T1.

[0074] The second period Tc may be a period continuous with the first period Ti, and the duration of the second period Tc may be greater than the duration of the first period Ti. As an example of the present disclosure, the duration of the second period Tc may be three times or more the duration of the first period Ti. When the duration of the second period Tc is long, the potential of the first node NA may be fully compensated so as to have a voltage value corresponding to the deviation and variation of the threshold voltage Vth of the first transistor T1.

[0075] Even during the second period Tc, the potential of the fourth node ND can be maintained at the reference voltage VREF by the turned-on seventh transistor T7.

[0076] During the second period Tc of the second write frame WF2, each of the j-th write scan signal SWj and the (j-1)-th emission control signal EMj-1 and the j-th emission control signal EMj has a disable level. Therefore, during the second period Tc, the fourth transistor T4 and the eighth transistor T8 are turned off in response to the j-th write scan signal SWj, and the fifth transistor T5 and the sixth transistor T6 are turned off in response to the (j-1)-th emission control signal EMj-1 and the j-th emission control signal EMj, respectively.

[0077] Reference Fig. 6A and Figure 6B , the third period Tw occurs after the second period Tc. During the third period Tw of the second write frame WF2, each of the j-th write scan signal SWj (i.e., the third scan signal and the fifth scan signal), the j-th compensation scan signal SCj (i.e., the first scan signal) and the (j+1)-th compensation scan signal SCj+1 (i.e., the second scan signal) has an activation level. Therefore, during the third period Tw, the second transistor T2, the third transistor T3, the fourth transistor T4 and the eighth transistor T8 are turned on. The i-th data voltage Vdata applied through the i-th data line DLi can be applied to the fourth node ND through the turned-on fourth transistor T4, and can be stored in the second capacitor C2. At this time, by coupling the first capacitor C1 and the second capacitor C2, the potential VA of the first node NA can be calculated based on the following equation 1.

[0078] [Equation 1]

[0079]

[0080] When the duration of the second period Tc becomes longer, a voltage higher than the threshold voltage Vth of the first transistor T1 may be sensed at the gate-source node of the first transistor T1. Figure 6CAs shown in FIG. 1 , due to the slope deviation at the threshold voltage Vth or less of the first transistor T1, a deviation (ie, current deviation) of the drain current Id may occur (in Figure 6C , Vgs may represent the gate-source voltage of the first transistor T1).

[0081] In order to compensate for the current deviation, the first transistor T1, the second transistor T2 and the third transistor T3 may be turned on during the third period Tw. The current path from the first voltage line VL1 to the first node NA via the second node NB and the third node NC is formed by the turned-on first transistor T1, the second transistor T2 and the third transistor T3. In this case, the current that flows to the first node NA through the first transistor T1 to the third transistor T3 may be referred to as "sinking current". The magnitude of the sinking current depends on the slope deviation at the threshold voltage Vth or less of the first transistor T1. During the third period Tw, the potential VA of the first node NA may be changed to "ELVDD-Vth+Vss" by the sinking current. Here, "Vss" may be a voltage corresponding to the slope deviation at the threshold voltage Vth or less of the first transistor T1. Therefore, the voltage Vss corresponding to the slope deviation at the threshold voltage Vth or less of the first transistor T1 may be stored (or reflected) in the first node NA.

[0082] Meanwhile, the potential of the anode of the light emitting element ED may be maintained at the reference voltage VREF by the eighth transistor T8 , which is turned on even during the third period Tw.

[0083] As an example of the present disclosure, the third period Tw may be a period continuous with the second period Tc, and a duration of the third period Tw is equal to a duration of the first period Ti, and may be shorter than a duration of the second period Tc.

[0084] During the third period Tw of the second write frame WF2, each of the (j-1)th compensation scan signal SCj-1 and the (j-1)th emission control signal EMj-1 and the j-th emission control signal EMj has a disable level. Therefore, during the third period Tw, the seventh transistor T7 is turned off in response to the (j-1)th compensation scan signal SCj-1, and the fifth transistor T5 and the sixth transistor T6 are turned off in response to the (j-1)th emission control signal EMj-1 and the j-th emission control signal EMj, respectively.

[0085] Reference Fig. 7A and Figure 7B, the fourth period Te occurs after the third period Tw. During the fourth period Te of the second writing frame WF2, each of the j-th compensation scanning signal SCj and the j-th writing scanning signal SWj has a disable level. Therefore, the second transistor T2, the third transistor T3 and the eighth transistor T8 are turned off during the fourth period Te.

[0086] During the fourth period Te of the second write frame WF2, the (j-1)th emission control signal EMj-1 has an activation level. Therefore, during the fourth period Te, the fifth transistor T5 is turned on in response to the (j-1)th emission control signal EMj-1. Therefore, the current flowing from the first voltage line VL1 to the second node NB through the first transistor T1 can be applied to the light emitting element ED through the turned-on fifth transistor T5. The emission current Ied flowing to the light emitting element ED can be controlled according to the voltage level of the first node NA, and the light emitting element ED can output light corresponding to the emission current Ied. Therefore, the fourth period Te can be an emission period Te in which the light emitting element ED emits light. At the same time, the first period Ti, the second period Tc, and the third period Tw can be non-emission periods in which the light emitting element ED does not emit light.

[0087] The emission current Ied depends on the threshold voltage Vth of the first transistor T1. The threshold voltage Vth of the first transistor T1 may vary depending on the pixel PX (see Figure 1 ) and may shift due to degradation according to the operation time. In detail, since the degree of change (or degradation) of the threshold voltage Vth of the first transistor T1 is different for each pixel PX, the shift degree of the threshold voltage Vth of the first transistor T1 is also different for each pixel PX.

[0088] As above Figure 5A and Figure 5B As described in , since the duration of the second period Tc is sufficiently long regardless of the operating frequency, the deviation of the threshold voltage Vth and the change of the threshold voltage Vth can be fully compensated. Fig. 6A and Figure 6B As shown in , the current deviation can be compensated by turning on the first transistor T1, the second transistor T2, and the third transistor T3 during the third period Tw, so that the voltage Vss corresponding to the slope deviation at the threshold voltage Vth or lower of the first transistor T1 is stored or reflected in the first node NA. Therefore, it is possible to effectively prevent the brightness deviation from being generated due to the current deviation in the high grayscale area for each pixel PX.

[0089] As an example of the present disclosure, in a specific period of the fourth period Te (hereinafter referred to as “previous transmission period Tp_e”) Figure 7BDuring the (j+1)th compensation scan signal SCj+1, the third transistor T3 may be turned on in response to the (j+1)th compensation scan signal SCj+1. However, since the jth emission control signal EMj is in an inactive state during the previous emission period Tp_e, the sixth transistor T6 may be turned off. Therefore, during the previous emission period Tp_e, the emission current Ied may not leak through the third transistor T3.

[0090] Reference Fig. 8A and Figure 8B , while holding frames HF1, HF2 and HF3 (see Figure 3B ) starts at the first hold frame HF1 among the holding frames HF1, HF2 and HF3, the i-th data voltage Vdata may be maintained as a bias voltage Vb. The bias voltage Vb may be a voltage maintained at a constant voltage level during the holding frames HF1, HF2 and HF3. As an example of the present disclosure, the bias voltage Vb may have a voltage level corresponding to a black grayscale, but is not limited thereto. During the holding frames HF1, HF2 and HF3, each of the (j-1)th compensation scan signal SCj-1, the j-th compensation scan signal SCj and the (j+1)th compensation scan signal SCj+1 maintains a disable level. The (j-1)th emission control signal EMj-1 defines a non-emission period of the first hold frame HF1. ​​That is, the (j-1)th emission control signal EMj-1 has a disable level during the non-emission period of the first hold frame HF1. ​​Each of the (j-1)th emission control signal EMj-1 and the j-th emission control signal EMj may include a disable period having a disable level within the first hold frame HF1.

[0091] The non-emission period includes a fifth period Tr, in which the j-th write scan signal SWj is in an effective state, and a blanking period Tb, in which the j-th write scan signal SWj is in an ineffective state. That is, the fifth period Tr may be an activation period in which the j-th write scan signal SWj has an activation level. The fifth period Tr may overlap with a disable period of each of the (j-1)-th emission control signal EMj-1 and the j-th emission control signal EMj.

[0092] During the fifth period Tr, the fourth transistor T4 and the eighth transistor T8 may be turned on in response to the j-th write scan signal SWj. Therefore, during the fifth period Tr, the anode of the light emitting element ED may be reset to the reference voltage VREF by the turned-on eighth transistor T8. The anode of the light emitting element ED may be periodically reset in synchronization with the j-th write scan signal SWj periodically activated during the hold frames HF1, HF2, and HF3. That is, the fifth period Tr may be referred to as a reset period, in which the anode of the light emitting element ED is reset.

[0093] When the fifth period Tr ends, the emission period Te (i.e., the fourth period Te) may be started. Since the operation during the emission period Te during the holding frames HF1, HF2, and HF3 is the same as the operation during the fourth period Te of the first write frame WF1 and the second write frame WF2, the description of the operation during the emission period Te of the holding frames HF1, HF2, and HF3 will be omitted.

[0094] Fig.9A and Fig. 9B is a diagram for describing an operation of maintaining a frame according to an embodiment of the present disclosure.

[0095] Reference Fig.9A and Fig. 9B , during the second write frame WF2, the voltage level of the reference voltage VREF may be fixed to the base level Vrb, and may be changed to a level higher than the base level Vrb during the hold frames HF1, HF2, and HF3. The reference voltage VREF may gradually rise to a level higher than a predetermined reference level Va, and then decline. Here, when the reference voltage VREF is lower than the reference level Va, a leakage current may flow from the first node NA to the third node NC. On the contrary, when the reference voltage VREF is higher than the reference level Va, an opposite leakage current may flow from the third node NC to the first node NA. That is, by periodically changing the direction of the leakage current leaked by the second transistor T2, the potential change of the first node NA may be effectively reduced. Therefore, when the voltage level of the reference voltage VREF is alternately changed to a level higher than the reference level Va and a level lower than the reference level Va during the hold frames HF1, HF2, and HF3, the phenomenon that the potential change of the first node NA is recognized as flickering during operation at a low operating frequency can be effectively prevented.

[0096] Fig. 10A is a circuit diagram of a pixel according to another embodiment of the present disclosure. Fig. 10B and Fig. 10C is a diagram for describing an operation of a pixel during a sixth period according to an embodiment of the present disclosure.

[0097] Reference Fig. 10A According to another embodiment, a pixel PXij-a includes a pixel circuit unit PXCa and a light emitting element ED. In an embodiment of the present disclosure, the pixel circuit unit PXCa may include nine transistors and two capacitors. Hereinafter, the nine transistors are respectively referred to as "a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9". The two capacitors are respectively referred to as "a first capacitor C1 and a second capacitor C2".

[0098] In an embodiment, each of the first transistor T1 to the ninth transistor T9 is a P-type transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer. Alternatively, each of the first transistor T1 to the ninth transistor T9 may be an N-type transistor. In addition, at least one of the first transistor T1 to the ninth transistor T9 may be an N-type transistor, and the other transistors may be a P-type transistor. Alternatively, at least one of the first transistor T1 to the ninth transistor T9 may be a transistor having an oxide semiconductor layer. In an embodiment, for example, some of the first transistor T1 to the ninth transistor T9 may be oxide semiconductor transistors, and the other transistors may be LTPS transistors.

[0099] In the pixel PXij-a according to the embodiment of the present disclosure, the circuit configuration of the pixel PXij-a consisting of the first transistor T1 to the eighth transistor T8 except the ninth transistor T9 and the first capacitor C1 and the second capacitor C2 can be the same as Figure 2 The circuit configuration shown in is the same as that shown in FIG. 10A to FIG. 10C The connection structure and operation of the ninth transistor T9 are described in detail in FIG.

[0100] The ninth transistor T9 (or "shift compensation transistor") is connected between the second node NB and the reference voltage line VL3 and receives a shift scan signal. The ninth transistor T9 includes a first electrode connected to the second node NB, a second electrode connected to the reference voltage line VL3, and a gate electrode for receiving the shift scan signal. The ninth transistor T9 can be connected to the (j+1)th write scan line SWLj+1 to receive the (j+1)th write scan signal SWj+1 as a "shift scan signal". The ninth transistor T9 electrically connects the second node NB and the reference voltage line VL3 in response to the shift scan signal.

[0101] Reference Fig. 10B and Fig. 10C , the sixth period may include a sixth-first period Th1 located in the second write frame WF2 and a sixth-second period Th2 located in the hold frames HF1, HF2, and HF3. The sixth-first period Th1 is located between the third period Tw and the fourth period Te. The sixth-second period Th2 is located between the fifth period Tr and the fourth period Te. The third period Tw may be before the sixth-first period Th1, and the fifth period Tr may be before the sixth-second period Th2. The sixth-first period Th1 and the sixth-second period Th2 may overlap with the disable period of each of the (j-1)th emission control signal EMj-1 and the jth emission control signal EMj.

[0102] During the sixth-first period Th1 of the second write frame WF2, each of the (j+1)th compensation scan signal SCj+1 (i.e., the second scan signal) and the (j+1)th write scan signal SWj+1 (i.e., the shift scan signal) has an activation level. That is, the sixth-first period Th1 may be an activation period of each of the (j+1)th compensation scan signal SCj+1 (i.e., the second scan signal) and the (j+1)th write scan signal SWj+1. Therefore, during the sixth-first period Th1, the third transistor T3 is turned on in response to the (j+1)th compensation scan signal SCj+1, and the ninth transistor T9 is turned on in response to the (j+1)th write scan signal SWj+1.

[0103] During the sixth-second period Th2 of the holding frames HF1, HF2 and HF3, the (j+1)th write scan signal SWj+1 (i.e., the shift scan signal) has an activation level. That is, the sixth-second period Th2 may be an activation period of the (j+1)th write scan signal SWj+1. Therefore, during the sixth-second period Th2, the ninth transistor T9 is turned on in response to the (j+1)th write scan signal SWj+1.

[0104] The reference voltage VREF is applied to the second node NB through the turned-on ninth transistor T9 and to the third node NC through the turned-on third transistor T3. Therefore, during the sixth-first period Th1 and the sixth-second period Th2, the second node NB and the third node NC can be compensated by the reference voltage VREF.

[0105] As an example of the present disclosure, during the sixth-first period Th1 and the sixth-second period Th2, the reference voltage VREF may have a voltage level higher than or equal to the voltage level of the target compensation voltage Vc. As an example of the present disclosure, the target compensation voltage Vc may have a voltage level higher than the voltage level of the first driving voltage ELVDD. In addition, after the sixth-second period Th2 of each of the frames HF1, HF2, and HF3 is maintained, the voltage level of the reference voltage VREF may gradually change to a level higher than the base level Vrb.

[0106] During the sixth-first period Th1 and the sixth-second period Th2, a negative bias may be applied to the first transistor T1 by a reference voltage VREF having a voltage level higher than that of the first driving voltage ELVDD. Due to the negative bias of the first transistor T1, the threshold voltage Vth of the first transistor T1 may be pre-shifted before the emission period (ie, the fourth period Te).

[0107] The fourth period Te may start after the sixth-first period Th1 and the sixth-second period Th2 in each frame. When the threshold voltage Vth is shifted in advance during the sixth-first period Th1 and the sixth-second period Th2 before the fourth period Te (i.e., the emission period) starts, the shift level (i.e., the shift amount) of the threshold voltage Vth may be reduced during the fourth period Te. As a result, the emission current Ied caused by the shift amount of the threshold voltage Vth may be effectively reduced (see Fig. 7A )’s change.

[0108] According to the embodiments of the present disclosure, even in high-speed operation, it is possible to ensure a sufficient compensation period to compensate for the threshold voltage deviation or change in the threshold voltage of the first transistor, thereby minimizing the current deviation supplied to the light-emitting element when displaying a low grayscale image at a high operating frequency. In addition, when displaying a high grayscale image, the current deviation occurring at a voltage less than the threshold voltage is compensated by injecting current, thereby preventing the occurrence of brightness deviation due to the current deviation.

[0109] Furthermore, the variation of the emission current during the emission period can be reduced by pre-shifting the threshold voltage of the first transistor before the emission period. As a result, the flicker phenomenon can be effectively prevented or reduced.

[0110] Although the embodiments of the present disclosure have been described for illustrative purposes, it will be understood by those skilled in the art that various modifications and substitutions are possible without departing from the scope and spirit of the present disclosure as disclosed in the appended claims. Therefore, the technical scope of the present disclosure is not limited to the detailed description of this specification, but should be defined by the claims.

[0111] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A display device, wherein: The display device comprises: Display panel, including pixels, Wherein, the pixels include: Light emitting element; A first capacitor connected between the first node and the voltage line; a first transistor connected to the first node, the voltage line, and a second node; a second transistor connected between the first node and a third node, and the second transistor is configured to receive a first scan signal; a third transistor connected between the second node and the third node, and configured to receive a second scan signal; a second capacitor connected between the third node and the fourth node; a fourth transistor connected between the fourth node and the data line, and configured to receive a third scan signal; and A fifth transistor is connected between the second node and the light emitting element, and the fifth transistor is configured to receive a first emission control signal.

2. The display device according to claim 1, wherein: The pixel also includes: a sixth transistor connected between the third node and a reference voltage line, and configured to receive a second emission control signal; a seventh transistor connected between the fourth node and the reference voltage line, and configured to receive a fourth scan signal; and An eighth transistor is connected between the light emitting element and the reference voltage line, and the eighth transistor is configured to receive a fifth scan signal.

3. The display device according to claim 2, wherein: During a first period, each of the first scan signal and the fourth scan signal has an activation level, and each of the second scan signal, the third scan signal, and the fifth scan signal has a deactivation level, and During the first period, the first emission control signal has the disable level, and the second emission control signal has the activate level.

4. The display device according to claim 3, wherein: During the first period, the first node, the third node, and the fourth node are initialized to a reference voltage applied through the reference voltage line.

5. The display device according to claim 4, wherein: The second cycle is after the first cycle, wherein, during the second period, each of the first scan signal, the second scan signal, and the fourth scan signal has the activation level, and each of the third scan signal and the fifth scan signal has the deactivation level, and During the second period, each of the first emission control signal and the second emission control signal has the disable level.

6. The display device according to claim 5, wherein: During the second period, the driving voltage applied to the voltage line is applied to the first node via the turned-on first transistor, the second transistor, and the third transistor, and the fourth node is maintained at the reference voltage.

7. The display device according to claim 5, wherein: The third cycle is after the second cycle. wherein, during the third period, each of the first scan signal, the second scan signal, the third scan signal, and the fifth scan signal has the activation level, and During the third period, each of the fourth scan signal, the first emission control signal, and the second emission control signal has the disable level.

8. The display device according to claim 7, wherein: The duration of the first cycle is the same as the duration of the third cycle, and The duration of the second cycle is greater than the duration of each of the first cycle and the third cycle.

9. The display device according to claim 7, wherein: The fourth cycle is after the third cycle. wherein, during the fourth period, the first emission control signal has the activation level, and During the fourth period, each of the first scan signal, the third scan signal, the fourth scan signal, and the fifth scan signal has the disable level.

10. The display device according to claim 2, wherein: The display panel displays an image during a plurality of frames, and at least one frame among the plurality of frames includes a writing frame and at least one holding frame, wherein each of the first scanning signal, the second scanning signal, and the fourth scanning signal includes an activation period having an activation level within the write frame, and is maintained in an inactive state during the hold frame, and Each of the third scanning signal and the fifth scanning signal includes an activation period having the activation level in each of the writing frame and the holding frame.

11. The display device according to claim 10, wherein: Each of the first emission control signal and the second emission control signal includes a disable period having a disable level within each of the write frame and the hold frame, and The activation period of each of the third scan signal and the fifth scan signal overlaps with the deactivation period of each of the first emission control signal and the second emission control signal.

12. The display device according to claim 10, wherein: The reference voltage applied through the reference voltage line has a base level during the write frame, and changes to a level higher than the base level in the hold frame.

13. The display device according to claim 12, wherein: The holding frame includes a period in which the reference voltage gradually rises from the base level to a level higher than a predetermined reference level and then falls, and the predetermined reference level is higher than the base level.

14. The display device according to claim 2, wherein: The pixel also includes: A ninth transistor is connected between the second node and the reference voltage line, and the ninth transistor is configured to receive a shift scan signal.

15. The display device according to claim 14, wherein: The display panel displays an image during a plurality of frames, and at least one frame among the plurality of frames includes a writing frame and at least one holding frame, wherein each of the first scanning signal, the second scanning signal, and the fourth scanning signal includes an activation period having an activation level within the write frame, and is maintained in an inactive state during the hold frame, and wherein each of the third scanning signal and the fifth scanning signal includes a first activation period having the activation level in each of the writing frame and the holding frame, and The shift scan signal includes a second activation period having the activation level in each of the write frame and the hold frame.

16. The display device according to claim 15, wherein: The first activation period is before the second activation period.

17. The display device according to claim 15, wherein: Each of the first emission control signal and the second emission control signal includes a disable period having a disable level within each of the write frame and the hold frame, and The first activation period and the second activation period overlap with the disable period of each of the first emission control signal and the second emission control signal.

18. The display device according to claim 15, wherein: The reference voltage applied through the reference voltage line has a voltage level higher than a voltage level of a driving voltage applied to the voltage line during the second active period.

19. The display device according to claim 18, wherein: The reference voltage has a base level during the write frame, and changes to a level higher than the base level after the second activation period during the hold frame.

20. A display device, wherein: The display device comprises: Display panel, including pixels, Wherein, the pixels include: Light emitting element; A first capacitor connected between the first node and the voltage line; a first transistor connected to the first node, the voltage line, and a second node; a second transistor connected between the first node and a third node, and the second transistor is configured to receive a first scan signal; a third transistor connected between the second node and the third node, and configured to receive a second scan signal; a second capacitor connected between the third node and the fourth node; a fourth transistor connected between the fourth node and the data line, and configured to receive a third scan signal; and The shift compensation transistor is connected between the second node and a reference voltage line, and the shift compensation transistor is configured to receive a shift scan signal.

21. The display device according to claim 20, wherein: The shift scan signal includes an activation period having an activation level, and The reference voltage applied through the reference voltage line has a voltage level higher than a voltage level of a driving voltage applied to the voltage line during the activation period.

22. The display device according to claim 20, wherein: The display panel displays an image during a plurality of frames, and at least one frame among the plurality of frames includes a writing frame and at least one holding frame, wherein each of the first scanning signal and the second scanning signal includes an activation period having an activation level within the write frame and remains in an inactive state during the hold frame, wherein the third scanning signal includes a first activation period having the activation level in each of the write frame and the hold frame, and The shift scan signal includes a second activation period having the activation level in each of the write frame and the hold frame.

23. The display device according to claim 22, wherein: The first activation period is before the second activation period.

24. The display device according to claim 22, wherein: The reference voltage applied through the reference voltage line has a voltage level higher than a voltage level of a driving voltage applied to the voltage line during the second active period.

25. The display device according to claim 24, wherein: The reference voltage has a base level during the write frame, and changes to a level higher than the base level after the second activation period during the hold frame.

Images