Gate driving unit and its driving method and display panel

Abstract

This invention discloses a gate driving unit, its driving method, and a display panel. The gate driving unit includes an input module, an output module, and a first output control module. The output terminal of the input module and the control terminal of the output module are connected to a first node. The output module outputs a gate driving signal in response to the voltage of the first node. The control terminal of the first output control module is connected to a touch control signal. The first output control module is connected between a first potential signal line and the output terminal of the output module. During the touch phase, the first output control module responds to the touch control signal, transmitting a first potential signal on the first potential signal line to the output terminal of the output module. During the display phase, it responds to the touch control signal to release the control of the potential at the output terminal of the output module. This solution can eliminate the brightness difference problem caused by the output difference of the gate driving signal at different locations, which is beneficial to improving the uniformity of display brightness and thus improving the display effect.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a gate driving unit and its driving method and a display panel. Background Technology

[0002] With the rapid development of display technology, touch display panels are widely used in various electronic products. Based on the placement of the touch sensor, touch display panels can be divided into architectures such as Out cell (the touch sensor is external to the display panel), On cell (the touch sensor is located on the display panel), and In cell (the touch sensor is integrated into the display panel).

[0003] In In-cell display panels, a gate drive circuit typically provides the corresponding gate drive signal to enable normal display functionality. However, during the touch phase, the gate drive circuit needs to stop transmitting the gate drive signal. Therefore, during the touch phase, the corresponding clock signal and reference voltage signal usually include a "touch pit" period to enable touch functionality. The signal during the "touch pit" period differs from the signal outside the "touch pit" period. Due to the existence of the "touch pit" period, the gate drive signal output by the gate drive circuit varies at different locations, causing brightness differences and resulting in horizontal lines on the display, affecting the display effect. Summary of the Invention

[0004] This invention provides a gate driving unit, its driving method, and a display panel to improve display performance.

[0005] According to one aspect of the present invention, a gate driving unit is provided, comprising:

[0006] An input module, the output of which is connected to the first node, is used to precharge the first node in response to a first control signal;

[0007] An output module, the control terminal of which is connected to the first node, is used to respond to the voltage output gate drive signal of the first node;

[0008] A first output control module is connected to a touch control signal at its control terminal. The first output control module is connected between a first potential signal line and the output terminal of the output module. The first output control module is used to respond to the touch control signal during the touch phase, transmit a first potential signal on the first potential signal line to the output terminal of the output module to stabilize the potential of the output terminal of the output module, and to release the control of the potential of the output terminal of the output module in response to the touch control signal during the display phase.

[0009] Optionally, the input terminal of the output module is connected to a first clock signal. During the touch control phase, the first clock signal is a synchronization signal for the touch signal. During the display phase, the first clock signal is a clock pulse signal.

[0010] During the touch phase, the first potential signal is a synchronization signal for the touch signal; during the display phase, the first potential signal is a fixed voltage signal.

[0011] Optionally, it may also include a second output control module and a first voltage control module;

[0012] The input terminal of the second output control module is connected to the first potential signal line, the output terminal of the second output control module is connected to the output terminal of the output module at the second node, the control terminal of the second output control module is connected to the second clock signal, and the second output control module is used to control the potential of the second node in response to the second clock signal;

[0013] The first voltage control module includes a drive control unit and a stabilization unit. The control terminal of the drive control unit is connected to the first node, the output terminal of the drive control unit is connected to the control terminal of the stabilization unit, the input terminal of the stabilization unit is connected to the first potential signal line, and the output terminal of the stabilization unit is connected to the first node and the second node respectively. The stabilization unit is used to control the potential of the first node and the potential of the second node in response to the voltage of the output terminal of the drive control unit when the output module is turned off.

[0014] It also includes a second voltage control module, the control terminal of which is connected to a second control signal, the input terminal of which is connected to a second potential signal line, and the output terminal of which is connected to the first node. The second voltage control module is used to transmit the second potential signal on the second potential signal line to the first node in response to the second control signal; wherein, the input module and the second voltage control module are time-division multiplexed.

[0015] Optionally, it further includes a third voltage control module, the control terminal of which is connected to the touch control signal, the input terminal of which is connected to the first potential signal line, and the output terminal of which is connected to the output terminal of the drive control unit. The third voltage control module is used to transmit the first potential signal to the output terminal of the drive control unit during the touch phase in order to maintain the voltage at the output terminal of the drive control unit and turn off the stabilization unit.

[0016] Optionally, the input module includes a first transistor, the output module includes a second transistor and a capacitor, the first output control module includes a third transistor, the second output control module includes a fourth transistor, the drive control unit includes a fifth transistor and a sixth transistor, the stabilization unit includes a seventh transistor and an eighth transistor, the second voltage control module includes a ninth transistor, and the third voltage control module includes a tenth transistor.

[0017] The gate of the first transistor is connected to the first control signal, the first terminal of the first transistor is connected to the third potential signal line, the second terminal of the first transistor is connected to the first node, the gate of the second transistor is connected to the first node, the first terminal of the second transistor is connected to the first clock signal, the second terminal of the second transistor is connected to the second node, and the capacitor is connected between the first node and the second node.

[0018] The gate of the third transistor is connected to the touch control signal, the first electrode of the third transistor is connected to the first potential signal line, and the second electrode of the third transistor is connected to the second node;

[0019] The gate of the fourth transistor is connected to the second clock signal, the first terminal of the fourth transistor is connected to the first potential signal line, and the second terminal of the fourth transistor is connected to the second node;

[0020] The first terminal and gate of the fifth transistor are both connected to the fourth potential signal line. The second terminal of the fifth transistor and the second terminal of the sixth transistor are connected to the third node. The first terminal of the sixth transistor is connected to the first potential signal line. The gate of the sixth transistor is connected to the first node. The gates of the seventh transistor and the eighth transistor are both connected to the third node. The first terminals of the seventh transistor and the eighth transistor are both connected to the first potential signal line. The second terminal of the seventh transistor is connected to the first node. The second terminal of the eighth transistor is connected to the second node.

[0021] The gate of the ninth transistor is connected to the second control signal, the first terminal of the ninth transistor is connected to the second potential signal line, and the second terminal of the ninth transistor is connected to the first node;

[0022] The gate of the tenth transistor is connected to the touch control signal, the first terminal of the tenth transistor is connected to the first potential signal line, and the second terminal of the tenth transistor is connected to the third node;

[0023] Wherein, the voltage value of the first potential signal transmitted on the first potential signal line is less than or equal to the voltage value of the second potential signal transmitted on the second potential signal line, the voltage value of the third potential signal transmitted on the third potential signal line is greater than the voltage value of the second potential signal, and the voltage value of the fourth potential signal transmitted on the fourth potential signal line is greater than the voltage value of the second potential signal and less than the voltage value of the third potential signal.

[0024] Optionally, it also includes a fourth voltage control module, which is used to control the potential of the first node during the touch phase to keep the output module on.

[0025] The fourth voltage control module includes a first subunit and a second subunit. The control terminal and input terminal of the first subunit are both connected to the touch control signal. The output terminal of the first subunit is connected to the input terminal of the second subunit. The output terminal and control terminal of the second subunit are both connected to the first node.

[0026] The first sub-unit includes an eleventh transistor, and the second sub-unit includes a twelfth transistor. The first terminal and the gate of the eleventh transistor are both connected to the touch control signal, and the second terminal of the eleventh transistor is connected to the first terminal of the twelfth transistor. The second terminal and the gate of the twelfth transistor are both connected to the first node.

[0027] According to another aspect of the present invention, a method for driving a gate driving unit is provided, comprising:

[0028] During the display phase, the control input module charges the first node in response to the first control signal of its own control terminal, and the control output module outputs the gate drive signal in response to the voltage of the first node.

[0029] During the touch control phase, the first output control module responds to the touch control signal of its own control terminal and transmits the first potential signal on the first potential signal line to the control terminal of the output module to stabilize the potential of the output terminal of the output module.

[0030] The input terminal of the input module is connected to a third potential signal line, and the input terminal of the output module is connected to a first clock signal. The gate driving unit further includes a second output control module, a first voltage control module, a second voltage control module, a third voltage control module, and a fourth voltage control module. The input terminal of the second output control module is connected to the first potential signal line, and the output terminal of the second output control module is connected to the output terminal of the output module at a second node. The control terminal of the second output control module is connected to a second clock signal. The first voltage control module includes a drive control unit and a stabilization unit. The control terminal of the drive control unit is connected to the first node, and the output terminal of the drive control unit is connected to the control terminal of the stabilization unit. The input terminal of the stabilization unit is connected to the first potential signal line. The output terminals of the first voltage control module are connected to the first node and the second node respectively. The control terminal of the second voltage control module is connected to the second control signal. The input terminal of the second voltage control module is connected to the second potential signal line. The output terminal of the second voltage control module is connected to the first node. The control terminal of the third voltage control module is connected to the touch control signal. The input terminal of the third voltage control module is connected to the first potential signal line. The output terminal of the third voltage control module is connected to the output terminal of the drive control unit. The fourth voltage control module includes a first sub-unit and a second sub-unit. The control terminal and the input terminal of the first sub-unit are both connected to the touch control signal. The output terminal of the first sub-unit is connected to the input terminal of the second sub-unit. The output terminal and the control terminal of the second sub-unit are both connected to the first node.

[0031] During the display phase, the driving method of the gate driving unit includes:

[0032] In the first sub-stage, the input module is controlled to transmit the third potential signal on the third potential signal line to the first node to precharge the first node, and the output module is controlled to output the first level pulse signal of the first clock signal.

[0033] In the second sub-stage, the first clock signal changes from a first level pulse signal to a second level pulse signal, controlling the output module to adjust the voltage of the first node according to the change of the first clock signal, and outputting the second level pulse signal of the first clock signal;

[0034] In the third sub-stage, the second voltage control module is controlled to transmit the second potential signal on the second potential signal line to the first node, the drive control unit is controlled to drive the stabilization unit to transmit the first potential signal on the first potential signal line to the first node according to the voltage of the first node, and the second output control module is controlled to transmit the first potential signal to the second node.

[0035] During the touch phase, the driving method of the gate driving unit includes:

[0036] During the touch control phase, the first output control module is controlled to transmit the first potential signal to the second node, the third voltage control module is controlled to transmit the first potential signal to the output terminal of the drive control unit, and the fourth voltage control module is controlled to transmit the touch control signal to the first node.

[0037] Optionally, a display cycle includes the display phase, the touch phase, and the blank phase, with the blank phase located between two adjacent display cycles;

[0038] During the touch phase and the blank phase, the potential of the touch control signal is the same, but different from the potential of the touch control signal during the display phase.

[0039] According to another aspect of the present invention, a display panel is provided, the display panel including a gate driving circuit, the gate driving circuit including a plurality of gate driving units provided in any embodiment of the present invention, the plurality of gate driving units being cascaded.

[0040] The technical solution provided by this invention provides a first output control module at the output end of the output module. During the touch phase, the first output control module responds to the touch control signal and transmits a first potential signal to the control end of the output module to control the potential of the gate driving signal. This ensures that the gate driving signals corresponding to all pixel rows in the plane are the same, all being the first potential signal. This eliminates the brightness difference problem caused by the output difference of the gate driving signal at different positions, which is beneficial to improving the uniformity of display brightness and thus improving the display effect.

[0041] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a schematic diagram of the structure of a gate driving unit provided in an embodiment of the present invention;

[0044] Figure 2 This is a schematic diagram of another gate driving unit provided in an embodiment of the present invention;

[0045] Figure 3 A schematic diagram of the driving waveform of a gate driving unit provided in an embodiment of the present invention;

[0046] Figure 4 This is a schematic diagram of another gate driving unit provided in an embodiment of the present invention;

[0047] Figure 5 This is a schematic diagram of another gate driving unit provided in an embodiment of the present invention;

[0048] Figure 6 This is a schematic diagram of another gate driving unit provided in an embodiment of the present invention;

[0049] Figure 7 A schematic diagram of the driving waveform of another gate driving unit provided in an embodiment of the present invention;

[0050] Figure 8 This is a schematic diagram of another gate driving unit provided in an embodiment of the present invention;

[0051] Figure 9 A flowchart illustrating a driving method for a gate driving unit provided in an embodiment of the present invention;

[0052] Figure 10 A flowchart of another driving method for a gate driving unit provided in an embodiment of the present invention;

[0053] Figure 11 A schematic diagram of the driving waveform of another gate driving unit provided in an embodiment of the present invention;

[0054] Figure 12 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0055] Figure 13 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0056] Figure 14 This is a waveform diagram of a clock signal provided in an embodiment of the present invention. Detailed Implementation

[0057] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0058] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0059] Figure 1 This is a schematic diagram of a gate driving unit provided in an embodiment of the present invention. This gate driving unit can be cascaded to form a gate driving circuit, and the gate driving circuit outputs gate driving signals stage by stage. (Reference) Figure 1 The gate driving unit provided in this embodiment includes:

[0060] Input module 110, the output terminal of input module 110 is connected to the first node N1, and input module 110 is used to precharge the first node N1 in response to the first control signal Gn-4;

[0061] Output module 120, the control terminal of output module 120 is connected to the first node N1, and output module 120 is used to output gate drive signal Gn in response to the voltage of the first node N1;

[0062] The first output control module 130 has its control terminal connected to the touch control signal TP-C. The first output control module 130 is connected between the first potential signal line and the output terminal of the output module 120. The first output control module 130 is used to respond to the touch control signal TP-C during the touch phase, transmit the first potential signal VGL1 on the first potential signal line to the output terminal of the output module 120 to stabilize the potential of the output terminal of the output module 120, and to respond to the touch control signal TP-C during the display phase to release the control of the potential of the output terminal of the output module 120.

[0063] During the touch phase, the output of the gate driving unit is typically paused by a stop signal, which can be a low-level or high-level signal. The current in the circuit is detected by the touch signal transmitted in the reference voltage signal (Vcom), thereby detecting the touch effect. However, during the touch phase, not all output modules 120 of the gate driving units corresponding to all row pixels are in the off state; some output modules 120 of the gate driving units corresponding to some row pixels are in the on state. This causes inconsistencies in the gate driving signals Gn between some rows, resulting in differences in the voltage of the lower pixel in the corresponding row. Consequently, horizontal lines appear during the touch phase, causing display defects.

[0064] In this embodiment, a first output control module 130 is provided at the output terminal of the output module 120. During the touch phase, the first output control module 130 is turned on by the touch control signal TP-C. The first output control module 130 transmits the first potential signal VGL1 on the first potential signal line to the output terminal of the output module 120, and pulls down the gate drive signal Gn to ensure that the gate drive signal Gn of all rows remains consistent. During the display phase, the first output control module 130 is turned off in response to the touch control signal TP-C, releasing the control of the potential at the output terminal of the output module 120, and the output module 120 outputs the gate drive signal Gn normally.

[0065] The technical solution provided by this invention provides a first output control module at the output end of the output module. During the touch phase, the first output control module responds to the touch control signal and transmits a first potential signal to the control end of the output module to control the potential of the gate driving signal. This ensures that the gate driving signals corresponding to all pixel rows in the plane are the same, all being the first potential signal. This eliminates the brightness difference problem caused by the output difference of the gate driving signal at different positions, which is beneficial to improving the uniformity of display brightness and thus improving the display effect.

[0066] Figure 2 This is a schematic diagram of another gate driving unit provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of the driving waveform of a gate driving unit provided in an embodiment of the present invention, with reference to... Figure 2 and Figure 3 Based on the above embodiments, optionally, the input terminal of the output module 120 is connected to a first clock signal CLK1. In the touch stage, the first clock signal CLK1 is the synchronization signal of the touch signal TP. In the display stage, the first clock signal CLK1 is a clock pulse signal. In the touch stage, the first potential signal VGL1 is the synchronization signal of the touch signal TP. In the display stage, the first potential signal VGL1 is a fixed voltage signal.

[0067] Specifically, during the display phase, the output module 120 transmits the first clock signal CLK1 to the output terminal of the output module 120 according to the voltage of the first node N1. The first potential signal VGL1 and the reference voltage signal Vcom are both fixed voltage signals so as to output the gate drive signal Gn.

[0068] During the touch phase, both the first clock signal CLK1 and the first potential signal VGL1 are synchronization signals for the touch signal TP within the reference voltage Vcom. This means the waveforms of the first clock signal CLK1 and the first potential signal VGL1 during the touch phase are identical to the waveform of the touch signal TP, which is beneficial for in-plane signal acquisition. When the touch phase begins, the first output control module 130 responds to the touch control signal TP-C and transmits the first potential signal VGL1 to the output terminal of the output module 120, pulling the gate drive signal Gn to the first potential signal VGL1. At this time, the gate drive signal Gn is the synchronization signal for the touch signal TP, eliminating the display unevenness caused by the difference in gate drive signals GN at different positions within the plane, thus helping to improve the abnormal problem of horizontal lines on the display.

[0069] Figure 4 This is a schematic diagram of another gate driving unit provided in an embodiment of the present invention, with reference to... Figure 4 Optionally, based on the above embodiments, the gate driving unit provided in this embodiment further includes a second output control module 140 and a first voltage control module 150. The input terminal of the second output control module 140 is connected to the first potential signal line, and the output terminal of the second output control module 140 and the output terminal of the output module 120 are connected to the second node N2. The control terminal of the second output control module 140 is connected to the second clock signal CLK2, and the second output control module 140 is used to control the potential of the second node N2 in response to the second clock signal CLK2.

[0070] Specifically, during the display phase, when the output module 120 responds to the voltage turn-off of the first node N1, the second output control module 140 can respond to the second clock signal CLK2 to turn on, thereby pulling the voltage of the second node N2 to the voltage of the first potential signal VGL1, thus maintaining the stability of the voltage of the second node N2, and thus ensuring the stable output of the gate drive signal Gn.

[0071] The first voltage control module 150 includes a drive control unit 1501 and a stabilization unit 1502. The control terminal of the drive control unit 1501 is connected to the first node N1, and the output terminal of the drive control unit 1501 is connected to the control terminal of the stabilization unit 1502. The input terminal of the stabilization unit 1502 is connected to the first potential signal line, and the output terminal of the stabilization unit 1502 is connected to the first node N1 and the second node N2 respectively. The stabilization unit 1502 is used to control the potential of the first node N1 and the potential of the second node N2 in response to the voltage at the output terminal of the drive control unit 1501 when the output module 120 is turned off.

[0072] Specifically, when the output module 120 responds to the voltage turn-off of the first node N1, the drive control unit 1501 responds to the voltage control stabilization unit 1502 of the first node N1 and turns on. The stabilization unit 1502 transmits the first potential signal VGL1 to the first node N1 to maintain the turn-off potential of the first node N1, ensuring a better turn-off of the output module 120. At the same time, the stabilization unit 1502 also transmits the first potential signal VGL1 to the second node N2 to further maintain the potential of the second node N2, thereby maintaining the stability of the gate drive signal Gn output.

[0073] When the output module 120 responds to the voltage of the first node N1 and turns on, the drive control unit 1501 responds to the voltage of the first node N1 and controls the stabilization unit 1502 to turn off.

[0074] Optionally, continue to refer to Figure 4 The gate driving unit also includes a second voltage control module 160. The control terminal of the second voltage control module 160 is connected to the second control signal Gn+4. The input terminal of the second voltage control module 160 is connected to the second potential signal line. The output terminal of the second voltage control module 160 is connected to the first node N1. The second voltage control module 160 is used to transmit the second potential signal VGL2 on the second potential signal line to the first node N1 in response to the second control signal Gn+4. The input module 110 and the second voltage control module 160 are turned on in a time-division multiplexing manner.

[0075] Specifically, when the input module 110 is turned on and the second voltage control module 160 is turned off, the input module 110 transmits the third potential signal VGH1 on the third potential signal line to the first node N1, and the output module 120 responds to the voltage turn-on of the first node N1. When the input module 110 is turned off and the second voltage control module 160 is turned on, the second voltage control module 160 transmits the second potential signal VGL2 to the first node N1, and the output module 120 responds to the voltage turn-off of the first node N1.

[0076] Figure 5 This is a schematic diagram of another gate driving unit provided in an embodiment of the present invention, with reference to... Figure 5Based on the above embodiments, optionally, the gate driving unit provided in this embodiment further includes a third voltage control module 170. The control terminal of the third voltage control module 170 is connected to the touch control signal TP-C. The input terminal of the third voltage control module 170 is connected to the first potential signal line. The output terminal of the third voltage control module 170 is connected to the output terminal of the drive control unit 1501. The third voltage control module 170 is used to transmit the first potential signal VGL1 to the output terminal of the drive control unit 1501 during the touch phase in order to maintain the voltage of the output terminal of the drive control unit 1501 and turn off the stabilization unit 1502.

[0077] Specifically, during the touch phase, the first node N1 is maintained at a conduction potential (e.g., a high potential), and the drive control unit 1501 responds to the potential of the first node N1 to control the stabilization unit 1502 to turn off. However, in the event of leakage in the first node N1, it is easy for the drive control unit 1501 to control the stabilization unit 1502 to turn on. In this embodiment, during the touch phase, the third voltage control module 170 responds to the touch control signal TP-C to turn on, transmitting the first potential signal VGL1 to the output terminal of the drive module 1501, thereby strengthening the voltage at the control terminal of the stabilization unit 1502, ensuring that the stabilization unit 1502 is in a turned-off state, avoiding interference with the voltage of the first node N1, and thus maintaining the stability of the voltage of the first node N1.

[0078] Figure 6 This is a schematic diagram of another gate driving unit provided in an embodiment of the present invention, with reference to... Figure 6 Based on the above embodiments, the input module 110 includes a first transistor Q1, the output module 120 includes a second transistor Q2 and a capacitor C1, the first output control module 130 includes a third transistor Q3, the second output control module 140 includes a fourth transistor Q4, the drive control unit 1501 includes a fifth transistor Q5 and a sixth transistor Q6, the stabilization unit 1502 includes a seventh transistor Q7 and an eighth transistor Q8, the second voltage control module 160 includes a ninth transistor Q9, and the third voltage control module 170 includes a tenth transistor Q10.

[0079] The gate of the first transistor Q1 is connected to the first control signal Gn-4, the first terminal of the first transistor Q1 is connected to the third potential signal line, the second terminal of the first transistor Q1 is connected to the first node N1, the gate of the second transistor Q2 is connected to the first node N1, the first terminal of the second transistor Q2 is connected to the first clock signal CLK1, the second terminal of the second transistor Q2 is connected to the second node N2, and the capacitor C1 is connected between the first node N1 and the second node N2.

[0080] The gate of the third transistor Q3 is connected to the contact control signal TP-C, the first terminal of the third transistor Q3 is connected to the first potential signal line, and the second terminal of the third transistor Q3 is connected to the second node N2; the gate of the fourth transistor Q4 is connected to the second clock signal CLK2, the first terminal of the fourth transistor Q4 is connected to the first potential signal line, and the second terminal of the fourth transistor Q4 is connected to the second node N2.

[0081] The first terminal and gate of the fifth transistor Q5 are both connected to the fourth potential signal line. The second terminal of the fifth transistor Q5 and the second terminal of the sixth transistor Q6 are connected to the third node N3. The first terminal of the sixth transistor Q6 is connected to the first potential signal line. The gate of the sixth transistor Q6 is connected to the first node N1. The gates of the seventh transistor Q7 and the eighth transistor Q8 are both connected to the third node N3. The first terminals of the seventh transistor Q7 and the eighth transistor Q8 are both connected to the first potential signal line. The second terminal of the seventh transistor Q7 is connected to the first node N1. The second terminal of the eighth transistor Q8 is connected to the second node N2.

[0082] The gate of the ninth transistor Q9 is connected to the second control signal Gn+4, the first terminal of the ninth transistor Q9 is connected to the second potential signal line, and the second terminal of the ninth transistor Q9 is connected to the first node N1; the gate of the tenth transistor Q10 is connected to the control signal TP-C, the first terminal of the tenth transistor Q10 is connected to the first potential signal line, and the second terminal of the tenth transistor Q10 is connected to the third node N3.

[0083] Specifically, the voltage value of the first potential signal VGL1 transmitted on the first potential signal line is less than or equal to the voltage value of the second potential signal VGL2 transmitted on the second potential signal line; the voltage value of the third potential signal VGH1 transmitted on the third potential signal line is greater than the voltage value of the second potential signal VGL2; and the voltage value of the fourth potential signal VGH2 transmitted on the fourth potential signal line is greater than the voltage value of the second potential signal VGL2 and less than the voltage value of the third potential signal VGH1.

[0084] Figure 7 This is a schematic diagram of the driving waveform of another gate driving unit provided in an embodiment of the present invention, which can be applied to... Figure 6 The gate drive unit shown is combined with Figure 6 and Figure 7 Taking an example where all transistors are N-type, the operation of the gate driving unit provided in this embodiment includes:

[0085] During the display phase:

[0086] In the first sub-stage (t1-t2), the first clock signal CLK1 is low, the second clock signal CLK2 is high, and the fourth transistor Q4 is turned on. The first transistor Q1 turns on in response to the first control signal Gn-4, and the ninth transistor Q9 turns off in response to the second control signal Gn+4. The first transistor Q1 transmits the third potential signal VGH1 to the first node N1, making the first node N1 high. The second transistor Q2 turns on and transmits the low level of the first clock signal CLK1 to the second node N2. Simultaneously, under the pull-down effect of the fourth transistor Q4, the second node N2 maintains a low output level, i.e., the output gate drive signal Gn is low. Here, Gn-N1on represents the gate drive signal Gn when the first node N1 is on, and Gn-N1off represents the gate drive signal Gn when the first node N1 is off.

[0087] In the second sub-stage (t2-t3), the second clock signal CLK2 transitions to a low level, the fourth transistor Q4 turns off, and the first clock signal CLK1 transitions to a high level. Under the bootstrap effect of capacitor C1, the voltage of the first node N1 is further pulled up to ensure that the second transistor Q2 is fully turned on. The second transistor Q2 transmits the high level of the first clock signal CLK1 to the second node N2, outputting a high level for the gate drive signal Gn. In addition, under the action of the first node N1, the sixth transistor Q6 turns on, pulling down the voltage of the third node N3 to ensure that the seventh transistor Q7 and the eighth transistor Q8 are turned off, thereby ensuring the stability of the voltage of the second node N2.

[0088] Optionally, the pull-down capability of the sixth transistor Q6 is stronger than that of the fifth transistor Q5, in order to better control the potential of the third node N3. For example, the channel width-to-length ratio of the sixth transistor Q6 is greater than that of the fifth transistor Q5.

[0089] In the third sub-stage, the period between time t3 and the touch stage, the ninth transistor Q9 turns on in response to the second control signal Gn+4, transmitting the second potential signal VGL2 to the first node N1. The first node N1 is at a low level, while the second transistor Q2 and the sixth transistor Q6 are off. Under the pull-up action of the fifth transistor Q5, the third node N3 is pulled high, and the seventh transistor Q7 and the eighth transistor Q8 turn on. The seventh transistor Q7 transmits the first potential signal VGL1 to the first node N1 to maintain its low potential, and the eighth transistor Q8 transmits the first potential signal VGL1 to the second node N2 to maintain its low potential, ensuring the stability of the gate drive signal Gn output. Simultaneously, the second clock signal CLK2 also periodically turns on the fourth transistor Q4 to further stabilize the potential of the second node N2.

[0090] During the touch phase, the third transistor Q3 and the tenth transistor Q10 are turned on in response to the touch control signal TP-C. The third transistor Q3 transmits the first potential signal VGL1 to the second node N2, pulling the gate drive signal Gn to the synchronization signal of the touch signal TP. Here, the touch control signal TP-C is a full-screen signal, and the gate drive signals Gn of all rows in the panel are pulled to the synchronization signal of the touch signal TP. This eliminates the brightness difference problem caused by the output difference of the gate drive signal Gn at different positions, which helps to improve the uniformity of display brightness and thus improve the display effect.

[0091] The tenth transistor Q10 transmits the first potential signal VGL1 to the third node N3, pulling down the voltage of the third node N3. This strengthens the gate voltages of the seventh transistor Q7 and the eighth transistor Q8, preventing the fifth transistor Q5 from remaining on under slow leakage current in the first node N1, which would cause the voltage of the third node N3 to rise, turning on the seventh transistor Q7 and the eighth transistor Q8 and pulling down the voltage of the first node N1. In this embodiment, by introducing the tenth transistor Q10, the gate voltages of the seventh transistor Q7 and the eighth transistor Q8 can be strengthened, preventing them from turning on and thus ensuring the stability of the voltage at the first node N1. Furthermore, the presence of the tenth transistor Q10 pulls down the voltage of the third node N3, reducing the time that the gates of the seventh transistor Q7 and the eighth transistor Q8 are subjected to the stress of the fourth potential signal VGH2. This helps increase the output capability of the seventh transistor Q7 and the eighth transistor Q8, thereby improving circuit stability.

[0092] Figure 8 This is a schematic diagram of another gate driving unit provided in an embodiment of the present invention, with reference to... Figure 8 Optionally, based on the above embodiments, a fourth voltage control module 180 is also included. The fourth voltage control module 180 is used to control the potential of the first node N1 during the touch phase to keep the output module 120 on. The fourth voltage control module 180 includes a first subunit 1801 and a second subunit 1802. The control terminal and input terminal of the first subunit 1801 are both connected to the touch control signal TP-C. The output terminal of the first subunit 1801 is connected to the input terminal of the second subunit 1802. The output terminal and control terminal of the second subunit 1802 are both connected to the first node N1.

[0093] Specifically, the first sub-unit 1801 includes an eleventh transistor Q11, and the second sub-unit 1802 includes a twelfth transistor Q12. The first terminal and gate of the eleventh transistor Q11 are both connected to the touch control signal TP-C, and the second terminal of the eleventh transistor Q11 is connected to the first terminal of the twelfth transistor Q12. The second terminal and gate of the twelfth transistor Q12 are both connected to the first node N1.

[0094] Combination Figure 7 During the touch phase, the eleventh transistor Q11 turns on in response to the high level of the touch control signal TP-C, and transmits the high level of the touch control signal TP-C to the first node N1 through the twelfth transistor Q12, so that the voltage of the first node N1 can be stably maintained at a high level, which can increase the high voltage holding capability of the first node N1 during the touch phase, so that the gate drive unit can be pulled up again in the subsequent display phase to output the gate drive signal Gn.

[0095] Optionally, in this embodiment, the high and low voltage levels of the touch control signal TP-C are adjustable. Taking an example where all transistors are N-type transistors, during the touch phase, the higher the voltage of the touch control signal TP-C, the stronger the conduction capability of the third transistor Q3 and the tenth transistor Q10. This is beneficial to improving the transmission quality of the first potential signal VGL1, so that the first potential signal VGL1 can be transmitted to the second node N2 and the third node N3 without attenuation, ensuring the stability of the voltages of the second node N2 and the third node N3, ensuring that the seventh transistor Q7 can be turned off better, so that the first potential signal VGL1 cannot leak to the first node N1 through the seventh transistor Q7, improving the stability of the voltage of the first node N1, and thus making the gate drive signal Gn more stable.

[0096] Similarly, during the touch phase, the higher the voltage of the touch control signal TP-C, the better the conduction capability of the eleventh transistor Q11, which is beneficial for achieving lossless transmission of the touch control signal TP-C. The twelfth transistor Q12 can then boost the voltage of the first node N1 to the high voltage of the touch control signal TP-C. That is, during the touch phase, the voltage of the first node N1 follows the high voltage of the touch control signal TP-C. By adjusting the voltage of the touch control signal TP-C, the voltage of the first node N1 is controlled, ensuring that the voltage of the first node N1 remains stably at the high level of the touch control signal TP-C throughout the entire touch phase, without decreasing over time.

[0097] When the touch phase ends, the touch control signal TP-C changes from high to low, and the third transistor Q3 and the tenth transistor Q10 turn off, disconnecting the first potential signal VGL1 from the second node N2 and the third node N3. At the same time, the eleventh transistor Q11 turns off, disconnecting the touch control signal TP-C from the first node N1, without affecting the transmission of subsequent signals, ensuring the normal operation of the gate drive unit.

[0098] It should be understood that because the gate of the twelfth transistor Q12 is connected to the first node N1, the high voltage of the touch control signal TP-C can only enter the first node N1 of the corresponding gate driving unit when the gate driving unit is outputting normally and the touch control signal TP-C simultaneously transitions to a high level. Simultaneously, during the touch phase, the gate driving units at non-touch pit locations have a low voltage at their corresponding first node N1, and the twelfth transistor Q12 is off. Therefore, even if the touch control signal TP-C is high, it cannot enter the first node N1 when the twelfth transistor Q12 is off. This ensures that the voltage of the first node N1 of the gate driving units at non-touch pit locations is unaffected, which helps improve the operational stability of the gate driving unit. The gate driving units at non-touch pit locations operate normally.

[0099] This invention also provides a method for driving a gate driving unit. Figure 9 This is a flowchart illustrating a driving method for a gate driving unit provided in an embodiment of the present invention. This method can be used to drive the gate driving unit provided in any of the above embodiments. (Refer to...) Figure 9 The method includes:

[0100] S110. During the display phase, the control input module charges the first node in response to the first control signal of its own control terminal, and the control output module outputs the gate drive signal in response to the voltage of the first node.

[0101] S120. During the touch control phase, the first output control module responds to the touch control signal of its own control terminal and transmits the first potential signal on the first potential signal line to the control terminal of the output module to stabilize the potential of the output terminal of the output module.

[0102] The technical solution provided by this invention provides a first output control module at the output end of the output module. During the touch phase, the first output control module responds to the touch control signal and transmits a first potential signal to the control end of the output module to control the potential of the gate driving signal. This ensures that the gate driving signals corresponding to all pixel rows in the plane are the same, all being the first potential signal. This eliminates the brightness difference problem caused by the output difference of the gate driving signal at different positions, which is beneficial to improving the uniformity of display brightness and thus improving the display effect.

[0103] Combination Figure 8In this embodiment, the input terminal of the input module 110 is connected to the third potential signal line, and the input terminal of the output module 120 is connected to the first clock signal CLK1. The gate driving unit also includes a second output control module 140, a first voltage control module 150, a second voltage control module 160, a third voltage control module 170, and a fourth voltage control module 180. The input terminal of the second output control module 140 is connected to the first potential signal line, and the output terminal of the second output control module 140 and the output terminal of the output module 120 are connected to the second node N2. The control terminal of the second output control module 140 is connected to the second clock signal CLK2. The first voltage control module 150 includes a drive control unit 1501 and a stabilization unit 1502. The control terminal of the drive control unit 1501 is connected to the first node N1, and the output terminal of the drive control unit 1501 is connected to the control terminal of the stabilization unit 1502. The input terminal of the stabilization unit 1502 is connected to the first potential signal line. The output terminal of unit 1502 is connected to the first node N1 and the second node N2 respectively. The control terminal of the second voltage control module 160 is connected to the second control signal Gn-4. The input terminal of the second voltage control module 160 is connected to the second potential signal line. The output terminal of the second voltage control module 160 is connected to the first node N1. The control terminal of the third voltage control module 170 is connected to the touch control signal TP-C. The input terminal of the third voltage control module 170 is connected to the first potential signal line. The output terminal of the third voltage control module 170 is connected to the output terminal of the drive control unit 1501 (i.e., the third node N3). The fourth voltage control module 180 includes a first subunit 1801 and a second subunit 1802. The control terminal and the input terminal of the first subunit 1801 are both connected to the touch control signal TP-C. The output terminal of the first subunit 1801 is connected to the input terminal of the second subunit 1802. The output terminal and the control terminal of the second subunit 1802 are both connected to the first node N1.

[0104] Figure 10 A flowchart of another gate driving unit driving method provided in an embodiment of the present invention is shown below. Figure 10 During the display phase, the driving method for the gate driving unit provided in this embodiment of the invention specifically includes:

[0105] S1101 In the first sub-stage, the control input module transmits the third potential signal on the third potential signal line to the first node to precharge the first node, and the control output module outputs the first level pulse signal of the first clock signal.

[0106] S1102. In the second sub-stage, the first clock signal changes from a first level pulse signal to a second level pulse signal. The control output module adjusts the voltage of the first node according to the change of the first clock signal and outputs the second level pulse signal of the first clock signal.

[0107] S1103. In the third sub-stage, the second voltage control module is controlled to transmit the second potential signal on the second potential signal line to the first node, the drive control unit is controlled to drive the stabilization unit according to the voltage of the first node to transmit the first potential signal on the first potential signal line to the first node, and the second output control module is controlled to transmit the first potential signal to the second node.

[0108] During the touch control phase, the driving method for the gate driving unit provided in this embodiment of the invention specifically includes:

[0109] S1201. During the touch control phase, the first output control module is controlled to transmit the first potential signal to the second node, the third voltage control module is controlled to transmit the first potential signal to the output terminal of the drive control unit, and the fourth voltage control module is controlled to transmit the touch control signal to the first node.

[0110] Among them, the first level pulse signal of the first clock signal CLK1 can be a low level signal, and the second level pulse signal can be a high level signal. Figure 10 The specific working process of the driving method shown can be referred to in the above embodiments. Figures 6 to 8 The relevant descriptions are the same, and they have the same beneficial effects, so they will not be repeated here.

[0111] Figure 11 This is a schematic diagram of the driving waveform of another gate driving unit provided in an embodiment of the present invention, with reference to... Figure 11 Within a display cycle, there are a display phase, a touch phase, and a blank phase, with the blank phase located between two adjacent display cycles. During the touch phase and the blank phase, the potential of the touch control signal TP-C is the same, but different from the potential of the touch control signal TP-C during the display phase. That is, during the non-display phases (touch phase and blank phase), the touch control signal TP-C is pulled high, causing the gate drive signal Gn during the non-display phase to be pulled down to the first potential signal VGL1, effectively clearing the gate drive signal Gn once. This helps reduce circuit noise and improve circuit stability.

[0112] in, Figure 11 The driving waveform shown is also applicable to Figure 6 and Figure 8 The gate drive unit shown has the same working process and beneficial effects.

[0113] Optionally, embodiments of the present invention also provide a display panel. Figure 12 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, with reference to... Figure 12The display panel 200 includes a gate driving circuit 300, which includes gate driving units provided in any embodiment of the present invention. Multiple gate driving units are cascaded to output gate driving signals stage by stage. Each stage of the gate driving unit is connected to a gate signal line GL to transmit the gate driving signal to the pixels in the panel via the gate signal line GL.

[0114] Combination Figure 8 In this embodiment, the output terminal of the nth-stage gate driving unit (i.e., the output terminal of the output module 120) is connected to the control terminal of the input module 110 of the (n-4)th-stage gate driving unit, and also to the control terminal of the second voltage control module 160 of the (n+4)th-stage gate driving unit. The nth-stage gate driving unit refers to the gate driving unit following the first four stages. The control terminals of the input modules 110 of the first four gate driving units can be connected to the same control signal, and the control terminals of the second voltage control module 160 of the first four gate driving units can also be connected to the same control signal.

[0115] Figure 13 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, with reference to... Figure 13 The gate driving unit 301 includes a first clock signal terminal SCK1 and a second clock signal terminal SCK2. The first clock signal terminal SCK1 is connected to the input terminal of the output module 120, and the second clock signal terminal SCK2 is connected to the control terminal of the second output control module 140.

[0116] The display panel also includes a first clock signal line CL1, a second clock signal line CL2, a third clock signal line CL3, and a fourth clock signal line CL4. The first clock signal line CL1 is used to transmit clock signal S1, the second clock signal line CL2 is used to transmit clock signal S2, the third clock signal line CL3 is used to transmit clock signal S3, and the fourth clock signal line CL4 is used to transmit clock signal S4. Figure 14 This is a waveform diagram of a clock signal provided in an embodiment of the present invention. The waveforms of clock signals S1 to S4 are as follows: Figure 14 As shown, clock signals S1 to S4 can be delayed by a quarter of a cycle in sequence.

[0117] The first clock signal terminal SCK1 of the first-stage gate driving unit 301 is connected to the second clock signal line CL2, the second clock signal terminal SCK2 is connected to the fourth clock signal line CL4, the clock signal S2 is used as the first clock signal CLK1 and connected to the input terminal of the output module 120, and the clock signal S4 is used as the second clock signal CLK2 and connected to the control terminal of the second output control module 140.

[0118] The first clock signal terminal SCK1 of the second-stage gate drive unit 301 is connected to the third clock signal line CL3, the second clock signal terminal SCK2 is connected to the first clock signal line CL1, the clock signal S3 is used as the first clock signal CLK1 and connected to the input terminal of the output module 120, and the clock signal S1 is used as the second clock signal CLK2 and connected to the control terminal of the second output control module 140.

[0119] The first clock signal terminal SCK1 of the third-stage gate drive unit 301 is connected to the fourth clock signal line CL4, the second clock signal terminal SCK2 is connected to the second clock signal line CL2, the clock signal S4 is used as the first clock signal CLK1 and connected to the input terminal of the output module 120, and the clock signal S2 is used as the second clock signal CLK2 and connected to the control terminal of the second output control module 140.

[0120] The first clock signal terminal SCK1 of the fourth-stage gate drive unit 301 is connected to the first clock signal line CL1, the second clock signal terminal SCK2 is connected to the third clock signal line CL3, the clock signal S1 is used as the first clock signal CLK1 and connected to the input terminal of the output module 120, and the clock signal S3 is used as the second clock signal CLK2 and connected to the control terminal of the second output control module 140.

[0121] The clock signal lines connected to the first clock signal terminal SCK1 and the second clock signal terminal SCK2 of the fifth-stage gate driving unit 301 are the same as those connected to the first clock signal terminal SCK1 and the second clock signal terminal SCK2 of the first-stage gate driving unit 301. That is, every four stages of gate driving units form a repeating cycle to achieve step-by-step output of gate driving signals.

[0122] In this embodiment, only the connection method of the multi-level gate driving unit 301 is given as an example. The specific connection architecture can be referred to the relevant description in the related technology, and will not be repeated here.

[0123] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0124] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A gate driving unit, characterized in that, include: An input module, the output of which is connected to the first node, is used to precharge the first node in response to a first control signal; An output module, the control terminal of which is connected to the first node, is used to respond to the voltage output gate drive signal of the first node; A first output control module is connected to a touch control signal at its control terminal. The first output control module is connected between a first potential signal line and the output terminal of the output module. The first output control module is used to respond to the touch control signal during the touch phase, transmit the first potential signal on the first potential signal line to the output terminal of the output module to stabilize the potential of the output terminal of the output module, and to release the control of the potential of the output terminal of the output module in response to the touch control signal during the display phase. The second output control module has its input terminal connected to the first potential signal line, its output terminal connected to the output terminal of the first output module at the second node, and its control terminal connected to the second clock signal. The second output control module is used to control the potential of the second node in response to the second clock signal. A first voltage control module includes a drive control unit and a stabilization unit. The control terminal of the drive control unit is connected to the first node, and the output terminal of the drive control unit is connected to the control terminal of the stabilization unit. The input terminal of the stabilization unit is connected to the first potential signal line, and the output terminal of the stabilization unit is connected to the first node and the second node respectively. The stabilization unit is used to control the potential of the first node and the potential of the second node in response to the voltage at the output terminal of the drive control unit when the output module is turned off. The third voltage control module has its control terminal connected to the touch control signal, its input terminal connected to the first potential signal line, and its output terminal connected to the output terminal of the drive control unit. The third voltage control module is used to transmit the first potential signal to the output terminal of the drive control unit during the touch phase in order to maintain the voltage at the output terminal of the drive control unit and turn off the stabilization unit.

2. The gate driving unit according to claim 1, characterized in that, The input terminal of the output module is connected to a first clock signal. During the touch control phase, the first clock signal is a synchronization signal for the touch signal. During the display phase, the first clock signal is a clock pulse signal. During the touch phase, the first potential signal is a synchronization signal for the touch signal; during the display phase, the first potential signal is a fixed voltage signal.

3. The gate driving unit according to claim 1, characterized in that, The gate driving unit further includes a second voltage control module. The control terminal of the second voltage control module is connected to a second control signal, the input terminal of the second voltage control module is connected to a second potential signal line, and the output terminal of the second voltage control module is connected to the first node. The second voltage control module is used to transmit the second potential signal on the second potential signal line to the first node in response to the second control signal. The input module and the second voltage control module are time-division multiplexed.

4. The gate driving unit according to claim 3, characterized in that, The input module includes a first transistor, the output module includes a second transistor and a capacitor, the first output control module includes a third transistor, the second output control module includes a fourth transistor, the drive control unit includes a fifth transistor and a sixth transistor, the stabilization unit includes a seventh transistor and an eighth transistor, the second voltage control module includes a ninth transistor, and the third voltage control module includes a tenth transistor. The gate of the first transistor is connected to the first control signal, the first terminal of the first transistor is connected to the third potential signal line, the second terminal of the first transistor is connected to the first node, the gate of the second transistor is connected to the first node, the first terminal of the second transistor is connected to the first clock signal, the second terminal of the second transistor is connected to the second node, and the capacitor is connected between the first node and the second node. The gate of the third transistor is connected to the touch control signal, the first electrode of the third transistor is connected to the first potential signal line, and the second electrode of the third transistor is connected to the second node; The gate of the fourth transistor is connected to the second clock signal, the first terminal of the fourth transistor is connected to the first potential signal line, and the second terminal of the fourth transistor is connected to the second node; The first terminal and gate of the fifth transistor are both connected to the fourth potential signal line. The second terminal of the fifth transistor and the second terminal of the sixth transistor are connected to the third node. The first terminal of the sixth transistor is connected to the first potential signal line. The gate of the sixth transistor is connected to the first node. The gates of the seventh transistor and the eighth transistor are both connected to the third node. The first terminals of the seventh transistor and the eighth transistor are both connected to the first potential signal line. The second terminal of the seventh transistor is connected to the first node. The second terminal of the eighth transistor is connected to the second node. The gate of the ninth transistor is connected to the second control signal, the first terminal of the ninth transistor is connected to the second potential signal line, and the second terminal of the ninth transistor is connected to the first node; The gate of the tenth transistor is connected to the touch control signal, the first terminal of the tenth transistor is connected to the first potential signal line, and the second terminal of the tenth transistor is connected to the third node; Wherein, the voltage value of the first potential signal transmitted on the first potential signal line is less than or equal to the voltage value of the second potential signal transmitted on the second potential signal line, the voltage value of the third potential signal transmitted on the third potential signal line is greater than the voltage value of the second potential signal, and the voltage value of the fourth potential signal transmitted on the fourth potential signal line is greater than the voltage value of the second potential signal and less than the voltage value of the third potential signal.

5. The gate driving unit according to claim 1, characterized in that, It also includes a fourth voltage control module, which is used to control the potential of the first node during the touch phase to keep the output module on. The fourth voltage control module includes a first subunit and a second subunit. The control terminal and input terminal of the first subunit are both connected to the touch control signal. The output terminal of the first subunit is connected to the input terminal of the second subunit. The output terminal and control terminal of the second subunit are both connected to the first node. The first sub-unit includes an eleventh transistor, and the second sub-unit includes a twelfth transistor. The first terminal and the gate of the eleventh transistor are both connected to the touch control signal, and the second terminal of the eleventh transistor is connected to the first terminal of the twelfth transistor. The second terminal and the gate of the twelfth transistor are both connected to the first node.

6. A driving method for a gate driving unit, characterized in that, include: During the display phase, the control input module charges the first node in response to the first control signal of its own control terminal, and the control output module outputs the gate drive signal in response to the voltage of the first node. During the touch phase, the first output control module responds to the touch control signal of its own control terminal and transmits the first potential signal on the first potential signal line to the control terminal of the output module to stabilize the potential of the output terminal of the output module. The gate driving unit further includes a second output control module, a first voltage control module, and a third voltage control module. The input terminal of the second output control module is connected to the first potential signal line, and the output terminal of the second output control module is connected to the output terminal of the output module at the second node. The control terminal of the second output control module is connected to a second clock signal, and the second output control module is used to control the potential of the second node in response to the second clock signal. The first voltage control module includes a drive control unit and a stabilization unit. The control terminal of the drive control unit is connected to the first node, and the output terminal of the drive control unit is connected to the control terminal of the stabilization unit. The input terminal of the stabilization unit is connected to the first potential signal line, and the output terminal of the stabilization unit is connected to both the first node and the second node. The stabilization unit is used to control the potential of the first node and the potential of the second node in response to the voltage at the output terminal of the drive control unit when the output module is turned off. The control terminal of the third voltage control module is connected to the touch control signal, the input terminal of the third voltage control module is connected to the first potential signal line, and the output terminal of the third voltage control module is connected to the output terminal of the drive control unit. During the touch phase, the driving method of the gate driving unit includes: During the touch control phase, the first output control module is controlled to transmit the first potential signal to the second node, and the third voltage control module is controlled to transmit the first potential signal to the output terminal of the drive control unit to maintain the voltage at the output terminal of the drive control unit and turn off the stabilization unit.

7. The driving method for the gate driving unit according to claim 6, characterized in that, The input terminal of the input module is connected to a third potential signal line, and the input terminal of the output module is connected to a first clock signal. The gate driving unit further includes a second voltage control module and a fourth voltage control module. The control terminal of the second voltage control module is connected to a second control signal, the input terminal of the second voltage control module is connected to the second potential signal line, and the output terminal of the second voltage control module is connected to the first node. The fourth voltage control module includes a first sub-unit and a second sub-unit. The control terminal and the input terminal of the first sub-unit are both connected to the touch control signal, the output terminal of the first sub-unit is connected to the input terminal of the second sub-unit, and the output terminal and the control terminal of the second sub-unit are both connected to the first node. During the display phase, the driving method of the gate driving unit includes: In the first sub-stage, the input module is controlled to transmit the third potential signal on the third potential signal line to the first node to precharge the first node, and the output module is controlled to output the first level pulse signal of the first clock signal. In the second sub-stage, the first clock signal changes from a first level pulse signal to a second level pulse signal, controlling the output module to adjust the voltage of the first node according to the change of the first clock signal, and outputting the second level pulse signal of the first clock signal; In the third sub-stage, the second voltage control module is controlled to transmit the second potential signal on the second potential signal line to the first node, the drive control unit is controlled to drive the stabilization unit to transmit the first potential signal on the first potential signal line to the first node according to the voltage of the first node, and the second output control module is controlled to transmit the first potential signal to the second node. During the touch phase, the driving method of the gate driving unit further includes: During the touch control phase, the fourth voltage control module is controlled to transmit the touch control signal to the first node.

8. The driving method for the gate driving unit according to claim 6, characterized in that, Within a display cycle, the display phase, the touch phase, and the blank phase are included, with the blank phase located between two adjacent display cycles; During the touch phase and the blank phase, the potential of the touch control signal is the same, but different from the potential of the touch control signal during the display phase.

9. A display panel, characterized in that, It includes a gate driving circuit, which includes a plurality of gate driving units as described in any one of claims 1-5, wherein the plurality of gate driving units are cascaded together.

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