Shift register and display panel

Abstract

The invention relates to a shift register and a display panel. The shift register comprises a first input module which comprises a first node, is electrically connected with an input signal line and a first control signal line and is configured to be controlled by a first control signal on the first control signal line to transmit the input signal on the input signal line to the first node; and the first output module comprises a first output end, is electrically connected with a correction voltage line and the first node and is configured to be controlled by the potential of the first node and the correction voltage on the correction voltage line, and a first scanning driving signal with a first effective potential or a first failure potential is output at the first output end. By adopting the scheme, the shift register capable of stably outputting the scanning driving signal can be realized.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a shift register and a display panel. Background Art

[0002] The display panel includes a plurality of pixel circuits distributed in an array in a display area and a shift register in a non-display area. The shift register can provide corresponding scanning drive signals for corresponding pixel circuits.

[0003] However, the stability of the scan driving signal provided by the shift register in the conventional technology is poor, which will affect the display performance of the display panel. Summary of the invention

[0004] Based on this, it is necessary to provide a shift register capable of stably outputting a scan drive signal to address the above technical issues, thereby improving a display panel with improved display performance.

[0005] In a first aspect, the present application provides a shift register, comprising:

[0006] A first input module includes a first node, is electrically connected to an input signal line and a first control signal line, and is configured to be controlled by a first control signal on the first control signal line to transmit an input signal on the input signal line to the first node;

[0007] The first output module includes a first output terminal, which is electrically connected to the correction voltage line and the first node, and is configured to be controlled by the potential of the first node and the correction voltage on the correction voltage line, and output a first scanning drive signal with a first effective potential or a first failure potential at the first output terminal.

[0008] The above-mentioned shift register includes a first input module and a first output module, wherein the first input module includes a first node, and is electrically connected to an input signal line and a first control signal line, and is configured to be controlled by a first control signal on the first control signal line to transmit an input signal on the input signal line to the first node; the first output module includes a first output terminal, and is electrically connected to a correction voltage line and a first node, and is configured to be controlled by a potential of the first node and a correction voltage on the correction voltage line, and output a first scanning drive signal having a first effective potential or a first failure potential at the first output terminal. By controlling the potential of the first node and the correction voltage on the correction voltage line of the first output module (for example, applying the correction voltage to the bottom gate of the transistor in the first output module), the PN junction of the transistor has a reverse bias relative to the substrate, so that the negative charge in the conductive channel moves to the depletion region, reducing the conductivity of the conductive channel, that is, the threshold voltage of the transistor is negatively biased to offset the amount of positive shift of the threshold voltage caused by the transistor working for a long time. Therefore, by adjusting the correction voltage, the gate and the source of the transistor are turned on at a constant voltage difference at different time periods, so that the process of the first scan drive signal "jumping from the first failure potential to the first effective potential" or "jumping from the first effective potential to the first failure potential" remains stable. Therefore, the first output module is configured to be controlled by the potential of the first node and the correction voltage on the correction voltage line, and can stably output the first scan drive signal.

[0009] In one embodiment, the first output module is also electrically connected to the first power signal line and the second power signal line, and is configured as follows:

[0010] When the first node is controlled by the input signal to have a first potential, the first power signal on the first power signal line is output at the first output terminal as the first scan drive signal having the first effective potential;

[0011] When the first node is not controlled by the input signal and is maintained at the first potential, the first power supply signal is output at the first output terminal as the first scan drive signal having the first effective potential; and

[0012] When the first node has a second potential under the control of the input signal, the second power signal on the second power signal line is outputted at the first output terminal as the first scan driving signal having the first failure potential.

[0013] In one embodiment, the first output module comprises a first indium gallium zinc oxide transistor, wherein:

[0014] The first electrode of the first InGaZnO transistor is electrically connected to the second power signal line, the second electrode of the first InGaZnO transistor is electrically connected to the first output terminal, the first control terminal of the first InGaZnO transistor is electrically connected to the first node, and the second control terminal of the first InGaZnO transistor is electrically connected to the correction voltage line;

[0015] Preferably, the threshold voltage of the first InGaZnO transistor in the first driving cycle is equal to the threshold voltage of the first InGaZnO transistor in the nth driving cycle, where n is greater than 1;

[0016] Preferably, from the first driving cycle to the nth driving cycle, the voltage value of the correction voltage gradually increases;

[0017] Preferably, the first InGaZnO transistor is an N-type transistor;

[0018] Preferably, the first InGaZnO transistor is disposed on a substrate, the second control end of the first InGaZnO transistor is located on a side of the active layer of the first InGaZnO transistor facing the substrate, and the first control end of the first InGaZnO transistor is located on a side of the active layer of the first InGaZnO transistor facing away from the substrate;

[0019] Preferably, the orthographic projection of the second control terminal of the first InGaZnO transistor on the substrate covers the orthographic projection of the active layer of the first InGaZnO transistor on the substrate;

[0020] Preferably, the first output module further comprises a first switching transistor, wherein:

[0021] A first electrode of the first switch transistor is electrically connected to the first power signal line, a second electrode of the first switch transistor is electrically connected to the first output terminal, and a control terminal of the first switch transistor is electrically connected to the first node;

[0022] Preferably, the first switch transistor is a P-type transistor.

[0023] In one embodiment, it also includes:

[0024] a second input module, comprising a second node, electrically connected to the first power signal line, the second power signal line and the first node, and configured to be controlled by the potential of the first node to transmit the first power signal or the second power signal to the second node;

[0025] Preferably, the second input module is configured to: transmit the first power signal to the second node when the first node has the first potential; and transmit the second power signal to the second node when the first node has the second potential;

[0026] Preferably, the second input module comprises a second indium gallium zinc oxide transistor, wherein:

[0027] The first electrode of the second InGaZnO transistor is electrically connected to the second node, the second electrode of the second InGaZnO transistor is electrically connected to the second power signal line, the first control terminal of the second InGaZnO transistor is electrically connected to the first node, and the second control terminal of the second InGaZnO transistor is electrically connected to the correction voltage line;

[0028] Preferably, a threshold voltage of the second InGaZnO transistor in the first driving cycle is equal to a threshold voltage of the second InGaZnO transistor in the nth driving cycle;

[0029] Preferably, the second indium gallium zinc oxide transistor is an N-type transistor;

[0030] Preferably, the second indium gallium zinc oxide transistor is disposed on the substrate, the second control end of the second indium gallium zinc oxide transistor is located on a side of the active layer of the second indium gallium zinc oxide transistor facing the substrate, and the first control end of the second indium gallium zinc oxide transistor is located on a side of the active layer of the second indium gallium zinc oxide transistor facing away from the substrate;

[0031] Preferably, the orthographic projection of the second control terminal of the second InGaZnO transistor on the substrate covers the orthographic projection of the active layer of the second InGaZnO transistor on the substrate;

[0032] Preferably, the second input module further comprises a second switching transistor, wherein:

[0033] A first electrode of the second switch transistor is electrically connected to the second node, a second electrode of the second switch transistor is electrically connected to the first power signal line, and a control terminal of the second switch transistor is electrically connected to the first node;

[0034] Preferably, the second switch transistor is a P-type transistor;

[0035] Preferably, the circuit structure of the second input module is the same as the circuit structure of the first output module.

[0036] In one embodiment, it also includes:

[0037] a second output module, comprising a second output terminal, electrically connected to a second control signal line, the first power signal line, the first node and the second node, and configured to be controlled by the potential of the first node and the potential of the second node, and output a second scan drive signal having a second effective potential or a second failure potential at the second output terminal;

[0038] Preferably, the second output module is configured as follows:

[0039] When the first node is controlled by the input signal to have the first potential, the second control signal having the second potential on the second control signal line is output at the second output end as the second scan drive signal having the second failure potential under the control of the first potential of the first node;

[0040] When the first node is not controlled by the input signal and is maintained at the first potential, the second control signal having the first potential on the second control signal line is output at the second output terminal as the second scan drive signal having the second effective potential under the control of the first potential of the first node; and

[0041] When the first node is controlled by the input signal to have the second potential, the first power signal on the first power signal line is output at the second output end as the second scan drive signal having the second failure potential under the control of the second power signal transmitted to the second node;

[0042] Preferably, the first control signal and the second control signal are inverted signals.

[0043] In one embodiment, the second output module includes:

[0044] a third switch transistor, wherein a first electrode of the third switch transistor is electrically connected to the second control signal line, a second electrode of the third switch transistor is electrically connected to the second output terminal, and a control terminal of the third switch transistor is electrically connected to the first node;

[0045] a fourth switch transistor, wherein a first electrode of the fourth switch transistor is electrically connected to the second output terminal, a second electrode of the fourth switch transistor is electrically connected to the first power signal line, and a control terminal of the fourth switch transistor is electrically connected to the second node;

[0046] A first capacitor connected between the second output terminal and the first node;

[0047] Preferably, the first capacitor is configured to keep the potential of the first node at the first potential when the first node is not controlled by the input signal.

[0048] In one embodiment, the first input module comprises an input unit, the input unit comprises a fifth switch transistor, wherein:

[0049] The first electrode of the fifth switch transistor serves as the first node, the second electrode of the fifth switch transistor is electrically connected to the input signal line, and the control end of the fifth switch transistor is electrically connected to the first control signal line.

[0050] In one embodiment, the first input module further includes a voltage stabilizing unit, and the voltage stabilizing unit includes a sixth switch transistor, wherein:

[0051] A first electrode of the sixth switch transistor is electrically connected to the second output module, a second electrode of the sixth switch transistor is electrically connected to the first node, and a control end of the sixth switch transistor is electrically connected to the second power signal line;

[0052] Preferably, the sixth switch transistor is configured to be controlled by the second power signal on the second power signal line to maintain a conducting state.

[0053] In one embodiment, the first input module further includes an initialization unit, wherein:

[0054] The initialization unit is electrically connected to the first node, the second node, the second control signal line and the first power signal line, and the initialization unit is configured as follows:

[0055] In the initialization stage, the first power signal on the first power signal line is transmitted to the first node under the control of the second power signal transmitted to the second node and the second control signal having the first potential on the second control signal line, so that the first output module outputs the first scan drive signal having the first failure potential at the first output terminal, and the second output terminal of the second output module and the second control signal line are in a disconnected state;

[0056] Preferably, in the initialization stage, the second output module is configured to: under the control of the second power signal transmitted to the second node, output the first power signal on the first power signal line as the second scan drive signal having the second failure potential at the second output end;

[0057] Preferably, the initialization unit comprises:

[0058] a seventh switch transistor, wherein a first electrode of the seventh switch transistor is electrically connected to the first node, and a control terminal of the seventh switch transistor is electrically connected to the second control signal line;

[0059] An eighth switch transistor, wherein a first electrode of the eighth switch transistor is electrically connected to a second electrode of the seventh switch transistor, a second electrode of the eighth switch transistor is electrically connected to the first power signal line, and a control end of the eighth switch transistor is electrically connected to the second node.

[0060] In a second aspect, the present application further provides a display panel, comprising a shift register as described in any one of the first aspects.

[0061] The above-mentioned display panel includes a shift register as described in any one of the first aspects, and by controlling the potential of the first node and the correction voltage on the correction voltage line of the first output module (for example, applying the correction voltage to the bottom gate of the transistor in the first output module), the PN junction of the transistor has a reverse bias relative to the substrate, so that the negative charge in the conductive channel moves to the depletion region, reducing the conductivity of the conductive channel, that is, the threshold voltage of the transistor is negatively biased to offset the amount of positive shift of the threshold voltage caused by the transistor working for a long time. Therefore, by adjusting the correction voltage, the gate and the source of the transistor are turned on at a constant voltage difference at different time periods, so that the process of the first scanning drive signal "jumping from the first failure potential to the first effective potential" or "jumping from the first effective potential to the first failure potential" remains stable, and then the opening or closing of the corresponding transistor in the pixel circuit electrically connected to it is also maintained stable, so as to avoid the occurrence of poor display conditions such as afterimage and smear on the display panel, thereby improving the display performance of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0063] FIG1 is a threshold voltage variation curve diagram of an N-type InGaZnO transistor in the related art;

[0064] FIG2 is a simulation diagram of a scan driving signal output by an output module under the control of the potential of a corresponding node of an N-type InGaZnO transistor in the related art;

[0065] FIG3 is a schematic diagram of a structure of a shift register according to an embodiment of the present invention;

[0066] FIG4 is a second schematic diagram of the structure of a shift register in one embodiment;

[0067] FIG5 is a curve diagram showing a change in the threshold voltage of a first InGaZnO transistor as a function of a correction voltage in one embodiment;

[0068] FIG6 is a curve diagram showing a change in the threshold voltage of a first InGaZnO transistor as a function of a correction voltage in another embodiment;

[0069] FIG7 is a third schematic diagram of the structure of a shift register in one embodiment;

[0070] FIG8 is a fourth schematic diagram of the structure of a shift register in one embodiment;

[0071] FIG9 is a timing diagram of the operation of the shift register shown in FIG8 in one embodiment;

[0072] FIG10 is a schematic diagram of the structure of a first indium gallium zinc oxide transistor in one embodiment;

[0073] FIG11 is a fifth structural diagram of a shift register in one embodiment;

[0074] FIG12 is a sixth schematic diagram of the structure of a shift register in one embodiment;

[0075] FIG13 is a seventh schematic diagram of the structure of a shift register in one embodiment;

[0076] FIG14 is a schematic diagram of the structure of a second indium gallium zinc oxide transistor in one embodiment;

[0077] FIG15 is an eighth schematic diagram of the structure of a shift register in one embodiment;

[0078] FIG16 is a timing diagram of the operation of the shift register shown in FIG15 according to one embodiment;

[0079] FIG17 is a ninth structural diagram of a shift register in one embodiment;

[0080] FIG18 is a tenth schematic diagram of the structure of a shift register in one embodiment;

[0081] FIG. 19 is an operation timing diagram of the shift register shown in FIG. 18 in one embodiment.

[0082] Description of reference numerals:

[0083] 100 - first input module; 200 - first output module; 300 - second input module; 400 - second output module; 101 - input unit; 102 - voltage stabilizing unit; 103 - initialization unit; 600 - substrate;

[0084] N1-first node; N2-second node; SIN-input signal line; SCK1-first control signal line; SCK2-second control signal line; STK-correction voltage line; VGH-first power signal line; VGL-second power signal line; GP1-first output terminal; GP2-second output terminal;

[0085] NM1-first indium gallium zinc oxide transistor; 601-second control terminal of the first indium gallium zinc oxide transistor; 602-active layer of the first indium gallium zinc oxide transistor; 603-first control terminal of the first indium gallium zinc oxide transistor; 604-first insulating layer of the first indium gallium zinc oxide transistor; 605-second insulating layer of the first indium gallium zinc oxide transistor; 606-third insulating layer of the first indium gallium zinc oxide transistor; 607-first electrode of the first indium gallium zinc oxide transistor; 608-second electrode of the first indium gallium zinc oxide transistor;

[0086] NM2-second indium gallium zinc oxide transistor; 1001-second control terminal of the second indium gallium zinc oxide transistor; 1002-active layer of the second indium gallium zinc oxide transistor; 1003-first control terminal of the second indium gallium zinc oxide transistor; 1004-first insulating layer of the second indium gallium zinc oxide transistor; 1005-second insulating layer of the second indium gallium zinc oxide transistor; 1006-third insulating layer of the second indium gallium zinc oxide transistor; 1007-first electrode of the second indium gallium zinc oxide transistor; 1008-second electrode of the second indium gallium zinc oxide transistor;

[0087] PM1-first switch transistor; PM2-second switch transistor; PM3-third switch transistor; PM4-fourth switch transistor; PM5-fifth switch transistor; PM6-sixth switch transistor; PM7-seventh switch transistor; PM8-eighth switch transistor; C1-first capacitor. DETAILED DESCRIPTION

[0088] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0089] As described in the background technology section, the stability of the scan drive signal provided by the shift register in the related art is poor, which is easy to affect the display performance of the display panel. In the related art, due to the poor positive bias thermal stability (Positive Bias Temperature Stability, PBTS) of the transistor of the first output module in the shift register, it is easy to gather electrons on the surface of the channel under the action of the positive bias electric field during operation, and some electrons will be injected into the gate oxide layer to form a negative fixed charge, resulting in the positive bias of the threshold voltage of the transistor. When the threshold voltage of the transistor is positively biased, a larger voltage difference needs to be formed between the gate and the source of the transistor to make the transistor in the on state. As time goes by, the positive bias of the threshold voltage of the transistor will gradually increase, as shown in Figure 1. Among them, the horizontal axis in Figure 1 is the threshold voltage Vth of the N-type indium gallium zinc oxide transistor, and the vertical axis is the current Id on the N-type indium gallium zinc oxide transistor.

[0090] In this way, when the output module turns on the transistor in the output module and outputs the scan drive signal under the control of the potential of the corresponding node, if the threshold voltage of the corresponding transistor is positively biased, the turn-on of the transistor will be slowed down, and further cause the process of the scan drive signal "jumping from the failure potential to the effective potential" or "jumping from the effective potential to the failure potential" to be slowed down. Taking the transistor as an N-type indium gallium zinc oxide transistor as an example, as shown in FIG2, when the threshold voltage of the N-type indium gallium zinc oxide transistor is positively biased at 0V, 1V, 2V, 3V, 4V and 5V respectively, the process of the scan drive signal "jumping from the effective potential to the failure potential" is slowed down. Among them, the horizontal axis in FIG2 is time t, and the vertical axis is the potential V of the first scan drive signal.

[0091] If the scanning drive signal's process of "jumping from a failure potential to a valid potential" or "jumping from a valid potential to a failure potential" slows down, the corresponding transistor in the corresponding pixel circuit electrically connected to it will turn on or off more slowly, causing poor display problems such as afterimages and ghosting on the display panel.

[0092] Based on the above technical problems, the inventors have found that by controlling the potential of the first node and the correction voltage on the correction voltage line STK of the first output module (for example, applying the correction voltage to the bottom gate of the transistor in the first output module), the PN junction of the transistor has a reverse bias relative to the substrate, so that the negative charge in the conductive channel moves to the depletion region, reducing the conductivity of the conductive channel, that is, the threshold voltage of the transistor is negatively biased to offset the amount of positive shift of the threshold voltage generated by the transistor due to working for a long time. Therefore, by applying the correction voltage to the transistor in the first output module, by adjusting the correction voltage, the gate and the source of the transistor can be turned on at a constant voltage difference at different time periods, so that the process of the first scanning drive signal "jumping from the first failure potential to the first effective potential" or "jumping from the first effective potential to the first failure potential" can be maintained stable, and then the opening or closing of the corresponding transistor in the corresponding pixel circuit electrically connected to it is also maintained stable, so as to avoid the occurrence of poor display such as afterimage and smear on the display panel, thereby improving the display performance of the display panel.

[0093] 3, in one embodiment, the shift register includes a first input module 100 and a first output module 200. The first input module 100 includes a first node N1, and the first input module 100 is electrically connected to the input signal line SIN and the first control signal line SCK1. The first input module 100 is configured to be controlled by a first control signal on the first control signal line SCK1, and transmits an input signal on the input signal line SIN to the first node N1.

[0094] Exemplarily, the first input module 100 is in an on or off state in response to the first control signal. For example, the first control signal has a first potential and a second potential. When the first input module 100 receives the first control signal with the first potential, it is in an on state to transmit the input signal on the input signal line SIN to the first node N1. When the first input module 100 receives the first control signal with the second potential, it is in an off state.

[0095] The first output module 200 includes a first output terminal GP1, which is electrically connected to the correction voltage line STK and the first node N1. The first output module 200 is configured to output a first scan driving signal having a first valid potential or a first failure potential at the first output terminal GP1 under the control of the potential of the first node N1 and the correction voltage on the correction voltage line STK.

[0096] In the embodiment of the present application, for the sake of convenience, the first scan drive signal is described by taking the Nscan signal as an example. When the first scan drive signal is the Nscan signal, its first effective potential may be a high level potential, and the first failure potential may be a low level potential. The first scan drive signal output by the first output module 100 can be provided to the corresponding pixel circuit to control the N-type transistor in the pixel circuit. For example, when the first scan drive signal (Nscan signal) is at the first effective potential (high level potential), the N-type transistor controlled by it is in the on state, and when the first scan drive signal (Nscan signal) is at the first failure potential (low level potential), the N-type transistor controlled by it is in the off state.

[0097] The shift register includes a first input module 100 and a first output module 200. The first input module 100 includes a first node N1, and the first input module 100 is electrically connected to the input signal line SIN and the first control signal line SCK1. The first input module 100 is configured to be controlled by a first control signal on the first control signal line SCK1, and transmit the input signal on the input signal line SIN to the first node N1. The first output module 200 includes a first output terminal GP1, and is electrically connected to the correction voltage line STK and the first node N1. The first output module 200 is configured to be controlled by the potential of the first node N1 and the correction voltage on the correction voltage line STK, and output a first scan drive signal having a first valid potential or a first failure potential at the first output terminal GP1. By controlling the potential of the first node N1 and the correction voltage on the correction voltage line STK of the first output module 200 (for example, applying the correction voltage to the bottom gate of the transistor in the first output module 200), the PN junction of the transistor has a reverse bias relative to the substrate, so that the negative charge in the conductive channel moves to the depletion region, reducing the conductivity of the conductive channel, that is, the threshold voltage of the transistor is negatively biased to offset the amount of positive shift of the threshold voltage caused by the transistor working for a long time. Therefore, by adjusting the correction voltage, the gate and the source of the transistor are turned on at a constant voltage difference at different time periods, so that the process of the first scan drive signal "jumping from the first failure potential to the first effective potential" or "jumping from the first effective potential to the first failure potential" remains stable. Therefore, the first output module 200 is configured to be controlled by the potential of the first node N1 and the correction voltage on the correction voltage line STK, and can stably output the first scan drive signal.

[0098] In one embodiment, please continue to refer to FIG. 3 , the first output module 200 is further electrically connected to the first power signal line VGH and the second power signal line VGL.

[0099] When the first input module 100 receives the first control signal with the first potential, it is in the on state, and the potential of the first node N1 is controlled by the input signal. When the input signal has the first potential, the first node N1 also has the first potential, and the first output terminal GP1 outputs the first power signal on the first power signal line VGH, and the first power signal is used as the Nscan signal with the first effective potential. When the input signal has the second potential, the first node N1 also has the second potential, and the first output terminal GP1 outputs the second power signal on the second power signal line VGL, and the second power signal is used as the Nscan signal with the first failure potential.

[0100] When the first input module 100 receives the first control signal with the second potential, it is in the off state, and the first node N1 is not controlled by the input signal. When the first node N1 maintains the first potential, the first output terminal GP1 outputs the first power signal as the Nscan signal with the first effective potential.

[0101] In this embodiment, the first potential is a low level potential and the second potential is a high level potential. When the potential of the first node N1 is controlled by the input signal and has a low level potential, the first output terminal GP1 outputs a high level signal, that is, an Nscan signal with a first effective potential; when the potential of the first node N1 is controlled by the input signal and has a high level potential, the first output terminal GP1 outputs a low level signal, that is, an Nscan signal with a first failure potential; when the potential of the first node N1 is not controlled by the input signal and has a low level potential, the first output terminal GP1 outputs a high level signal, that is, an Nscan signal with a first effective potential.

[0102] In one embodiment, as shown in FIG. 4 , the first output module 200 includes a first indium gallium zinc oxide transistor NM1, a first electrode of the first indium gallium zinc oxide transistor NM1 is electrically connected to the second power signal line VGL, a second electrode of the first indium gallium zinc oxide transistor NM1 is electrically connected to the first output terminal GP1, a first control terminal of the first indium gallium zinc oxide transistor NM1 is electrically connected to the first node N1, and a second control terminal of the first indium gallium zinc oxide transistor NM1 is electrically connected to the correction voltage line STK.

[0103] Wherein, the first indium gallium zinc oxide transistor NM1 is an N-type transistor. The first electrode and the second electrode of the first indium gallium zinc oxide transistor NM1 can be a drain and a source, respectively, but are not limited thereto. After applying the correction voltage only to the bottom gate of the first indium gallium zinc oxide transistor NM1, as shown in FIG5, the threshold voltage of the first indium gallium zinc oxide transistor NM1 and the correction voltage are linearly related. As shown in FIG6, the threshold voltage of the first indium gallium zinc oxide transistor NM1 will be negatively biased when the correction voltage is a positive voltage value, and positively biased when it is a negative voltage value. Wherein, the abscissa in FIG5 is the correction voltage Vrec, and the ordinate is the threshold voltage Vth; the abscissa of FIG6 (a) is the threshold voltage Vth of the N-type indium gallium zinc oxide transistor, the ordinate of FIG6 (a) is the current Id on the N-type indium gallium zinc oxide transistor, and FIG6 (b) is the figure after the current Id in FIG6 (a) is derived. Therefore, a correction voltage is applied to the first InGaZnO transistor NM1 , and by adjusting the correction voltage, the first InGaZnO transistor NM1 can be turned on when the gate and the source have a small voltage difference in different time periods.

[0104] In one embodiment, the voltage value of the correction voltage provided by the correction voltage line STK gradually increases from the first driving cycle to the nth driving cycle, so as to ensure that the threshold voltage of the first InGaZnO transistor NM1 in the first driving cycle is equal to the threshold voltage of the first InGaZnO transistor NM1 in the nth driving cycle, where n is greater than 1. In this way, the gate and source of the first InGaZnO transistor NM1 can be turned on when there is a small voltage difference in different time periods, so that the process of the first scanning driving signal "jumping from the first effective potential to the first failure potential" remains stable. Therefore, the voltage value of the correction voltage provided by the correction voltage line STK gradually increases from the first driving cycle to the nth driving cycle, so that the shift register can stably output the first scanning driving signal.

[0105] In one embodiment, as shown in Figure 7, the first output module 200 also includes a first switching transistor PM1, wherein: the first electrode of the first switching transistor PM1 is electrically connected to the first power signal line VGH, the second electrode of the first switching transistor PM1 is electrically connected to the first output terminal GP1, and the control terminal of the first switching transistor PM1 is electrically connected to the first node N1.

[0106] The first switch transistor PM1 may be a P-type transistor, and the first electrode and the second electrode of the first switch transistor PM1 may be a source and a drain, respectively, but the present invention is not limited thereto.

[0107] In one embodiment, based on any of the above embodiments, the first input module 100 includes an input unit 101, as shown in Figure 8. The input unit 101 includes a fifth switch transistor PM5, wherein: a first electrode of the fifth switch transistor PM5 serves as a first node N1, a second electrode of the fifth switch transistor PM5 is electrically connected to an input signal line SIN, and a control end of the fifth switch transistor PM5 is electrically connected to a first control signal line SCK1.

[0108] The fifth switch transistor PM5 may be a P-type transistor, such as a P-type low temperature polysilicon transistor. The first electrode and the second electrode of the fifth switch transistor PM5 may be a drain and a source, respectively.

[0109] When the first control signal provided by the first control signal line SCK1 is a low level signal, the fifth switching transistor PM5 is turned on, and the potential of the first node N1 is related to the voltage signal provided by the input signal line SIN. When the input signal line SIN provides a high level signal, the potential of the first node N1 becomes a high level potential. Conversely, when the input signal line SIN provides a low level signal, the potential of the first node N1 becomes a low level potential.

[0110] As shown in FIG. 9 , a working timing diagram of the shift register shown in FIG. 8 is provided. The driving cycle of the shift register includes an input phase t1 , an output phase t2 and a reset phase t3 .

[0111] In the input stage t1, the first control signal line SCK1 provides a low level signal, the first power signal line VGH provides a high level signal, the second power signal line VGL provides a low level signal, the input signal line SIN provides a low level signal, and the fifth switching transistor PM5 is turned on to change the potential of the first node N1 to a low level potential; the first indium gallium zinc oxide transistor NM1 is turned off, the first switching transistor PM1 is turned on, and the first output terminal GP1 outputs a high level signal provided by the first power signal line VGH, that is, an Nscan signal having a first effective potential (high level potential).

[0112] In the output stage t2, the first control signal line SCK1 provides a high level signal, the input signal line SIN provides a high level signal, the fifth switch transistor PM5 is turned off, and the potential of the first node N1 is maintained at a low level potential; the first indium gallium zinc oxide transistor NM1 is turned off, the first switch transistor PM1 is turned on, and the first output terminal GP1 outputs the high level signal provided by the first power signal line VGH, that is, the Nscan signal with a first effective potential (high level potential).

[0113] In the reset stage t3, the first control signal line SCK1 provides a low level signal, the input signal line SIN provides a high level signal, and the fifth switch transistor PM5 is turned on to change the potential of the first node N1 to a high level potential; the first switch transistor PM1 is turned off, the first indium gallium zinc oxide transistor NM1 is turned on, and the first output terminal GP1 outputs the low level signal provided by the second power signal line VGL, that is, the Nscan signal with a first failure potential (low level potential).

[0114] In an example, as shown in FIG10 , a structural diagram of a first indium gallium zinc oxide transistor NM1 is provided, wherein the first indium gallium zinc oxide transistor NM1 is disposed on a substrate 600, a second control terminal 601 of the first indium gallium zinc oxide transistor NM1 is located on a side of an active layer 602 of the first indium gallium zinc oxide transistor NM1 facing the substrate 600, and a first control terminal 603 of the first indium gallium zinc oxide transistor NM1 is located on a side of the active layer 602 of the first indium gallium zinc oxide transistor NM1 facing away from the substrate 600.

[0115] The substrate 600 may be a flexible substrate, and the material of the flexible substrate may be polyimide (PI), polyethylene naphthalene-2,6-dicarboxylate (PEN) or polyethylene terephthalate (PET), or a mixture of the above materials. The substrate 600 may also be a hard substrate formed of materials such as glass.

[0116] The first control terminal 603 can be regarded as the top gate of the first indium gallium zinc oxide transistor NM1; the second control terminal 601 can be regarded as the bottom gate of the first indium gallium zinc oxide transistor NM1. The materials of the first control terminal 603 and the second control terminal 601 can be metals such as molybdenum Mo, aluminum Al, copper Cu or titanium Ti, or a mixed material of the above multiple metals. The material of the active layer 602 is indium gallium zinc oxide.

[0117] It can be understood that the first InGaZnO transistor NM1 may also include multiple insulating layers, such as a first insulating layer 604, a second insulating layer 605 and a third insulating layer 606. Specifically, the film layers of the first InGaZnO transistor NM1 are arranged in the following relationship:

[0118] The second control terminal 601 is disposed on one side of the substrate 600; the first insulating layer 604 is disposed on the side of the second control terminal 601 away from the substrate 600; the active layer 602 is disposed on the side of the first insulating layer 604 away from the substrate 600; the second insulating layer 605 is disposed on the side of the active layer 602 away from the substrate 600; the first control terminal 603 is disposed on the side of the second insulating layer 605 away from the substrate 600; the third insulating layer 606 is disposed on the side of the first control terminal 603 away from the substrate 600; the first electrode 607 of the first indium gallium zinc oxide transistor NM1 is connected to the active layer 602 through a first via hole penetrating the second insulating layer 605 and the third insulating layer 606; the second electrode 608 of the first indium gallium zinc oxide transistor NM1 is connected to the active layer 602 through a second via hole penetrating the second insulating layer 605 and the third insulating layer 606. In this way, the second control terminal 601 can be connected to the correction voltage line STK to receive the correction voltage.

[0119] In one embodiment, the size of the second control terminal 601 is larger than the size of the active layer 602, that is, the orthographic projection of the second control terminal 601 on the substrate 600 covers the orthographic projection of the active layer 602 on the substrate 600, so that the second control terminal 601 can avoid the problem of the active layer 602 continuously generating electron pairs under the influence of bottom illumination, causing the performance degradation of the first indium gallium zinc oxide transistor NM1, thereby improving the stability of the shift register. In addition, when other film layers are provided between the second control terminal 601 and the substrate 600, the size of the second control terminal 601 is set to be larger than the size of the active layer 602, so that the second control terminal 601 can shield the influence of the charges in other film layers on the first indium gallium zinc oxide transistor NM1, thereby improving the stability of the shift register.

[0120] In one embodiment, as shown in Fig. 11, the shift register further includes a second input module 300 and a second output module 400. The second input module 300 includes a second node N2, and the second input module 300 is electrically connected to the first power signal line VGH, the second power signal line VGL and the first node N1, and is configured to be controlled by the potential of the first node N1 to transmit the first power signal or the second power signal to the second node N2.

[0121] Exemplarily, when the first input module 100 receives the first control signal with the first potential, it is in the on state, and the potential of the first node N1 is controlled by the input signal. When the input signal has the first potential, the first node N1 also has the first potential, and the second input module 300 transmits the first power signal to the second node N2; when the input signal has the second potential, the first node N1 also has the second potential, and the second input module 300 transmits the second power signal to the second node N2. When the potential of the first node N1 is a low level potential, the potential of the second node N2 is a high level potential; when the potential of the first node N1 is a high level potential, the potential of the second node N2 is a low level potential.

[0122] The second output module 400 includes a second output terminal GP2, and the second output module 400 is electrically connected to the second control signal line SCK2, the first power signal line VGH, the first node N1 and the second node N2, and is configured to be controlled by the potential of the first node N1 and the potential of the second node N2, and output a second scan drive signal having a second valid potential or a second failure potential at the second output terminal GP2.

[0123] In the embodiment of the present application, for the sake of convenience, the second scan drive signal is described by taking the Pscan signal as an example. When the second scan signal is the Pscan signal, its second effective potential may be a low level potential, and the second failure potential may be a high level potential. The second scan signal output by the second output module 400 may be provided to the corresponding pixel circuit to control the P-type transistor in the pixel circuit. For example, when the second scan drive signal (Pscan signal) is at the second effective potential (low level potential), the P-type transistor controlled by it is in the on state, and when the second scan drive signal (Pscan signal) is at the second failure potential (high level potential), the P-type transistor controlled by it is in the off state.

[0124] In this embodiment, the shift register can output the Nscan signal and the Pscan signal at the same time. This integrated design reduces the number of electronic components required, thereby directly reducing the size of the circuit board, and further realizing a narrow-frame design of the display panel.

[0125] In one embodiment, the second input module 300 may also be electrically connected to the correction voltage line STK, and the second input module 300 is configured to be controlled by the potential of the first node N1 and the correction voltage on the correction voltage line STK to transmit the first power signal or the second power signal to the second node N2. By controlling the potential of the first node N1 and the correction voltage on the correction voltage line STK of the second input module 300 (for example, applying the correction voltage to the bottom gate of the transistor in the second input module 300), the PN junction of the transistor has a reverse bias relative to the substrate, so that the negative charge in the conductive channel moves to the depletion region, reducing the conductivity of the conductive channel, that is, the threshold voltage of the transistor is negatively biased to offset the amount of positive shift of the threshold voltage caused by the transistor working for a long time. Therefore, by adjusting the correction voltage, the gate and the source of the transistor are turned on at a constant voltage difference at different time periods, so that the corresponding transistor in the second output module 400 is turned on and turned off stably, so that the process of the second scan drive signal "jumping from the second failure potential to the second effective potential" or "changing from the second effective potential to the second failure potential" is also maintained stable. Therefore, the second input module 300 is configured to be controlled by the potential of the first node N1 and the correction voltage on the correction voltage line STK, and can stably output the second scan drive signal.

[0126] In one embodiment, as shown in FIG. 12 , the second input module 300 includes a second InGaZnO transistor NM2, a first electrode of the second InGaZnO transistor NM2 is electrically connected to the second node N2, a second electrode of the second InGaZnO transistor NM2 is electrically connected to the second power signal line VGL, a first control terminal of the second InGaZnO transistor NM2 is electrically connected to the first node N1, and a second control terminal of the second InGaZnO transistor NM2 is electrically connected to the correction voltage line STK.

[0127] The second InGaZnO transistor NM2 is an N-type transistor. The first electrode and the second electrode of the second InGaZnO transistor NM2 may be a source electrode and a drain electrode, respectively, but not limited thereto.

[0128] In one embodiment, the voltage value of the correction voltage provided by the correction voltage line STK gradually increases from the first driving cycle to the nth driving cycle, thereby ensuring that the threshold voltage of the second InGaZnO transistor NM2 in the first driving cycle is equal to the threshold voltage of the second InGaZnO transistor NM2 in the nth driving cycle, wherein n is greater than 1. In this way, the second InGaZnO transistor NM2 can be turned on with a small voltage difference in different time periods over time, so that the corresponding transistor in the second output module 400 is driven to turn on and off stably, thereby making the process of the second scan drive signal "changing from the second effective potential to the second failure potential" also stable. Therefore, the voltage value of the correction voltage provided by the correction voltage line STK gradually increases from the first driving cycle to the nth driving cycle, so that the shift register can stably output the second scan drive signal.

[0129] In one embodiment, as shown in Figure 13, the second input module 300 also includes a second switching transistor PM2, wherein: the first electrode of the second switching transistor PM2 is electrically connected to the second node N2, the second electrode of the second switching transistor PM2 is electrically connected to the first power signal line VGH, and the control end of the second switching transistor PM2 is electrically connected to the first node N1.

[0130] The second switch transistor PM2 may be a P-type transistor, and the first electrode and the second electrode of the second switch transistor PM2 may be a drain and a source, respectively, but the present invention is not limited thereto.

[0131] It should be noted that the shift register may use the first output module 200 and the second input module 300 with different structures, or may use the first output module 200 and the second input module 300 with the same structure. Preferably, the first output module 200 and the second input module 300 with the same structure are selected. Preferably, the first output module 200 shown in FIG. 7 and the second input module 300 shown in FIG. 13 are selected. When the first output module 200 shown in FIG. 7 and the second input module 300 shown in FIG. 13 are selected, the second control terminal of the first indium gallium zinc oxide transistor NM1 and the second control terminal of the second indium gallium zinc oxide transistor NM2 may be electrically connected.

[0132] In one example, as shown in FIG14 , a structural diagram of a second Indium Gallium Zinc Oxide transistor NM2 is provided, wherein the second Indium Gallium Zinc Oxide transistor NM2 is disposed on a substrate 600, a second control terminal 1001 of the second Indium Gallium Zinc Oxide transistor NM2 is located on a side of an active layer 1002 of the second Indium Gallium Zinc Oxide transistor NM2 that faces the substrate 600, and a first control terminal 1003 of the second Indium Gallium Zinc Oxide transistor NM2 is located on a side of an active layer 1002 of the second Indium Gallium Zinc Oxide transistor NM2 that faces away from the substrate 600.

[0133] The first control terminal 1003 can be regarded as the top gate of the second indium gallium zinc oxide transistor NM2; the second control terminal 1001 can be regarded as the bottom gate of the second indium gallium zinc oxide transistor NM2. The materials of the first control terminal 1003 and the second control terminal 1001 can be metals such as molybdenum Mo, aluminum Al, copper Cu or titanium Ti, or a mixed material of the above multiple metals. The material of the active layer 1002 is indium gallium zinc oxide.

[0134] It can be understood that the second InGaZnO transistor NM2 further includes a plurality of insulating layers, such as a first insulating layer 1004, a second insulating layer 1005, and a third insulating layer 1006. Specifically, the film layers of the second InGaZnO transistor NM2 are arranged in the following relationship:

[0135] The second control terminal 1001 is arranged on one side of the substrate 600; the first insulating layer 1004 is arranged on the side of the second control terminal 1001 away from the substrate 600; the active layer 1002 is arranged on the side of the first insulating layer 1004 away from the substrate 600; the second insulating layer 1005 is arranged on the side of the active layer 1002 away from the substrate 600; the first control terminal 1003 is arranged on the side of the second insulating layer 1005 away from the substrate 600; the third insulating layer 1006 is arranged on the side of the first control terminal 1003 away from the substrate 600; the first electrode 1007 of the second indium gallium zinc oxide transistor NM2 is connected to the active layer 1002 through a first via hole penetrating the second insulating layer 1005 and the third insulating layer 1006; the second electrode 1008 of the second indium gallium zinc oxide transistor NM2 is connected to the active layer 1002 through a second via hole penetrating the second insulating layer 1005 and the third insulating layer 1006. In this way, the second control terminal 1001 can be connected to the correction voltage line STK to receive the correction voltage.

[0136] In one embodiment, the size of the second control terminal 1001 is larger than the size of the active layer 1002, that is, the orthographic projection of the second control terminal 1001 on the substrate 600 covers the orthographic projection of the active layer 1002 on the substrate 600, so that the second control terminal 1001 can avoid the problem of the active layer 1002 continuously generating electron pairs under the influence of bottom illumination, causing the performance degradation of the second indium gallium zinc oxide transistor NM2, thereby improving the stability of the shift register. In addition, when other film layers are provided between the second control terminal 1001 and the substrate 600, the size of the second control terminal 1001 is set to be larger than the size of the active layer 1002, so that the second control terminal 1001 can shield the influence of the charges in other film layers on the second indium gallium zinc oxide transistor NM2, thereby improving the stability of the shift register.

[0137] In one embodiment, please continue to refer to FIG. 11, when the first input module 100 receives the first control signal with the first potential, it is in the on state, and the potential of the first node N1 is controlled by the input signal. When the input signal has the first potential, the first node N1 also has the first potential, and the second output module 400 is controlled by the first potential of the first node N1, and outputs the second control signal on the second control signal line SCK2 at the second output terminal GP2, and when the second control signal and the first control signal are mutually inverted signals, the second output module 400 outputs the second control signal with the second potential at the second output terminal GP2, that is, the Pscan signal of the second failure potential. When the input signal has the second potential, the first node N1 also has the second potential, and the second input module 300 outputs the second power signal, and the second output module 400 is controlled by the second power signal transmitted to the second node N2, and outputs the first power signal at the second output terminal GP2, that is, the Pscan signal of the second failure potential.

[0138] When the first input module 100 receives the first control signal with a second potential, it is in an off state. At this time, the first node N1 is not controlled by the input signal, and the first node N1 is maintained at the first potential. At this time, the second output module 400 is controlled by the first potential of the first node N1, and outputs the second control signal on the second control signal line SCK2 at the second output terminal GP2. When the second control signal and the first control signal are inverted signals to each other, the second output module 400 outputs the second control signal with the first potential at the second output terminal GP2, which is the Pscan signal of the second effective potential.

[0139] In this embodiment, when the potential of the first node N1 is controlled by the input signal and has a low level potential, the second output terminal GP2 outputs a high level signal, that is, the Pscan signal of the second failure potential; when the potential of the first node N1 is controlled by the input signal and has a high level potential, the second output terminal GP2 outputs a high level signal, that is, the Pscan signal of the second failure potential; when the potential of the first node N1 is not controlled by the input signal and has a low level potential, the second output terminal GP2 outputs a low level signal, that is, the Pscan signal of the second valid potential.

[0140] In one embodiment, as shown in FIG. 15 , the second output module 400 includes a third switch transistor PM3, a fourth switch transistor PM4 and a first capacitor C1. Wherein: the first electrode of the third switch transistor PM3 is electrically connected to the second control signal line SCK2, the second electrode of the third switch transistor PM3 is electrically connected to the second output terminal GP2, and the control terminal of the third switch transistor PM3 is electrically connected to the first node N1; the first electrode of the fourth switch transistor PM4 is electrically connected to the second output terminal GP2, the second electrode of the fourth switch transistor PM4 is electrically connected to the first power signal line VGH, and the control terminal of the fourth switch transistor PM4 is electrically connected to the second node N2; the first capacitor C1 is connected between the second output terminal GP2 and the first node N1. The first capacitor is configured to maintain the potential of the first node N1 at the first potential when the first node N1 is not controlled by the input signal.

[0141] The third switch transistor PM3 and the fourth switch transistor PM4 can both be P-type transistors. The first electrode and the second electrode of the third switch transistor PM3 can be a source and a drain respectively; the first electrode and the second electrode of the fourth switch transistor PM4 can be a drain and a source respectively.

[0142] As shown in Fig. 16, a working timing diagram of the shift register shown in Fig. 15 is provided. It should be noted that the first control signal and the second control signal are mutually inverted signals.

[0143] In the input stage t1, the first control signal line SCK1 provides a low level signal, the second control signal line SCK2 provides a high level signal, the input signal line SIN provides a low level signal, the potential of the first node N1 becomes a low level potential, the second indium gallium zinc oxide transistor NM2 is turned off, the second switch transistor PM2 is turned on to pull up the potential of the second node N2, and the fourth switch transistor PM4 is turned off; the third switch transistor PM3 is turned on, and the second output terminal GP2 outputs the high level signal provided by the second control signal line SCK2, that is, the Pscan signal with a second failure potential (high level potential).

[0144] In the output stage t2, the first control signal line SCK1 provides a high level signal, the second control signal line SCK2 provides a low level signal, the input signal line SIN provides a high level signal, the capacitor C1 discharges to provide a low level signal, the potential of the first node N1 is maintained at a low level potential, the second indium gallium zinc oxide transistor NM2 is turned off, the second switching transistor PM2 is turned on, the potential of the second node N2 is maintained at a high level potential, and the fourth switching transistor PM4 is turned off; the third switching transistor PM3 is turned on, and the second output terminal GP2 outputs the low level signal provided by the second control signal line SCK2, that is, the Pscan signal with a second effective potential (low level potential).

[0145] In the reset stage t3, the first control signal line SCK1 provides a low level signal, the second control signal line SCK2 provides a high level signal, the input signal line SIN provides a high level signal, the potential of the first node N1 becomes a high level potential, the third switching transistor PM3 is turned off, the second switching transistor PM2 is turned off, the second indium gallium zinc oxide transistor NM2 is turned on, the potential of the second node N2 becomes a low level potential, the fourth switching transistor PM4 is turned on, and the second output terminal GP2 outputs the high level signal provided by the first power signal line VGH, that is, the Pscan signal with a second failure potential (high level potential).

[0146] In addition, the Nscan signal output by the first output terminal GP1 at different stages in FIG. 16 can refer to that shown in the above-mentioned FIG. 9 , which will not be described again here.

[0147] In one embodiment, as shown in FIG17 , the first input module 100 further includes a voltage stabilizing unit 102. The voltage stabilizing unit 102 is used to stabilize the voltage of the signal input from the input unit 101 to the second output module 400.

[0148] Exemplarily, the voltage stabilizing unit 102 may include a sixth switching transistor PM6, wherein: a first electrode of the sixth switching transistor PM6 is electrically connected to the second output module 400, a second electrode of the sixth switching transistor PM6 is electrically connected to the first node N1, and a control end of the sixth switching transistor PM6 is electrically connected to the second power signal line VGL; the sixth switching transistor PM6 is configured to remain in an on state under the control of a second power signal on the second power signal line VGL.

[0149] The sixth switch transistor PM6 may be a P-type transistor. The first electrode and the second electrode of the sixth switch transistor PM6 may be a drain and a source, respectively, but the present invention is not limited thereto.

[0150] In one embodiment, as shown in FIG. 18 , the first input module 100 further includes an initialization unit 103 , and the initialization unit 103 is electrically connected to the first node N1 , the second node N2 , the second control signal line SCK2 , and the first power signal line VGH.

[0151] The initialization unit 103 includes: a seventh switch transistor PM7 and an eighth switch transistor PM8. A first electrode of the seventh switch transistor PM7 is electrically connected to the first node N1, and a control terminal of the seventh switch transistor PM7 is electrically connected to the second control signal line SCK2; a first electrode of the eighth switch transistor PM8 is electrically connected to the second electrode of the seventh switch transistor PM7, a second electrode of the eighth switch transistor PM8 is electrically connected to the first power signal line VGH, and a control terminal of the eighth switch transistor PM8 is electrically connected to the second node N2.

[0152] The seventh switch transistor PM7 and the eighth switch transistor PM8 are both P-type transistors. The first electrode and the second electrode of the seventh switch transistor PM7 can be a drain and a source respectively, and the first electrode and the second electrode of the eighth switch transistor PM8 can be a drain and a source respectively, but not limited thereto.

[0153] As shown in FIG. 19 , a working timing diagram of the shift register shown in FIG. 18 is provided, and the driving cycle of the shift register also includes an initialization phase t0 .

[0154] In the initialization stage t0, the first control signal line SCK1 provides a high-level signal, the second control signal line SCK2 provides a low-level signal, the input signal line SIN provides a high-level signal, the potential of the second node N2 becomes a low-level potential, the eighth switch transistor PM8 is turned on, and the seventh switch transistor PM7 is also turned on, so that the high-level signal provided by the first power signal line VGH is transmitted to the first node N1, the potential of the first node N1 is a high-level potential, the first switch transistor PM1 is turned off, the first indium gallium zinc oxide transistor NM1 is turned on, and the first output terminal GP1 outputs the low-level signal provided by the second power signal line VGL, that is, the Nscan signal with a first failure potential (low-level potential); the third switch transistor PM3 is turned off; the fourth switch transistor PM4 is turned on, and the second output terminal GP2 outputs the high-level signal provided by the first power signal line VGH, that is, the Pscan signal with a second failure potential (high-level potential).

[0155] In addition, the input stage t1, output stage t2 and reset stage t3 in Figure 19, the Nscan signal output by the first output terminal GP1 and the Pscan signal output by the second output terminal GP2 can be referred to Figure 16 and will not be repeated here.

[0156] In one embodiment, the present application provides a display panel, which includes the shift register described in any of the above shift register embodiments.

[0157] The display panel may be an OLED (Organic Light Emitting Diode) display panel or a QLED (Quantum Dot Light Emitting Diodes) display panel.

[0158] The above-mentioned display panel includes the shift register described in any of the above-mentioned shift register embodiments. By controlling the potential of the first node N1 and the correction voltage on the correction voltage line STK of the first output module 200 (for example, applying the correction voltage to the bottom gate of the transistor in the first output module 200), the PN junction of the transistor has a reverse bias relative to the substrate, so that the negative charge in the conductive channel moves to the depletion region, reducing the conductivity of the conductive channel, that is, the threshold voltage of the transistor is negatively biased to offset the amount of positive shift of the threshold voltage caused by the transistor working for a long time. Therefore, by adjusting the correction voltage, the gate and the source of the transistor are turned on at a constant voltage difference at different time periods, so that the process of the first scan drive signal "jumping from the first failure potential to the first effective potential" or the process of "jumping from the first effective potential to the first failure potential" remains stable, and then the opening or closing of the corresponding transistor in the pixel circuit electrically connected to it remains stable, so as to avoid the occurrence of poor display such as afterimage and smear on the display panel, thereby improving the display performance of the display panel.

[0159] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0160] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A shift register, characterized in that: include: A first input module includes a first node, is electrically connected to an input signal line and a first control signal line, and is configured to be controlled by a first control signal on the first control signal line to transmit an input signal on the input signal line to the first node; The first output module includes a first output terminal, which is electrically connected to the correction voltage line and the first node, and is configured to be controlled by the potential of the first node and the correction voltage on the correction voltage line, and output a first scanning drive signal with a first effective potential or a first failure potential at the first output terminal.

2. The shift register according to claim 1, characterized in that: The first output module is also electrically connected to the first power signal line and the second power signal line, and is configured as follows: When the first node is controlled by the input signal to have a first potential, the first output terminal outputs the first power signal on the first power signal line as the first scan drive signal having the first effective potential; When the first node is not controlled by the input signal and is maintained at the first potential, the first power supply signal is output at the first output terminal as the first scan drive signal having the first effective potential; as well as, When the first node has a second potential under the control of the input signal, the second power signal on the second power signal line is outputted at the first output terminal as the first scan driving signal having the first failure potential.

3. The shift register according to claim 2, characterized in that: The first output module comprises a first indium gallium zinc oxide transistor, wherein: The first electrode of the first InGaZnO transistor is electrically connected to the second power signal line, the second electrode of the first InGaZnO transistor is electrically connected to the first output terminal, the first control terminal of the first InGaZnO transistor is electrically connected to the first node, and the second control terminal of the first InGaZnO transistor is electrically connected to the correction voltage line; Preferably, the threshold voltage of the first InGaZnO transistor in the first driving cycle is equal to the threshold voltage of the first InGaZnO transistor in the nth driving cycle, where n is greater than 1; Preferably, from the first driving cycle to the nth driving cycle, the voltage value of the correction voltage gradually increases; Preferably, the first InGaZnO transistor is an N-type transistor; Preferably, the first InGaZnO transistor is disposed on a substrate, the second control end of the first InGaZnO transistor is located on a side of the active layer of the first InGaZnO transistor facing the substrate, and the first control end of the first InGaZnO transistor is located on a side of the active layer of the first InGaZnO transistor facing away from the substrate; Preferably, the orthographic projection of the second control terminal of the first InGaZnO transistor on the substrate covers the orthographic projection of the active layer of the first InGaZnO transistor on the substrate; Preferably, the first output module further comprises a first switching transistor, wherein: A first electrode of the first switch transistor is electrically connected to the first power signal line, a second electrode of the first switch transistor is electrically connected to the first output terminal, and a control terminal of the first switch transistor is electrically connected to the first node; Preferably, the first switch transistor is a P-type transistor.

4. The shift register according to claim 3, characterized in that: Also includes: a second input module, comprising a second node, electrically connected to the first power signal line, the second power signal line and the first node, and configured to be controlled by the potential of the first node to transmit the first power signal or the second power signal to the second node; Preferably, the second input module is configured to: transmit the first power signal to the second node when the first node has the first potential; and, when the first node has the second potential, transmitting the second power signal to the second node; Preferably, the second input module comprises a second indium gallium zinc oxide transistor, wherein: The first electrode of the second InGaZnO transistor is electrically connected to the second node, the second electrode of the second InGaZnO transistor is electrically connected to the second power signal line, the first control terminal of the second InGaZnO transistor is electrically connected to the first node, and the second control terminal of the second InGaZnO transistor is electrically connected to the correction voltage line; Preferably, a threshold voltage of the second InGaZnO transistor in the first driving cycle is equal to a threshold voltage of the second InGaZnO transistor in the nth driving cycle; Preferably, the second indium gallium zinc oxide transistor is an N-type transistor; Preferably, the second indium gallium zinc oxide transistor is disposed on the substrate, the second control end of the second indium gallium zinc oxide transistor is located on a side of the active layer of the second indium gallium zinc oxide transistor facing the substrate, and the first control end of the second indium gallium zinc oxide transistor is located on a side of the active layer of the second indium gallium zinc oxide transistor facing away from the substrate; Preferably, the orthographic projection of the second control terminal of the second InGaZnO transistor on the substrate covers the orthographic projection of the active layer of the second InGaZnO transistor on the substrate; Preferably, the second input module further comprises a second switching transistor, wherein: A first electrode of the second switch transistor is electrically connected to the second node, a second electrode of the second switch transistor is electrically connected to the first power signal line, and a control terminal of the second switch transistor is electrically connected to the first node; Preferably, the second switch transistor is a P-type transistor; Preferably, the circuit structure of the second input module is the same as the circuit structure of the first output module.

5. The shift register according to claim 4, characterized in that: Also includes: a second output module, comprising a second output terminal, electrically connected to a second control signal line, the first power signal line, the first node and the second node, and configured to be controlled by the potential of the first node and the potential of the second node, and output a second scan drive signal having a second effective potential or a second failure potential at the second output terminal; Preferably, the second output module is configured as follows: When the first node is controlled by the input signal to have the first potential, the second control signal having the second potential on the second control signal line is output at the second output end as the second scan drive signal having the second failure potential under the control of the first potential of the first node; When the first node is not controlled by the input signal and is maintained at the first potential, the second control signal having the first potential on the second control signal line is output at the second output terminal as the second scan drive signal having the second effective potential under the control of the first potential of the first node; as well as, When the first node is controlled by the input signal to have the second potential, the first power signal on the first power signal line is output at the second output end as the second scan drive signal having the second failure potential under the control of the second power signal transmitted to the second node; Preferably, the first control signal and the second control signal are inverted signals.

6. The shift register according to claim 5, characterized in that: The second output module comprises: a third switch transistor, wherein a first electrode of the third switch transistor is electrically connected to the second control signal line, a second electrode of the third switch transistor is electrically connected to the second output terminal, and a control terminal of the third switch transistor is electrically connected to the first node; a fourth switch transistor, wherein a first electrode of the fourth switch transistor is electrically connected to the second output terminal, a second electrode of the fourth switch transistor is electrically connected to the first power signal line, and a control terminal of the fourth switch transistor is electrically connected to the second node; A first capacitor connected between the second output terminal and the first node; Preferably, the first capacitor is configured to keep the potential of the first node at the first potential when the first node is not controlled by the input signal.

7. The shift register according to claim 5, characterized in that: The first input module comprises an input unit, and the input unit comprises a fifth switch transistor, wherein: The first electrode of the fifth switch transistor serves as the first node, the second electrode of the fifth switch transistor is electrically connected to the input signal line, and the control end of the fifth switch transistor is electrically connected to the first control signal line.

8. The shift register according to claim 7, characterized in that: The first input module further includes a voltage stabilizing unit, and the voltage stabilizing unit includes a sixth switch transistor, wherein: A first electrode of the sixth switch transistor is electrically connected to the second output module, a second electrode of the sixth switch transistor is electrically connected to the first node, and a control end of the sixth switch transistor is electrically connected to the second power signal line; Preferably, the sixth switch transistor is configured to be controlled by the second power signal on the second power signal line to maintain a conducting state.

9. The shift register according to claim 7, characterized in that: The first input module further includes an initialization unit, wherein: The initialization unit is electrically connected to the first node, the second node, the second control signal line and the first power signal line, and the initialization unit is configured as follows: In the initialization stage, the first power signal on the first power signal line is transmitted to the first node under the control of the second power signal transmitted to the second node and the second control signal having the first potential on the second control signal line, so that the first output module outputs the first scan drive signal having the first failure potential at the first output terminal, and the second output terminal of the second output module and the second control signal line are in a disconnected state; Preferably, in the initialization stage, the second output module is configured to: under the control of the second power signal transmitted to the second node, output the first power signal on the first power signal line as the second scan drive signal having the second failure potential at the second output end; Preferably, the initialization unit comprises: a seventh switch transistor, wherein a first electrode of the seventh switch transistor is electrically connected to the first node, and a control terminal of the seventh switch transistor is electrically connected to the second control signal line; An eighth switch transistor, wherein a first electrode of the eighth switch transistor is electrically connected to a second electrode of the seventh switch transistor, a second electrode of the eighth switch transistor is electrically connected to the first power signal line, and a control end of the eighth switch transistor is electrically connected to the second node.

10. A display panel, characterized in that: The display panel comprises the shift register according to any one of claims 1 to 9.

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