Optoelectronic drive circuit and electronic device

Abstract

The application discloses an optoelectronic drive circuit and electronic equipment, and belongs to the technical field of electronic circuits, and comprises a detection circuit, a calibration circuit and a drive circuit. The detection circuit detects direct current power flowing through a light-emitting component to output a detection signal. The calibration circuit outputs each enable signal based on the detection signal, and in response to the detection signal being greater than a first preset voltage, the number of the output enable signals is reduced, and in response to the detection signal being less than a second preset voltage, the number of the output enable signals is increased. The drive circuit comprises a plurality of parallel driving components. The driving components transmit the direct current power based on the enable signals. Each enable signal is one-to-one connected to each driving component. The current of the direct current power is dynamically adjusted, the possibility of LED aging in the light-emitting component is reduced, and the stability and reliability of the optoelectronic drive circuit are improved.

Description

Technical Field

[0001] This application belongs to the field of drive technology, and in particular relates to a photoelectric drive circuit and electronic device. Background Technology

[0002] Light-emitting components typically include at least one LED, and the forward current of an LED varies with temperature. Once the ambient temperature exceeds 50°C, the forward current of the LED increases significantly. Under these conditions, if a large current is still applied, it can easily cause the LED to age prematurely.

[0003] Therefore, the related photoelectric drive circuits have poor stability and reliability. Summary of the Invention

[0004] The purpose of this application is to provide a photoelectric drive circuit and an image sensor, which aims to solve the problems of poor stability and reliability of related photoelectric drive circuits.

[0005] This application provides a photoelectric driving circuit connected to a light-emitting component, including a detection circuit, a calibration circuit, and a driving circuit;

[0006] The detection circuit is connected to the light-emitting component and is used to detect the DC power supply flowing through the light-emitting component in order to output a detection signal.

[0007] The calibration circuit is connected to the detection circuit and is used to output various enable signals based on the detection signal. In response to the detection signal being greater than a first preset voltage, the number of output enable signals is reduced, and in response to the detection signal being less than a second preset voltage, the number of output enable signals is increased.

[0008] The drive circuit includes multiple drive components connected in parallel;

[0009] The driving component is connected to the light-emitting component and the calibration circuit, and is used to transmit the power supply DC based on the enable signal;

[0010] Each of the aforementioned enable signals is connected to a corresponding drive component.

[0011] In one embodiment, the calibration circuit includes:

[0012] A first comparison circuit, connected to the detection circuit, is used to output a first decision signal in response to the detection signal being greater than a first preset voltage.

[0013] The second comparison circuit is connected to the detection circuit and is used to output a second decision signal in response to the detection signal being less than the second preset voltage.

[0014] The output circuit, together with the first comparison circuit, the second comparison circuit, and the plurality of driving components, is used to output the enable signal, decrease the number of output enable signals according to the first decision signal, and increase the number of output enable signals according to the second decision signal.

[0015] In one embodiment, there are n driving components, where n is an even number; the output circuit includes:

[0016] A first output module, connected to the first comparison circuit and n / 2 of the driving components, is configured to output n / 2 enable signals according to a first configuration signal, and reduce the number of output enable signals according to the first decision signal.

[0017] The second output module, connected to the second comparison circuit and n / 2 of the driving components, is used to stop the output of the enable signal according to the second configuration signal and to increase the number of the output enable signals according to the second decision signal.

[0018] In one embodiment, the first decision signal includes a first positive decision signal and a first negative decision signal; the first configuration signal includes a first reset signal and a first set signal;

[0019] The first output module includes a first D flip-flop, a first transmission gate, and n / 2 second D flip-flops;

[0020] The data input terminal of the first D flip-flop and the positive control terminal of the first transmission gate are used together as the first negative decision signal input terminal of the first output module, and are connected to the first comparison circuit to receive the first negative decision signal.

[0021] The negative control terminal of the first transmission gate serves as the first positive decision signal input terminal of the first output module, and is connected to the first comparison circuit to receive the first positive decision signal.

[0022] The data output terminal of the first D flip-flop is connected to the input terminal of the first transmission gate, and the output terminal of the first transmission gate is connected to the data input terminal of the first second D flip-flop.

[0023] The data input terminal of the i-th second D flip-flop and the data output terminal of the (i+1)-th second D flip-flop together serve as the i-th enable signal output terminal of the first output module, and are connected to the i-th driving component to output the i-th enable signal;

[0024] The data output terminals of the n / 2nd second D flip-flops are used together as the n / 2nd enable signal output terminal of the first output module, and are connected to the n / 2nd driving component to output the n / 2nd enable signal;

[0025] The clock input of the first D flip-flop and the clock inputs of n / 2 second D flip-flops are used together as the clock signal input of the first output module to receive the clock signal.

[0026] The reset terminals of n / 2 of the second D flip-flops (DFF1 to DFF(n / 2)) are used together as the first reset signal input terminal of the first output module to receive the first reset signal;

[0027] The set terminals of n / 2 of the second D flip-flops are used together as the first set signal input terminal of the first output module to receive the first set signal;

[0028] Where i is a positive integer less than n / 2.

[0029] In one embodiment, the second decision signal includes a second positive decision signal and a second negative decision signal; the second configuration signal includes a second reset signal and a second set signal.

[0030] The second output module includes a third D flip-flop, a second transmission gate, and n / 2 fourth D flip-flops;

[0031] The data input terminal of the third D flip-flop and the negative control terminal of the second transmission gate together serve as the second positive decision signal input terminal of the second output module, and are connected to the second comparison circuit to receive the second positive decision signal;

[0032] The positive control terminal of the second transmission gate serves as the second negative decision signal input terminal of the second output module and is connected to the second comparison circuit to receive the second negative decision signal.

[0033] The data output terminal of the third D flip-flop is connected to the input terminal of the second transmission gate, and the output terminal of the second transmission gate is connected to the data input terminal of the first fourth D flip-flop.

[0034] The data input terminal of the j-th fourth D flip-flop and the data output terminal of the (i+1)-th second D flip-flop together serve as the j-th enable signal output terminal of the second output module, and are connected to the n / 2+j-th driving component to output the n / 2+j-th enable signal;

[0035] The data output terminal of the n / 2nd fourth D flip-flop serves as the n / 2nd enable signal output terminal of the second output module, and is connected to the nth driving component to output the nth enable signal;

[0036] The clock input of the third D flip-flop and the clock inputs of n / 2 fourth D flip-flops are used together as the clock signal input of the second output module to receive the clock signal.

[0037] The reset terminals of n / 2 of the fourth D flip-flops are used together as the second reset signal input terminal of the second output module to receive the second reset signal;

[0038] The set terminals of n / 2 of the fourth D flip-flops are used together as the second set signal input terminal of the second output module to receive the second set signal;

[0039] Where j is an integer less than n and greater than or equal to n / 2+1.

[0040] In one embodiment, the first decision signal includes a first positive decision signal and a first negative decision signal;

[0041] The first comparison circuit includes a first comparator and a first inverter;

[0042] The non-inverting input terminal of the first comparator serves as the first reference voltage input terminal of the first comparator circuit, so as to connect to the first reference voltage;

[0043] The inverting input terminal of the first comparator serves as the detection signal input terminal of the first comparator circuit and is connected to the detection circuit to receive the detection signal;

[0044] The output terminal of the first comparator and the input terminal of the first inverter together serve as the first positive decision signal output terminal of the first comparator circuit, and are connected to the output circuit to output the first positive decision signal;

[0045] The output terminal of the first inverter serves as the first negative decision signal output terminal of the first comparator circuit and is connected to the output circuit to output the first negative decision signal.

[0046] In one embodiment, the second decision signal includes a second positive decision signal and a second negative decision signal;

[0047] The second comparison circuit includes a second comparator and a second inverter;

[0048] The inverting input of the second comparator serves as the second reference voltage input of the second comparator circuit, so as to connect to the second reference voltage;

[0049] The non-inverting input terminal of the second comparator serves as the detection signal input terminal of the second comparator circuit and is connected to the detection circuit to receive the detection signal;

[0050] The output terminal of the second comparator and the input terminal of the second inverter together serve as the second positive decision signal output terminal of the second comparator circuit, and are connected to the output circuit to output the second positive decision signal;

[0051] The output terminal of the second inverter serves as the second negative decision signal output terminal of the second comparator circuit and is connected to the output circuit to output the second negative decision signal.

[0052] In one embodiment, the detection circuit includes:

[0053] A sampling circuit, connected to the light-emitting component, is used to sample the DC power supply flowing through the light-emitting component to output a two-ended sampling signal.

[0054] A conversion circuit, connected to the sampling circuit and the calibration circuit, is used to convert a double-ended sampling signal into a single-ended detection signal.

[0055] In one embodiment, the sampling circuit includes a first field-effect transistor, a second field-effect transistor, and a first resistor;

[0056] The source of the first field-effect transistor and the source of the second field-effect transistor are used together as the DC power input terminal of the sampling circuit to connect to the DC power supply.

[0057] The drain of the second field-effect transistor, the drain of the first field-effect transistor, the first end of the first resistor, and the second end of the first resistor together serve as the sampling signal output terminal of the sampling circuit, and are connected to the conversion circuit to output the sampling signal.

[0058] This invention also provides an electronic device, which includes the above-described photoelectric driving circuit.

[0059] The beneficial effects of this invention compared to the prior art are as follows: The detection circuit detects the DC power supply flowing through the light-emitting component and outputs a detection signal; the calibration circuit outputs various enable signals based on the detection signal; when the detection signal is greater than a first preset voltage, the calibration circuit reduces the number of output enable signals, thereby reducing the number of driving components transmitting the DC power supply and decreasing the DC power supply current; when the detection signal is less than a second preset voltage, the number of output enable signals increases, thereby increasing the number of driving components transmitting the DC power supply and increasing the DC power supply current; therefore, dynamically adjusting the DC power supply current reduces the possibility of LED aging in the light-emitting component and improves the stability and reliability of the photoelectric driving circuit; simultaneously, while dynamically adjusting the DC power supply current, a microprocessor is not required, simplifying the circuit and reducing costs. Attached Figure Description

[0060] To more clearly illustrate the technical inventions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0061] Figure 1 A schematic diagram of a photoelectric driving circuit provided in an embodiment of this application;

[0062] Figure 2 This is a schematic diagram of a calibration circuit in a photoelectric driving circuit provided in an embodiment of this application;

[0063] Figure 3 This is a schematic diagram of a detection circuit in a photoelectric driving circuit provided in an embodiment of this application;

[0064] Figure 4 This is a partial example circuit schematic diagram of a calibration circuit in a photoelectric driving circuit provided in an embodiment of this application;

[0065] Figure 5 This is a partial example circuit schematic diagram of a photoelectric driving circuit provided in an embodiment of this application;

[0066] Figure 6 This is a partial example circuit schematic diagram of a photoelectric driving circuit provided in one embodiment of this application. Detailed Implementation

[0067] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0068] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0069] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0070] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0071] Figure 1 A schematic diagram of the photoelectric driving circuit provided in a preferred embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0072] The aforementioned photoelectric driving circuit, connected to the light-emitting component 80, includes a detection circuit 01, a calibration circuit 02, and a driving circuit 03.

[0073] The detection circuit 01 is connected to the light-emitting component 80 and is used to detect the DC power supply flowing through the light-emitting component 80 in order to output a detection signal.

[0074] The calibration circuit 02 is connected to the detection circuit 01 and is used to output various enable signals based on the detection signal. In response to the detection signal being greater than a first preset voltage, the number of output enable signals is reduced, and in response to the detection signal being less than a second preset voltage, the number of output enable signals is increased.

[0075] The drive circuit 03 includes multiple drive components 31 connected in parallel.

[0076] The driving component 31, connected to the light-emitting component 80 and the calibration circuit 02, is used to transmit DC power based on the enable signal.

[0077] Each enable signal is connected to a corresponding drive component 31.

[0078] The light-emitting component 80 is used to emit light according to the power supply DC.

[0079] like Figure 2 As shown, the calibration circuit 02 includes a first comparison circuit 21, a second comparison circuit 22, and an output circuit 23.

[0080] The first comparison circuit 21 is connected to the detection circuit 01 and is used to output a first decision signal in response to the detection signal being greater than a first preset voltage.

[0081] The second comparison circuit 22 is connected to the detection circuit 01 and is used to output a second decision signal in response to the detection signal being less than the second preset voltage.

[0082] The output circuit 23, together with the first comparison circuit 21, the second comparison circuit 22, and a plurality of driving components 31, is used to output an enable signal, and decrease the number of output enable signals according to the first decision signal, and increase the number of output enable signals according to the second decision signal.

[0083] The calibration circuit 02, comprising a first comparator circuit 21, a second comparator circuit 22, and an output circuit 23, can be implemented using only comparators and logic circuits, eliminating the need for a microprocessor. This simplifies the circuit and reduces costs while dynamically adjusting the current of the supplied DC power.

[0084] There are n driving components 31, where n is an even number; the output circuit 23 includes a first output module and a second output module.

[0085] The first output module is connected to the first comparison circuit 21 and n / 2 driving components 31, and is used to output n / 2 enable signals according to the first configuration signal, and reduce the number of output enable signals according to the first decision signal.

[0086] The second output module, connected to the second comparison circuit 22 and n / 2 drive components 31, is used to stop the output of the enable signal according to the second configuration signal and increase the number of output enable signals according to the second decision signal.

[0087] Understandably, when the photoelectric drive circuit is activated, the first output module outputs n / 2 enable signals according to the first reset signal, and the second output module stops outputting enable signals according to the second reset signal. Then, when the detection signal is greater than the first preset voltage, the first output circuit 23 reduces the number of output enable signals, thereby reducing the number of drive components 31 transmitting DC power and reducing the current of the DC power supply. When the detection signal is less than the second preset voltage, the second output module increases the number of output enable signals, thereby increasing the number of drive components 31 transmitting DC power and increasing the current of the DC power supply.

[0088] In one embodiment, the current generated by the DC power transmitted by n / 2 driving components 31 is the current required by the light-emitting component 80 at room temperature.

[0089] The output circuit 23 is implemented by two output modules, which achieves circuit symmetry and improves adjustment accuracy.

[0090] like Figure 3 As shown, the detection circuit 01 includes a sampling circuit 11 and a conversion circuit 12.

[0091] The sampling circuit 11 is connected to the light-emitting component 80 and is used to sample the DC power supply flowing through the light-emitting component 80 to output a two-terminal sampling signal.

[0092] The conversion circuit 12, connected to the sampling circuit 11 and the calibration circuit 02, is used to convert the double-ended sampling signal into a single-ended detection signal.

[0093] The detection circuit 01 has a simple structure and low cost.

[0094] Figure 4 This invention illustrates a partial example circuit structure of the calibration circuit for the photoelectric driving circuit provided in an embodiment of the present invention. Figure 5 This invention illustrates a partial example circuit structure of a photoelectric driving circuit provided in an embodiment of the present invention. Figure 6 The present invention illustrates another partial example circuit structure of the photoelectric driving circuit provided in an embodiment of the invention. For ease of explanation, only the parts related to the embodiment of the invention are shown, and are described in detail below:

[0095] like Figure 4 As shown, the first decision signal includes a first positive decision signal and a first negative decision signal; the first configuration signal includes a first reset signal and a first set signal; the first output module 231 includes a first D flip-flop U1, a first transmission gate U2 and n / 2 second D flip-flops (DFF1 to DFF(n / 2)).

[0096] The data input terminal D of the first D flip-flop U1 and the positive control terminal of the first transmission gate U2 together serve as the first negative decision signal input terminal of the first output module 231, and are connected to the first comparison circuit 21 to receive the first negative decision signal.

[0097] The negative control terminal of the first transmission gate U2 serves as the first positive decision signal input terminal of the first output module 231, and is connected to the first comparison circuit 21 to receive the first positive decision signal.

[0098] The data output terminal Q of the first D flip-flop U1 is connected to the input terminal of the first transmission gate U2, and the output terminal of the first transmission gate U2 is connected to the data input terminal D of the first second D flip-flop DFF1.

[0099] The data input terminal D of the i-th second D flip-flop DFFi and the data output terminal Q of the (i+1)-th second D flip-flop DFF1 together serve as the i-th enable signal output terminal of the first output module 231, which is connected to the i-th driving component 31 to output the i-th enable signal.

[0100] The data output terminal Q of the second D flip-flop DFF(n / 2) serves as the second enable signal output terminal of the first output module 231, and is connected to the second drive component 31 to output the second enable signal.

[0101] The clock input of the first D flip-flop U1 and the clock inputs of n / 2 second D flip-flops (DFF1 to DFF(n / 2)) are used together as the clock signal input of the first output module 231 to receive the clock signal CLK.

[0102] The reset terminals R of n / 2 second D flip-flops (DFF1 to DFF(n / 2)) are used together as the first reset signal input terminal of the first output module 231 to connect to the first reset signal R1.

[0103] The set terminals S of n / 2 second D flip-flops (DFF1 to DFF(n / 2)) are used together as the first set signal input terminal of the first output module 231 to connect to the first set signal S1.

[0104] Where i is a positive integer less than n / 2.

[0105] like Figure 4 As shown, the second decision signal includes a second positive decision signal and a second negative decision signal; the second configuration signal includes a second reset signal and a second set signal; the second output module 232 includes a third D flip-flop U3, a second transmission gate U4, and n / 2 fourth D flip-flops (DFF(n / 2+1) to DFFn).

[0106] The data input terminal D of the third D flip-flop U3 and the negative control terminal of the second transmission gate U2 together serve as the second positive decision signal input terminal of the second output module 232, and are connected to the second comparison circuit 22 to receive the second positive decision signal.

[0107] The positive control terminal of the second transmission gate U4 serves as the second negative decision signal input terminal of the second output module 232 and is connected to the second comparison circuit 22 to receive the second negative decision signal.

[0108] The data output terminal Q of the third D flip-flop U3 is connected to the input terminal of the second transmission gate U4, and the output terminal of the second transmission gate U4 is connected to the data input terminal D of the first fourth D flip-flop DFF(n / 2+1).

[0109] The data input terminal D of the j-th fourth D flip-flop DFF(n / 2+j) and the data output terminal Q of the (i+1)-th second D flip-flop DFF(n / 2+j+1) together serve as the j-th enable signal output terminal of the second output module 232, and are connected to the n / 2+j-th drive component 31 to output the n / 2+j-th enable signal.

[0110] The data output terminal Q of the n / 2nd fourth D flip-flop DFFn serves as the n / 2nd enable signal output terminal of the second output module 232, and is connected to the nth drive component 31 to output the nth enable signal.

[0111] The clock input of the third D flip-flop U3 and the clock inputs of the n / 2 fourth D flip-flops (DFF(n / 2+1) to DFFn) are used together as the clock signal input of the second output module 232 to receive the clock signal CLK.

[0112] The reset terminals R of n / 2 fourth D flip-flops (DFF(n / 2+1) to DFFn) are used together as the second reset signal input terminal of the second output module 232 to connect to the second reset signal R2.

[0113] The set terminals S of n / 2 fourth D flip-flops (DFF(n / 2+1) to DFFn) are used together as the second set signal input terminal of the second output module 232 to connect to the second set signal S2.

[0114] Where j is an integer less than n and greater than or equal to n / 2+1.

[0115] like Figure 4 As shown, the first decision signal includes a first positive decision signal and a first negative decision signal; the first comparison circuit 21 includes a first comparator U5 and a first inverter U6;

[0116] The non-inverting input of the first comparator U5 serves as the first reference voltage input of the first comparator circuit 21, and is connected to the first reference voltage VH. The inverting input of the first comparator U5 serves as the detection signal input of the first comparator circuit 21, and is connected to the detection circuit 01, and is connected to the detection signal VRO. The output of the first comparator U5 and the input of the first inverter U6 together serve as the first positive decision signal output of the first comparator circuit 21, and are connected to the output circuit 23, and are connected to output the first positive decision signal. The output of the first inverter U6 serves as the first negative decision signal output of the first comparator circuit 21, and is connected to the output circuit 23, and are connected to output the first negative decision signal.

[0117] like Figure 4 As shown, the second decision signal includes a second positive decision signal and a second negative decision signal; the second comparison circuit 22 includes a second comparator U7 and a second inverter U8.

[0118] The inverting input of the second comparator U7 serves as the second reference voltage input of the second comparator circuit 22, and is connected to the second reference voltage VL. The non-inverting input of the second comparator U7 serves as the detection signal input of the second comparator circuit 22, and is connected to the detection circuit 01, and is connected to the detection signal VRO. The output of the second comparator U7 and the input of the second inverter U8 together serve as the second positive decision signal output of the second comparator circuit 22, and are connected to the output circuit 23, and are used to output the second positive decision signal. The output of the second inverter U8 serves as the second negative decision signal output of the second comparator circuit 22, and is connected to the output circuit 23, and is used to output the second negative decision signal.

[0119] like Figure 5 and Figure 6 As shown, the sampling circuit 11 includes a first field-effect transistor M1, a second field-effect transistor M2, and a first resistor R1;

[0120] The source of the first field-effect transistor M1 and the source of the second field-effect transistor M2 together serve as the DC power input terminal of the sampling circuit 11 to connect to the DC power supply; the drain of the second field-effect transistor M2, the drain of the first field-effect transistor M1, the first end of the first resistor R1 and the second end of the first resistor R1 together serve as the sampling signal output terminal of the sampling circuit 11, which is connected to the conversion circuit 12 to output the sampling signal.

[0121] In the specific implementation, both the first field-effect transistor M1 and the second field-effect transistor M2 are PMOS transistors. The width-to-length ratio of the first field-effect transistor M1 and the second field-effect transistor M2 are proportional, with the width-to-length ratio (W / L) of the first field-effect transistor M1 being K times that of the second field-effect transistor M2. According to the conduction characteristics of PMOS switching transistors, when the second field-effect transistor M2 is in the closed state, its on-resistance is K times that of the first field-effect transistor M1. The first resistor R1 is a current sensing resistor, typically several mΩ. By detecting the voltage across the first resistor R1, the sampling signal of the current flowing through the LED (the DC current supplying the circuit) when the calibration circuit 02 is working can be accurately obtained.

[0122] It is understandable that the first field-effect transistor M1 and the second field-effect transistor M2 can be turned on based on the enable signal; the gate of the first field-effect transistor M1 and the gate of the second field-effect transistor M2 together serve as the enable signal input terminal of the sampling circuit 11 to receive the enable signal; or

[0123] The gates of the first field-effect transistor M1 and the second field-effect transistor M2 are both connected to an effective level, and both the first field-effect transistor M1 and the second field-effect transistor M2 are turned on based on the effective level.

[0124] like Figure 5 and Figure 6As shown, the conversion circuit 12 includes an operational amplifier U9, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5.

[0125] The second resistor R2 and the first terminal of the first resistor and the first terminal of the third resistor R3 together serve as the sampling signal input terminal of the conversion circuit 12, and are connected to the sampling circuit 11 to receive the sampling signal; the inverting input terminal of the operational amplifier U9 is connected to the second terminal of the second resistor R2 and the first terminal of the fourth resistor R4, the non-inverting input terminal of the operational amplifier U9 is connected to the second terminal of the third resistor R3 and the first terminal of the fifth resistor R5, and the second terminal of the fifth resistor R5 is connected to the power supply ground; the output terminal of the operational amplifier U9 and the second terminal of the fourth resistor R4 together serve as the detection signal output terminal of the conversion circuit 12, and are connected to the calibration circuit 02 to output the detection signal.

[0126] like Figure 5 and Figure 6 As shown, the light-emitting component 80 includes a light-emitting diode (LED).

[0127] like Figure 5 As shown, the driving component 31 includes a third field-effect transistor M3 and a fourth field-effect transistor M4;

[0128] The drain of the fourth field-effect transistor M4 serves as the DC power input terminal of the driving component 31 and is connected to the light-emitting component 80 to receive the DC power supply. The source of the fourth field-effect transistor M4 is connected to the drain of the third field-effect transistor M3, and the source of the third field-effect transistor M3 is connected to the power supply ground. The gate of the fourth field-effect transistor M4 serves as the enable signal input terminal of the driving component 31 and is connected to the calibration circuit 02 to receive the enable signal. The gate of the fourth field-effect transistor M3 serves as the switch signal input terminal of the driving component 31 to receive the switch signal.

[0129] like Figure 6 As shown, the driving component 31 includes a fourth field-effect transistor M4;

[0130] The drain of the fourth field-effect transistor M4 serves as the DC power input terminal of the driving component 31 and is connected to the light-emitting component 80 to receive the DC power supply; the source of the fourth field-effect transistor M4 is connected to the power supply ground, and the gate of the fourth field-effect transistor M4 serves as the enable signal input terminal of the driving component 31 and is connected to the calibration circuit 02 to receive the enable signal.

[0131] The following is based on the working principle. Figures 4 to 6 Further explanation is provided below:

[0132] like Figure 5 and Figure 6As shown, the first field-effect transistor M1 and the second field-effect transistor M2 can be turned on based on an enable signal or an effective level; the first field-effect transistor M1, the second field-effect transistor M2 and the first resistor R1 sample the DC power supply flowing through the light-emitting diode LED to output a double-ended sampling signal; the operational amplifier U9 and its peripheral circuit convert the double-ended detection signal into a single-ended detection signal VRO.

[0133] like Figure 4 As shown, the second comparator U7 responds to the detection signal being greater than the first preset voltage VH by outputting a first positive decision signal. The first positive decision signal is inverted by the second inverter U8 to obtain a first negative decision signal. The first comparator U5 responds to the detection signal being less than the second preset voltage VL by outputting a second positive decision signal. The second positive decision signal is inverted by the first inverter U6 to obtain a second negative decision signal.

[0134] In the initial state, a first configuration signal and a second configuration signal are connected. The first configuration signal includes a low-level first reset signal R1 and a high-level first set signal S1. n / 2 second D flip-flops (DFF1 to DFF(n / 2)) output n / 2 enable signals according to the first configuration signal. The second configuration signal includes a high-level second reset signal R2 and a low-level second set signal S2. n / 2 fourth D flip-flops (DFF(n / 2+1) to DFFn) stop outputting n / 2 enable signals according to the second configuration signal. Thus, n / 2 fourth field-effect transistors M4 are turned on under the control of n / 2 enable signals, that is, half of the driving components 31 are turned on.

[0135] Then, stop inputting the first configuration signal and the second configuration signal.

[0136] If the voltage of the detection signal VRO is greater than the first preset voltage VH, the first comparator U5 outputs the first positive decision signal SH (from high level to low level), and the first inverter U6 outputs the first negative decision signal SHN (from low level to high level). At this time, the second comparator U7 stops outputting the second positive decision signal SL (remains at high level), and the second inverter U8 stops outputting the second negative decision signal SLN (remains at low level). The first negative decision signal SHN passes through the first D flip-flop U1 and the first transmission gate U2 and reaches the input of the first second D flip-flop DFF1. As the clock signal is transmitted, n / 2 second D flip-flops (DFF1 to DFF(n / 2)) will gradually switch to low level (i.e., reduce the number of enable signals), thereby gradually turning off the corresponding fourth field-effect transistor M4 in the driving component 31 and reducing the driving current (current of the DC power supply) of the light-emitting diode LED.

[0137] If the voltage of the detection signal VRO is less than the second preset voltage VL, the first comparator U5 stops outputting the first positive decision signal SH (SH remains high), and the first inverter U6 stops outputting the first negative decision signal SHN (SHN remains low); the second comparator U7 outputs the second positive decision signal SL (SL changes from high to low), and the second inverter U8 outputs the second negative decision signal SLN (SLN changes from low to high). The second positive decision signal SL passes through the third D flip-flop U3 and the second transmission gate U4 to the input of the first fourth D flip-flop (DFF(n / 2+1)). As the clock signal is transmitted, the output signals (D(n / 2) to D(n)) of n / 2 fourth D flip-flops (DFF(n / 2+1) to DFFn) will gradually jump to high level, thereby gradually turning on the corresponding fourth field-effect transistor M4 in the driving component 31, increasing the driving current (current of the DC power supply) of the light-emitting diode LED.

[0138] Figure 5 The photoelectric drive circuit shown is Figure 6 The difference in the photoelectric drive circuit shown is that the drive component 31 operates when a switch signal is received.

[0139] The present invention also provides an electronic device, which includes the above-described photoelectric driving circuit.

[0140] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0141] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A photoelectric driving circuit, characterized in that, It is connected to the light-emitting component and includes a detection circuit, a calibration circuit, and a driving circuit; The detection circuit is connected to the light-emitting component and is used to detect the DC power supply flowing through the light-emitting component in order to output a detection signal. The calibration circuit is connected to the detection circuit and is used to output various enable signals based on the detection signal. In response to the detection signal being greater than a first preset voltage, the number of output enable signals is reduced, and in response to the detection signal being less than a second preset voltage, the number of output enable signals is increased. The drive circuit includes multiple drive components connected in parallel; The driving component is connected to the light-emitting component and the calibration circuit, and is used to transmit the power supply DC based on the enable signal; Each of the aforementioned enable signals is connected to a corresponding drive component; The calibration circuit includes: A first comparison circuit, connected to the detection circuit, is used to output a first decision signal in response to the detection signal being greater than a first preset voltage. The second comparison circuit is connected to the detection circuit and is used to output a second decision signal in response to the detection signal being less than the second preset voltage. An output circuit, together with the first comparison circuit, the second comparison circuit, and the plurality of driving components, is used to output the enable signal, decrease the number of output enable signals according to the first decision signal, and increase the number of output enable signals according to the second decision signal. The driving components number n, where n is an even number; the output circuit includes: A first output module, connected to the first comparison circuit and n / 2 of the driving components, is used to output n / 2 enable signals according to a first configuration signal, and to reduce the number of the output enable signals according to the first decision signal. The second output module, connected to the second comparison circuit and n / 2 of the driving components, is used to stop the output of the enable signal according to the second configuration signal and to increase the number of the output enable signals according to the second decision signal.

2. The photoelectric driving circuit as described in claim 1, characterized in that, The first decision signal includes a first positive decision signal and a first negative decision signal; the first configuration signal includes a first reset signal and a first set signal; The first output module includes a first D flip-flop, a first transmission gate, and n / 2 second D flip-flops; The data input terminal of the first D flip-flop and the positive control terminal of the first transmission gate are used together as the first negative decision signal input terminal of the first output module, and are connected to the first comparison circuit to receive the first negative decision signal. The negative control terminal of the first transmission gate serves as the first positive decision signal input terminal of the first output module, and is connected to the first comparison circuit to receive the first positive decision signal. The data output terminal of the first D flip-flop is connected to the input terminal of the first transmission gate, and the output terminal of the first transmission gate is connected to the data input terminal of the first second D flip-flop. The data input terminal of the i-th second D flip-flop and the data output terminal of the (i+1)-th second D flip-flop together serve as the i-th enable signal output terminal of the first output module, and are connected to the i-th driving component to output the i-th enable signal; The data output terminals of the n / 2nd second D flip-flops are used together as the n / 2nd enable signal output terminal of the first output module, and are connected to the n / 2nd driving component to output the n / 2nd enable signal; The clock input of the first D flip-flop and the clock inputs of n / 2 second D flip-flops are used together as the clock signal input of the first output module to receive the clock signal. The reset terminals of n / 2 of the second D flip-flops (DFF1 to DFF(n / 2)) are used together as the first reset signal input terminal of the first output module to receive the first reset signal; The set terminals of n / 2 of the second D flip-flops are used together as the first set signal input terminal of the first output module to receive the first set signal; Where i is a positive integer less than n / 2.

3. The photoelectric driving circuit as described in claim 2, characterized in that, The second decision signal includes a second positive decision signal and a second negative decision signal; the second configuration signal includes a second reset signal and a second set signal. The second output module includes a third D flip-flop, a second transmission gate, and n / 2 fourth D flip-flops; The data input terminal of the third D flip-flop and the negative control terminal of the second transmission gate together serve as the second positive decision signal input terminal of the second output module, and are connected to the second comparison circuit to receive the second positive decision signal; The positive control terminal of the second transmission gate serves as the second negative decision signal input terminal of the second output module and is connected to the second comparison circuit to receive the second negative decision signal. The data output terminal of the third D flip-flop is connected to the input terminal of the second transmission gate, and the output terminal of the second transmission gate is connected to the data input terminal of the first fourth D flip-flop. The data input terminal of the j-th fourth D flip-flop and the data output terminal of the (i+1)-th second D flip-flop together serve as the j-th enable signal output terminal of the second output module, and are connected to the n / 2+j-th driving component to output the n / 2+j-th enable signal; The data output terminal of the n / 2nd fourth D flip-flop serves as the n / 2nd enable signal output terminal of the second output module, and is connected to the nth driving component to output the nth enable signal; The clock input of the third D flip-flop and the clock inputs of n / 2 fourth D flip-flops are used together as the clock signal input of the second output module to receive the clock signal. The reset terminals of n / 2 of the fourth D flip-flops are used together as the second reset signal input terminal of the second output module to receive the second reset signal; The set terminals of n / 2 of the fourth D flip-flops are used together as the second set signal input terminal of the second output module to receive the second set signal; Where j is an integer less than n and greater than or equal to n / 2+1.

4. The photoelectric driving circuit as described in claim 1, characterized in that, The first decision signal includes a first positive decision signal and a first negative decision signal; The first comparison circuit includes a first comparator and a first inverter; The non-inverting input terminal of the first comparator serves as the first reference voltage input terminal of the first comparator circuit, so as to connect to the first reference voltage; The inverting input terminal of the first comparator serves as the detection signal input terminal of the first comparator circuit and is connected to the detection circuit to receive the detection signal; The output terminal of the first comparator and the input terminal of the first inverter together serve as the first positive decision signal output terminal of the first comparator circuit, and are connected to the output circuit to output the first positive decision signal; The output terminal of the first inverter serves as the first negative decision signal output terminal of the first comparator circuit and is connected to the output circuit to output the first negative decision signal.

5. The photoelectric driving circuit as described in claim 1, characterized in that, The second decision signal includes a second positive decision signal and a second negative decision signal; The second comparison circuit includes a second comparator and a second inverter; The inverting input of the second comparator serves as the second reference voltage input of the second comparator circuit, so as to connect to the second reference voltage; The non-inverting input terminal of the second comparator serves as the detection signal input terminal of the second comparator circuit and is connected to the detection circuit to receive the detection signal; The output terminal of the second comparator and the input terminal of the second inverter together serve as the second positive decision signal output terminal of the second comparator circuit, and are connected to the output circuit to output the second positive decision signal; The output terminal of the second inverter serves as the second negative decision signal output terminal of the second comparator circuit and is connected to the output circuit to output the second negative decision signal.

6. The photoelectric driving circuit according to any one of claims 1 to 5, characterized in that, The detection circuit includes: A sampling circuit, connected to the light-emitting component, is used to sample the DC power supply flowing through the light-emitting component to output a two-ended sampling signal. A conversion circuit, connected to the sampling circuit and the calibration circuit, is used to convert a double-ended sampling signal into a single-ended detection signal.

7. The photoelectric driving circuit as described in claim 6, characterized in that, The sampling circuit includes a first field-effect transistor, a second field-effect transistor, and a first resistor; The source of the first field-effect transistor and the source of the second field-effect transistor are used together as the DC power input terminal of the sampling circuit to connect to the DC power supply. The drain of the second field-effect transistor, the drain of the first field-effect transistor, the first end of the first resistor, and the second end of the first resistor together serve as the sampling signal output terminal of the sampling circuit, and are connected to the conversion circuit to output the sampling signal.

8. An electronic device, characterized in that, The electronic device includes the photoelectric driving circuit as described in any one of claims 1 to 7.

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