Gate drive module and display panel

Abstract

This invention provides a gate driving module and a display panel, including multiple cascaded gate driving circuits. Each gate driving circuit includes a cascade transmission unit (a cascade receiving unit for receiving cascade transmission signals generated by an upper-level gate driving circuit, and outputting its own cascade transmission signal to a lower-level gate driving circuit based on signals from a first node and a second node), an output unit (for outputting gate control signals based on signals from one of the first and second nodes and a third node), a cascade transmission frequency division control unit, and an output frequency division control unit. The cascade transmission frequency division control unit controls the output unit to output its own cascade transmission signal based on signals from one of the first and second nodes and both of the third node. The output frequency division control unit controls the signal from the third node based on the frequency division control signal, thereby controlling the output unit to output its own gate control signal, thus achieving differentiated refresh rate settings for different display areas.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to gate driving modules and display panels. Background Technology

[0002] OLED (Organic Light-Emitting Diode) display panels are widely used due to their flexibility and other characteristics.

[0003] In OLED display panels, the gate driving circuit typically outputs effective pulses step by step to sequentially activate multiple rows of sub-pixels. The refresh rate of the entire display area is the same, making it impossible to drive different areas with different refresh rates, which limits the application scenarios.

[0004] Therefore, existing OLED display panels have the drawback that different areas cannot achieve different refresh rates, which urgently needs to be improved. Summary of the Invention

[0005] This invention provides a gate driving module and a display panel to enable different refresh rates to be used for driving different areas.

[0006] This invention provides a gate driving module, including a frequency division signal line and multiple cascaded gate driving circuits. The frequency division signal line is used to transmit a frequency division control signal to the multiple gate driving circuits. The gate driving circuits include:

[0007] The stage transmission unit includes a stage transmission receiving unit and a stage transmission output unit. The stage transmission receiving unit is used to receive the stage transmission signal generated by the gate driving circuit of the upper stage. The stage transmission output unit is electrically connected to the stage transmission receiving unit through a first node and a second node, and is used to output the stage transmission signal of this stage to the gate driving circuit of the lower stage according to the signal of the first node and the signal of the second node.

[0008] An output unit is electrically connected to the stage output unit via one of the first node, the second node, and the third node, and is used to output a gate control signal based on the signal from one of the first node, the second node, and the signal from the third node; and

[0009] The cascade frequency division control unit is electrically connected to the cascade receiving unit through the first node or the second node, and electrically connected to the cascade output unit through the fourth node. It is used to control the signal of one of the first node and the second node according to the frequency division control signal, so as to control the cascade output unit to output the cascade signal of this stage.

[0010] An output frequency division control unit is connected between the first node, the second node, and the third node, and is used to control the signal of the third node according to the frequency division control signal, so as to control the output unit to output the gate control signal of this stage.

[0011] In one embodiment, the frequency division control signal includes a first frequency division control signal and a second frequency division control signal, and the frequency division signal line includes a first frequency division signal line for transmitting the first frequency division control signal and a second frequency division control signal for transmitting the second frequency division control signal;

[0012] The first frequency division signal line is electrically connected to the output frequency division control unit to control the signal of the third node;

[0013] The second frequency division signal line is electrically connected to the cascade frequency division control unit to control the signal of one of the first node and the second node.

[0014] In one embodiment, the output frequency division control unit includes:

[0015] The first frequency divider transistor has its gate connected to the first frequency divider signal line, its source electrically connected to the first node or the second node, and its drain electrically connected to the third node.

[0016] The first frequency division control signal is used to control the third node to be electrically connected or disconnected from the first node or the second node.

[0017] In one embodiment, the output frequency division control unit further includes:

[0018] The second frequency divider transistor has its gate electrically connected to the fifth node of the stage transmission unit, its source electrically connected to the first frequency divider signal line, and its drain electrically connected to the gate of the first frequency divider transistor.

[0019] Wherein, the first frequency division control signal and the signal of the fifth node are used to control the third node to be electrically connected or disconnected from the first node or the second node;

[0020] The signal of the fifth node is also used to control the stage transmission signal and the gate control signal output by the gate drive circuit of this stage.

[0021] In one embodiment, the cascade frequency division control unit includes:

[0022] The third frequency divider transistor has its gate electrically connected to the second frequency divider signal line, the source of the first frequency divider transistor is electrically connected to the stage receiver unit through the fourth node, and the drain of the third frequency divider transistor is electrically connected to the first node or the second node.

[0023] The second frequency division control signal is used to control the fourth node to be electrically connected or disconnected from the first node or the second node.

[0024] In one embodiment, the stage transmission output unit includes:

[0025] The first stage output transistor has its gate electrically connected to the first node, its source electrically connected to the first voltage line to apply a first voltage, and its drain electrically connected to the stage output terminal in the gate drive circuit for outputting the stage transmission signal.

[0026] The second-stage output transistor has its gate electrically connected to the second node, its source electrically connected to the second voltage line to apply a second voltage, and its drain electrically connected to the stage output terminal.

[0027] In one embodiment, the output unit includes:

[0028] The first output transistor has its gate electrically connected to the third node, its source electrically connected to the first voltage line, and its drain electrically connected to the gate output terminal of the gate driving circuit used to output the gate control signal.

[0029] The second output transistor has its gate electrically connected to the first node or the second node, its source electrically connected to the second voltage line, and its drain electrically connected to the gate output terminal.

[0030] In one embodiment, the gate driving circuit is electrically connected to at least one corresponding pixel driving circuit, and the gate output terminal is electrically connected to the pixel transistor in each of the corresponding pixel driving circuits, wherein the first voltage is greater than the second voltage.

[0031] The pixel transistor is an N-type transistor, and the drain of the third frequency divider transistor and the source of the first frequency divider transistor are electrically connected to the first node.

[0032] Alternatively, the pixel transistor is a P-type transistor, and the drain of the third frequency divider transistor and the source of the first frequency divider transistor are both electrically connected to the second node.

[0033] In one embodiment, the cascading receiving unit includes:

[0034] The fourth node control unit is electrically connected to the clock signal line and the fourth node, and is used to control the signal of the fourth node according to the clock signal transmitted by the clock signal line.

[0035] The second node control unit or the first node control unit is electrically connected to the clock signal line and the second node, and is used to control the signal of the second node according to the clock signal. The first node control unit is electrically connected to the clock signal line and the first node, and is used to control the signal of the first node according to the clock signal.

[0036] An input unit, wherein the input terminal of the input unit is electrically connected to the gate driving circuit of the upper level to load the stage transmission signal generated by the gate driving circuit of the upper level, and the output terminal of the input unit is electrically connected to the fourth node control unit and the second node control unit, or electrically connected to the fourth node control unit and the first node control unit.

[0037] In one embodiment, both the cascade frequency division control unit and the output frequency division control unit are electrically connected to the first node;

[0038] The input unit includes an input transistor, the gate of which is loaded with the clock signal, the source of which is configured as the input terminal of the input unit, and the drain of which is configured as the output terminal of the input unit.

[0039] The fourth node control unit includes a first transistor, a seventh transistor, a second transistor and a third transistor connected in series. The gate of the seventh transistor is electrically connected to the drain of the input transistor, and the source of the seventh transistor is loaded with the clock signal. The gate of the first transistor is loaded with the clock signal, and the source of the first transistor is loaded with the second voltage. The drain of the first transistor is electrically connected to the gate of the second transistor and the drain of the seventh transistor. The drain of the second transistor is electrically connected to the source of the third transistor. The source of the second transistor and the gate of the third transistor are both loaded with the clock signal. The drain of the third transistor is electrically connected to the fourth node.

[0040] The second node control unit includes a fourth transistor, a first capacitor, a fifth transistor and a sixth transistor connected in series. The gate of the fourth transistor is loaded with a control signal, the source of the fourth transistor is loaded with the first voltage, and the drain of the fourth transistor is electrically connected to the second node. The gate of the fifth transistor is electrically connected to the drain of the first transistor, the source of the fifth transistor is loaded with the first voltage, the drain of the fifth transistor is electrically connected to the source of the sixth transistor, the drain of the sixth transistor is loaded with the clock signal, and the gate of the sixth transistor is also loaded with the stage transmission signal generated by the gate driving circuit of the upper stage. The first capacitor is electrically connected between the gate and drain of the sixth transistor.

[0041] In one embodiment, the second node control unit further includes:

[0042] The tenth transistor has a source loaded with the transmission signal generated by the gate drive circuit of the previous stage, a gate loaded with the clock signal, and a drain electrically connected to the gate of the sixth transistor.

[0043] The eleventh transistor has its gate and source electrically connected to the gate of the sixth transistor, and its drain electrically connected to the second node.

[0044] Embodiments of the present invention also provide a display panel, including:

[0045] Gate drive modules as described above;

[0046] The panel body includes multiple sub-pixels and multiple scan lines. Each sub-pixel includes a light-emitting device and a pixel driving circuit that drives the light-emitting device to emit light. The pixel driving circuit includes at least one transistor.

[0047] The gate control signal output by the gate driving circuit is transmitted to the gate of the transistor in the corresponding pixel driving circuit via the corresponding scan line.

[0048] In one embodiment, the display panel is in a time-division multiplexing mode of down-frequency and up-frequency mode, and the plurality of gate driving circuits include a plurality of cascaded first gate driving circuits and a plurality of cascaded second gate driving circuits cascaded after the plurality of first gate driving circuits.

[0049] The plurality of sub-pixels include a plurality of first sub-pixels electrically connected to a plurality of first gate driving circuits and a plurality of second sub-pixels electrically connected to a plurality of second gate driving circuits. The plurality of first sub-pixels constitute a first display area and the plurality of second sub-pixels constitute a second display area.

[0050] In the frequency reduction mode, the refresh rate of the first display area is greater than the refresh rate of the second display area;

[0051] In the upscaling mode, the refresh rate of the first display area is less than the refresh rate of the second display area.

[0052] In one embodiment, in the frequency reduction mode, the first frequency division control signal is used to control the third node in each stage of the gate drive circuit to be electrically connected to the first node or the second node;

[0053] Within the first type of frame, the second frequency division control signal is used to control the first node or the second node in the first gate driving circuit to be electrically connected to the fourth node, so as to control the output gate control signal to have a gate effective pulse, so as to turn on the corresponding light-emitting device;

[0054] Within the first type of frame, the second frequency division control signal is also used to control the first node or the second node and the fourth node in the second gate driving circuit to disconnect, so as to control the output gate control signal to not have the gate effective pulse, so as not to turn on the corresponding light-emitting device.

[0055] In one embodiment, in the frequency reduction mode, the second frequency division control signal is used to control the fourth node in each stage of the gate drive circuit to be electrically connected to the first node or the second node;

[0056] Within the second type of frame, the first frequency division control signal is used to control the third node in the first gate drive circuit to be electrically connected to the first node or the second node, so as to control the output gate control signal to have a gate effective pulse, so as to turn on the corresponding light-emitting device.

[0057] Within the second type of frame, the first frequency division control signal is also used to control the third node in the second gate driving circuit to disconnect from the first node or the second node, so as to control the output gate control signal to not have the gate effective pulse, so as not to turn on the corresponding light-emitting device.

[0058] In one embodiment, in the up-frequency mode, the second frequency division control signal is used to control the fourth node in each stage of the gate drive circuit to be electrically connected to the first node or the second node;

[0059] Within the third type of frame, the first frequency division control signal is used to control the third node in the first gate driving circuit to disconnect from the first node or the second node, so as to control the output gate control signal to not have the gate effective pulse, so as not to turn on the corresponding light-emitting device.

[0060] Within the third type of frame, the first frequency division control signal is used to control the first node or the second node in the second gate drive circuit to be electrically connected to the fourth node, so as to control the output gate control signal to have the gate effective pulse, so as to turn on the corresponding light-emitting device.

[0061] In one embodiment, the gate driving module includes n cascaded gate driving circuits, where n is a positive integer greater than or equal to 2, and all n gate driving circuits are loaded with the same clock signal.

[0062] Within a frame, the clock signal alternates between the first clock voltage and the second clock voltage during the period when it is effectively applied to the gate drive circuit from the i-th to the (i+k)-th stage, where i and k are both positive integers greater than or equal to 1;

[0063] Wherein, when the gate control signals output by the gate driving circuits from the (i+k+1)th to the nth stage do not include the gate effective pulse, the clock signal is always equal to the first clock voltage or the second clock voltage during the period when it is effectively applied to the gate driving circuits from the (i+k+1)th to the nth stage.

[0064] This invention provides a gate driving module and a display panel, including the frequency division signal line as described above and multiple cascaded gate driving circuits. The gate driving circuit includes the cascade transmission unit and the output unit as described above. It further includes a cascade transmission frequency division control unit electrically connected to the cascade transmission receiving unit via a first node or a second node (and also electrically connected to the cascade transmission output unit via a fourth node), and an output frequency division control unit connected between the first node, the second node, and the third node. Both control units are respectively used to control the signal of the first node or the second node according to the frequency division control signal, thereby controlling the cascade transmission output unit to output the cascade transmission signal of its current stage. They also control the signal of the third node according to the frequency division control signal, thereby controlling the output unit to output the gate control signal of its current stage. This ensures that the invalidity of the gate control signal does not affect the invalidity of the cascade transmission signal. A sequential frequency reduction mode for multiple areas of the display panel can be achieved by setting whether the cascade transmission signal has a valid cascade transmission pulse, and an arbitrary frequency conversion mode for multiple areas of the display panel can be achieved by setting whether the gate control signal has a valid gate pulse (since a valid cascade transmission pulse can always exist). Attached Figure Description

[0065] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0066] Figure 1 This is a schematic diagram of the gate driving module provided in an embodiment of the present invention.

[0067] Figure 2 and Figure 3 The following are circuit diagrams of two gate drive circuits provided in the embodiments of the present invention.

[0068] Figure 4 and Figure 5 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention.

[0069] Figure 6 and Figure 7 A circuit diagram of a pixel driving circuit provided in an embodiment of the present invention.

[0070] Figure 8 and Figure 9 They are respectively Figure 6 and Figure 7 Waveform diagram of the middle part of the signal.

[0071] Figure 10 The waveform diagram shows a portion of the signals in the single-stage gate drive circuit provided in an embodiment of the present invention.

[0072] Figures 11 to 16 The waveform diagram shows some signals in the multi-stage gate drive circuit provided in the embodiment of the present invention.

[0073] Figure 17 The waveforms of the data signal transmitted on the same data line and the two frequency division control signals corresponding to the two gate drive circuits are shown. Detailed Implementation

[0074] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0075] In the description of this invention, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In this document, the source and drain of a transistor are not distinguished and can be interchanged. The terms "low voltage" and "high voltage" refer to two voltages with relatively small and large voltage values, respectively, and can represent two voltage values ​​of the same signal at different times, or two voltage values ​​of different signals at the same or different times. Furthermore, it should be noted that the accompanying drawings only provide structures closely related to the invention, omitting some details less relevant to the invention. The purpose is to simplify the drawings and make the inventive points clear at a glance, not to indicate that the actual device is identical to the accompanying drawings. Figure 1 It is identical, but this is not a limitation of the actual device.

[0076] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase at various points in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0077] The present invention provides a gate driving module, which includes, but is not limited to, the following embodiments and combinations thereof.

[0078] In one embodiment, such as Figure 1 As shown, the gate drive module 10 includes a frequency divider signal line FDL and multiple cascaded gate drive circuits 20. The frequency divider signal line FDL is used to transmit the frequency divider control signal FD to the multiple gate drive circuits 20, such as... Figure 2 and Figure 3As shown, the gate driving circuit 20 includes: a stage transmission unit 201, including a stage transmission receiving unit 2011 and a stage transmission output unit 2012. The stage transmission receiving unit 2011 is used to receive the stage transmission signal generated by the upper-level gate driving circuit 20. The stage transmission output unit 2012 is electrically connected to the stage transmission receiving unit 2011 through a first node P and a second node Q, and is used to output the stage transmission signal of this stage to the lower-level gate driving circuit 20 according to the signal of the first node P and the signal of the second node Q; and an output unit 202, electrically connected to the stage transmission output unit 2012 through one of the first node P, the second node Q, and a third node S, and is used to output the stage transmission signal of this stage to the lower-level gate driving circuit 20 according to the signal of the first node P and the signal of the second node Q. The third node S outputs the gate control signal of this stage; and the stage transmission frequency division control unit 203 is electrically connected to the stage transmission receiving unit 2011 through the first node P or the second node Q, and electrically connected to the stage transmission output unit 2012 through the fourth node R, for controlling the signal of one of the first node P and the second node Q according to the frequency division control signal FD, so as to control the stage transmission output unit 2012 to output the stage transmission signal of this stage; the output frequency division control unit 204 is connected between the first node P, the second node Q and the third node S, for controlling the signal of the third node S according to the frequency division control signal FD, so as to control the output unit 202 to output the gate control signal of this stage.

[0079] Specifically, Figure 1 The following description uses n (n≥2) cascaded gate drive circuits 20 as an example. The first-stage gate drive circuit 2010 can use the first start signal STV1 or the second start signal STV2 (which are out of phase) as its corresponding "upper-stage gate control signal". Based on this, the gate control signal Scan(1) of this stage is transmitted to the next stage (second stage) gate drive circuit 20. Similarly, the nth stage gate drive circuit 20 can generate and output the gate control signal Scan(n) of this stage (n stage) based on the gate control signal Scan(n-1) of the (n-1)th stage. Figure 2 and Figure 3 The i-th stage gate driving circuit 20 is used as an example for explanation. The i-th stage gate driving circuit 20 can generate and output the gate control signal Scan(i) of the current stage (i-th stage) according to the gate control signal Scan(i-1) of the (i-1)-th stage.

[0080] Understandably, while the signal of one of the first node P and the second node Q electrically connected to the stage transmission output unit 2012 remains unchanged, this embodiment provides a stage transmission frequency division control unit 203 connected between the stage transmission receiving unit 2011 and the stage transmission output unit 2012. This control unit 203 can control the signal of the other of the first node P and the second node Q (whether it can be affected by the fourth node R) according to the frequency division control signal FD. This allows control over the signal transmitted to the stage transmission output unit 2012, thereby determining the specific situation of the stage transmission signal output by the stage transmission output unit 2012 (whether it has a valid stage transmission pulse), and thus determining whether it drives the next stage gate drive circuit 20. If the stage transmission signal has a valid stage transmission pulse, then the stage transmission receiving unit 2011 in the next stage gate drive circuit 2012 can be considered to have a driving effect. If 011 can work normally, similarly, the specific situation of the stage transmission signal output by the stage transmission output unit 2012 can be determined by combining the stage transmission frequency division control unit 203 of this stage; on the other hand, this embodiment also provides an output frequency division control unit 204 connected between one of the first node P, the second node Q and the third node S, so as to control the signal of the third node S according to the frequency division control signal FD, thereby controlling the specific situation (whether there is a gate effective pulse) of the gate control signal (i.e., the signal transmitted to the corresponding multiple sub-pixels Pi in the display panel to control whether the sub-pixels Pi are turned on) output by the output unit 202, so as to determine whether the corresponding multiple sub-pixels Pi are turned on. If the gate control signal has a gate effective pulse, it can be considered that the corresponding multiple sub-pixels Pi can be refreshed for later light emission.

[0081] It is important to understand that for multiple gate driving circuits 20 cascaded in sequence, if the gate control signals output by the first part of the multiple gate driving circuits 20 all output a gate effective pulse once in one frame of every n1 frames, the gate control signals output by the second part of the multiple gate driving circuits 20 all output a gate effective pulse once in one frame of every n2 frames, and the gate control signals output by the third part of the multiple gate driving circuits 20 all output a gate effective pulse once in one frame of every n3 frames, then it can be considered that the three display areas formed by the three sub-pixels Pi corresponding to these three parts of the gate driving circuits 20 have three corresponding refresh rates of (1 / n1)*m, (1 / n2)*m, and (1 / n3)*m, respectively, where m is the least common multiple of n1, n1, and n1.

[0082] In summary, in this embodiment, the gate control signal used to determine the refresh rate of any display area of ​​the display panel is directly determined by the corresponding output frequency divider unit and the frequency divider control signal FD at this time. One input terminal of the output frequency divider unit is connected to one of the first node P and the second node Q, and the other input terminal is connected to the third node S. The third node S is connected to the first node P or the second node Q through the cascade frequency divider unit. That is, it can be considered that the signal of the third node S is jointly determined by the cascade frequency divider unit and the frequency divider control signal FD loaded to the cascade frequency divider unit. Therefore, the gate control signal is jointly determined by the cascade frequency divider unit, the output frequency divider unit, and the frequency divider control signal FD loaded to the cascade frequency divider unit and the output frequency divider unit. By reasonably setting these three elements, the refresh rate of the corresponding display area can be determined. Furthermore, the above three elements in the different gate drive circuits 20 corresponding to different display areas of the display panel can be reasonably set to achieve different refresh rates respectively.

[0083] In this embodiment, there are no restrictions on whether the stage transmission frequency division unit, the output frequency division unit, and the effective time period of the frequency division control signal FD in different gate driving circuits 20 are set differently. For the convenience of circuit design, the stage transmission frequency division unit and the output frequency division unit in the multi-stage gate driving circuit 20 can be set to be the same. Correspondingly, the effective time period of the frequency division control signal FD in different gate driving circuits 20 can be set differently to achieve the differentiated refresh rate settings of different display areas.

[0084] In one embodiment, such as Figures 1 to 3 As shown, the frequency division control signal FD includes a first frequency division control signal FD1 and a second frequency division control signal FD2. The frequency division signal line FDL includes a first frequency division signal line FDL1 for transmitting the first frequency division control signal FD1 and a second frequency division signal line FDL2 for transmitting the second frequency division control signal FD2. The first frequency division signal line FDL is electrically connected to the output frequency division control unit 204 to control the signal of the third node S. The second frequency division signal line FDL is electrically connected to the cascade frequency division control unit 203 to control the signal of one of the first node P and the second node Q.

[0085] Understandably, in this embodiment, by specifically setting the frequency division signal line FDL as an independent first frequency division signal line FDL and the first frequency division signal line FDL, independent first frequency division control signal FD1 and second frequency division control signal FD2 (the two do not have to be the same) can be transmitted respectively, so as to independently control the working state of the output frequency division control unit 204 and the stage transmission frequency division control unit 203, thereby controlling the specific situation of the stage transmission signal and the gate signal generated by the gate drive circuit 20 of this stage respectively.

[0086] Specifically, the effective operating time periods of the first frequency division control signal FD1 and the second frequency division control signal FD2 for each stage of the gate drive circuit 20 can be reasonably set to meet different situations. For each stage of the gate drive circuit 20, this may include, but is not limited to, the following situations:

[0087] Case 1: The second frequency division control signal FD2 is set reasonably so that the signal of the fourth node R can act on the signal of the first node P or the signal of the second node Q, so that the cascade transmission signal generated and output by the cascade transmission frequency division control unit 203 has a cascade transmission effective pulse, thereby controlling the cascade transmission receiving unit 2011 in the next stage gate drive circuit 20 to work normally.

[0088] Based on scenario 1, the specific scenarios may include, but are not limited to, the following:

[0089] Case 1.1: Set the first frequency division control signal FD1 appropriately so that the gate control signal generated and output by the output frequency division unit has a gate effective pulse, thereby controlling the corresponding multiple sub-pixels Pi to turn on, that is, refreshing the corresponding multiple sub-pixels Pi for later light emission.

[0090] In case 1.2, the first frequency division control signal FD1 is set reasonably so that the gate control signal generated and output by the output frequency division unit does not have a gate effective pulse, thereby controlling the corresponding multiple sub-pixels Pi not to be turned on, that is, not to refresh the corresponding multiple sub-pixels Pi for later light emission.

[0091] Furthermore, in Case 1, if the effective time period of the second frequency division control signal FD2 corresponding to each stage of the gate drive circuit 20 is set so that each stage transmission signal has a stage transmission effective pulse, that is, each stage transmission signal is uninterrupted, then the first frequency division control signal FD1 can be set to control whether each stage gate control signal has a gate effective pulse. Combined with the above discussion, arbitrary frequency division of multiple display areas can be realized (the refresh rate of the later display area can be increased or decreased compared to the previous display area). That is, in one frame, the gate control signals of the preceding and following stages are controlled to have or not have gate effective pulses, or to not have or have gate effective pulses.

[0092] In scenario 2, the second frequency division control signal FD2 is set appropriately so that the signal of the fourth node R cannot act on the signal of the first node P or the signal of the second node Q. This causes the cascade transmission signal generated and output by the cascade transmission frequency division control unit 203 to not have a valid cascade transmission pulse (determined by the signal of the first node P or the signal of the second node Q). This prevents the cascade transmission receiving unit 2011 in the next stage gate drive circuit 20 from working properly. At the same time, since the signal of the third node S connected to the source of the output unit 202 is also determined by the signal of the first node P or the signal of the second node Q, it can also be considered that the signal of the third node S will cause the gate control signal of this stage to not have a valid gate pulse. Therefore, it can be considered that the gate control signal from the current stage to the gate control signal of the last stage does not have a valid gate pulse. The corresponding multiple sub-pixels Pi cannot be refreshed for later light emission. In combination with the above discussion, it can only achieve frequency reduction of multiple display areas.

[0093] Case 3: The first frequency division control signal FD1 is set reasonably so that the output frequency division control unit 204 can control the third node S to be acted by the first node P or the second node Q, thereby making the output unit 202 acted by the first node P or the second node Q.

[0094] Based on scenario 3, the specific scenarios may include, but are not limited to, the following:

[0095] In case 3.1, the second frequency division control signal FD2 is set appropriately so that the signal of the fourth node R can act on the signal of the first node P or the signal of the second node Q, so that the cascade signal generated and output by the cascade frequency division control unit 203 has a cascade effective pulse, thereby controlling the cascade receiving unit 2011 in the next stage gate drive circuit 20 to work normally. Since the signal of the first node P or the signal of the second node Q can also act on the third node S to act on the output unit 202, the gate control signal generated and output by the output frequency division unit at this time also has a gate effective pulse, thereby controlling the corresponding multiple sub-pixels Pi to turn on, that is, refreshing the corresponding multiple sub-pixels Pi for later light emission;

[0096] In case 3.2, the second frequency division control signal FD2 is set reasonably so that the signal of the fourth node R can act on the signal of the first node P or the signal of the second node Q, so that the level transmission signal generated and output by the level transmission frequency division control unit 203 does not have a level transmission effective pulse. Similarly, as can be seen from "case 2", the signal of the first node P or the signal of the second node Q cannot make the signal of the third node S invalid, which will also cause the gate control signal of this level to not have a gate effective pulse. Therefore, it can be considered that the gate control signal from the current level to the gate control signal of the last level does not have a gate effective pulse, and the corresponding multiple sub-pixels Pi cannot be refreshed for later light emission.

[0097] Furthermore, in case 3, if the effective time period of the first frequency division control signal FD1 corresponding to each stage gate drive circuit 20 is set such that the third node S of each stage is acted upon by the first node P or the second node Q, then the second frequency division control signal FD2 can be set to control whether the signal of the fourth node R acts upon the signal of the first node P or the signal of the second node Q, thereby controlling whether the stage transmission signal generated and output by each stage transmission frequency division control unit 203 has a stage transmission effective pulse. Combined with the above discussion, frequency reduction of multiple display areas can be achieved.

[0098] Case 4: By reasonably setting the first frequency division control signal FD1, the output frequency division control unit 204 cannot control the third node S to be acted upon by the first node P or the second node Q. Consequently, the output unit 202 cannot be acted upon by the first node P or the second node Q. That is, regardless of the signal of the first node P or the signal of the second node Q, the first frequency division control signal FD1 will act on the output frequency division control unit 204. This will cause the signal of the third node S to result in the gate control signal of this stage not having a valid gate pulse. Therefore, it can be considered that the gate control signal from the current stage to the gate control signal of the last stage does not have a valid gate pulse. The corresponding multiple sub-pixels Pi cannot be refreshed for later light emission. In conjunction with the above discussion, this means that only the frequency reduction of multiple display areas can be achieved.

[0099] In one embodiment, such as Figures 1 to 3 As shown, the output frequency division control unit 204 includes: a first frequency division transistor T18, the gate of the first frequency division transistor T18 being connected to the first frequency division signal line FDL, the source of the first frequency division transistor T18 being electrically connected to the first node P or the second node Q, and the drain of the first frequency division transistor T18 being electrically connected to the third node S; wherein, the first frequency division control signal FD1 is used to control the third node S to be electrically connected or disconnected from the first node P or the second node Q.

[0100] As discussed above, the first frequency division control signal FD1 can be applied to the output frequency division control unit 204 to control whether the third node S is affected by the first node P or the second node Q. Furthermore, in this embodiment, it is explained that the first frequency division control signal FD1 can be applied to the gate of the first frequency division transistor T18 in the output frequency division control unit 204 to control the electrical connection or disconnection between the third node S and the first node P or the second node Q.

[0101] Specifically, if electrically connected, the third node S can be considered to be acted upon by the first node P or the second node Q, which means that the signal of the first node P or the signal of the second node Q can control whether the gate control signal generated and output by the output unit 202 has a gate effective pulse (i.e., case 3 above); if disconnected, the third node S cannot be acted upon by the first node P or the second node Q, since neither the first node P nor the second node Q used to control the generation of the stage transmission signal can act on the output unit 202, so the gate control signal generated and output by the output unit 202 does not have a gate effective pulse (i.e., case 4 above).

[0102] In one embodiment, such as Figures 1 to 3 As shown, the output frequency division control unit 204 further includes: a second frequency division transistor T20, the gate of which is electrically connected to the fifth node of the cascade unit 201, the source of which is electrically connected to the first frequency division signal line FDL, and the drain of which is electrically connected to the gate of the first frequency division transistor T18; wherein, the first frequency division control signal FD1 and the signal of the fifth node are used to control the third node S to be electrically connected or disconnected from the first node P or the second node Q; wherein, the signal of the fifth node is also used to control the cascade signal and the gate control signal output by the gate drive circuit 20 of this stage.

[0103] Understandably, in this embodiment, a second frequency divider transistor T20 is further provided electrically connected to the gate of the first frequency divider transistor T18, and the on-state of the second frequency divider transistor T20 is determined by the signal of the fifth node. The signal of the fifth node is also used to control the stage transmission signal and the gate control signal output by this stage. That is, it can be considered that the state of the signal of the fifth node can reflect the state of both the stage transmission signal and the gate control signal of this stage. This ensures that the second frequency divider transistor T20 is turned on only when the state of both the stage transmission signal and the gate control signal generated by this stage is appropriate. This allows the first frequency divider control signal FD1 to be transmitted to the gate of the first frequency divider transistor T18 of this stage to control the on-state of the first frequency divider transistor T18. This can achieve differentiated refresh rate settings for different display areas while ensuring that the output of the stage transmission signal and the gate control signal of each stage is the correct waveform.

[0104] It should be noted that the specific connection relationship between the fifth node and the above-mentioned modules is not limited in this embodiment, as long as the limitation that "the signal of the fifth node is also used to control the stage transmission signal and the gate control signal output by the gate drive circuit 20 of this stage" is met. For example, the fifth node can be electrically connected to the first node P or the second node Q, or even the fifth node can be the first node P or the second node Q. In this invention, the fifth node is taken as node D as an example for explanation (based on...). Figure 2 , Figure 3 The second frequency divider transistors T20 in the diagram are a P-type transistor and an N-type transistor, both of which can be referred to later in the text. Figure 10 (Analysis).

[0105] Specifically, refer to the following text about Figure 2 and Figure 10 Analysis shows that the stage-transmitted signal generated in this stage has a stage-transmitted effective pulse (i.e., the signals of the first node P and the second node Q are both effective signals). If the gate control signal of this stage needs to output a gate effective pulse, then the time node in the signal of the fifth node that can guarantee the complete output of the gate effective pulse of this stage (e.g., the time node in the signal of the fifth node) can be considered. Figure 10 The voltage after the end of the fifth stage (t5) can be used to control the transmission of the first frequency divider control signal FD1 to the gate of the first frequency divider transistor T18 in this stage. For example, if the second frequency divider transistor T20 is a P-type transistor, the voltage of the fifth node can be considered to be a higher voltage before and a lower voltage after the time node when the gate effective pulse of this stage is fully output, so as to ensure that the second frequency divider transistor T20 will be turned on only after the gate effective pulse of this stage is fully output.

[0106] Specifically, if the gate control signal of this stage does not require the output of a valid gate pulse, as discussed above, the first frequency division control signal FD1 can be corresponding to the start of the effective operating period of this stage (voltage transition), and set in the signal of the fifth node to correspond to the moment when the voltage at which the valid gate pulse of this stage begins to be output (e.g., the time when the voltage appears). Figure 10 Before the start time of the third stage t3, to ensure that the electrical connection between the third node S and the first node P or the second node Q is cut off before the effective gate pulse output of this stage.

[0107] In one embodiment, such as Figures 1 to 3As shown, the cascade frequency division control unit 203 includes: a third frequency divider transistor T17, the gate of which is electrically connected to the second frequency division signal line FDL; the source of the first frequency divider transistor T18 is electrically connected to the cascade receiving unit 2011 through the fourth node R; and the drain of the third frequency divider transistor T17 is electrically connected to the first node P or the second node Q. The second frequency division control signal FD2 is used to control the fourth node R to be electrically connected or disconnected from the first node P or the second node Q.

[0108] As discussed above, the second frequency division control signal FD2 can be applied to the cascade frequency division control unit 203 to control whether the first node P or the second node Q is affected by the fourth node R. Furthermore, in this embodiment, it is explained that the second frequency division control signal FD2 can be applied to the gate of the third frequency division transistor T17 in the cascade frequency division control unit 203 to control the fourth node R to be electrically connected or disconnected from the first node P or the second node Q.

[0109] Specifically, if electrically connected, it can be assumed that the first node P or the second node Q can be acted upon by the fourth node R. This means that the signal of the fourth node R can control whether the stage transmission signal generated and output by the stage transmission output unit 2012 has a valid stage transmission pulse (i.e., case 1 above). If disconnected, it can be assumed that the first node P or the second node Q cannot be acted upon by the fourth node R. Since the fourth node R, which is used to control the stage transmission signal generated by this stage, cannot act on the stage transmission output unit 2012, it can be assumed that the stage transmission signal generated and output by the stage transmission output unit 2012 does not have a valid stage transmission pulse (i.e., case 2 above).

[0110] In one embodiment, such as Figure 2 and Figure 3 As shown, the stage transmission output unit 2012 includes: a first stage transmission output transistor T10, the gate of the first stage transmission output transistor T10 being electrically connected to the first node P, the source of the first stage transmission output transistor T10 being electrically connected to a first voltage line to apply a first voltage VGH, and the drain of the first stage transmission output transistor T10 being electrically connected to the stage transmission output terminal OUT in the gate driving circuit 20 for outputting the stage transmission signal; and a second stage transmission output transistor T9, the gate of the second stage transmission output transistor T9 being electrically connected to the second node Q, the source of the second stage transmission output transistor T9 being electrically connected to a second voltage line to apply a second voltage VGL, and the drain of the second stage transmission output transistor T9 being electrically connected to the stage transmission output terminal OUT.

[0111] Specifically, the first node P can control the on / off state of the first-stage output transistor T10 to control whether the first voltage can be transmitted to the stage output terminal OUT. The second node Q can control the on / off state of the second-stage output transistor T9 to control whether the second voltage can be transmitted to the stage output terminal OUT. As discussed above, in this invention, by setting a third frequency divider transistor T17 connected between the fourth node R and the first node P or the second node Q, the first node P or the second node Q can control whether it can receive the signal from the fourth node R, thereby controlling the on / off state of the first output transistor T22 or the second output transistor T21, and thus controlling the specific details of the stage transmission signal generated and output by the stage output terminal OUT.

[0112] For example, when the first-stage output transistor T10 is turned on and the second-stage output transistor T9 is turned off, the gate control signal can be equal to the first voltage; for another example, when the first-stage output transistor T10 is turned off and the second-stage output transistor T9 is turned on, the resulting stage transmission signal can be equal to the second voltage; for yet another example, when both are turned off, the resulting stage transmission signal can be equal to the previous voltage; for yet another example, when both are turned on, the resulting stage transmission signal can be between the first voltage and the second voltage.

[0113] In one embodiment, such as Figure 2 and Figure 3 As shown, the output unit 202 includes: a first output transistor T22, the gate of which is electrically connected to the third node S, the source of which is electrically connected to the first voltage line, and the drain of which is electrically connected to the gate output terminal OUTA of the gate driving circuit 20 for outputting the gate control signal; and a second output transistor T21, the gate of which is electrically connected to the first node P or the second node Q, the source of which is electrically connected to the second voltage line, and the drain of which is electrically connected to the gate output terminal OUTA.

[0114] Similarly, as discussed above, the third node S can control the on / off state of the first output transistor T22 to control whether the first voltage can be transmitted to the gate output terminal OUTA. The first node P or the second node Q can control the on / off state of the second output transistor T21 to control whether the second voltage can be transmitted to the gate output terminal OUTA. Combining the above discussion, it can be seen that in this invention, by setting a first frequency divider transistor T18 connected between the third node S and the first node P or the second node Q, the third node S can be controlled to receive signals from the first node P or the second node Q, thereby controlling the on / off state of the first output transistor T22 or the second output transistor T21, and thus controlling the specific situation of the gate control signal generated and output at the gate output terminal OUTA.

[0115] In one embodiment, the gate driving circuit 20 is electrically connected to at least one corresponding pixel driving circuit 302, and the gate output terminal OUTA is electrically connected to the pixel transistor in each corresponding pixel driving circuit 302, wherein the first voltage is greater than the second voltage; wherein, as Figure 2 As shown, the pixel transistor is an N-type transistor, and the drain of the third frequency divider transistor T17 and the source of the first frequency divider transistor T18 are both electrically connected to the first node P (at this time, the gate drive circuit 20 can be considered as the i-th stage NScan circuit, and the generated gate control signal is the NScano(i) signal, the stage transmission signal is the NScan(i) signal, and the stage transmission signal of the previous stage is the NScan(i-1) signal); or, as Figure 3 As shown, the pixel transistor is a P-type transistor. The drain of the third frequency divider transistor T17 and the source of the first frequency divider transistor T18 are electrically connected to the second node Q (at this time, the gate drive circuit 20 can be considered as the i-th stage PScan circuit, and the generated gate control signal is the PScano(i) signal, the stage transmission signal is the PScan(i) signal, and the stage transmission signal of the previous stage is the PScan(i-1) signal).

[0116] In this embodiment, the architecture of the pixel driving circuit 302 is not limited. It can be assumed that the pixel transistors therein can control the opening status of the corresponding sub-pixels Pi under the control of the gate control signal output by the gate driving circuit 20. Specifically, in this embodiment, based on the first voltage being greater than the second voltage, when the pixel transistor is an N-type transistor, the drain of the third frequency divider transistor T17 and the source of the first frequency divider transistor T18 are electrically connected to the first node P. This allows control over the on / off states of the first-stage output transistor T10 and the first output transistor T22, thereby controlling whether a larger first voltage (which can be the effective voltage of the N-type transistor) can be transmitted to the gate of the N-type pixel transistor, thus controlling whether the corresponding sub-pixel Pi is turned on. When the pixel transistor is a P-type transistor, the drain of the third frequency divider transistor T17 and the source of the first frequency divider transistor T18 are electrically connected to the second node Q. This allows control over the on / off states of the second-stage output transistor T9 and the second output transistor T21, thereby controlling whether a smaller second voltage (which can be the effective voltage of the P-type transistor) can be transmitted to the gate of the P-type pixel transistor, thus controlling whether the corresponding sub-pixel Pi is turned on.

[0117] As discussed above, if the duration of the effective voltage required to turn on an N-type or P-type pixel transistor is equal, it can be assumed that the voltage value of the gate effective pulse of the former (e.g., but not limited to being equal to the first voltage) is greater than the voltage value of the gate effective pulse of the latter (e.g., but not limited to being equal to the second voltage) in the NScan and PScan signals output by the NScan and PScan circuits, respectively, and the pulse widths of the gate effective pulses of the two can be equal.

[0118] Furthermore, since the cascade receiving unit 2011 can receive the cascade signal generated by the previous stage, according to the cascade effect of the cascade signal, the first start signal STV1 and the second start signal STV2 loaded onto the first-stage NScan circuit and the first-stage PScan circuit, respectively, can also be obtained by shifting the cascade signals (NScan(1)) and PScan(1)) generated by their respective first-stage gate drive circuits 20 along the negative direction of the time axis by the same distance. That is, the voltage values ​​of the effective cascade pulses of the two can be equal to the first voltage and the second voltage, respectively. Among them, the first start signal STV1, the second start signal STV2, the NScano signal, the PScano signal, the NScan signal, and the PScan signal can all be periodic signals.

[0119] In one embodiment, such as Figure 2 and Figure 3As shown, the cascading receiving unit 2011 includes: a fourth node control unit 20111, electrically connected to the clock signal lines (including but not limited to the first clock signal line CKL1 and the second clock signal line CKL2, the first clock signal XCK and the second clock signal line CKL2CK respectively loaded on the two can be symmetrical about the time axis, the voltage value at the intersection of the time axis and the voltage axis is not limited here, and both can include two different voltage values) and the fourth node R, for controlling the signal of the fourth node R according to the clock signal transmitted by the clock signal lines; a second node control unit 20112 (as shown in the figure) Figure 2 (as shown) or the first node control unit 20113 (as shown) Figure 3 As shown), the second node control unit 20112 is electrically connected to the clock signal line and the second node Q, and is used to control the signal of the second node Q according to the clock signal. The first node control unit 20113 is electrically connected to the clock signal line and the first node P, and is used to control the signal of the first node according to the clock signal. The input unit 20114 has its input terminal electrically connected to the upper-level gate drive circuit 20 to load the stage transmission signal generated by the upper-level gate drive circuit 20. The output terminal of the input unit 20114 is electrically connected to the fourth node control unit 20111 and the second node control unit 20112, or electrically connected to the fourth node control unit 20111 and the first node control unit 20113.

[0120] It should be noted that, for ease of description, the schematic diagram in this invention only illustrates the case where the second-stage output transistor T9 is located below the first-stage output transistor T10 (i.e., the second node Q is located below the first node P). Similarly, the second output transistor T21 is located below the first output transistor T22. In reality, this invention protects the connection relationship of multiple electronic devices, not just their positional relationship. Based on the input unit 20114 loading the stage transmission signal generated by the upper-stage gate drive circuit 20, such as... Figure 2 As shown, for the NScan circuit, since the cascade frequency divider control unit 203 is connected to the first node P located at the top, it can be assumed that the fourth node R is also located at the top. Therefore, it can be assumed that the fourth node control unit 20111 also needs to be located near the top to control the voltage of the fourth node R (further combined with the cascade frequency divider control unit 203 to control the voltage of the first node P). The voltage of the second node Q needs to be controlled by the second node control unit 20112 located near the bottom. Figure 3As shown, for the PScan circuit, since the cascade frequency divider control unit 203 is connected to the second node Q located at the bottom, it can be assumed that the fourth node R is also located at the bottom. Therefore, it can be assumed that the fourth node control unit 20111 also needs to be located near the bottom to control the voltage of the fourth node R (further combined with the cascade frequency divider control unit 203 to control the voltage of the second node Q). The voltage of the first node P needs to be controlled by the first node control unit 20113 located near the top.

[0121] In one embodiment, such as Figure 2As shown, the cascade frequency division control unit 203 and the output frequency division control unit 204 are both electrically connected to the first node P (i.e., the gate drive circuit 20 is described as an NScan circuit). The input unit 20114 includes an input transistor T3, the gate of which is loaded with the clock signal (e.g., connected to the first clock signal line CKL1 to load the first clock signal). The source of the input transistor T3 is configured as the input terminal of the input unit 20114, and the drain of the input transistor T3 is configured as the output terminal of the input unit 20114. The fourth node control unit 20111 includes a first transistor T4, a seventh transistor T5, a second transistor T6 and a third transistor T7 connected in series. The gate of the seventh transistor T5 is electrically connected to the drain of the input transistor T3, the source of the seventh transistor T5 is loaded with the clock signal (e.g., the first clock signal), the gate of the first transistor T4 is loaded with the clock signal (e.g., the first clock signal), the source of the first transistor T4 is loaded with the second voltage, and the drain of the first transistor T4 is electrically connected to the gate of the second transistor T6 and the seventh transistor T7. The drain of transistor T5 and the drain of the second transistor T6 are electrically connected to the source of the third transistor T7. The source of the second transistor T6 and the gate of the third transistor T7 are both loaded with the clock signal. The drain of the third transistor T7 is electrically connected to the fourth node R. The second node control unit 20112 includes a fourth transistor T13, a first capacitor C1, a fifth transistor T1 and a sixth transistor T2 connected in series. The gate of the fourth transistor T13 (electrically connected to the control line CL) is loaded with the control signal, and the source of the fourth transistor T13 is loaded with the clock signal. The first voltage is applied to the drain of the fourth transistor T13, which is electrically connected to the second node Q. The gate of the fifth transistor T1 is electrically connected to the drain of the first transistor T4. The source of the fifth transistor T1 is loaded with the first voltage. The drain of the fifth transistor T1 is electrically connected to the source of the sixth transistor T2. The drain of the sixth transistor T2 is loaded with the clock signal. The gate of the sixth transistor T2 is also loaded with the stage transmission signal generated by the gate drive circuit 20 above. The first capacitor C1 is electrically connected between the gate and drain of the sixth transistor T2.

[0122] In this invention, taking the gate drive circuit 20 as an example where all transistors are P-type transistors, the operation of some signals in some states is explained as follows: At power-on, the control signal transmitted by CL can control the fourth transistor T13 to turn on to transmit the first voltage to the second node Q; later, when the voltage in the first clock signal is low and the voltage in the (i-1)th stage gate control signal NScano(i-1) is low, the gate control signal NScano(i-1) controls the seventh transistor T5 and the second output transistor T21 to turn on. The second voltage is transmitted to the stage output terminal OUT through the second output transistor T21, and the first clock signal controls the first transistor T4 to turn on. The second voltage is transmitted to the gate of the second transistor T6 to control its turn on. At this time, the high voltage in the second clock signal controls the third transistor T7 to turn off; later, when the voltage in the first clock signal is high, the input transistor T3, the second transistor T6 and the first transistor T4 are turned off. At this time, it can be considered that the second output transistor T21 remains on, the low voltage in the second clock signal controls the third transistor T7 to turn on, the fourth node R is still not loaded with voltage, and the stage output terminal OUT still outputs the second voltage.

[0123] It should be noted that the present invention does not limit the type of each transistor in the gate drive circuit 20. For example, they can all be P-type transistors, or some can be N-type transistors and the other part can be P-type transistors. The corresponding signals can also be matched and set according to the type of transistor. For details, please refer to the full text of the principle explanation that "the transistors in the gate drive circuit 20 are all P-type transistors".

[0124] Furthermore, the fourth node control unit 20111 may also include an eighth transistor T11 and a second capacitor C2, the second node control unit 20112 may also include a ninth transistor T12, and the stage output unit 2012 may also include a third capacitor C3 electrically connected between the gate and source of the first output transistor T22. The gate of the eighth transistor T11 and the gate of the ninth transistor T12 can both be applied with a second voltage to maintain their on state. The source and drain of the eighth transistor T11 are electrically connected to the drain of the first transistor T4 and the gate of the second transistor T6, respectively. The second capacitor C2 is electrically connected between the gate and drain of the second transistor T6. The source and drain of the ninth transistor T12 are electrically connected to the drain of the input transistor T3 and the second node Q, respectively.

[0125] Among them, the first capacitor C1, the second capacitor C2 and the third capacitor C3 can be used to maintain the voltage of the corresponding node and play a coupling role. The eighth transistor T11 and the ninth transistor T12 can be ensured to turn on only when their source voltage is low enough, so as to maintain their drain voltage at a low level, which is beneficial to the turn-on of the first output transistor T22 and the second output transistor T21 respectively.

[0126] In one embodiment, such as Figure 2 As shown, the second node control unit 20112 further includes: a tenth transistor T14, the source of which is loaded with the transmission signal generated by the gate drive circuit 20 above, the gate of which is loaded with the clock signal (first clock signal), and the drain of which is electrically connected to the gate of the sixth transistor T2; and an eleventh transistor T16, the gate and source of which are both electrically connected to the gate of the sixth transistor T2, and the drain of which is electrically connected to the second node Q. Similarly, a twelfth transistor T15 can be provided to maintain a lower voltage at the gate of the sixth transistor T2. The gate of the twelfth transistor T15 can be loaded with a second voltage, and the source and drain of the twelfth transistor T15 can be electrically connected to the drain of the tenth transistor T14 and the gate of the sixth transistor T2, respectively.

[0127] Understandably, in this embodiment, the second node control unit 20112 is also provided with the aforementioned tenth transistor T14 and eleventh transistor T16. The tenth transistor T14 can be used to control the voltage of the gate of the sixth transistor T2. Furthermore, by setting the eleventh transistor T16 connected between the second node Q and the gate of the sixth transistor T2, the second node Q is not directly electrically connected to the first capacitor C1, so as to avoid being coupled by the first capacitor C1 and maintaining the second node Q with a low voltage.

[0128] It is important to note that the comparison Figure 3 and Figure 2As can be seen, one difference between the PScan circuit and the NScan circuit lies in the difference between the second start signal STV2 and the first start signal STV1, as discussed above. The specific structures of the input unit 20114 and the output unit 202 of both can be the same. Another difference is that the NScan circuit requires a fourth node control unit 20111 and a second node control unit 20112, while the PScan circuit requires a fourth node control unit 20111 and a first node control unit 20113. Specifically, the specific structure of the fourth node control unit 20111 in the NScan circuit can be the same as the specific structure of the first node control unit 20113 in the PScan circuit. The difference is that the output of the former is connected to the first node P through a cascaded frequency divider control unit 203, while the output of the latter is directly connected to the first node P. Similarly, the specific structure of the second node control unit 20112 in the NScan circuit can be the same as the specific structure of the third node S control unit in the PScan circuit. The difference is that the output of the former is directly connected to the second node Q, while the output of the latter is connected to the second node Q through a cascaded frequency divider control unit 203.

[0129] Furthermore, the gate drive circuit 20 in this invention can also be, but is not limited to, an EM circuit. The difference between the EM circuit and the NScan circuit is that the first start signal STV1 is replaced with a third start signal STV3. The third start signal STV3 can be understood as the first start signal STV1 being shifted a certain distance along the negative or positive direction of the time axis, and the waveforms of the two do not overlap. Similarly, the third start signal STV3 can also be a periodic signal.

[0130] The present invention provides a display panel, which includes, but is not limited to, the following embodiments and combinations thereof.

[0131] In one embodiment, combined with Figures 4 to 7 As shown, the display panel 100 includes: a gate driving module 10 as described above; a panel body 30, including multiple sub-pixels Pi and multiple scan lines SL, wherein the multiple sub-pixels Pi include light-emitting devices 301 and pixel driving circuits 302 for driving the light-emitting devices 301 to emit light, and the pixel driving circuits 302 include at least one transistor (i.e., the pixel transistor discussed above); wherein the gate control signal output by the gate driving circuit 20 is transmitted to the gate of the multiple transistors in the corresponding multiple pixel driving circuits 302 via the corresponding scan lines.

[0132] in, Figure 4Taking a display panel 100 comprising six gate drive modules 10 (GOA1, GOA2, two GOA3, GOA4, and GOA5, electrically connected to the corresponding sub-pixels Pi via a first scan line EML1, a second scan line NSL1, a third scan line PSL, a fourth scan line NSL2, and a fifth scan line EML2, respectively) as an example: For example, the two GOA3s can be, but are not limited to, the same PScan circuit, meaning that the signals loaded (second activation signal STV2) and the output signals of both can be the same to improve the reliability of the PScan signals output by both; for example, GOA1 and GOA5 can be two different EM circuits, and the two third activation signals STV3 corresponding to them can be different (for example, but not limited to, the pulse width and / or start time of their effective pulses can be different); for example, GOA2 and GOA4 can be two different NScan circuits, and the two first activation signals STV1 corresponding to them can be different (for example, but not limited to, the pulse width and / or start time of their effective pulses can be different).

[0133] Figure 5 and Figure 4 The difference is that the six gate drive modules 10 include two GOA1', GOA2', two GOA3', and GOA4', which are electrically connected to the corresponding sub-pixels Pi through the sixth scan line EML', the seventh scan line NSL1', the eighth scan line PSL1', and the ninth scan line NSL2', respectively. Similarly, the two GOA1' can be, but are not limited to, the same EM circuit, and GOA2' and GOA4' can be two different NScan circuits. For example, the two first start signals STV1 corresponding to them can be different, and the two GOA3 can be, but are not limited to, the same PScan circuit.

[0134] It is important to note that Figure 4 and Figure 5 The diagram only illustrates the interconnections between multiple gate drive circuits 20 within the same gate module, and the connection between each circuit and multiple sub-pixels Pi. For the signal lines connected to each gate drive circuit 20, please refer to [reference needed]. Figures 1 to 3 And the related text description above.

[0135] Specifically, in combination Figure 4 and Figure 6 As shown, Figure 6 include Figure 4The pixel driving circuit 302 corresponding to the gate driving module 10 setting method can include a data transistor M2. The source of the data transistor M2 is loaded with a data signal Vdata. The drain of the data transistor is electrically connected to the source of the driving transistor M1. The gate of the data transistor M2 (e.g., a P-type transistor) can be electrically connected to the third scan line PSL to load the PScan signal.

[0136] The pixel driving circuit 302 may further include a reset transistor M4 and a compensation transistor M3. The gate of the reset transistor M4 (e.g., an N-type transistor) may be electrically connected to the scan line NSL1 to load the NScan1 signal. The reset transistor M4 is configured to transmit the reset signal VI1 to the gate of the driving transistor M1 for reset. The gate of the compensation transistor M3 (e.g., an N-type transistor) may be electrically connected to the fourth scan line NSL2 to load the NScan2 signal. The source and drain of the compensation transistor M3 are electrically connected to the drain and gate of the driving transistor M1, respectively.

[0137] The pixel driving circuit 302 may further include an initialization transistor M7, the gate of which (e.g., a P-type transistor) is electrically connected to the fifth scan line EML2 to load the EM2 signal, and the drain of the initialization transistor M7 is electrically connected to one end of the light-emitting device 301 (the other end of the light-emitting device 301 may be loaded with a low voltage signal VSS). The initialization transistor M7 is configured to transmit the initialization signal VI2 to one end of the light-emitting device 301 for initialization.

[0138] The pixel driving circuit 302 further includes a reset transistor M8. The gate of the reset transistor M8 (e.g., a P-type transistor) can be electrically connected to the fifth scan line EML2 to load the EM2 signal. The drain of the reset transistor M8 is electrically connected to the source of the driving transistor M1. The reset transistor M8 is configured to transmit the reset signal VI3 to the source of the driving transistor M1 to reset its voltage.

[0139] The pixel driving circuit 302 may further include a first light-emitting control transistor M5 and a second light-emitting control transistor M6. The source of the first light-emitting control transistor M5 is loaded with a first high voltage VDD, and the drain of the first light-emitting control transistor M5 is electrically connected to the source of the driving transistor M1. The source and drain of the second light-emitting control transistor M6 are electrically connected to the drain of the driving transistor M1 and one end of the light-emitting device 301, respectively. The gates of both the first light-emitting control transistor M5 and the second light-emitting control transistor M6 (e.g., both are P-type transistors) are electrically connected to the first scan line EML1 to load the EM1 signal. Both are configured to control the light-emitting time of the light-emitting device 301 according to the EM1 signal.

[0140] The pixel driving circuit 302 also includes a storage capacitor Cst, which is connected in series between the source of the first light-emitting control transistor M5 and the gate of the driving transistor M1.

[0141] The pixel driving circuit 302 also includes a boost capacitor Cboost, which is connected in series between the gate of the driving transistor M1 and the gate of the data transistor M2.

[0142] Based on the above discussion, such as Figure 8 As shown, Figure 8 for Figure 7 The timing diagram corresponding to the pixel driving circuit 302 in the figure shows that the write frame WF of the display panel can include a first reset stage tim1, a second reset stage tim2, a data writing stage tim3, and a light emission stage tim4. The specific working process is as follows:

[0143] In the first reset phase tim1, the initial transistor M7 and the reset transistor M8 are turned on according to the corresponding EMo2 signal, and the compensation transistor M3 is turned on according to the corresponding NScano2 signal, so that the anode of the light-emitting device 301 is reset according to the initialization signal VI2, and the input terminal, output terminal and control terminal source, drain and gate of the driving transistor M1 are reset according to the reset signal VI3.

[0144] In the second reset phase tim2, the reset transistor M4 is turned on according to the corresponding NScano1 signal, and the compensation transistor M3 is turned on according to the corresponding NScano2 signal, so that the gate and drain of the driving transistor M1 can be reset according to the initialization signal VI2.

[0145] During the data writing phase tim3, the data transistor M2 is turned on according to the corresponding PScano signal, and the compensation transistor M3 is turned on according to the corresponding NScano2 signal, so that the gate of the driving transistor M1 can be written with the data signal Vdata.

[0146] During the light-emitting stage tim4, the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are turned on according to the EMo1 signal, so that the driving transistor M1 generates a driving current to drive the corresponding light-emitting device 301 to emit light.

[0147] Furthermore, between the light-emitting stage tim4 and the data writing stage tim3, a third reset stage tin may also be included. In the third reset stage tin, the initial transistor M7 and the reset transistor M8 are turned on according to the corresponding EMo2 signal, so that the anode of the light-emitting device 301 is reset according to the initialization signal VI2, and the source and drain of the driving transistor M1 are reset according to the reset signal VI3.

[0148] It should be noted that, by Figure 5 and Figure 4 The difference in the setting of the gate drive module 10 can be seen from the combination of Figure 5 and Figure 7 As shown, Figure 7 include Figure 5 The pixel driving circuit 302 corresponding to the gate driving module 10 setting method in the middle, namely Figure 7 Each element can only be driven by the same EM circuit, so it can only be electrically connected to the same sixth scan line EML' and be loaded with the same signal (unlike...). Figure 6 It can be electrically connected to the first scan line EML1 and the fifth scan line EML2 to be loaded with two different signals.

[0149] Specifically, such as Figure 7 As shown, compared Figure 6 The difference lies in the removal of the reset transistor M8, the replacement of the first scan line EML1 with the sixth scan line EML', the replacement of the second scan line NSL1 with the seventh scan line NSL1', the replacement of the third scan line PSL with the eighth scan line PSL1', the replacement of the fourth scan line NSL2 with the ninth scan line NSL2', and the replacement of the fifth scan line EML2 with the eighth scan line PSL1' from the previous stage.

[0150] Based on the above discussion, such as Figure 9 As shown, Figure 9 for Figure 7 The timing diagram corresponding to the pixel driving circuit 302 in the figure shows that the write frame WF of the display panel may include a first reset stage tim1', a second reset stage tim2', a data writing stage tim3', and a light emission stage tim4'. Taking the i-th stage gate driving circuit 20 as an example, the specific working process is as follows:

[0151] In the first reset phase tim1', the reset transistor M4 is turned on according to the corresponding NScano1'(i) signal, so that the gate of the driving transistor M1 is reset according to the initialization signal VI1;

[0152] In the second reset phase tim2', the initial transistor M7 is turned on according to the corresponding PScano1'(i-1) signal, so that the anode of the light-emitting device 301 is reset according to the initialization signal VI2, and the compensation transistor M3 is turned on according to the corresponding NScano1'(2) signal;

[0153] During the data writing phase tim3', the data transistor M2 is turned on according to the corresponding PScano1'(i) signal, and the compensation transistor M3 is turned on according to the corresponding NScano2'(i) signal, so that the gate of the driving transistor M1 can be written with the data signal Vdata;

[0154] In the third reset phase tim4', the initial transistor M7 is turned on according to the corresponding PScano1'(i-1) signal, so that the anode of the light-emitting device 301 can be reset again according to the initialization signal VI2;

[0155] During the coupling phase tim5', the data transistor M2 is turned on according to the corresponding PScano1'(i) signal. At this time, regardless of the data signal Vdata, since the compensation transistor M3 is turned off, it will not affect the gate voltage of the driving transistor M1. However, since the gate voltage of the data transistor M2 is reduced, the gate voltage of the driving transistor M1 will also increase.

[0156] During the light-emitting stage tim6', the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are turned on according to the EMo'(i) signal, causing the driving transistor M1 to generate a driving current to drive the corresponding light-emitting device 301 to emit light. Since the gate voltage of the driving transistor M1 in the coupling stage tim5' rises to a level greater than the data voltage given by the data signal Vdata in the data writing stage tim3', the light-emitting device 301 will have a larger brightness. It can also be considered that the upper limit of the data voltage can be effectively reduced, saving power consumption.

[0157] As can be seen from the above analysis, in order to enable the normal light emission of each row of sub-pixels Pi, each gate driving circuit 20 (each of GOA1 to GOA5 and each of GOA1' to GOA4') needs to output the corresponding gate effective pulse in the corresponding time period to control the corresponding transistor in the pixel driving circuit 302 to turn on, thereby realizing the corresponding function to turn on the sub-pixel Pi. It can also be considered that if the gate driving circuit 20 fails to output the corresponding gate effective pulse in the corresponding time period, the sub-pixel Pi in the corresponding row will not light up.

[0158] like Figure 6 and Figure 7As shown, if the PScano signal and the PScano1'(i) signal do not have a gate-active (low voltage) pulse, the data transistor M2 cannot be turned on, resulting in the data signal not being able to be written to the source of the driving transistor M1, and the sub-pixel Pi will not be able to turn on. If the EM1 signal and the EMo'(i) signal do not have a gate-active (low voltage) pulse, the first light-emitting control transistor M5 and the second light-emitting control transistor M6 cannot be turned on, resulting in the driving current not being able to be formed, and the sub-pixel Pi will not be able to turn on. If the NScano2 signal and the NScano2'(i) signal do not have a gate-active (high voltage) pulse, the compensation transistor M3 cannot be turned on, resulting in the data signal not being able to be written to the gate of the driving transistor M1, and the sub-pixel Pi will not be able to turn on. Of course, if the EMo2 signal, the NScano1 signal, and the NScano1'(i) signal do not have a valid pulse, it will also have a certain impact on the light emission of the sub-pixel Pi.

[0159] Specifically, based on Figure 6 The pixel driving circuit 302 shown, in this invention, is at least one of the three gate driving circuits 20 used to generate PScano signal, EMo1 signal, and NScano2 signal, and may be equipped with the cascade frequency division control unit 203 and the output frequency division control unit 204 discussed above, based on... Figure 7 The pixel driving circuit 302 shown in this invention, at least one of the three gate driving circuits 20 used to generate the PScano1'(i) signal, EMo'(i) signal, and NScano2'(i) signal respectively, can be equipped with the cascade frequency division control unit 203 and the output frequency division control unit 204 discussed above. Thus, based on the already set activation signals (e.g., the first activation signal STV1, the second activation signal STV2, and the third activation signal STV3) in the first-stage gate driving circuit 20, in each frame, and in conjunction with the setting of the frequency division control signal FD (refer to the discussion of cases 1 to 4 above), the first node P (for...) can be controlled. Figure 2 (Regarding) or the second node Q (for) Figure 3 Whether the third node S is electrically connected to the fourth node R, and whether the third node S is electrically connected to the first node P (for...) Figure 2 (Regarding) or the second node Q (for) Figure 3 In other words, the output gate control signal is given or denied a gate active pulse to control whether the sub-pixel Pi of the corresponding row is turned on (refreshed).

[0160] In one embodiment, such as Figure 4 and Figure 5As shown, the display panel is in a time-division multiplexing mode of down-clocking and up-clocking mode. The multiple gate driving circuits 20 include multiple cascaded first gate driving circuits 2001 and multiple cascaded second gate driving circuits 2002 cascaded after the multiple first gate driving circuits 2001. The multiple sub-pixels Pi include multiple first sub-pixels Pi1 electrically connected to the multiple first gate driving circuits 2001 and multiple second sub-pixels Pi2 electrically connected to the multiple second gate driving circuits 2002. The multiple first sub-pixels Pi constitute a first display area, and the multiple second sub-pixels Pi constitute a second display area. In the down-clocking mode, the refresh rate of the first display area is greater than the refresh rate of the second display area. In the up-clocking mode, the refresh rate of the first display area is less than the refresh rate of the second display area.

[0161] As can be seen from the above discussion, by setting the aforementioned stage transmission frequency division control unit 203 and output frequency division control unit 204 in the gate driving unit, the present invention can control whether the stage transmission signal generated in this stage has a stage transmission effective pulse, and whether the gate control signal has a gate effective pulse.

[0162] Specifically, here we take Figure 2 Taking the i-th stage NScan circuit shown as an example, here based on Figure 2 The transistors in the circuit are all P-type transistors (i.e., active low voltage). During the period when the third divider transistor T17 is on (i.e., the second divider control signal FD2 is at its lower voltage), the first clock signal line CKL1 and the second clock signal line CKL2 transmit the first clock signal and the second clock signal, respectively. Figure 9 The timing diagram of the NScan circuit shown may include, but is not limited to, the following six operating stages t1 to t6.

[0163] In the first stage t1, the first clock signal XCK is set low, the second clock signal CK is set high, and the stage transmission signal NScan(i-1) generated by the previous stage is set low. The third transistor T7 is turned off according to the second clock signal CK. The first transistor T4, the input transistor T3, and the tenth transistor T14 are turned on according to the first clock signal XCK. The low stage transmission signal NScan(i-1) is transmitted to nodes D, Q, and F, causing the seventh transistor T5, the thirteenth transistor T8, the second stage output transistor T9, the sixth transistor T2, and the eleventh transistor T16 to be turned on according to NScan(i-1). The second voltage VGL is transmitted to nodes C and B, and the high second clock signal CK is transmitted to node E. The first voltage VGH is transmitted to node P (the fourth node R), causing the second transistor T6 and the fifth transistor T1 to turn on according to the second voltage VGL. The high second clock signal line CK is transmitted to node A to charge the second capacitor C2 to the voltage difference between nodes A and B. The first voltage VGH is transmitted to node E (the voltage of node E can be between the first voltage VGH and the high voltage of the second clock signal line CK) to charge the first capacitor C1 to the voltage difference between nodes E and F, so that the voltage of node F is coupled and increases. Since the first stage output transistor T10 is turned off and the second stage output transistor T9 is turned on, the generated gate control signal NScano(i) is low voltage.

[0164] In the second stage t2, the first clock signal XCK is set high, the second clock signal line CK is set low, and the stage transmission signal NScan(i-1) generated by the previous stage is set low. The first transistor T4, input transistor T3, and tenth transistor T14 are turned off according to the first clock signal XCK. The gate, node D, second node Q, and node F of the seventh transistor T5 remain at their previous voltages. The sixth transistor T2 remains on. The low-set second clock signal line CK is transmitted to node E. The voltage at node F is further pulled down by the falling coupling of the second clock signal CK through the first capacitor C1, so that the eleventh transistor T16 remains on. The voltage at node F is transmitted to node D, but the voltage at node D is also increased due to the rising coupling effect of the first clock signal XCK transmitted through the first clock signal line CKL1 in the circuit layout. The eleventh transistor T16 is turned off because... The function of the ninth transistor T12 is to prevent the voltage of the second node Q from changing with the voltage of node D, and the second-stage output transistor T9 remains on; the seventh transistor T5 remains on, and the high first clock signal XCK is transmitted to nodes C and B, while the fifth transistor T1 and the second transistor T6 are off; the thirteenth transistor T8 is turned on according to the voltage of node D, and the first voltage VGH is transmitted to the first node P (the fourth node R), causing the first-stage output transistor T10 to turn off, while the low second clock signal CK turns on the third transistor T7, and the first voltage VGH is further transmitted to node A to charge the second capacitor C2 to equal the voltage difference between nodes A and B; since the first-stage output transistor T10 is off and the second-stage output transistor T9 is on, the generated gate control signal NScano(i) is low voltage;

[0165] In the third stage t3, the first clock signal XCK is set low, the second clock signal CK is set high, and the stage transfer signal NScan(i-1) generated by the previous stage is set high. The third transistor T7 is turned off according to the second clock signal CK. The first transistor T4, input transistor T3, and tenth transistor T14 are turned on according to the first clock signal XCK. The high stage transfer signal NScan(i-1) is transmitted to the gates of nodes D, Q, F, and the seventh transistor T5. The second voltage VGL is transmitted to nodes C and B. The second stage output transistor T9 is turned off, and the seventh transistor T5 is turned off according to the high stage transfer signal NScan(i-1). The fifth transistor T1 and the second transistor T6 are turned off according to the second stage output transistor T9. The second voltage VGL is turned on, and the first voltage VGH is transmitted to node E to charge the first capacitor C1 to the voltage difference between nodes E and F. The second clock signal line CK, which is set high, is transmitted to node A to charge the second capacitor C2 to the voltage difference between nodes A and B. The thirteenth transistor T8 is turned off according to the stage transmission signal NScan(i-1) which is set high. The first node P (the fourth node R) maintains the previous (high) voltage through the third capacitor C3, so that the first stage output transistor T10 is turned off. Since the first stage output transistor T10 is turned off and the second stage output transistor T9 is turned off, that is, the stage output terminal OUT is floating, so the generated gate control signal NScano(i) is maintained at a low voltage.

[0166] In the fourth stage t4, the first clock signal XCK is set high, the second clock signal CK is set low, and the stage transfer signal NScan(i-1) generated by the previous stage is set high. Input transistor T3, first transistor T4, and tenth transistor T14 are turned off according to the first clock signal XCK. The gate, node D, second node Q, and node C of the seventh transistor T5 remain at their previous voltages. The seventh transistor T5 is turned off according to its previous high voltage. The second-stage output transistor T9 is turned off according to its previous high voltage at the second node Q. The thirteenth transistor T8 is turned off according to its high voltage at node D. The fifth transistor T1 and the second transistor T6 are turned on according to their previous low voltage at node C. The sixth transistor T2 is turned on according to its previous high voltage at node F. The voltage is turned off; the first voltage VGH is transmitted to node E through the fifth transistor T1, meaning the voltage at node E remains essentially unchanged. Combined with the coupling effect of the first capacitor C1, the voltage at node F can also remain essentially unchanged; the second clock signal CK, which is set low, is transmitted to node A through the second transistor T6. Combined with the coupling effect of the second capacitor C2, the voltage at node B also decreases; the third transistor T7 is turned on according to the second clock signal CK. The low voltage at point A is transmitted to node P (the fourth node R) through the third transistor T7, thereby turning on the first-stage output transistor T10. Since the first-stage output transistor T10 is turned on and the second-stage output transistor T9 is turned off, the generated gate control signal NScano(i) is a high voltage;

[0167] In the fifth stage t5, the first clock signal XCK is set low, the second clock signal line CK is set high, and the stage transmission signal NScan(i-1) generated by the previous stage is set low. The third transistor T7 is turned off according to the second clock signal line CK. The first transistor T4, input transistor T3, and tenth transistor T14 are turned on according to the first clock signal XCK. The low stage transmission signal NScan(i-1) is transmitted through input transistor T3 to the gates of nodes D, Q, and T5. The second stage output transistor T9 is turned on according to the low voltage of Q. The sixth transistor T2 is turned on according to the voltage of F so that the high second clock signal line CK is transmitted to E, charging the first capacitor C1 to equal the voltage difference between nodes E and F. The seventh transistor T5 is turned on so that the low first clock signal XCK is transmitted to nodes C and B. The fifth transistor T1 is turned on according to the low first clock signal XCK and the second voltage VGL. The voltage VGH is transmitted to node E through the fifth transistor T1 (the voltage of node E can be between the first voltage VGH and the high voltage of the second clock signal line CK). Since the first voltage VGH and the high voltage of the second clock signal line CK are equal, the voltage of node E is almost unchanged, and the voltage of node F is almost unchanged. The eleventh transistor T16 is turned off, which can prevent the first capacitor C1 from affecting the voltage drop rate of the second node Q. The second transistor T6 is turned on according to the low voltage of node B, so that the high second clock signal line CK is transmitted to node A, so as to charge the second capacitor C2 to be equal to the voltage difference between nodes A and B. The thirteenth transistor T8 is turned on according to the low voltage of node D, so that the first voltage VGH is transmitted to the first node P (the fourth node R), thereby turning off the first stage output transistor T10. Since the first stage output transistor T10 is turned off and the second stage output transistor T9 is turned on, the generated gate control signal NScano(i) is low voltage.

[0168] In the sixth stage t6, the stage transmission signal NScan(i-1) generated by the previous stage is set low, and the first clock signal XCK and the second clock signal line CK are alternately set low and high, causing the voltage of node F to couple downward. The voltage of node F gradually decreases with each downward coupling, approaching -16V, and the voltage of the second node Q gradually decreases, approaching -20V. In the first few cycles after the seventh transistor T5 in the fifth stage, the voltage of node F is more significantly coupled downward, and the voltage of the second node Q is greatly affected by the voltage of node F. Later, when the eleventh transistor T16 is turned off, the voltage of the second node Q tends to stabilize and is no longer affected by the voltage of node F.

[0169] It should be noted that the gate drive circuit provided in this invention can be, but is not limited to, a 16T3C structure or a 13T3C structure. Figure 2 and Figure 3 (Using only the former as an example for illustration), compared to the 13T3C structure, the 16T3C structure adds the aforementioned tenth transistor T14, twelfth transistor T15, and eleventh transistor T16. On the one hand, when the stage transmission signal NScan(i-1) of the previous stage writes a low voltage to the second node Q and node F, the voltage of the second node Q can simultaneously flow out from the eleventh transistor T16 and the ninth transistor T12. Moreover, the second node Q is not directly connected to the first capacitor C1 (it is blocked by the eleventh transistor T16) to maintain the voltage. Therefore, the voltage of the second node Q can drop faster, which is beneficial to the turn-on of the second stage transmission transistor T9. On the other hand, since the second node Q is not directly connected to the first capacitor C1 (it is blocked by the eleventh transistor T16), the fluctuation of the voltage of node E will not drive the change of the voltage of the second node Q. Furthermore, the eleventh transistor T16 acts like a diode, and the voltage of the second node Q will not be pulled up by node F.

[0170] Based on the above discussion, it can be seen that, referring to Figure 2 and Figure 10 It can be seen that if the stage transmission signal NScan(i-1) generated by the upper stage is always low (excluding effective high voltage pulses), it can be assumed that the second node and node D are always kept at low voltage, so as to always turn on the second stage transmission transistor T9 and the thirteenth transistor T8, and to always turn off the first stage transmission transistor T10. Thus, the stage transmission signal NScan(i) output by this stage is always low voltage (excluding effective high voltage pulses).

[0171] Based on the above discussion, it can be seen that, referring to Figure 2 and Figure 10 It can be seen that when the third frequency divider transistor T17 is off (i.e., the second frequency divider control signal FD2 is at its higher voltage), that is, when the first node P and the fourth node R are disconnected, the voltage of the first node P can only be determined by the on state of the thirteenth transistor T8 and the coupling effect of the third capacitor C3.

[0172] Specifically, in the first stage t1, the thirteenth transistor T8 is turned on, the first voltage VGH is transmitted to the first node P, and the first-stage output transistor T10 is turned off; in the second stage t2, the thirteenth transistor T8 is turned on, the first voltage VGH is transmitted to the first node P, and the first-stage output transistor T10 is turned off; in the third stage t3, the thirteenth transistor T8 is turned off, the first node P maintains the first voltage VGH, and the first-stage output transistor T10 is turned off; in the fourth stage t4, the thirteenth transistor T8 is turned off, the first node P maintains the first voltage VGH, and the first-stage output transistor T10 is turned off; in the fifth stage t5, the thirteenth transistor T8 is turned on, the first voltage VGH is transmitted to the first node P, and the first-stage output transistor T10 is turned off; in the sixth stage t6, the thirteenth transistor T8 is turned on, the first voltage VGH is transmitted to the first node P, and the first-stage output transistor T10 is turned off. Therefore, it can be considered that the first-stage output transistor T10 is turned off in each stage, and the gate control signal is related to the on / off state of the second-stage output transistor T9, as follows:

[0173] In the first stage t1, the second stage output transistor T9 is turned on, so the stage transmission signal NScan(i) generated in this stage is low voltage;

[0174] In the second stage t2, the second stage output transistor T9 is turned on, so the stage transmission signal NScan(i) generated in this stage is low voltage;

[0175] In the third stage t3, the second stage output transistor T9 is turned off, that is, the stage output terminal OUT is floating, so the stage transmission signal NScano(i) generated in this stage remains at a low voltage.

[0176] In the fourth stage t4, the second stage output transistor T9 is turned off, that is, the stage output terminal OUT is floating, so the stage transmission signal NScano(i) generated in this stage remains at a low voltage.

[0177] In the fifth stage t5, the second stage output transistor T9 is turned on, so the stage transmission signal NScano(i) generated in this stage is low voltage;

[0178] In the sixth stage t6, the second-stage output transistor T9 is turned on, so the stage transmission signal NScano(i) generated in this stage is low voltage.

[0179] In summary, when the third frequency divider transistor T17 is off (i.e., the second frequency divider control signal FD2 is at its higher voltage), the stage transfer signal NScan(i) generated by this stage is always at a low voltage. When the third frequency divider transistor T17 is on (i.e., the second frequency divider control signal FD2 is at its lower voltage), under the alternating high and low voltage effects of the stage transfer signal NScan(i-1) generated by the previous stage, the first clock signal XCK, and the second clock signal CK, the stage transfer signal NScan(i) generated by this stage can be at a low voltage during the corresponding time period (e.g., ...). Figure 10 Between the start of the fourth stage t4 and the end of the fifth stage, a stage-transmitting effective pulse (e.g., a high-voltage pulse) is formed, thereby acting on the corresponding transistor (e.g., in the pixel driving circuit 302 of the corresponding row) in the pixel driving circuit 302. Figure 6 and Figure 7 The compensation transistor M3 in the middle is used to turn on (refresh) the light-emitting device 301 in the corresponding row.

[0180] Understandably, in this invention, the gate drive circuit 20 of this stage generates a transmission signal that is only transmitted to the gate drive circuit 20 of the next stage, and the generated gate control signal is only loaded onto the sub-pixel Pi of the corresponding row of this stage; combined with the above analysis, it can be seen that in a frame, if the first node P in the gate drive circuit 20 of this stage (for...) Figure 2 (Regarding) or the second node Q (for) Figure 3 If the third node S is not electrically connected to the fourth node R, regardless of whether the third node S is electrically connected to the first node P or the second node Q, the gate control signal of this stage will not have a valid pulse. This will cause the sub-pixel Pi in the corresponding row of this stage to fail to turn on. At the same time, the stage transmission signal of this stage will not have a valid stage transmission pulse, so it will also be unable to control the gate drive circuit 20 of the next stage to work. As a result, the stage transmission signal and gate control signal of the next stage will also not have a valid stage transmission pulse and a valid gate pulse, respectively (that is, the sub-pixel Pi in the corresponding row of the next stage will also fail to turn on). This will continue, and the sub-pixel Pi in subsequent rows will also fail to turn on. That is, only the first node P in the gate drive circuit 20 of each stage (for the first node R) will fail to turn on. Figure 2 (Regarding) or the second node Q (for) Figure 3 Only when the third node S is electrically connected to the fourth node R can the control of whether the sub-pixel Pi of each row is turned on be further controlled by controlling whether the third node S is electrically connected to the first node P or the second node Q.

[0181] It is important to understand that if multiple first sub-pixels Pi have more frames enabled in consecutive frames compared to multiple second sub-pixels Pi, it means that the first display area has a higher refresh rate than the second display area, and vice versa.

[0182] To achieve a reduced refresh rate mode (refresh rate decreases from the first display area to the second display area), the following method can be used: In a series of consecutive frames, in at least one of the earlier frames (e.g.) Figure 11 Frame 1 in the code can control the stage transmission signals and gate control signals generated by all stages (e.g., ...). Figure 11 NScano(1) to NScano(6) in the series each have a stage transmission active pulse and a gate active pulse pl, respectively; in at least one later frame (e.g. Figure 11 (Frame 4 in the text), controls the stage transmission signal and gate control signal (e.g., in each first gate drive circuit 2001) generated by the gate drive circuit 2001. Figure 11 NScano(1) to NScano(2) in the circuit have a stage pass effective pulse and a gate effective pulse p1, respectively, and control the stage pass signal generated by each second gate drive circuit 2002 to not have a stage pass effective pulse so that the corresponding gate control signal (e.g. Figure 11 NScano(3) to NScano(6) in the middle do not have a gate active pulse, or only generate a gate control signal (e.g. Figure 11 NScano(3) to NScano(6) do not have a gate active pulse.

[0183] Specifically, this is combined Figure 2 and Figure 3 As can be seen from the relevant discussions, in the frequency reduction mode, taking the first frequency divider transistor T18 as a P-type transistor as an example, there are the following two implementation methods:

[0184] Method 1, please refer to but not limited to Figure 11 The first frequency division control signal FD1 (i.e., its voltage is equal to the low voltage) is used to control the third node S in each stage of the gate drive circuit 20 to be electrically connected to the first node P (for... Figure 2 (Regarding) or the second node Q (for) Figure 3 In one frame, the second frequency division control signal FD2 is used to control the first node P or the second node Q in the first gate driving circuit 2001 to be electrically connected to the fourth node R, so as to control the output gate control signal to have a gate effective pulse pl, so as to turn on the corresponding light-emitting device 301; in the same frame, the second frequency division control signal FD2 is also used to control the first node P or the second node Q in the second gate driving circuit 2002 to disconnect from the fourth node R, so as to control the output gate control signal to not have the gate effective pulse pl, so as not to turn on the corresponding light-emitting device 301.

[0185] Method 2 differs from Method 1 in that the second frequency division control signal FD2 (i.e., its voltage is equal to a low voltage) is used to control the fourth node R in each stage of the gate drive circuit 20 to be electrically connected to the first node P (for...). Figure 2 (Regarding) or the second node Q (for) Figure 3 In a frame, the first frequency division control signal FD1 is used to control the third node S in the first gate driving circuit 2001 to be electrically connected to the first node P or the second node Q, so as to control the output gate control signal to have a gate effective pulse pl, so as to turn on the corresponding light-emitting device 301; in the frame, the first frequency division control signal FD1 is also used to control the third node S in the second gate driving circuit 2002 to be disconnected from the first node P or the second node Q, so as to control the output gate control signal to not have the gate effective pulse pl, so as not to turn on the corresponding light-emitting device 301.

[0186] Regardless of whether method 1 or 2 is adopted, for the first-stage gate driving circuit 20 to the sixth-stage gate driving circuit 20, assuming that the refresh rates of the first two stages (first-stage to second-stage) gate driving circuit 20, the middle two stages (third-stage to fourth-stage) gate driving circuit 20, and the last two stages (fifth-stage to sixth-stage) gate driving circuit 20 are 120Hz, 60Hz, and 30Hz respectively, then according to the above, in the four consecutive frames (Frame 1 to Frame 4), it can be set as follows: NScano(1) to NScano(2) have gate effective pulse pl in Frame 1 to Frame 4, gate control signals NScano(3) to NScano(4) have gate effective pulse pl in Frame 1 and Frame 3, and gate control signals NScano(5) to NScano(6) have gate effective pulse pl only in Frame 1;

[0187] That is, the frequency division control signal FD needs to be set as follows (the following is an example of method 1):

[0188] The first frequency division control signal FD1 is low in Frame 1 to Frame 4 to turn on the six first frequency division transistors T18 corresponding to the gate drive circuits 20 of the first to sixth stages, so that the gate control signal generated by each transistor can be the same as the corresponding stage transmission signal.

[0189] The second frequency division control signal FD2 is low voltage in Frame 1 for each stage, so that the six third frequency division transistors T17 corresponding to the gate drive circuits 20 of stages 1 to 6 are turned on, so that the six stage transmission signals NScan(1) to NScan(6) and the six gate control signals NScano(1) to NScano(6) all have gate effective pulses pl in Frame 1;

[0190] The second frequency division control signal FD2 is low before tf1 in Frame 2 to turn on the two third frequency division transistors T17 corresponding to the gate drive circuits 20 of the first to second stages, so that NScano(1) to NScano(2) all have gate effective pulse pl in Frame 2. After tf1, it is high to turn off the four third frequency division transistors T17 corresponding to the gate drive circuits 20 of the third to sixth stages, so that NScano(3) to NScano(6) do not have gate effective pulse pl in Frame 2.

[0191] The second frequency division control signal FD2 is low before tf2 in Frame 3 to turn on the four third frequency division transistors T17 corresponding to the gate drive circuits 20 of the first to fourth stages, so that NScan(1) to NScan(4) have gate effective pulse pl in Frame 3. After tf2, it is high to turn off the two third frequency division transistors T17 corresponding to the gate drive circuits 20 of the fifth to sixth stages, so that NScan(5) to NScan(6) do not have gate effective pulse pl in Frame 3.

[0192] The analysis of the second frequency division control signal FD2 in Frame 4 can be referenced from the analysis in Frame 2.

[0193] Of course, as analyzed above, in comparison Figure 11 Alternatively, the second frequency division control signal FD2 can be kept at a low voltage in Frame 1 to Frame 4 to turn on the six third frequency division transistors T17 corresponding to the gate drive circuits 20 of the first to sixth stages, so that the stage transmission signal generated by each transistor has a stage transmission effective pulse.

[0194] Furthermore, the corresponding frequency division setting is achieved by controlling the first frequency division control signal FD1 in each frame to have or not have a valid gate pulse during the period when it is effectively acting on the gate drive circuit of the corresponding stage.

[0195] In summary, the display panel can be divided into at least a first region, a second region, and a third region. The first region (corresponding to the region acted upon by the first to second level gate drive circuits 20) performs data writing (i.e., 4 data refreshes) by applying effective pulses pl to frames 1 to 4. The second region (corresponding to the region acted upon by the third to fourth level gate drive circuits 20) performs data writing (i.e., 2 data refreshes) by applying effective gate pulses pl to frames 1 and 3. That is, its refresh rate is half that of the first region. Similarly, the second region (corresponding to the region acted upon by the fifth to sixth level gate drive circuits 20) performs data writing (i.e., 1 data refresh) only by applying effective pulses pl to frame 1. Its refresh rate is 1 / 4 that of the first region. In the example above, the refresh rates of the first, second, and third regions can be a, (1 / 2)*a, and (1 / 4)*a, respectively. Since a is an integer multiple of 4, the regions need to be divided into 4 frames, for example, 120Hz, 60Hz, and 30Hz, respectively.

[0196] For ease of explanation, this example only illustrates a display panel divided into three regions, each controlled by two levels of gate control signals, with refresh rates of a, (1 / 2)*a, and (1 / 4)*a respectively. Those skilled in the art should understand that the number of regions on the display panel and the number of rows of sub-pixels Pi in each region can vary, and the corresponding refresh rates can also be adjusted. This example only illustrates the degree of refresh rate difference among the illustrated regions, which affects the frame rate setting requirements. If the refresh rate of the latter region is 1 / 3 of the refresh rate of the former region, then 9 frames are required to make the refresh times of the three regions 3 times each, that is, the three regions are refreshed 9 times, 3 times, and 1 time respectively in 9 frames.

[0197] Specifically, to achieve upsampling mode (frequency increases from the first display area to the second display area), the following method can be used: In a series of consecutive frames, in at least one of the earlier frames (e.g.) Figures 12 to 16 In Frame 1, all stage-generated transmission signals and gate control signals can be controlled to have valid transmission pulses and valid gate pulses, respectively; in at least one later frame (e.g., Figures 12 to 13 Frame 4 in Figures 14 to 15 Frame 3 in Figure 16 In Frame 4), the cascade signal generated by each first gate drive circuit 2001 has a cascade effective pulse (cascade continuously acts on the second gate drive circuit 2002), and the generated gate control signal does not have a gate effective pulse (e.g., Figures 12 to 13 NScan(1) to NScan(2) Figures 14 to 15NScan(3) to NScan(4) Figure 16 In NScan(1) to NScan(4)), the stage transmission signal and gate control signal generated by each second gate drive circuit 2002 have stage transmission effective pulse and gate effective pulse respectively (e.g. Figures 12 to 13 NScan(3) to NScan(4) Figures 14 to 15 NScan(5) to NScan(6) Figure 16 NScan(5) to NScan(6) in the middle.

[0198] Specifically, this is combined Figure 2 and Figure 3 As can be seen from the relevant discussions, in the aforementioned upsampling mode, please refer to, but not limited to, [the following]. Figures 12 to 16 Taking the third frequency divider transistor T17 as an example, which is a P-type transistor, the second frequency divider control signal FD2 (e.g., its voltage is equal to a low voltage) is used to control the fourth node R in each stage of the gate drive circuit 20 to be electrically connected to the first node P (for...). Figure 2 (Regarding) or the second node Q (for) Figure 3 In one frame, the first frequency division control signal FD1 is used to control the third node S and the first node P in the first gate drive circuit 2001 (for...). Figure 2 (Regarding) or the second node Q (for) Figure 3 The first frequency division control signal FD1 is used to control the first node P (for) in the second gate drive circuit 2002 to disconnect the gate control signal to prevent it from having a valid gate pulse, so as not to turn on the corresponding light-emitting device 301; within the frame, the first frequency division control signal FD1 is used to control the first node P (for) in the second gate drive circuit 2002. Figure 2 (Regarding) or the second node Q (for) Figure 3 (In other words) it is electrically connected to the fourth node R to control the output gate control signal to have the gate effective pulse, so as to turn on the corresponding light-emitting device 301.

[0199] For example Figure 12As shown, the refresh rates of the first two gate drive circuits 20, the middle two gate drive circuits 20, and the last two gate drive circuits 20 are 30Hz, 120Hz, and 60Hz, respectively. According to the above, it can be set that NScano(1) to NScano(2) have gate effective pulse pl in Frame 1, NScano(3) to NScano(4) have gate effective pulse pl in Frame 1 to Frame 4, and gate control signals NScano(5) to NScano(6) have gate effective pulse pl in Frame 1 and Frame 3.

[0200] In other words, the frequency division control signal FD needs to be set as follows:

[0201] The second frequency division control signal FD2 is low in Frame 1 to Frame 4 so that the six third frequency division transistors T17 corresponding to the gate drive circuits 20 of the first to sixth stages are all turned on, so that the stage transmission signal generated by each transistor has a stage transmission effective pulse.

[0202] The first frequency division control signal FD1 is low voltage in Frame 1 for each stage, so that the six first frequency division transistors T18 corresponding to the gate drive circuits 20 of stages 1 to 6 are turned on, so that the third node S can be electrically connected to the first node P or the second node Q, so that the six gate control signals NScano(1) to NScano(6) also have gate effective pulses pl in Frame 1.

[0203] The first frequency division control signal FD1 is high before tf1 and after ft2 in Frame 2, so that the two first frequency division transistors T18 corresponding to the gate drive circuits 20 of the first, second, fifth and sixth stages are turned off, so that NScano(1) to NScano(2) and NScano(5) to NScano(6) do not have a gate effective pulse pl in Frame 2. The first frequency division control signal FD1 is low between tf1 and ft2, so that the two first frequency division transistors T18 corresponding to the gate drive circuits 20 of the first and third stages are turned on, so that NScano(1) to NScano(3) do not have a gate effective pulse pl in Frame 2.

[0204] The first frequency division control signal FD1 is high before tf3 in Frame 3 to turn off the two first frequency division transistors T18 corresponding to the gate drive circuits 20 of the first and second stages, so that NScano(1) to NScano(2) do not have a gate effective pulse pl in Frame 3. After tf3, it is low to turn on the four first frequency division transistors T18 corresponding to the gate drive circuits 20 of the third to sixth stages, so that NScano(3) to NScano(6) all have a gate effective pulse pl in Frame 3.

[0205] The analysis of the first frequency division control signal FD1 in Frame 4 can be referenced from the analysis in Frame 2.

[0206] Similarly, for example Figure 13 As shown, the refresh rates of the first two gate drive circuits 20, the middle two gate drive circuits 20, and the last two gate drive circuits 20 are 60Hz, 120Hz, and 30Hz, respectively. According to the above, it can be set that within Frame 1 to Frame 4, NScano(1) to NScano(2) have gate effective pulses pl in Frame 1 and Frame 3, NScano(3) to NScano(4) have gate effective pulses pl in Frame 1 to Frame 4, and gate control signals NScano(5) to NScano(6) only have gate effective pulses pl in Frame 1.

[0207] In other words, the frequency division control signal FD needs to be set as follows:

[0208] The second frequency division control signal FD2 is the same. Figure 12 The same settings are used to ensure that the stage transmission signal generated by each stage gate drive circuit 20 has a stage transmission effective pulse.

[0209] The first frequency division control signal FD1 is a low voltage for each stage in Frame 1. Similarly, this ensures that the six gate control signals NScano(1) to NScano(6) also have a gate effective pulse pl in Frame 1.

[0210] The first frequency division control signal FD1 is high voltage before tf1 and after ft2 in Frame 2. Similarly, this ensures that NScano(1) to NScano(2) and NScano(5) to NScano(6) do not have a gate effective pulse pl in Frame 2, while they are low voltage between tf1 and ft2. Similarly, this ensures that NScano(3) to NScano(4) have a gate effective pulse pl in Frame 2.

[0211] The first frequency division control signal FD1 is low voltage before tf3 in Frame 3. Similarly, this ensures that NScano(1) to NScano(4) have gate effective pulse pl in Frame 3, and high voltage after tf3. Similarly, this ensures that NScano(5) to NScano(6) do not have gate effective pulse pl in Frame 3.

[0212] The analysis of the first frequency division control signal FD1 in Frame 4 can be referenced from the analysis in Frame 2.

[0213] Similarly, for example Figure 14 As shown, the refresh rates of the first two gate drive circuits 20, the middle two gate drive circuits 20, and the last two gate drive circuits 20 are 120Hz, 30Hz, and 60Hz, respectively. According to the above, within Frame 1 to Frame 4, it can be set as follows: NScano(1) to NScano(2) have gate effective pulses pl in Frame 1 to Frame 4, NScano(3) to NScano(4) only have gate effective pulses pl in Frame 1, and gate control signals NScano(5) to NScano(6) have gate effective pulses pl in Frame 1 and Frame 3.

[0214] In other words, the frequency division control signal FD needs to be set as follows:

[0215] The second frequency division control signal FD2 is the same. Figure 12 The same settings are used to ensure that the stage transmission signal generated by each stage gate drive circuit 20 has a stage transmission effective pulse.

[0216] The first frequency division control signal FD1 is a low voltage for each stage in Frame 1. Similarly, this ensures that the six gate control signals NScano(1) to NScano(6) also have a gate effective pulse pl in Frame 1.

[0217] The first frequency division control signal FD1 is low voltage before tf1 in Frame 2. Similarly, this ensures that NScano(1) to NScano(2) have gate effective pulse pl in Frame 2, and high voltage after tf1. Similarly, this ensures that NScano(3) to NScano(6) do not have gate effective pulse pl in Frame 2.

[0218] The first frequency division control signal FD1 is low voltage before tf2 and after ft3 in Frame 3. Similarly, this ensures that NScano(1) to NScano(2) and NScano(5) to NScano(6) have gate effective pulse pl in Frame 3, while they are high voltage between tf2 and ft3. Similarly, this ensures that NScano(3) to NScano(4) do not have gate effective pulse pl in Frame 3.

[0219] The analysis of the first frequency division control signal FD1 in Frame 4 can be referenced from the analysis in Frame 2.

[0220] Similarly, for example Figure 15 As shown, the refresh rates of the first two gate drive circuits 20, the middle two gate drive circuits 20, and the last two gate drive circuits 20 are 60Hz, 30Hz, and 120Hz, respectively. According to the above, it can be set that within Frame 1 to Frame 4, NScano(1) to NScano(2) have gate effective pulses pl in Frame 1 and Frame 3, NScano(3) to NScano(4) have gate effective pulses pl only in Frame 1, and gate control signals NScano(5) to NScano(6) have gate effective pulses pl in Frame 1 to Frame 4.

[0221] In other words, the frequency division control signal FD needs to be set as follows:

[0222] The second frequency division control signal FD2 is the same. Figure 12 The same settings are used to ensure that the stage transmission signal generated by each stage gate drive circuit 20 has a stage transmission effective pulse.

[0223] The first frequency division control signal FD1 is a low voltage for each stage in Frame 1. Similarly, this ensures that the six gate control signals NScano(1) to NScano(6) also have a gate effective pulse pl in Frame 1.

[0224] The first frequency division control signal FD1 is high voltage before tf1 in Frame 2. Similarly, this ensures that NScano(1) to NScano(4) do not have a gate effective pulse pl in Frame 2, and are low voltage after tf1. Similarly, this ensures that NScano(5) to NScano(6) have a gate effective pulse pl in Frame 2.

[0225] The first frequency division control signal FD1 is low voltage before tf2 and after ft3 in Frame 3. Similarly, this ensures that NScano(1) to NScano(2) and NScano(5) to NScano(6) have gate effective pulse pl in Frame 3, while they are high voltage between tf2 and ft3. Similarly, this ensures that NScano(3) to NScano(4) do not have gate effective pulse pl in Frame 3.

[0226] The analysis of the first frequency division control signal FD1 in Frame 4 can be referenced from the analysis in Frame 2.

[0227] Similarly, for example Figure 16 As shown, the refresh rates of the first two gate drive circuits 20, the middle two gate drive circuits 20, and the last two gate drive circuits 20 are 30Hz, 60Hz, and 120Hz, respectively. According to the above, it can be set that within Frame 1 to Frame 4, NScano(1) to NScano(2) have gate effective pulse pl only in Frame 1, NScano(3) to NScano(4) have gate effective pulse pl in Frame 1 and Frame 3, and gate control signals NScano(5) to NScano(6) have gate effective pulse pl in Frame 1 to Frame 4.

[0228] In other words, the frequency division control signal FD needs to be set as follows:

[0229] The second frequency division control signal FD2 is the same. Figure 12 The same settings are used to ensure that the stage transmission signal generated by each stage gate drive circuit 20 has a stage transmission effective pulse.

[0230] The first frequency division control signal FD1 is a low voltage for each stage in Frame 1. Similarly, this ensures that the six gate control signals NScano(1) to NScano(6) also have a gate effective pulse pl in Frame 1.

[0231] The first frequency division control signal FD1 is high voltage before tf1 in Frame 2. Similarly, this ensures that NScano(1) to NScano(4) do not have a gate effective pulse pl in Frame 2, and are low voltage after tf1. Similarly, this ensures that NScano(5) to NScano(6) have a gate effective pulse pl in Frame 2.

[0232] The first frequency division control signal FD1 is high voltage before tf2 in Frame 3. Similarly, this ensures that NScano(1) to NScano(2) do not have a gate effective pulse pl in Frame 3, and are low voltage after tf2. Similarly, this ensures that NScano(3) to NScano(6) have a gate effective pulse pl in Frame 3.

[0233] The analysis of the first frequency division control signal FD1 in Frame 4 can be referenced from the analysis in Frame 2.

[0234] Combination Figures 11 to 16 The related discussion can be further elaborated by dividing the display panel into m regions corresponding to m cascaded gate drive circuits 20. The corresponding m refresh rates can be expressed as a / (j1), a / (j2) up to a / (jm), where j1 to jm are all positive integers. Since all m refresh rates are positive integers, the number of frames should be set to the least common multiple of these m numbers. For example, including refresh rates of 120Hz and 1Hz, there should be 120 frames per cycle. Similarly, refer to the above description regarding "m being the least common multiple of n1, n1, n1".

[0235] In summary, based on the refresh rate relationship among the first region, the second region A2, and the third region, the first frequency division control signal FD1 and the second frequency division control signal FD2 can be reasonably controlled. For example, the first region A1, the second region A2, and the third region A3 can be used for video playback, the comment section screen (which can be scrolled as needed), and the keyboard screen, respectively, meaning their refresh rates decrease sequentially. This can be achieved by maintaining the first frequency division control signal FD1 at a low voltage across multiple frames, and relying on the transition of the second frequency division control signal FD2 from an effective (low) voltage to an ineffective (high) voltage. Alternatively, the second frequency division control signal FD2 can be used to... Maintaining a low voltage continuously is achieved by relying on the first frequency division control signal FD1 to transition from an effective (low) voltage to an ineffective (high) voltage. For example, the first region A1, the second region A2, and the third region A3 are used for date display, video playback, and comment section display (which can be scrolled as needed), respectively. The refresh rates of the three regions show a trend of first increasing and then decreasing. In this case, the only way to maintain the second frequency division control signal FD2 at a low voltage for multiple frames is to ensure that each stage can output an effective transmission pulse. This is achieved by relying on the first frequency division control signal FD1 to transition from an ineffective (high) voltage to an effective (low) voltage and then from an effective (low) voltage to an ineffective (high) voltage.

[0236] In this context, the frame containing the gate effect pulse of the multi-level gate control signal corresponding to any region can be called the write frame of that region. This frame is used to enable sub-pixels Pi so that at least one data string can be loaded onto at least one row of sub-pixels Pi. Frames without gate effect pulses are called hold frames of that region, so that at least one row of sub-pixels Pi remains as at least one data string. For example... Figures 11 to 16 Frame 1 in the text is simultaneously a write frame for the three regions corresponding to the first two stages, the middle two stages, and the last two stages of the gate drive circuit 20. Figures 12 to 13 Frame 2 and Frame 4 are both write frames for a region corresponding to the middle two-stage gate drive circuit 20, and also hold frames for a region corresponding to the front two-stage and back two-stage gate drive circuits 20. Figures 14 to 15 Frame 3 in the middle is simultaneously a holding frame for a region corresponding to the middle two-stage gate driving circuit 20, and also a write frame for a region corresponding to the first two and last two-stage gate driving circuits 20. Figures 15 to 16 Frame 2 and Frame 4 are simultaneously holding frames for a region corresponding to the first two and middle two gate drive circuits 20, and also writing frames for a region corresponding to the last two gate drive circuits 20.

[0237] Following the previous discussion, it can be assumed that in a write frame, the gate active pulse in the gate control signal activates the corresponding row of sub-pixels Pi, causing multiple sub-data in the corresponding data string to be transmitted to the corresponding multiple sub-pixels Pi respectively. Therefore, it can be determined whether the frame is a write frame for the next row of sub-pixels Pi or a hold frame for the previous row of sub-pixels Pi based on whether the two data strings corresponding to two adjacent rows of sub-pixels Pi change (that is, whether the two voltage values ​​corresponding to the two adjacent sub-data transmitted by the data line electrically connected to any column of sub-pixels Pi are the same, i.e., whether the data signal transmitted by the data line changes).

[0238] like Figure 17 As shown, if the data signal source transmitted by the data line changes, due to line-by-line scanning, that is, the data signal transmitted by each data line will simultaneously undergo a valid change hop1 (that is, the gate control signal of the corresponding level needs to have a gate valid pulse to turn on the sub-pixel Pi of the corresponding row to load multiple sub-data after the change), the frequency division control signal FD can be set to control the generation of the corresponding gate valid pulse before the corresponding data string appears, so as to ensure the turn-on of the sub-pixel Pi of the corresponding row. Since the first frequency divider transistor T18 and the second frequency divider transistor T20 are both P-row transistors, that is, the first frequency divider control signal FD1 and the first frequency divider control signal FD1 are both set to low voltage to turn on the above two.

[0239] Specifically, with Figure 6 For example, Figure 8 The NScano2 and NScano1 signals respectively represent the loading to Figure 6 The signals on the gates of M3 and M4 (both P-type transistors) in the diagram. Figure 17 The con(M3) and con(M4) signals can represent the total frequency division control signal FD in the two NScan circuits used to generate the NScano2 and NScano1 signals, respectively. The "total frequency division control signal FD" can be understood as the signal obtained by performing a summation operation on the first frequency division control signal FD1 and the second frequency division control signal FD2 in the NScan circuit. That is, the "total frequency division control signal FD" will only be at an effective (low) voltage when both of them are at an effective (low) voltage, otherwise they will be at an ineffective (high) voltage.

[0240] Referring to the above text about Figure 6 and Figure 8 According to the discussion, the NScano2 signal needs to be an effective (high) voltage before the NScano1 signal in order to enable the compensation transistor M3 to be turned on in the first reset phase, so that the anode of the light-emitting device 301 can be reset according to the initialization signal VI2. Then, in the second reset phase, the reset transistor M4 is turned on in the second reset phase, so that the gate of the driving transistor M1 is reset according to the initialization signal VI2. Therefore, as shown here... Figure 17 As shown, for example, the con(M3) and con(M4) signals corresponding to the two NScan circuits can be transitioned from invalid (high) voltage to valid (low) voltage 32 and 16 line cycles before the "sub-data valid transition hop1" respectively, so as to sequentially turn on the compensation transistor and the reset transistor in combination. Figure 2 and Figure 3 According to the relevant discussion, the first reset stage tim1 and the second reset stage tim2 of the corresponding row sub-pixel Pi are completed in sequence.

[0241] Furthermore, still based on Figure 6 As shown, the frequency division control signal FD (also known as the con(M2) signal) in the PScan circuit used to generate the PScano signal can be controlled to transition from an invalid (high) voltage to an effective (low) voltage before the "sub-data valid transition hop1" (less than 16 line cycles), or equal to the "sub-data valid transition hop1". Figure 17 (Not shown in the diagram) to turn on the data transistor, and to continuously transmit the data signal for the data line from the valid transition hop1 to the invalid transition hop2, to perform the data writing phase tim3;

[0242] Further, still based on Figure 6As shown, after the "sub-data invalid transition hop2", the frequency division control signal FD (also known as the con(M5 / 6) signal) in the EM circuit used to generate the EMo1 signal can be controlled to transition from an invalid (high) voltage to an effective (low) voltage. Figure 17 (Not shown in the diagram) to turn on the first light-emitting control transistor and the second light-emitting control transistor, and to continuously perform the light-emitting phase tim4 during the period from the valid transition hop1 to the invalid transition hop2 of the data signal transmitted by the data line;

[0243] Among them, still based on Figure 6 As shown, between the light-emitting stage tim4 and the data-writing stage tim3, the frequency division control signal FD (also known as the con(M7 / 8) signal) in the EM circuit used to generate the EMo2 signal can be controlled to switch from an invalid (high) voltage to an effective (low) voltage. Figure 17 (Not shown in the image) to turn on the initial transistor, reset the transistor, and then proceed to the third reset phase tin.

[0244] The aforementioned "row period" can be understood as the sum of the on-time of each row's sub-pixel Pi and the row blanking time. Figure 17 In a single frame, the first 878 rows of sub-pixels Pi are in a hold frame (i.e., the duration of the corresponding con(M3) signal and con(M4) signal in invalid (high) voltage is initially maintained for 878 line cycles). Furthermore, the con(M3) signal and con(M4) signal change from valid (low) voltage to invalid (high) voltage 30 and 14 line cycles respectively before the "sub-data invalid transition hop2". The subsequent 878 rows of sub-pixels Pi are also in a hold frame (i.e., the duration of the corresponding con(M3) signal and con(M4) signal in invalid (high) voltage is also maintained for 878 line cycles).

[0245] In summary, in this embodiment, the waveform of the "total frequency division control signal FD" in at least one gate driving circuit 20 can be set according to the "sub-data valid transition hop1" of the data signal transmitted by the data line. For example, in the low-frequency region, the Source signal is a constant voltage signal in the holding frame. At this time, the "total frequency division control signal FD" can be equal to an invalid (high) voltage, so that the valid gate pulse cannot be output. Or, for example, in the high-frequency region, when the Source signal experiences "sub-data valid transition hop1", it can trigger the "total frequency division control signal FD" to transition to an valid (low) voltage, so that the valid gate pulse can be output normally. Furthermore, as can be seen from the above analysis, the transition time of the "total frequency division control signal FD" in different gate driving circuits 20 of different transistors in the pixel driving circuit 302 can be at or before or after "sub-data valid transition hop1", so as to achieve different working stages respectively.

[0246] It is important to note that, in conjunction with the above text regarding... Figure 2 , Figure 3 and Figure 10 According to the discussion, in any level gate drive circuit 20, if at least one of the first clock signal and the second clock signal is equal to the constant voltage, the corresponding stage transmission signal and gate control signal will not have stage transmission effective pulse and gate effective pulse respectively, thus failing to refresh (i.e. failing to enable) the sub-pixel Pi of the corresponding row.

[0247] Furthermore, the gate driving module 10 includes n cascaded gate driving circuits 20, where n is a positive integer greater than or equal to 2, and all n gate driving circuits 20 are loaded with the same clock signal (e.g., Figures 11 to 16 All six gate driving circuits 20 are loaded with a first clock signal and a second clock signal. It can be considered that the positions of the first clock signal and the second clock signal in adjacent stages are opposite. Within a frame, the clock signal alternately equals the first clock voltage and the second clock voltage (which can be the high voltage and low voltage of the first clock signal and the second clock signal, respectively, which can control the multiple rows of sub-pixels Pi corresponding to the gate control signals of the i-th to (i+k)-th stages to be turned on) during the effective period of the gate driving circuits 20 of the i-th to (i+k)-th stages, i and k are both positive integers greater than or equal to 1. When the gate control signals output by the gate driving circuits 20 of the (i+k+1)-th to n-th stages do not include the gate effective pulse, the clock signal is always equal to the first clock voltage or the second clock voltage during the effective period of the gate driving circuits 20 of the (i+k+1)-th to n-th stages (which also just satisfies that the corresponding multiple sub-pixels Pi are not turned on).

[0248] Understandably, since the gate control signals from stage i to stage (i+k) each have a valid gate pulse, and the gate control signals from stage (i+k+1) to stage n each do not have a valid gate pulse, in this embodiment, the clock signal is set to a constant voltage during the period when it is effectively applied to the gate drive circuits 20 from stage (i+k+1) to stage n. This not only meets the requirement that "the gate control signals from stage (i+k+1) to stage n each do not have a valid gate pulse", but also saves power consumption.

[0249] Furthermore, to ensure that the gate active pulse of the (i+k)th level gate control signal is fully generated (to avoid interruption due to the clock signal becoming a constant voltage signal), the clock signal can be set to be equal to the constant voltage signal after the gate active pulse is fully generated.

[0250] It is important to note that the last few gate control signals must each lack a valid gate pulse. If at least one last gate control signal has a valid gate pulse, the voltage of the gate drive circuit 20 corresponding to the gate control signals that did not have valid gate pulses before it cannot be set to a constant voltage. This is because it would also prevent the generation of the stage transmission signal for the next stage, thus failing to ensure that at least one subsequent gate control signal has a valid gate pulse.

[0251] Specifically, for example Figure 11 As shown, in Frame 2 and Frame 4, after the end of the gate active pulse in NScano(2), at least one of the first clock signal and the second clock signal (which may be equal or unequal) can be set to be equal to at least one of the high voltage and the low voltage. In Frame 3, after the end of the gate active pulse in NScano(4), at least one of the first clock signal and the second clock signal can be set to be equal to at least one of the high voltage and the low voltage.

[0252] Similarly, for example Figure 12 As shown, in Frame 2 and Frame 4, after the end of the gate active pulse in NScano(4), at least one of the first clock signal and the second clock signal can be set to be equal to at least one of the high voltage and the low voltage.

[0253] Similarly, for example Figure 13 As shown, in Frame 2 to Frame 4, after the end of the gate active pulse in NScano(4), at least one of the first clock signal and the second clock signal can be set to be equal to at least one of the high voltage and the low voltage.

[0254] Similarly, for example Figure 14 As shown, in Frame 2 and Frame 4, after the end of the gate active pulse in NScano(2), at least one of the first clock signal and the second clock signal can be set to be equal to at least one of the high voltage and the low voltage.

[0255] As discussed above, for example Figure 15 and Figure 16As shown, in Frame 1 and Frame 4, since NScano(5) and NScano(6) (i.e., the last two gate drive circuits 20) both have gate effective pulses, the first clock signal and the second clock signal need to be maintained alternately set to the first clock voltage and the second clock voltage in each frame to ensure that the stage transmission signal of each stage can be generated until the generation of the sixth stage, i.e., the gate control signal, is controlled.

[0256] This invention provides a gate driving module and a display panel, including the frequency division signal line as described above and multiple cascaded gate driving circuits. The gate driving circuit includes the cascade transmission unit and the output unit as described above. It further includes a cascade transmission frequency division control unit electrically connected to the cascade transmission receiving unit via a first node or a second node (and also electrically connected to the cascade transmission output unit via a fourth node), and an output frequency division control unit connected between the first node, the second node, and the third node. Both control units are respectively used to control the signal of the first node or the second node according to the frequency division control signal, thereby controlling the cascade transmission output unit to output the cascade transmission signal of its current stage. They also control the signal of the third node according to the frequency division control signal, thereby controlling the output unit to output the gate control signal of its current stage. This ensures that the invalidity of the gate control signal does not affect the invalidity of the cascade transmission signal. A sequential frequency reduction mode for multiple areas of the display panel can be achieved by setting whether the cascade transmission signal has a valid cascade transmission pulse, and an arbitrary frequency conversion mode for multiple areas of the display panel can be achieved by setting whether the gate control signal has a valid gate pulse (since a valid cascade transmission pulse can always exist).

[0257] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A gate driving module, characterized in that, It includes a frequency division signal line and multiple cascaded gate drive circuits. The frequency division signal line is used to transmit a frequency division control signal to the multiple gate drive circuits. The gate drive circuits include: The stage transmission unit includes a stage transmission receiving unit and a stage transmission output unit. The stage transmission receiving unit is used to receive the stage transmission signal generated by the gate driving circuit of the upper stage. The stage transmission output unit is electrically connected to the stage transmission receiving unit through a first node and a second node, and is used to output the stage transmission signal of this stage to the gate driving circuit of the lower stage according to the signal of the first node and the signal of the second node. An output unit is electrically connected to the stage output unit via one of the first node, the second node, and the third node, and is used to output a gate control signal based on the signal from one of the first node, the second node, and the signal from the third node; and The cascade frequency division control unit is electrically connected to the cascade receiving unit through the first node or the second node, and electrically connected to the cascade output unit through the fourth node. It is used to control the signal of one of the first node and the second node according to the frequency division control signal, so as to control the cascade output unit to output the cascade signal of this stage. An output frequency division control unit is connected between the first node, the second node, and the third node, and is used to control the signal of the third node according to the frequency division control signal, so as to control the output unit to output the gate control signal of this stage.

2. The gate driving module according to claim 1, characterized in that, The frequency division control signal includes a first frequency division control signal and a second frequency division control signal, and the frequency division signal line includes a first frequency division signal line for transmitting the first frequency division control signal and a second frequency division control signal for transmitting the second frequency division control signal; The first frequency division signal line is electrically connected to the output frequency division control unit to control the signal of the third node; The second frequency division signal line is electrically connected to the cascade frequency division control unit to control the signal of one of the first node and the second node.

3. The gate driving module according to claim 2, characterized in that, The output frequency division control unit includes: The first frequency divider transistor has its gate connected to the first frequency divider signal line, its source electrically connected to the first node or the second node, and its drain electrically connected to the third node. The first frequency division control signal is used to control the third node to be electrically connected or disconnected from the first node or the second node.

4. The gate driving module according to claim 3, characterized in that, The output frequency division control unit also includes: The second frequency divider transistor has its gate electrically connected to the fifth node of the stage transmission unit, its source electrically connected to the first frequency divider signal line, and its drain electrically connected to the gate of the first frequency divider transistor. Wherein, the first frequency division control signal and the signal of the fifth node are used to control the third node to be electrically connected or disconnected from the first node or the second node; The signal of the fifth node is also used to control the stage transmission signal and the gate control signal output by the gate drive circuit of this stage.

5. The gate driving module according to claim 3 or 4, characterized in that, The frequency division control unit includes: The third frequency divider transistor has its gate electrically connected to the second frequency divider signal line, the source of the first frequency divider transistor is electrically connected to the stage receiver unit through the fourth node, and the drain of the third frequency divider transistor is electrically connected to the first node or the second node. The second frequency division control signal is used to control the fourth node to be electrically connected or disconnected from the first node or the second node.

6. The gate driving module according to claim 5, characterized in that, The stage transmission output unit includes: The first stage output transistor has its gate electrically connected to the first node, its source electrically connected to the first voltage line to apply a first voltage, and its drain electrically connected to the stage output terminal in the gate drive circuit for outputting the stage transmission signal. The second-stage output transistor has its gate electrically connected to the second node, its source electrically connected to the second voltage line to apply a second voltage, and its drain electrically connected to the stage output terminal.

7. The gate driving module according to claim 6, characterized in that, The output unit includes: The first output transistor has its gate electrically connected to the third node, its source electrically connected to the first voltage line, and its drain electrically connected to the gate output terminal of the gate driving circuit used to output the gate control signal. The second output transistor has its gate electrically connected to the first node or the second node, its source electrically connected to the second voltage line, and its drain electrically connected to the gate output terminal.

8. The gate driving module according to claim 7, characterized in that, The gate driving circuit is electrically connected to at least one corresponding pixel driving circuit, and the gate output terminal is electrically connected to the pixel transistor in each of the corresponding pixel driving circuits, wherein the first voltage is greater than the second voltage. The pixel transistor is an N-type transistor, and the drain of the third frequency divider transistor and the source of the first frequency divider transistor are electrically connected to the first node. Alternatively, the pixel transistor is a P-type transistor, and the drain of the third frequency divider transistor and the source of the first frequency divider transistor are both electrically connected to the second node.

9. The gate driving module according to claim 6, characterized in that, The cascade receiving unit includes: The fourth node control unit is electrically connected to the clock signal line and the fourth node, and is used to control the signal of the fourth node according to the clock signal transmitted by the clock signal line. The second node control unit or the first node control unit is electrically connected to the clock signal line and the second node, and is used to control the signal of the second node according to the clock signal. The first node control unit is electrically connected to the clock signal line and the first node, and is used to control the signal of the first node according to the clock signal. An input unit, wherein the input terminal of the input unit is electrically connected to the gate driving circuit of the upper level to load the stage transmission signal generated by the gate driving circuit of the upper level, and the output terminal of the input unit is electrically connected to the fourth node control unit and the second node control unit, or electrically connected to the fourth node control unit and the first node control unit.

10. The gate driving module according to claim 9, characterized in that, Both the cascade frequency division control unit and the output frequency division control unit are electrically connected to the first node; The input unit includes an input transistor, the gate of which is loaded with the clock signal, the source of which is configured as the input terminal of the input unit, and the drain of which is configured as the output terminal of the input unit. The fourth node control unit includes a first transistor, a seventh transistor, a second transistor and a third transistor connected in series. The gate of the seventh transistor is electrically connected to the drain of the input transistor, and the source of the seventh transistor is loaded with the clock signal. The gate of the first transistor is loaded with the clock signal, and the source of the first transistor is loaded with the second voltage. The drain of the first transistor is electrically connected to the gate of the second transistor and the drain of the seventh transistor. The drain of the second transistor is electrically connected to the source of the third transistor. The source of the second transistor and the gate of the third transistor are both loaded with the clock signal. The drain of the third transistor is electrically connected to the fourth node. The second node control unit includes a fourth transistor, a first capacitor, a fifth transistor and a sixth transistor connected in series. The gate of the fourth transistor is loaded with a control signal, the source of the fourth transistor is loaded with the first voltage, and the drain of the fourth transistor is electrically connected to the second node. The gate of the fifth transistor is electrically connected to the drain of the first transistor, the source of the fifth transistor is loaded with the first voltage, the drain of the fifth transistor is electrically connected to the source of the sixth transistor, the drain of the sixth transistor is loaded with the clock signal, and the gate of the sixth transistor is also loaded with the stage transmission signal generated by the gate driving circuit of the upper stage. The first capacitor is electrically connected between the gate and drain of the sixth transistor.

11. The gate driving module according to claim 10, characterized in that, The second node control unit also includes: The tenth transistor has a source loaded with the transmission signal generated by the gate drive circuit of the previous stage, a gate loaded with the clock signal, and a drain electrically connected to the gate of the sixth transistor. The eleventh transistor has its gate and source electrically connected to the gate of the sixth transistor, and its drain electrically connected to the second node.

12. A display panel, characterized in that, include: The gate driving module as described in any one of claims 2 to 11; The panel body includes multiple sub-pixels and multiple scan lines. Each sub-pixel includes a light-emitting device and a pixel driving circuit that drives the light-emitting device to emit light. The pixel driving circuit includes at least one transistor. The gate control signal output by the gate driving circuit is transmitted to the gate of the transistor in the corresponding pixel driving circuit via the corresponding scan line.

13. The display panel according to claim 12, characterized in that, The display panel is in time-division multiplexing frequency reduction mode and frequency increase mode, and the multiple gate driving circuits include multiple cascaded first gate driving circuits and multiple cascaded second gate driving circuits cascaded after the multiple first gate driving circuits. The plurality of sub-pixels include a plurality of first sub-pixels electrically connected to a plurality of first gate driving circuits and a plurality of second sub-pixels electrically connected to a plurality of second gate driving circuits. The plurality of first sub-pixels constitute a first display area and the plurality of second sub-pixels constitute a second display area. In the frequency reduction mode, the refresh rate of the first display area is greater than the refresh rate of the second display area; In the upscaling mode, the refresh rate of the first display area is less than the refresh rate of the second display area.

14. The display panel according to claim 13, characterized in that, In the frequency reduction mode, the first frequency division control signal is used to control the third node in each stage of the gate drive circuit to be electrically connected to the first node or the second node. Within the first type of frame, the second frequency division control signal is used to control the first node or the second node in the first gate driving circuit to be electrically connected to the fourth node, so as to control the output gate control signal to have a gate effective pulse, so as to turn on the corresponding light-emitting device; Within the first type of frame, the second frequency division control signal is also used to control the first node or the second node and the fourth node in the second gate driving circuit to disconnect, so as to control the output gate control signal to not have the gate effective pulse, so as not to turn on the corresponding light-emitting device.

15. The display panel according to claim 13, characterized in that, In the frequency reduction mode, the second frequency division control signal is used to control the fourth node in each stage of the gate drive circuit to be electrically connected to the first node or the second node. Within the second type of frame, the first frequency division control signal is used to control the third node in the first gate drive circuit to be electrically connected to the first node or the second node, so as to control the output gate control signal to have a gate effective pulse, so as to turn on the corresponding light-emitting device. Within the second type of frame, the first frequency division control signal is also used to control the third node in the second gate driving circuit to disconnect from the first node or the second node, so as to control the output gate control signal to not have the gate effective pulse, so as not to turn on the corresponding light-emitting device.

16. The display panel according to claim 14 or 15, characterized in that, In the up-frequency mode, the second frequency division control signal is used to control the fourth node in each stage of the gate drive circuit to be electrically connected to the first node or the second node. Within the third type of frame, the first frequency division control signal is used to control the third node in the first gate driving circuit to disconnect from the first node or the second node, so as to control the output gate control signal to not have the gate effective pulse, so as not to turn on the corresponding light-emitting device. Within the third type of frame, the first frequency division control signal is used to control the first node or the second node in the second gate drive circuit to be electrically connected to the fourth node, so as to control the output gate control signal to have the gate effective pulse, so as to turn on the corresponding light-emitting device.

17. The display panel according to claim 14, characterized in that, The gate driving module includes n cascaded gate driving circuits, where n is a positive integer greater than or equal to 2, and all n gate driving circuits are loaded with the same clock signal. Within a frame, the clock signal alternates between the first clock voltage and the second clock voltage during the period when it is effectively applied to the gate drive circuit from the i-th to the (i+k)-th stage, where i and k are both positive integers greater than or equal to 1; Wherein, when the gate control signals output by the gate driving circuits from the (i+k+1)th to the nth stage do not include the gate effective pulse, the clock signal is always equal to the first clock voltage or the second clock voltage during the period when it is effectively applied to the gate driving circuits from the (i+k+1)th to the nth stage.

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