Test method of sensitive amplifier and electronic equipment

Abstract

The invention provides a test method of a sensitive amplifier and electronic equipment. The test method comprises the following steps: acquiring a first mapping relation between a first loss amount and a first error rate in a reference test mode; wherein the reference test mode comprises a reference factor, the first loss amount is the loss amount of the reference factor to the bit line voltage, the first error rate is the read error rate of reading data from the target storage area under the action of the first loss amount, and a second mapping relation between the second loss amount and the second error rate is obtained in the target test mode. Wherein the target test mode comprises a reference factor and a target factor, the second loss amount is the loss amount of the reference factor and the target factor on the bit line voltage together, and the second error rate is the read error rate of reading data from the target storage area under the action of the second loss amount. According to the first mapping relation and the second mapping relation, the influence value of the target factor on the sensing margin of the sensitive amplifier is obtained through calculation.

Description

Technical Field

[0001] The present application relates to, but is not limited to, a testing method and electronic equipment for a sensitive amplifier. Background Art

[0002] With the development of memory technology, memories are widely used in various fields. For example, dynamic random access memory (DRAM) is widely used.

[0003] The sense amplifier (SA) is an important component of semiconductor memory. Its main function is to sense and amplify the small signal on the bit line, and then perform read or write operations. Improvements to the sense amplifier are conducive to improving data reading and writing performance. Summary of the invention

[0004] Some embodiments of the present application provide a method for testing a sense amplifier, wherein a target storage area includes a sense amplifier and a storage unit, and a bit line is connected to the sense amplifier and the storage unit; the method includes:

[0005] Acquire a first mapping relationship between a first loss amount and a first error rate in a reference test mode; wherein the reference test mode includes a reference factor, the first loss amount is a loss amount of the reference factor to a bit line voltage, and the first error rate is a read error rate of data read from a target storage area under the effect of the first loss amount;

[0006] Acquire a second mapping relationship between a second loss amount and a second error rate in a target test mode; wherein the target test mode includes a reference factor and a target factor, the second loss amount is a loss amount of the bit line voltage caused by the reference factor and the target factor, and the second error rate is a read error rate of data read from a target storage area under the effect of the second loss amount;

[0007] According to the first mapping relationship and the second mapping relationship, an influence value of the target factor on the sensing margin of the sense amplifier is calculated.

[0008] Some embodiments of the present application provide an electronic device, including: a processor, and a memory communicatively connected to the processor;

[0009] Memory stores computer-executable instructions;

[0010] The processor executes the computer-executable instructions stored in the memory to implement the methods involved in the above embodiments.

[0011] The test method and electronic device for the sensitive amplifier provided in the present application obtain a first mapping relationship between a first loss amount and a first error rate in a reference test mode, and obtain a second mapping relationship between a second loss amount and a second error rate in a target test mode. The target test mode has more target factors than the reference test mode. Based on the first mapping relationship and the second mapping relationship, the bit line voltage loss amount caused by introducing the target factor can be obtained, and then the influence value of the target factor on the sensing margin of the sensitive amplifier can be determined. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0013] Figure 1 An architectural schematic diagram of a memory provided for some embodiments of the present disclosure;

[0014] Figure 2 An example diagram of a storage unit structure shown in some embodiments of the present disclosure;

[0015] Figure 3 A schematic flow chart of a method for testing a sense amplifier provided in some embodiments of the present disclosure;

[0016] Figure 4A and Figure 4B To adopt Figure 3 A schematic diagram of the mapping relationship obtained by the test method shown;

[0017] Figure 5 A schematic flow chart of a method for testing a sense amplifier provided in some embodiments of the present disclosure;

[0018] Figure 6 A schematic flow chart of a method for testing a sense amplifier provided in some embodiments of the present disclosure;

[0019] Figure 7 To adopt Figure 6 A schematic diagram of the mapping relationship obtained by the test method shown;

[0020] Fig. 8A is a flow chart of the test method under test mode (a);

[0021] Figure 8B is a flow chart of the test method under test mode (b);

[0022] Figure 8C is a flow chart of the test method under test mode (c);

[0023] Fig.8D is a flow chart of the test method under test mode (d);

[0024] Fig. 8E is a flow chart of the test method under test mode (e);

[0025] Figure 8F is a flow chart of the test method under test mode (f);

[0026] Fig. 9 Schematic diagram of the mapping relationship corresponding to test mode (a) to test mode (f).

[0027] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0028] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0029] In the description of the present disclosure, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0030] At present, memory technology is developing rapidly. Taking DRAM as an example, the main applications include synchronous dynamic random access memory (Synchronous Dynamic Random-Access Memory, referred to as: SDRAM), various generations of double data rate (Double Data Rate, referred to as: DDR) SDRAM, various generations of low power double data rate (Low Power Double Data Rate, referred to as: LPDDR) SDRAM and other types.

[0031] Figure 1 This is a sample diagram of a memory architecture, such as Figure 1As shown, taking DRAM as an example, it includes an address processing circuit 210, a command decoding circuit 220, a data input / output circuit 230, a row decoder 240, a column decoder 250, a sense amplifier (SA) 260 and a storage array. Among them, the address processing circuit 210, the command decoding circuit 220 and the data input / output circuit 230 belong to the peripheral area circuit, and the row decoder 240, the column decoder 250, the sense amplifier 260 and the storage array belong to the array area circuit. The storage array is mainly composed of a storage cell 270, a bit line BL and a word line WL. The word line WL in the storage array extends in the row direction, and the bit line BL in the storage array extends in the column direction. The intersection of the word line WL and the bit line BL is the storage cell 270 of the storage array.

[0032] Each storage unit 270 is used to store one bit of data. Figure 2 FIG. 1 is a structural diagram of a storage unit according to an embodiment of the present invention. Figure 2 As shown, the storage unit 270 includes a switching transistor M and a capacitor C, any one of the source or drain of the switching transistor M is connected to the upper plate of the capacitor C, the lower plate of the capacitor C is connected to the power line, the other of the source or drain of the switching transistor M is connected to the bit line BL, and the gate of the switching transistor M is connected to the word line WL, wherein the capacitor C is used to store data, and the switching transistor M is used to turn off or turn on according to the selected state. The lower plate voltage of the capacitor C is called Vap2. The precharge voltage before charge sharing on the bit line is called Vad2. The gate turn-on voltage of the switching transistor M is called Vpp.

[0033] As the integration of chips becomes higher and higher, the feature size of transistor technology is constantly decreasing. The threshold voltage fluctuation of MOS tubes in sense amplifiers and the susceptibility of small voltage signals to noise interference are becoming increasingly prominent, which seriously affects the accuracy of sense amplifiers in sensing data in storage cells. Sensing margin (SM) is an important indicator to measure the performance of sense amplifiers. The calculation formula of sensing margin SM is: SM = Supply dVBL-Required dVBL, where Supply dVBL specifically refers to the voltage difference between the bit line and the complementary bit line at the end of the charge sharing phase, Supply dVBL is also called the supply of sensing margin, Required dVBL refers to the voltage difference required for SA to correctly amplify, and Required dVBL is also called the loss of sensing margin. The loss of sensing margin is caused by the offset voltage and coupling noise caused by the mismatch of MOS tube threshold voltage.

[0034] In practical applications, the sensing margin of the sense amplifier is usually obtained by testing the sense amplifier. Figure 3 This is a test method for sensitive amplifiers. Figure 3 As shown, a test method for a sensitive amplifier specifically includes the following steps:

[0035] S101. Writing background data into a target storage area.

[0036] The target storage area includes a plurality of sub-areas, each of which includes a word line arranged along a row and a plurality of bit lines arranged along a column. A storage unit is arranged at the intersection of the word line and the bit line.

[0037] Each bit line in each sub-region is connected to a column selection line. When the word line of the sub-region is turned on, a column selection signal controls the opening of multiple bit lines to write or read data into or from the storage unit of the sub-region.

[0038] The background data can be determined according to the test requirements. In order to obtain the sensing margin of the sense amplifier, it is usually necessary to test the sensing margin when reading data "1" through the sense amplifier, and it is also necessary to test the sensing margin when reading data "0" through the sense amplifier.

[0039] In order to improve the test speed, the background data of the two sub-areas can be the same, and the background data in the sub-areas can be set to meet the test requirements. Usually, 8 bit lines are connected to one column selection line, and the sub-area includes 8 storage cells. For ease of understanding, the 8 storage cells mentioned below refer to the 8 storage cells in one sub-area.

[0040] In order to test the performance of reading data "0", background data that is not conducive to reading data "0" is set, for example: the background data of the 6th storage unit among 8 storage units is data "0", and the background data of the remaining storage units is data "1".

[0041] In order to test the performance of reading data "1", background data that is not conducive to reading data "0" is set, for example: the background data of the 6th storage unit among 8 storage units is data "1", and the background data of the remaining storage units is data "0".

[0042] In order to improve the test speed, the X-direction fast write mode is used to write the background to the target storage area. That is, before each write operation, all word lines on the same bit line are sequentially opened. Among them, each time a word line is opened, the contents of the 8 storage cells on this word line are sequentially written, and then the word line is closed. Then the next word line is opened and the contents of the 8 storage cells on this word line are sequentially written until all storage cells are written.

[0043] S102, adjusting the voltage of the lower plate of the capacitor in the storage unit.

[0044] In order to obtain the sensing margin of the sense amplifier, the voltage of the capacitor bottom plate in the storage unit is adjusted multiple times. In this adjustment, the current scanning voltage of the bottom plate is generated, and the capacitor bottom plate voltages of all storage units in the target storage area are adjusted to the current scanning voltage.

[0045] Since the charge on the capacitor is non-mutational, the voltage on the capacitor plate will also change, which will change the supply of the sensing margin Supply dVBL, and further affect the error rate of the sense amplifier when reading data in the storage unit.

[0046] The storage of data "1" or data "0" is usually achieved in the following manner in a storage unit. The lower plate voltage Vap2 of the storage unit is set to the lower plate reference value, for example: the lower plate voltage Vap2 = 0.5V. The upper plate voltage is greater than the lower plate voltage, indicating that the data "1" is stored. The upper plate voltage is less than the lower plate voltage, indicating that the data "0" is stored.

[0047] In order to test the sensing margin of reading data "1" and the sensing margin of reading data "0" through the sense amplifier, the lower plate scanning voltage can be gradually increased from the lower plate reference voltage to create an environment that is not conducive to reading data "1". Accordingly, the background data can be made to be background data that is not conducive to reading data "1". In order to obtain the sensing margin of the sense amplifier reading data "1". The lower plate scanning voltage can also be gradually reduced from the lower plate reference voltage to create an environment that is not conducive to reading data "0". Accordingly, the background data can be made to be background data that is not conducive to reading data "0". In order to obtain the sensing margin of the sense amplifier reading data "0".

[0048] S103, read the background data from the target storage area, and count the read error rate. If the scanning of the lower plate voltage is not completed, return to S101, and if the scanning of the lower plate capacitance is completed, return to S104.

[0049] In order to improve the test speed, the X-direction fast read mode is used to read the background data from the target storage area. The background data written into each storage unit in the target storage area is compared with the read background data. If the two data are the same, the data is read correctly. If the two data are different, the read data is wrong.

[0050] The number of storage cells with read data errors in the target storage area is counted, the proportion of storage cells with read data errors is calculated, and the read error rate is obtained. A mapping relationship between the current scanning voltage and the read error rate is established.

[0051] S104 , calculating a sensing margin according to a mapping relationship between multiple sets of scanning voltages and readout error rates.

[0052] The statistical readout error rate is smaller than the voltage range ΔV covered by the lower plate scanning voltage corresponding to the preset threshold, and the sensing margin SM is calculated according to the voltage range.

[0053] The sensing margin SM can be calculated by the following formula:

[0054]

[0055] Wherein, Cs is the capacitance of the capacitor in the storage unit, and ΔV is the voltage range covered by the scanning voltage corresponding to the read error rate being less than the preset threshold. total =(Cbl+Csa+Cs). Cs is the capacitance of the capacitor, Cbl is the bit line parasitic capacitance, and Csa refers to the bit line coupling capacitance of the sense amplifier.

[0056] More specifically, the mapping relationship between multiple sets of scanning voltages and readout error rates is plotted as a curve. Figure 4A and Figure 4B As shown, the curve is bowl-shaped, so it is called a bowl graph. By drawing a straight line representing a preset threshold on the ordinate of the curve, the voltage range ΔV can be obtained.

[0057] However, since the above method uses the scanning capacitor lower plate to obtain the sensing margin of the sense amplifier, that is, the sensing margin of the sense amplifier is obtained by adjusting the supply amount Supply dVBL of the sensing margin, it cannot reflect the influence of various factors in the target storage area on the loss of the sensing margin of the sense amplifier.

[0058] For example, Figure 4A Bowl diagram showing the capacitance Cs of the capacitor in each memory cell in the target memory area is 5 fF, the bit line coupling capacitance Cbl is 30 fF, Figure 4B The bowl diagram shows that the capacitance Cs of the capacitor in the storage cell in the target storage area is 10fF, and the bit line coupling capacitance Cbl is 30fF. The capacitance Cs of the two capacitors is different, but the voltage range calculated by the two bowl diagrams is the same ΔV. The bowl diagram cannot reflect the impact of the storage capacitance Cs on the loss degree of the sensing margin.

[0059] In addition, since multiple influencing factors are mixed together, it is difficult to associate the bit line voltage difference loss with design or process defects in theoretical analysis, and it is also impossible to measure the impact values ​​of different influencing factors on the sensing margin from a theoretical analysis.

[0060] For ease of description, data "1" is referred to as first data, data "0" is referred to as second data, the supply amount Supply dVBL of the sensing margin is referred to as the supply amount of the bit line voltage, and the consumption amount Required dVBL of the sensing margin is referred to as the consumption amount of the bit line voltage.

[0061] Some aspects of the embodiments of the present disclosure relate to the above considerations. The following is an example introduction of the solution in combination with some embodiments of the present disclosure.

[0062] like Figure 5 As shown, some embodiments of the present application provide a method for testing a sense amplifier. The sense amplifier is located in a target storage area, and the target storage area also includes a storage unit, a bit line, and a word line. A storage unit is provided at the intersection of the bit line and the word line, and the bit line is connected to the sense amplifier. The method for testing the sense amplifier specifically includes the following steps:

[0063] S201. Obtain a first mapping relationship between a first loss amount and a first error rate in a reference test mode.

[0064] The test mode of the sense amplifier includes a reference test mode, the reference test mode includes a reference factor, and the reference factor will affect the loss amount of the bit line voltage.

[0065] The first loss is the loss of the bit line voltage by the reference factor in the reference test mode, and the first error rate is the read error rate of data read from the target storage area under the effect of the first loss. The first mapping relationship can be obtained by testing the target storage unit in the reference test mode.

[0066] The first mapping relationship includes two mapping relationship sets, each mapping relationship set includes multiple groups of mapping relationships between first loss amounts and first error rates. Multiple groups of mapping relationships between first loss amounts and first error rates are obtained by performing multiple tests on the target storage area under a reference test mode, thereby obtaining the first mapping relationship.

[0067] The first mapping relationship set includes multiple sets of mapping relationships under reading the first data, and the mapping relationship under reading the first data refers to the mapping relationship between the first loss amount and the first read error rate when the test condition is not conducive to reading the first data based on the lower plate voltage of the storage unit in the reference test mode, for example: by adjusting the lower plate voltage to make the lower plate voltage greater than the lower plate reference voltage, then writing data, and restoring the lower plate voltage when reading data, to create a mapping relationship obtained when the test condition is not conducive to reading the first data. In this way, the sensing margin for reading the first data can be obtained based on the first mapping relationship.

[0068] The second mapping relationship set includes multiple sets of mapping relationships under reading the second data, and the mapping relationship under reading the second data refers to the mapping relationship between the first loss amount and the first read error rate when the test condition is not conducive to reading the second data based on the lower plate voltage of the storage unit in the reference test mode, for example: by adjusting the lower plate voltage to make the lower plate voltage less than the lower plate reference voltage, then writing data, and restoring the lower plate voltage when reading data, to create a mapping relationship obtained when the test condition is not conducive to reading the second data. In this way, the sensing margin for reading the first data can be obtained based on the first mapping relationship.

[0069] S202: Obtain a second mapping relationship between a second loss amount and a second error rate in a target test mode.

[0070] The test mode of the sense amplifier includes a target test mode, and the target test mode includes a reference factor and a target factor.

[0071] The second loss is the loss of the bit line voltage caused by the reference factor and the target factor in the target test mode, and the second error rate is the read error rate of data read from the target storage area under the second loss. The second mapping relationship can be obtained by testing the target storage unit in the target test mode.

[0072] The second mapping relationship includes two mapping relationship sets, each mapping relationship set includes multiple groups of mapping relationships between second loss amounts and second error rates. The second mapping relationship is obtained by performing multiple tests on the target storage area under the target test mode to obtain multiple groups of mapping relationships between second loss amounts and second error rates.

[0073] The two mapping relationship sets include a third mapping relationship set and a fourth mapping relationship set. The third mapping relationship set includes multiple groups of mapping relationships under reading the first data, and the mapping relationship under reading the first data refers to the mapping relationship between the second loss amount and the second read error rate obtained when the test conditions are set based on the lower plate voltage of the storage unit in the target test mode, which is not conducive to reading the first data, for example: by adjusting the lower plate voltage so that the lower plate voltage is greater than the lower plate reference voltage, and then writing data, and restoring the lower plate voltage when reading the data, to create a mapping relationship obtained when the test conditions are not conducive to reading the first data.

[0074] The fourth mapping relationship set includes multiple groups of mapping relationships under reading the second data. The mapping relationship under reading the second data refers to the mapping relationship between the second loss amount and the second read error rate when the test conditions set based on the lower plate voltage of the storage unit in the target test mode are not conducive to reading the second data. For example: by adjusting the lower plate voltage so that the lower plate voltage is less than the lower plate reference voltage, and then writing data, and restoring the lower plate voltage when reading the data, a mapping relationship is obtained when the test conditions that are not conducive to reading the second data are created.

[0075] S203 . Calculate and obtain, according to the first mapping relationship and the second mapping relationship, an influence value of the target factor on the sensing margin of the sense amplifier.

[0076] In some embodiments, a first target loss amount corresponding to an error rate threshold is obtained according to a first mapping relationship, and a second target loss amount corresponding to an error rate threshold is obtained according to a second mapping relationship. The influence value of the target factor on the sensing margin of the sense amplifier is calculated according to the first target loss amount and the second target loss amount. By setting it in this way, the first mapping relationship can directly reflect the influence of the reference factor on the sensing margin, and the second mapping relationship can reflect the influence of the reference factor and the target factor on the sensing margin, and then the influence value of the target factor corresponding to the sensing margin is intuitively determined based on the first mapping relationship and the second mapping relationship.

[0077] As an implementation method, a first fitting curve is obtained by curve fitting the first mapping relationship, and a second fitting curve is obtained by curve fitting the second mapping relationship. Since the first mapping relationship and the second mapping relationship both contain two mapping relationship sets, and the data in the two mapping relationship sets are symmetrical, the first fitting curve and the second fitting curve are symmetrical graphs, and one error read rate corresponds to two loss amounts. The first target loss amount of the first fitting curve is calculated when the first read error rate is the error rate threshold. The first target loss amount is the larger or smaller of the two first loss amounts corresponding to the error rate threshold.

[0078] The second target loss amount of the second fitting curve when the second readout error rate is the error rate threshold is calculated. If the first target loss amount is the larger one of the two first loss amounts corresponding to the error rate threshold, the second target loss amount is the larger one of the two second loss amounts corresponding to the error rate threshold. If the first target loss amount is the smaller one of the two first loss amounts corresponding to the error rate threshold, the second target loss amount is the smaller one of the two second loss amounts corresponding to the error rate threshold.

[0079] As another implementation, a first loss amount corresponding to a first read error rate having a minimum difference with an error rate threshold and being less than the error rate threshold is selected from a first mapping set in the first mapping relationship as a first target loss amount. A second loss amount corresponding to a second read error rate having a minimum difference with an error rate threshold and being less than the error rate threshold is selected from a first mapping set in the second mapping relationship as a third target loss amount.

[0080] In some embodiments, a first loss difference between the first target loss and the second target loss is calculated, which can be used as an impact value of the target factor on the sensing margin of the sense amplifier.

[0081] In the above technical scheme, a first mapping relationship between the first loss amount and the first error rate is obtained in the reference test mode, and a second mapping relationship between the second loss amount and the second error rate is obtained in the target test mode. The target test mode has more target factors than the reference test mode. Based on the first mapping relationship and the second mapping relationship, the bit line voltage loss amount caused by introducing the target factor can be obtained, and then the influence value of the target factor on the sensing margin of the sensitive amplifier can be determined.

[0082] like Figure 6 As shown, the following describes an implementation method for obtaining a first mapping relationship between a first loss amount and a first error rate. Specifically, it includes the following steps:

[0083] S301. Determine first background data, first target data, and first control parameters according to reference factors.

[0084] The factors affecting the sensing margin of the sense amplifier include transistor mismatch of the sense amplifier, bit line coupling, power line coupling of the sense amplifier, channel resistance of the transistor in the memory cell, transistor contact resistance, and gate voltage effect of the transistor in the memory cell. The reference factor includes one or more combinations of transistor mismatch of the sense amplifier, bit line coupling, power line coupling of the sense amplifier, channel resistance of the transistor in the memory cell, transistor contact resistance, and gate voltage effect of the transistor in the memory cell.

[0085] Specifically, bit line coupling means that the bit lines of the sensitive amplifier are metal lines located in the metal layer, and the distance between the bit lines is relatively close, so coupling capacitance will be generated between two adjacent bit lines. When the voltages of the adjacent bit lines are respectively high and low, the voltages of the two adjacent bit lines will affect each other through the coupling capacitance, thereby introducing the bit line coupling effect.

[0086] The power line coupling of the sense amplifier specifically refers to the fact that different sense amplifiers share a power line in the actual circuit. When the data stored in the target storage cell is the first data "1", and the surrounding background storage cells are the second data "0", the pull-down effect of the power line will be relatively strong, which will affect the data reading process in the target storage cell, and more specifically, affect the sensing margin of the sense amplifier. Conversely, when the data stored in the target storage cell is the second data "0", and the surrounding background storage cells are the first data "1", the pull-up effect of the power line will be relatively strong, which will affect the data reading process in the target storage cell. This phenomenon is called the power line coupling effect of the sense amplifier.

[0087] The first control parameter includes any one of a write operation recovery time, a transistor turn-on voltage, and a transistor turn-off voltage. The influence of the above factors on the sensing margin of the sense amplifier can be reflected by setting one or more of the operation recovery time, the transistor turn-on voltage, and the transistor turn-off voltage, and then designing the first background data and the first target data.

[0088] S302: Write first background data into the target storage area.

[0089] In order to improve the test speed, the first background data is written into the storage unit by fast writing in the Y direction. Before each write operation, a word line is turned on, and after the contents of the 8 storage units on this word line are written in sequence, the word line is turned off. Then the word line is turned on again to write the contents of the 8 storage units in sequence. The word line is turned on and off repeatedly until all the corresponding storage units on this word line are written, and then the next word line is turned on to perform the same operation until all the storage units are written.

[0090] S303: Obtain the address of the current sub-region in the target storage region, and modify the data in the current sub-region to the first target data according to the address of the current sub-region and the first control parameter.

[0091] The target storage area includes multiple sub-areas, which are storage cells on the same word line, and the storage cells share a column selection line. By scanning each sub-area one by one, the background data in each sub-area is modified to the first target data.

[0092] In the current cycle, the address of the current sub-region in the target storage region is obtained, the current sub-region of the data to be modified is determined according to the address of the current sub-region, and the first target data is written into the current sub-region based on the first control parameter.

[0093] Since there are slight differences in the storage cells of each sub-region in the target storage region, the loss amounts in different sub-regions are also different. By testing each sub-region one by one, the loss amount and data read error rate of each sub-region are obtained.

[0094] S304: Setting a test condition that is not conducive to reading data based on the lower plate voltage of the memory cell.

[0095] Among them, the lower plate voltage of the storage unit refers to the lower plate voltage of the capacitor in the storage unit, and the test conditions that are not conducive to reading the first data are created based on adjusting the lower plate voltage of the storage unit, or the test conditions that are not conducive to reading the second data are created based on adjusting the lower plate voltage of the storage unit.

[0096] In some embodiments, when creating test conditions that are not conducive to reading the first data, the adjusted lower plate voltage of the storage unit can be made greater than the lower plate reference voltage. After adjusting the lower plate voltage, data is written to the storage unit, and then the lower plate voltage is adjusted back to the original value when reading the data in the storage unit. Since the voltage difference on the capacitor in the storage unit will not change, the upper plate voltage of the storage unit will also drop. Through such a setting, test conditions that are not conducive to reading the first data are created.

[0097] When creating test conditions that are not conducive to reading the second data, the adjusted lower plate voltage of the storage unit can be made smaller than the lower plate reference voltage. After adjusting the lower plate voltage, data is written to the storage unit, and then the lower plate voltage is adjusted back to the original value when reading the data in the storage unit. Since the voltage difference on the capacitor in the storage unit will not change, the upper plate voltage of the storage unit will also rise. Through such an arrangement, test conditions that are not conducive to reading the second data are created.

[0098] In other embodiments, when creating test conditions that are not conducive to reading the first data, the lower plate voltage of the storage cell is used as a lower plate voltage reference, data is written to the storage cell, and then the lower plate voltage is adjusted downward when reading the data in the storage cell. Since the voltage difference on the capacitor in the storage cell will not change, the upper plate voltage of the storage cell will also decrease. Through such an arrangement, test conditions that are not conducive to reading the first data are created.

[0099] When creating test conditions that are not conducive to reading the second data, the lower plate voltage of the storage cell is set to the lower plate voltage reference value, data is written to the storage cell, and then the lower plate voltage is adjusted upward when reading the data in the storage cell. Since the voltage difference on the capacitor in the storage cell will not change, the upper plate voltage of the storage cell will also rise. Through such an arrangement, test conditions that are not conducive to reading the second data are created.

[0100] S305, reading the data in the target storage area, calculating the first loss amount and the first error rate of the current sub-area; and obtaining a set of mapping relationships.

[0101] The first loss amount of the current sub-area can be calculated by the following formula:

[0102]

[0103] Among them, Cs is the capacitance of the capacitor, Vblh is the high voltage on the bit line, that is, the upper plate voltage of the capacitor when writing the first data, Vap2 Bump refers to the adjustment amount of the lower plate voltage, Cbl is the bit line parasitic capacitance, Csa refers to the bit line coupling capacitance of the sense amplifier, and Vad2 is the pre-charge voltage before charge sharing on the bit line.

[0104] The first error rate of the current sub-region can be calculated by comparing the data read from the current sub-region with the first target data written into the current sub-region, counting the number of storage units with different data in the current sub-region, and calculating the first error rate based on the number obtained by the statistical result. That is, the first error rate is obtained by dividing the data of the storage units with different data by the total number of storage units in the current sub-region. Then, the first loss amount and the first error rate of the current sub-region are obtained.

[0105] S306: Determine whether all sub-regions in the target storage unit are traversed. If yes, end the process. If no, update the current sub-region to the next sub-region and return to S301.

[0106] In the above technical solution, by traversing each sub-region of the target storage unit one by one, the first loss amount and the first error rate of multiple sub-regions can be obtained. The first loss amount and the first error rate of multiple sub-regions are combined into a first mapping relationship.

[0107] Through Figure 4A and Figure 4B The target storage area for the two parameter cases shown uses Figure 6 The test method shown is used to test and obtain Figure 7 As shown in the mapping diagram. Figure 7As shown, the thick line represents the mapping relationship under the first parameter condition, that is, the mapping relationship when the transistor capacitance Cs of the storage unit is 5fF and the bit line coupling capacitance Cbl is 30fF, and the thin line represents the mapping relationship under the second parameter condition, that is, the mapping relationship when the transistor capacitance Cs of the storage unit is 10fF and the bit line coupling capacitance Cbl is 30fF, and the mapping relationship is in the shape of a wave peak. The error rate threshold is set to 10%, and the loss values ​​corresponding to the two mapping relationship curves under the error rate threshold of 10% are different. The loss value corresponding to the first parameter condition is 28.6mV, and the corresponding supply value is 71.4mV. The loss value corresponding to the second parameter condition is 50mV, and the corresponding supply value is 125mV. Therefore, the peak diagram can directly reflect the loss value of the bit line voltage under different parameters, and can directly reflect the influence of the transistor capacitance Cs in the storage unit on the sensing margin.

[0108] The following describes an implementation method for obtaining a second mapping relationship between a second loss amount and a second error rate, which specifically includes the following steps:

[0109] S401. Determine second background data, second target data, and second control parameters according to reference factors and target factors.

[0110] The reference factors include one or more combinations of transistor mismatch of the sense amplifier, bit line coupling, power line coupling of the sense amplifier, channel resistance of the transistor in the memory cell, contact resistance of the transistor in the memory cell, and gate voltage effect of the transistor in the memory cell. The target factors include one or more combinations of transistor mismatch of the sense amplifier, bit line coupling, power line coupling of the sense amplifier, channel resistance of the transistor in the memory cell, contact resistance of the transistor in the memory cell, and gate voltage effect of the transistor in the memory cell.

[0111] The second control parameter includes any one of the write operation recovery time, transistor turn-on voltage, and transistor turn-off voltage. The influence of the above factors on the sensing margin of the sense amplifier can be reflected by setting one or more of the second control parameters of the operation recovery time, transistor turn-on voltage, and transistor turn-off voltage, and then designing the second background data and the second target data.

[0112] S402: Write the second background data into the target storage area.

[0113] S403: Acquire the address of the current sub-region in the target storage region, and modify the data in the current sub-region to the second target data according to the address of the current sub-region and the second control parameter.

[0114] S404: Setting a test condition that is not conducive to reading data based on the lower plate voltage of the memory cell.

[0115] S405 , reading the data in the target storage area, calculating the second loss amount and the second error rate of the current sub-area, and obtaining a set of mapping relationships.

[0116] S406: Determine whether all sub-regions in the target storage unit are traversed. If yes, end the process. If no, update the current sub-region to the next sub-region and return to S401.

[0117] In the above technical solution, by traversing each sub-region of the target storage unit one by one, the second loss amount and the second error rate of multiple sub-regions can be obtained. The second loss amount and the second error rate of multiple sub-regions are combined into a second mapping relationship.

[0118] Seven test modes are designed based on factors that affect the sensing margin of the sense amplifier. By combining the seven test modes, the influence of a certain factor on the sensing margin of the sense amplifier can be obtained.

[0119] Table 1 shows the factors of the test mode

[0120]

[0121] Based on the factors involved in the test mode in Table 1, the background data, target data and control parameters in each test mode are set, as shown in Table 2.

[0122] Table 2 is the configuration table of the test mode

[0123] Test mode number Background Data Target data Wr Turn-on voltage Shutoff voltage (a) Data #55 Data#AA t2 Von1 - (b) Data#00 Data#AA t2 Von1 - (c) Data#00 Data#01 / 2 / 4 / 8 t2 Von1 - (d) Data#00 Data#01 / 2 / 4 / 8 t1 Von2 - (e) Data#00 Data#01 / 2 / 4 / 8 t1 Von1 - (f) Data#00 Data#01 / 2 / 4 / 8 t1 Von1 [Voff1,Voff2]

[0124] In Table 2, data #00 means that the data in a sub-area is 00000000, data #55 means that the data in a sub-area is 01010101, data #AA means that the data in a sub-area is 10101010, data #01 means that the data in a sub-area is 00000001, data #02 means that the data in a sub-area is 00000010, data #04 means that the data in a sub-area is 00000100, and data #08 means that the data in a sub-area is 00001000.

[0125] The first reference time t1 is less than the second reference time t2. When the write recovery operation time tWR is t1, it is a short write recovery operation time. When the write recovery operation time tWR is t2, it is a long write recovery operation time (long tWR). The first reference voltage Von1 is less than the second reference voltage Von2, and Voff1 is less than Voff2.

[0126] like Fig. 8AAs shown, in test mode (a), the background data stored in two adjacent storage cells in each sub-area are different, for example, the background data is data #55 or data #AA. The target data stored in two adjacent storage cells in the sub-area are different, for example, the target data is data #55 or data #AA. The background data and the target data are different, for example, when the background data is #55, the target data is #AA; when the background data is #AA, the target data is #55.

[0127] For each cycle, under the condition of long write recovery operation time tWR, the background data of the sub-region is rewritten to the target data. When the data in the sub-region is modified to the target data, the transistor turn-on voltage of the storage unit in the sub-region is the first reference voltage Von1.

[0128] In the case of the above background data and target data, the first data "1" and the second data "0" of data #55 and data #AA are distributed similarly, and the distribution of the data stored in the surrounding storage cells has little effect on the reading of the current storage cell, so the influence of the power line coupling and the bit line coupling of the sense amplifier on the sensing margin of the sense amplifier can be excluded. And the timing condition of the write recovery operation time tWR is good, so the influence of the channel resistance of the transistor in the storage cell, the contact resistance of the transistor in the storage cell, the gate voltage effect of the transistor in the storage cell and the write recovery operation time tWR on the sensing margin of the sense amplifier can be excluded, thereby quantifying the influence of the transistor mismatch of the sense amplifier in the sense amplifier.

[0129] like Figure 8B As shown, in test mode (b), the background data stored in each storage unit in each sub-area is the same, for example, the background data is data #00, and the target data stored in two adjacent storage units in the sub-area is different, for example, the target data is data #AA or #55.

[0130] For each cycle, under the condition of long write recovery operation time tWR, the background data of the sub-region is rewritten to the target data. When the data in the sub-region is modified to the target data, the transistor turn-on voltage of the storage unit in the sub-region is the first reference voltage Von1.

[0131] In the case of the above background data and target data, since the background data is the same, after the target data is written in the current sub-region, the pull-up effect or pull-down effect of the power line is more obvious, for example: when the background data is number #00, the pull-down effect of the power line is more obvious. Therefore, the power line coupling of the sense amplifier is introduced. The distribution of the first data "1" and the second data "0" of the target data is equivalent, and the distribution of the stored data in the storage cells in the surrounding sub-regions has little effect on the reading of the storage cells in the current sub-region, so the influence of the bit line coupling on the sensing margin of the sense amplifier can be excluded. And the timing condition of the write recovery operation time tWR is optimal, so the influence of the write recovery operation time tWR, the channel resistance of the transistor in the storage cell, the contact resistance of the transistor in the storage cell, and the gate voltage effect of the transistor in the storage cell on the sensing margin of the sense amplifier can be excluded, thereby quantifying the influence of the power line coupling of the sense amplifier and the transistor mismatch of the sense amplifier.

[0132] like Figure 8C As shown, in the test mode (c), the background data stored in each storage unit in the sub-area is the first data or the second data, for example: the background data of each sub-area is data #00. When the background data of each storage unit in the sub-area is the first data, only one storage unit in the sub-area stores the target data as the second data, and the target data stored in the other storage units are the first data. For example: the target data is any one of data #00, data #01, data #02, data #04, and data #08. When the background data of each storage unit in the sub-area is the second data, only one storage unit in the sub-area stores the target data as the first data, and the target data stored in the other storage units are the second data.

[0133] For each cycle, under the condition of long write recovery operation time tWR, the background data of the sub-region is rewritten to the target data. When the data in the sub-region is modified to the target data, the transistor turn-on voltage of the storage unit in the sub-region is the first reference voltage Von1.

[0134] It should also be noted that when the target data condition is met, the target data of the two loops can be different or the same. For example, if both data #01 and data #02 meet the target data condition, data #01 can be selected as the target data in one loop and data #02 can be selected as the target data in the other loop. Data #01 can also be selected as the target data in both loops.

[0135] In the case of the above background data and target data, since the background data is the same, the pull-up effect or pull-down effect of the power line is more obvious. For example, when the background data is number #00, the pull-down effect of the power line is more obvious. Therefore, the power line coupling of the sense amplifier is introduced. The target data makes one of the two adjacent bit lines high, and the target data makes the other of the two adjacent bit lines low, which will introduce the bit line coupling factor. The timing condition of the write recovery operation time tWR is relatively good, and the turn-on voltage of the transistor is relatively good. Therefore, the influence of the write recovery operation time tWR, the channel resistance of the transistor in the memory cell, the contact resistance of the transistor in the memory cell, and the gate voltage effect of the transistor in the memory cell on the sensing margin of the sense amplifier can be excluded. Quantify the influence of the power line coupling, bit line coupling and transistor mismatch of the sense amplifier.

[0136] like Fig.8D As shown, the background data in the test pattern (d) is the same as the background data in the test pattern (c). The target data in the test pattern (d) is the same as the target data in the test pattern (c).

[0137] For each cycle, under the condition of short write recovery operation time tWR, the background data of the sub-region is rewritten to the target data. When the data in the sub-region is modified to the target data, the transistor turn-on voltage of the storage unit in the sub-region is the second reference voltage Von2.

[0138] In the case of the above background data and target data, since the background data is the same, the pull-up effect or pull-down effect of the power line is more obvious. For example, when the background data is number #00, the pull-down effect of the power line is more obvious. The target data makes one of the two adjacent bit lines high, and the target data makes the other of the two adjacent bit lines low, which will introduce the bit line coupling factor. The timing condition of the write recovery operation time tWR is relatively poor, and the turn-on voltage of the transistor is higher. The high turn-on voltage can increase the writing speed. Assuming that there is no contact resistance, data writing can also be completed within the short write operation recovery time tWR. If there is a contact resistance effect, the written data is insufficient, resulting in a read failure. Therefore, the contact resistance of the transistor in the memory cell can be introduced to exclude the influence of the channel resistance of the transistor in the memory cell and the gate voltage effect of the transistor in the memory cell on the sensing margin of the sense amplifier. Quantify the influence of the power line coupling, bit line coupling, transistor mismatch of the sense amplifier and transistor contact resistance of the sense amplifier.

[0139] like Fig. 8E As shown, the background data in the test pattern (e) is the same as the background data in the test pattern (c). The target data in the test pattern (e) is the same as the target data in the test pattern (c).

[0140] For each cycle, under the condition of short write recovery operation time tWR, the background data of the sub-region is rewritten to the target data. When the data in the sub-region is modified to the target data, the transistor turn-on voltage of the storage unit in the sub-region is the first reference voltage Von1.

[0141] In the case of the above background data and target data, since the background data is the same, the pull-up effect or pull-down effect of the power line is more obvious. For example, when the background data is number #00, the pull-down effect of the power line is more obvious. The target data makes one of the two adjacent bit lines high, and the target data makes the other of the two adjacent bit lines low, which will introduce the bit line coupling factor. The timing condition of the write recovery operation time tWR is relatively poor, and the turn-on voltage of the transistor is relatively small. If the channel resistance or contact resistance is large, the voltage difference will be lost on the resistance. Therefore, the channel resistance and contact resistance of the transistor in the memory cell can be introduced to eliminate the influence of the gate voltage effect of the transistor in the memory cell on the sensing margin of the sense amplifier. Quantify the influence of the power line coupling, bit line coupling, transistor mismatch of the sense amplifier, transistor contact resistance and channel resistance of the transistor in the memory cell.

[0142] like Figure 8F As shown, the background data in the test pattern (f) is the same as the background data in the test pattern (c). The target data in the test pattern (f) is the same as the target data in the test pattern (c).

[0143] For each cycle, under the condition of a short write recovery operation time tWR, the background data of the sub-region is rewritten as the target data. When the data in the sub-region is modified to the target data, the transistor turn-on voltage of the storage unit in the sub-region is the first reference voltage Von1. A plurality of transistor turn-off voltages are generated according to the voltage range of the transistor turn-off voltage. When the data in the sub-region is modified to the target data in each cycle, the transistor turn-off voltage of the storage unit in the sub-region is set to one of the transistor turn-off voltages, and the transistor turn-off voltage of each cycle is different, so as to realize the scanning of the transistor turn-off voltage. It should also be noted here that when the conditions of the target data are met, the target data of the two cycles can be different or the same. For example, data #01 and data #02 both meet the conditions of the target data, and data #01 can be selected as the target data in one cycle, and data #02 can be selected as the target data in the other cycle. Data #01 can also be selected as the target data in both cycles.

[0144] In the case of the above background data and target data, since the background data is the same, the pull-up effect or pull-down effect of the power line is more obvious. For example, when the background data is number #00, the pull-down effect of the power line is more obvious. The target data makes one of the two adjacent bit lines high, and the target data makes the other of the two adjacent bit lines low, which will introduce the bit line coupling factor. The timing condition of the write recovery operation time tWR is relatively poor, and the turn-on voltage of the transistor is relatively small. If the channel resistance or contact resistance is large, the voltage difference will be lost on the resistance. Therefore, the channel resistance and contact resistance of the transistor in the memory cell can be introduced. The transistor turn-off voltage is scanned again, and the gate voltage effect of the transistor in the memory cell can be introduced. The influence of the power line coupling, bit line coupling, transistor mismatch of the sense amplifier, contact resistance of the transistor, channel resistance of the transistor, and gate voltage effect of the transistor are quantified.

[0145] By testing the target storage area in the above test mode (a) to test mode (f), 6 mapping relationship curves are obtained, such as Fig. 9 As shown. Curve 1 corresponds to test mode (a), curve 2 corresponds to test mode (b), curve 3 corresponds to test mode (c), curve 4 corresponds to test mode (d), curve 5 corresponds to test mode (e), and curve 6 corresponds to test mode (f). The supply amount of the bit line voltage in test mode (a) to test mode (f) is 80mV.

[0146] The following example illustrates the effect of combining the above six test modes to obtain the target factor on the sensing margin of the sense amplifier.

[0147] Test mode (a) is used as a reference test mode, and the reference factors include: transistor mismatch of the sense amplifier. Test mode (b) is used as a target test mode, and the reference factors include: transistor mismatch of the sense amplifier and power line coupling of the sense amplifier. Test mode (a) is tested on the target storage area to obtain a first mapping relationship. Test mode (b) is tested on the target storage area to obtain a second mapping relationship. The influence of the power line coupling of the sense amplifier on the sensing margin is obtained based on the first mapping relationship and the second mapping relationship. Fig. 9 It can be seen that the influence of the power line coupling of the sense amplifier on the sensing margin is 25mV.

[0148] Test mode (b) is used as a reference test mode, and reference factors include: transistor mismatch and power line mismatch of the sense amplifier. Test mode (c) is used as a target test mode, and reference factors include: transistor mismatch of the sense amplifier, power line coupling of the sense amplifier, and bit line coupling. Test mode (b) is tested on the target storage area to obtain a first mapping relationship. Test mode (c) is tested on the target storage area to obtain a second mapping relationship. The influence of bit line coupling on the sensing margin is obtained based on the first mapping relationship and the second mapping relationship. Fig. 9 It can be seen that the impact of bit line coupling on the sensing margin is 15mV.

[0149] Test mode (c) is used as a reference test mode, and reference factors include: transistor mismatch of the sense amplifier, power line coupling of the sense amplifier, and bit line coupling. Test mode (d) is used as a target test mode, and reference factors include: transistor mismatch of the sense amplifier, power line coupling of the sense amplifier, bit line coupling, and contact resistance of the transistor in the storage cell. Test mode (c) is tested on the target storage area to obtain a first mapping relationship. Test mode (d) is tested on the target storage area to obtain a second mapping relationship. Based on the first mapping relationship and the second mapping relationship, the influence of the contact resistance of the transistor in the storage cell on the sensing margin is obtained. Fig. 9 It can be seen that the contact resistance of the transistor in the memory cell has an impact value of 10mV on the sensing margin.

[0150] Test mode (d) is used as a reference test mode, and reference factors include: transistor mismatch of the sense amplifier, power line coupling of the sense amplifier, bit line coupling, and contact resistance of the sense amplifier. Test mode (e) is used as a target test mode, and reference factors include: transistor mismatch of the sense amplifier, power line coupling of the sense amplifier, bit line coupling, contact resistance of the transistor in the memory cell, and channel resistance of the transistor in the memory cell. Test mode (e) is tested on the target storage area to obtain a first mapping relationship. Test mode (d) is tested on the target storage area to obtain a second mapping relationship. Based on the first mapping relationship and the second mapping relationship, the influence of the channel resistance of the transistor in the memory cell on the sensing margin is obtained. Fig. 9 It can be seen that the influence of the channel resistance of the transistor in the memory cell on the sensing margin is 10mV.

[0151] Test mode (e) is used as a reference test mode, and reference factors include: transistor mismatch of the sense amplifier, power line coupling of the sense amplifier, bit line coupling, contact resistance of the transistor in the memory cell, and channel resistance of the transistor in the memory cell. Test mode (f) is used as a target test mode, and reference factors include: transistor mismatch of the sense amplifier, power line coupling of the sense amplifier, bit line coupling, contact resistance of the transistor in the memory cell, channel resistance of the transistor in the memory cell, and gate voltage effect of the transistor in the memory cell. Test mode (e) is tested on the target storage area to obtain a first mapping relationship. Test mode (f) is tested on the target storage area to obtain a second mapping relationship. Based on the first mapping relationship and the second mapping relationship, the influence of the gate voltage effect of the transistor in the memory cell on the sensing margin is obtained. Fig. 9 It can be seen that the gate voltage effect of the transistor in the memory cell has an influence value of 10mV on the sensing margin.

[0152] An embodiment of the present application provides an electronic device, which includes a memory and a processor.

[0153] Wherein, the memory is used to store computer instructions executable by the processor;

[0154] The processor implements each step of the method in the above embodiment when executing the computer instruction. For details, please refer to the relevant description in the above method embodiment.

[0155] Optionally, the memory can be independent or integrated with the processor. When the memory is independent, the electronic device further includes a bus for connecting the memory and the processor.

[0156] An embodiment of the present application further provides a computer-readable storage medium, in which computer instructions are stored. When a processor executes the computer instructions, each step of the method in the above embodiment is implemented.

[0157] The embodiment of the present application also provides a computer program product, including computer instructions, which implement the various steps of the method in the above embodiment when executed by a processor.

[0158] It should be noted that the high level and low level referred to in the above embodiments are relative concepts (i.e., the voltage value of the high level is higher than the voltage value of the corresponding low level), and the specific voltage value of the high level and the specific voltage value of the low level are not limited. In addition, it is not limited that the high levels applied on different signal lines in this specific embodiment are equal. For example, the high level on the bit line and the high level on the word line can be different voltages, and it is not limited that the high levels of a specific signal line at different stages are equal. For example, the high level applied to the bit line when writing 1 and when reading can be different voltage values. Those skilled in the art should understand that the corresponding high level and low level values ​​can be set according to the process node, speed requirements, reliability requirements, etc.

[0159] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0160] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for testing a sensitive amplifier, characterized in that: The target storage area includes the sense amplifier and the storage unit, and the bit line is connected to the sense amplifier and the storage unit; the method includes: Acquire a first mapping relationship between a first loss amount and a first error rate in a reference test mode; wherein the reference test mode includes a reference factor, the first loss amount is a loss amount of the reference factor to the bit line voltage, and the first error rate is a read error rate of data read from the target storage area under the effect of the first loss amount; Acquire a second mapping relationship between a second loss amount and a second error rate in a target test mode; wherein the target test mode includes the reference factor and the target factor, the second loss amount is the loss amount of the bit line voltage caused by the reference factor and the target factor together, and the second error rate is a read error rate of data read from the target storage area under the effect of the second loss amount; According to the first mapping relationship and the second mapping relationship, an influence value of the target factor on the sensing margin of the sense amplifier is calculated and obtained.

2. The testing method according to claim 1, characterized in that: The first mapping relationship includes a plurality of mapping relationships between the first loss amount and the first error rate, and obtaining the first mapping relationship between the first loss amount and the first error rate in the reference test mode specifically includes: Determine first background data, first target data and first control parameter according to the reference factor; wherein the first control parameter includes any one of a write operation recovery time, a transistor turn-on voltage and a transistor turn-off voltage; Writing the first background data into the target storage area; Acquire the address of the current sub-region in the target storage region, and modify the data in the current sub-region to the first target data according to the address of the current sub-region and the first control parameter; Setting a test condition that is not conducive to reading data based on the lower plate voltage of the storage unit; The data in the target storage area is read, and a first loss amount and a first error rate of the sub-area are calculated; and a set of mapping relationships is obtained.

3. The testing method according to claim 2, characterized in that: Setting a test condition that is not conducive to reading data based on the lower plate voltage of the storage unit specifically includes: Before writing the first background data into the target storage area, increasing the lower plate voltage of each storage unit in the target storage area; After modifying the data in the current sub-region to the first target data, setting a test condition that is not conducive to reading the first data by adjusting the lower plate voltage of each storage unit in the target storage region back to an initial value; Accordingly, setting a test condition that is not conducive to reading data based on the lower plate voltage of the memory cell specifically includes: Before writing the first background data into the target storage area, reducing the lower plate voltage of each storage unit in the target storage area; After the data in the current sub-region is modified to be the first target data, a test condition that is not conducive to reading out the second data is set by adjusting the lower plate voltage of each storage unit in the target storage region back to an initial value.

4. The testing method according to claim 3, characterized in that: in, The first mapping relationship includes a first mapping relationship set and a second mapping relationship set; The first mapping relationship set is a mapping relationship set obtained by setting a test condition that is not conducive to reading the first data based on the lower plate voltage of the storage unit in the reference test mode; The second mapping relationship set is a mapping relationship set obtained by setting a test condition that is not conducive to reading out the second data based on the bottom plate voltage of the memory cell in the reference test mode.

5. The testing method according to claim 2, characterized in that: The sub-regions are memory cells on the same word line, and the memory cells share a column selection line.

6. The testing method according to claim 2, characterized in that: The second mapping relationship includes a plurality of mapping relationships between the second loss amount and the second error rate, and obtaining the second mapping relationship between the second loss amount and the second error rate in the reference test mode specifically includes: Determine the second background data, the second target data and the second control parameter according to the reference factor and the target factor; the second control parameter includes any one of a write operation recovery time, a transistor turn-on voltage and a transistor turn-off voltage; Writing the second background data into the target storage area; Acquire the address of the current sub-region in the target storage region, and modify the data in the current sub-region to the second target data according to the address of the current sub-region and the second control parameter; Setting a test condition that is not conducive to reading data based on the lower plate voltage of the storage unit; The data in the target storage area is read, and a second loss amount and a second error rate of the sub-area are calculated; and a set of mapping relationships is obtained.

7. The testing method according to any one of claims 1 to 6, characterized in that: Calculating and obtaining the influence value of the target factor on the sensing margin of the sense amplifier according to the first mapping relationship and the second mapping relationship specifically includes: Calculate a first target loss amount corresponding to an error rate threshold value according to the first mapping relationship, and calculate a second target loss amount corresponding to the error rate threshold value according to the second mapping relationship; An influence value of the target factor on the sensing margin of the sense amplifier is calculated according to the first target loss amount and the second target loss amount.

8. The testing method according to claim 6, characterized in that: In the reference test mode, the first background data stored in two adjacent storage units in the current sub-area are different, the first target data stored in two adjacent storage units in the current sub-area are different, the first background data and the first target data are different; and the write operation recovery time when modifying the data in the current sub-area to the first target number is the second reference time; When the data in the current sub-region is changed to the first target data, the transistor turn-on voltage of the storage unit in the current sub-region is changed to the first reference voltage; In the target test mode, the second background data stored in each storage unit in the current sub-region is the same, and the second target data stored in two adjacent storage units in the current sub-region is different; and the write operation recovery time when modifying the data in the current sub-region to the second target number is the second reference time; When the data in the current sub-region is modified to be the second target data, the transistor turn-on voltage of the storage unit in the current sub-region is the first reference voltage.

9. The testing method according to claim 6, characterized in that: In the reference test mode, the first background data stored in each storage unit in the current sub-region is the same, and the first target data stored in two adjacent storage units in the current sub-region is different; and the write operation recovery time when modifying the data in the current sub-region to the first target number is the second reference time; When modifying the data in the current sub-region to be the first target data, the transistor turn-on voltage of the storage unit in the current sub-region is the first reference voltage; In the target test mode, the second background data stored in each storage unit in the current sub-region is the same, the second target data stored in only one storage unit in the current sub-region is different from the second target data stored in other storage units in the current sub-region; and the write operation recovery time when modifying the data in the current sub-region to the second target number is the second reference time; When the data in the current sub-region is modified to be the second target data, the transistor turn-on voltage of the storage unit in the current sub-region is the first reference voltage.

10. The testing method according to claim 6, characterized in that: In the reference test mode, the first background data stored in each storage unit in the current sub-region is the same, and the first target data stored in only one storage unit in the current sub-region is different from the first target data stored in other storage units in the current sub-region; and when the data in the current sub-region is modified to the first target data, the write operation recovery time is the second reference time, and when the data in the current sub-region is modified to the first target data, the transistor turn-on voltage of the storage unit in the current sub-region is the first reference voltage; In the target test mode, the second background data stored in each storage unit in the current sub-region is the same, and the second target data stored in only one storage unit in the current sub-region is different from the second target data stored in other storage units in the current sub-region; and when the data in the current sub-region is modified to the second target number, the write operation recovery time is the first reference time, and when the data in the current sub-region is modified to the second target data, the transistor turn-on voltage of the storage unit in the current sub-region is the second reference voltage, and the first reference time is less than the second reference time.

11. The testing method according to claim 6, characterized in that: In the reference test mode, the first background data stored in each storage unit in the current sub-region is the same, and the first target data stored in only one storage unit in the current sub-region is different from the first target data stored in other storage units in the current sub-region; and when the data in the current sub-region is modified to the first target data, the write operation recovery time is the first reference time, and when the data in the current sub-region is modified to the first target data, the transistor turn-on voltage of the storage unit in the current sub-region is the second reference voltage; In the target test mode, the second background data stored in each storage unit in the current sub-region is the same, and the second target data stored in only one storage unit in the current sub-region is different from the second target data stored in other storage units in the current sub-region; and when the data in the current sub-region is modified to the second target number, the write operation recovery time is the first reference time, and when the data in the current sub-region is modified to the second target data, the transistor turn-on voltage of the storage unit in the current sub-region is the first reference voltage; the first reference voltage is less than the second reference voltage.

12. The testing method according to claim 6, characterized in that: In the reference test mode, the first background data stored in each storage unit in the current sub-region is the same, and the first target data stored in only one storage unit in the current sub-region is different from the first target data stored in other storage units in the current sub-region; and when the data in the current sub-region is modified to the first target data, the write operation recovery time is the first reference time, and when the data in the current sub-region is modified to the first target data, the transistor turn-on voltage of the storage unit in the current sub-region is the first reference voltage; In the target test mode, the second background data stored in each storage unit in the current sub-region is the same, and the second target data stored in only one storage unit in the current sub-region is different from the second target data stored in other storage units in the current sub-region; and when the data in the current sub-region is modified to the second target data, the write operation recovery time is the first reference time, when the data in the current sub-region is modified to the second target data, the transistor turn-on voltage of the storage unit in the current sub-region is the first reference voltage, and when the data in the current sub-region is modified to the second target data, the transistor turn-off voltage of the storage unit in the current sub-region is the current reference voltage; Furthermore, the transistor turn-off voltage of the memory cell in the next sub-region is different from the transistor turn-off voltage of the memory cell in the current sub-region.

13. An electronic device, characterized in that: include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 12.

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