Test method and electronic equipment for sensitive amplifier

Abstract

The present application provides a test method and electronic device for a sense amplifier, comprising: obtaining a first mapping relationship between a first loss amount and a first error rate in a reference test mode. The reference test mode includes a reference factor, the first loss amount is the loss amount of the reference factor on the bit line voltage, and the first error rate is the read error rate of data read from a target storage area under the influence of the first loss amount; and obtaining a second mapping relationship between a second loss amount and a second error rate in a target test mode. The target test mode includes a reference factor and a target factor, the second loss amount is the loss amount of the reference factor and the target factor on the bit line voltage together, and the second error rate is the read error rate of data read from the target storage area under the influence of the second loss amount. Based on the first and second mapping relationships, calculating the impact value of the target factor on the sensing margin of the sense amplifier.

Description

Technical Field

[0001] The present application relates to, but is not limited to, a testing method and electronic equipment for a sensitive amplifier. Background Art

[0002] With the development of memory technology, memory is widely used in various fields. For example, dynamic random access memory (DRAM) is widely used.

[0003] The sense amplifier (SA) is a crucial component of semiconductor memory. Its primary function is to sense and amplify small signals on the bit line, enabling read or write operations. Improvements to the sense amplifier can help improve data read and write performance. Summary of the Invention

[0004] Some embodiments of the present application provide a method for testing a sense amplifier, wherein a target storage area includes a sense amplifier and a storage cell, and a bit line is connected to the sense amplifier and the storage cell; the method includes:

[0005] Obtaining a first mapping relationship between a first loss amount and a first error rate in a reference test mode; wherein the reference test mode includes a reference factor, the first loss amount is a loss amount of the reference factor to the bit line voltage, and the first error rate is a read error rate of data read from the target storage area under the effect of the first loss amount;

[0006] Obtaining a second mapping relationship between a second loss amount and a second error rate in a target test mode; wherein the target test mode includes a reference factor and a target factor, the second loss amount is a loss amount of the bit line voltage caused by the reference factor and the target factor, and the second error rate is a read error rate of data read from the target storage area under the effect of the second loss amount;

[0007] An influence value of the target factor on the sensing margin of the sense amplifier is obtained by calculation according to the first mapping relationship and the second mapping relationship.

[0008] Some embodiments of the present application provide an electronic device, comprising: a processor, and a memory communicatively connected to the processor;

[0009] Memory stores computer-executable instructions;

[0010] The processor executes the computer-executable instructions stored in the memory to implement the methods involved in the above embodiments.

[0011] The test method and electronic device for a sensitive amplifier provided in the present application obtain a first mapping relationship between a first loss amount and a first error rate in a reference test mode, and obtain a second mapping relationship between a second loss amount and a second error rate in a target test mode. The target test mode has more target factors than the reference test mode. Based on the first mapping relationship and the second mapping relationship, the bit line voltage loss amount caused by the introduction of the target factor can be obtained, and then the impact value of the target factor on the sensing margin of the sensitive amplifier can be determined. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0013] Figure 1 A schematic diagram of the memory architecture provided for some embodiments of the present disclosure;

[0014] Figure 2 An exemplary structural diagram of a storage unit according to some embodiments of the present disclosure is shown;

[0015] Figure 3 A schematic flow chart of a method for testing a sense amplifier provided in some embodiments of the present disclosure;

[0016] Figure 4A and Figure 4B To adopt Figure 3 Schematic diagram of the mapping relationship obtained by the test method shown;

[0017] Figure 5 A schematic flow chart of a method for testing a sense amplifier provided in some embodiments of the present disclosure;

[0018] Figure 6 A schematic flow chart of a method for testing a sense amplifier provided in some embodiments of the present disclosure;

[0019] Figure 7 To adopt Figure 6 Schematic diagram of the mapping relationship obtained by the test method shown;

[0020] Figure 8A is a flow chart of the test method under test mode (a);

[0021] Figure 8B is a flow chart of the test method under test mode (b);

[0022] Figure 8C is a flow chart of the test method under test mode (c);

[0023] Figure 8D is a flow chart of the test method under test mode (d);

[0024] Figure 8E is a flow chart of the test method under test mode (e);

[0025] Figure 8F is a flow chart of the test method under test mode (f);

[0026] Figure 9 Schematic diagram of the mapping relationship corresponding to test mode (a) to test mode (f).

[0027] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0028] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0029] In the description of this disclosure, it should be noted that, unless otherwise expressly specified or limited, the terms "connected" and "connection" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections; and direct connections or indirect connections through an intermediary. Those skilled in the art will understand the specific meanings of the above terms in this disclosure based on the specific circumstances.

[0030] Currently, memory technology is developing rapidly. Taking DRAM as an example, the main applications include Synchronous Dynamic Random-Access Memory (SDRAM), various generations of Double Data Rate (DDR) SDRAM, and various generations of Low Power Double Data Rate (LPDDR) SDRAM.

[0031] Figure 1 This is an example diagram of a memory architecture, such as Figure 1As shown, taking DRAM as an example, it includes an address processing circuit 210, a command decoding circuit 220, a data input / output circuit 230, a row decoder 240, a column decoder 250, a sense amplifier (SA) 260, and a memory array. The address processing circuit 210, command decoding circuit 220, and data input / output circuit 230 belong to the peripheral area circuit, while the row decoder 240, column decoder 250, sense amplifier 260, and memory array belong to the array area circuit. The memory array is mainly composed of memory cells 270, bit lines BL, and word lines WL. The word lines WL in the memory array extend in the row direction, and the bit lines BL in the memory array extend in the column direction. The intersection of the word lines WL and the bit lines BL is the memory cell 270 of the memory array.

[0032] Each storage unit 270 is used to store one bit of data. Figure 2 FIG. 1 is a structural diagram of a storage unit according to an embodiment of the present invention. Figure 2 As shown, memory cell 270 includes a switching transistor M and a capacitor C. Either the source or the drain of switching transistor M is connected to the upper plate of capacitor C, the lower plate of capacitor C is connected to a power line, the other of the source or the drain of switching transistor M is connected to a bit line BL, and the gate of switching transistor M is connected to a word line WL. Capacitor C is used to store data, and switching transistor M is used to turn off or on depending on the selected state. The voltage at the lower plate of capacitor C is referred to as Vap2. The precharge voltage on the bit line before charge sharing is performed is referred to as Vad2. The gate turn-on voltage of switching transistor M is referred to as Vpp.

[0033] As chip integration increases and transistor feature sizes continue to shrink, issues such as threshold voltage fluctuations and the susceptibility of small voltage signals to noise in MOS transistors (MOS transistors) in sense amplifiers (SAMPs) are becoming increasingly prominent, seriously impacting the accuracy of the sense amplifier's sensing of data in memory cells. Sensing margin (SM) is a key performance metric for sense amplifiers. The formula for calculating SM is: SM = Supply dVBL - Required dVBL, where Supply dVBL refers to the voltage difference between the bit line and the complementary bit line at the end of the charge sharing phase (also known as the supply of the sensing margin). Required dVBL refers to the voltage difference required for accurate SAMP amplification (also known as the loss of the sensing margin). This loss of sensing margin is caused by offset voltage and coupling noise, both caused by mismatched MOS transistor threshold voltages.

[0034] In practical applications, the sensing margin of the sense amplifier is usually obtained by testing the sense amplifier. Figure 3 This is a test method for sensitive amplifiers. Figure 3 As shown, a test method for a sensitive amplifier specifically includes the following steps:

[0035] S101. Writing background data into a target storage area.

[0036] The target storage area includes a plurality of sub-areas, each of which includes a word line arranged along a row and a plurality of bit lines arranged along a column. A storage unit is provided at the intersection of the word line and the bit line.

[0037] Each bit line in each sub-region is connected to a column selection line. When the word line of the sub-region is turned on, a column selection signal controls the turning on of multiple bit lines to write or read data to the storage cells of the sub-region.

[0038] The background data can be determined according to the test requirements. In order to obtain the sensing margin of the sense amplifier, it is usually necessary to test the sensing margin when reading data "1" through the sense amplifier, and also to test the sensing margin when reading data "0" through the sense amplifier.

[0039] To increase test speed, the background data of the two sub-regions can be identical. By setting the background data within each sub-region to meet test requirements, the test can be performed. Typically, eight bit lines are connected to one column select line, so a sub-region includes eight memory cells. For ease of understanding, the eight memory cells mentioned below refer to the eight memory cells in one sub-region.

[0040] In order to test the performance of reading data "0", background data that is not conducive to reading data "0" is set. For example, the background data of the 6th storage unit among the 8 storage units is data "0", and the background data of the remaining storage units is data "1".

[0041] In order to test the performance of reading data "1", background data that is not conducive to reading data "0" is set. For example, the background data of the 6th storage unit among 8 storage units is data "1", and the background data of the remaining storage units is data "0".

[0042] To increase test speed, a fast X-direction write mode is used to write background data to the target memory area. This means that before each write operation, all word lines on the same bit line are sequentially enabled. Each time a word line is enabled, the contents of the eight memory cells on that word line are sequentially written, and then the word line is closed. The next word line is then enabled and the contents of the eight memory cells on that word line are sequentially written, until all memory cells are written.

[0043] S102: Adjust the voltage of the lower plate of the capacitor in the storage unit.

[0044] To obtain the sensing margin of the sense amplifier, the voltage of the capacitor bottom plate in the memory cell is adjusted multiple times. During this adjustment, a current scan voltage of the bottom plate is generated, and the capacitor bottom plate voltages of all memory cells in the target memory area are adjusted to the current scan voltage.

[0045] Since the charge on the capacitor is non-mutagenic, the voltage on the capacitor plate will also change, which will change the supply of sensing margin Supply dVBL, and thus affect the error rate of the sense amplifier when reading data from the memory cell.

[0046] Typically, a memory cell stores data "1" or "0" in the following manner. The memory cell's lower plate voltage Vap2 is set to a lower plate reference value, for example, Vap2 = 0.5V. A voltage greater than the upper plate voltage indicates the storage of data "1." A voltage less than the lower plate voltage indicates the storage of data "0."

[0047] To test the sensing margins for reading data "1" and "0" using the sense amplifier, the lower plate scan voltage can be gradually increased from the lower plate reference voltage to create an environment unfavorable for reading data "1." Accordingly, the background data can be set to a value unfavorable for reading data "1." This allows the sense amplifier to determine the sensing margins for reading data "1." The lower plate scan voltage can also be gradually decreased from the lower plate reference voltage to create an environment unfavorable for reading data "0." Accordingly, the background data can be set to a value unfavorable for reading data "0." This allows the sense amplifier to determine the sensing margins for reading data "0."

[0048] S103, read the background data from the target storage area, and count the read error rate. If the scan of the lower plate voltage is not completed, return to S101, and if the scan of the lower plate capacitance is completed, return to S104.

[0049] To increase test speed, a fast readout mode in the X direction is used to read background data from the target storage area. The background data written to each memory cell in the target storage area is compared with the background data read out. If the two data are identical, the data is read correctly. If the two data are different, the data read is incorrect.

[0050] Count the number of memory cells in the target storage area that have read data errors, calculate the proportion of memory cells with read data errors, and obtain the read error rate. Establish a mapping relationship between the current scan voltage and the read error rate.

[0051] S104 , calculating a sensing margin according to a mapping relationship between multiple sets of scanning voltages and readout error rates.

[0052] The statistical readout error rate is smaller than the voltage range ΔV covered by the lower plate scanning voltage corresponding to the preset threshold, and the sensing margin SM is calculated according to the voltage range.

[0053] The sensing margin SM can be calculated by the following formula:

[0054]

[0055] Wherein, Cs is the capacitance of the capacitor in the memory cell, and ΔV is the voltage range covered by the scan voltage corresponding to the read error rate being less than the preset threshold. total =(Cbl+Csa+Cs). Cs is the capacitance of the capacitor, Cbl is the bit line parasitic capacitance, and Csa refers to the bit line coupling capacitance of the sense amplifier.

[0056] More specifically, the mapping relationship between multiple sets of scanning voltages and readout error rates is plotted as a curve. Figure 4A and Figure 4B As shown in FIG, the curve is bowl-shaped, so it is called a bowl plot. By drawing a straight line representing the preset threshold value on the vertical axis of the curve, the voltage range ΔV can be obtained.

[0057] However, since the above method uses the lower plate of the scanning capacitor to obtain the sensing margin of the sense amplifier, that is, the sensing margin of the sense amplifier is obtained by adjusting the supply amount Supply dVBL of the sensing margin, it cannot reflect the impact of various factors in the target storage area on the loss of the sensing margin of the sense amplifier.

[0058] For example, Figure 4A Bowl diagram showing the case where the capacitance Cs of the capacitor in each memory cell in the target memory area is 5 fF, and the bit line coupling capacitance Cbl is 30 fF. Figure 4B A bowl diagram shows a capacitor with a capacitance Cs of 10 fF in a memory cell in the target storage region and a bit line coupling capacitance Cbl of 30 fF. Although the capacitances Cs of the two capacitors are different, the voltage ranges calculated by the two bowl diagrams are the same, ΔV. Therefore, the bowl diagrams fail to reflect the impact of the storage capacitance Cs on the loss of sensing margin.

[0059] In addition, due to the mixture of multiple influencing factors, it is difficult to correlate the bit line voltage difference loss with design or process defects in theoretical analysis, and it is also impossible to measure the impact of different influencing factors on the sensing margin from a theoretical analysis.

[0060] For ease of description, data "1" is referred to as first data, data "0" is referred to as second data, the supply amount of the sensing margin Supply dVBL is referred to as the supply amount of the bit line voltage, and the loss amount of the sensing margin Required dVBL is referred to as the loss amount of the bit line voltage.

[0061] Some aspects of the embodiments of the present disclosure relate to the above considerations. The following describes the solutions with examples in conjunction with some embodiments of the present disclosure.

[0062] like Figure 5 As shown, some embodiments of the present application provide a method for testing a sense amplifier. The sense amplifier is located in a target storage area, which also includes a storage cell, a bit line, and a word line. The storage cell is located where the bit line and the word line intersect, and the bit line is connected to the sense amplifier. The method for testing the sense amplifier specifically includes the following steps:

[0063] S201: Obtain a first mapping relationship between a first loss amount and a first error rate in a reference test mode.

[0064] The test mode of the sense amplifier includes a reference test mode, the reference test mode includes a reference factor, and the reference factor affects the loss of the bit line voltage.

[0065] The first loss amount is the loss amount of the bit line voltage due to the reference factor in the reference test mode, and the first error rate is the read error rate of data read from the target storage area under the effect of the first loss amount. The first mapping relationship can be obtained by testing the target storage cell in the reference test mode.

[0066] The first mapping relationship includes two mapping relationship sets, each mapping relationship set includes multiple groups of mapping relationships between first loss amounts and first error rates. By performing multiple tests on the target storage area under a reference test mode, multiple groups of mapping relationships between first loss amounts and first error rates are obtained, and then the first mapping relationship is obtained.

[0067] The first mapping relationship set includes multiple sets of mapping relationships for reading the first data. The mapping relationships for reading the first data refer to mapping relationships between a first loss amount and a first read error rate when a test condition is set based on the lower plate voltage of the memory cell in a reference test mode that is unfavorable for reading the first data. For example, the mapping relationships are obtained by adjusting the lower plate voltage so that the lower plate voltage is greater than a lower plate reference voltage, then writing data, and restoring the lower plate voltage when reading data, thereby creating a test condition that is unfavorable for reading the first data. In this manner, a sensing margin for reading the first data can be obtained based on the first mapping relationships.

[0068] The second mapping relationship set includes multiple sets of mapping relationships for reading the second data. The mapping relationships for reading the second data refer to mapping relationships between the first loss amount and the first read error rate when setting test conditions that are unfavorable for reading the second data based on the lower plate voltage of the memory cell in a reference test mode. For example, the mapping relationships are obtained when test conditions that are unfavorable for reading the second data are created by adjusting the lower plate voltage so that the lower plate voltage is less than the lower plate reference voltage, then writing data, and restoring the lower plate voltage when reading data. In this way, a sensing margin for reading the first data can be obtained based on the first mapping relationship.

[0069] S202: Obtain a second mapping relationship between a second loss amount and a second error rate in a target test mode.

[0070] The test mode of the sense amplifier includes a target test mode, and the target test mode includes a reference factor and a target factor.

[0071] The second loss amount is the loss amount of the bit line voltage caused by the reference factor and the target factor in the target test mode. The second error rate is the read error rate of data read from the target storage area under the influence of the second loss amount. The second mapping relationship can be obtained by testing the target memory cell in the target test mode.

[0072] The second mapping relationship includes two mapping relationship sets, each mapping relationship set includes multiple groups of mapping relationships between second loss amounts and second error rates. By performing multiple tests on the target storage area under the target test mode, multiple groups of mapping relationships between second loss amounts and second error rates are obtained, and then the second mapping relationship is obtained.

[0073] The two mapping relationship sets include a third mapping relationship set and a fourth mapping relationship set. The third mapping relationship set includes multiple sets of mapping relationships for reading the first data. The mapping relationship for reading the first data refers to a mapping relationship between a second loss amount and a second read error rate obtained when a test condition is set based on the lower plate voltage of the storage cell in a target test mode that is not conducive to reading the first data. For example, the mapping relationship is obtained by adjusting the lower plate voltage so that the lower plate voltage is greater than the lower plate reference voltage, then writing data, and restoring the lower plate voltage when reading data, thereby creating a test condition that is not conducive to reading the first data.

[0074] The fourth mapping relationship set includes multiple groups of mapping relationships under reading the second data. The mapping relationship under reading the second data refers to the mapping relationship between the second loss amount and the second read error rate when the test conditions are set based on the lower plate voltage of the storage unit in the target test mode, which is not conducive to reading the second data. For example: by adjusting the lower plate voltage so that the lower plate voltage is less than the lower plate reference voltage, and then writing the data, and restoring the lower plate voltage when reading the data, a mapping relationship is obtained when the test conditions that are not conducive to reading the second data are created.

[0075] S203 : Calculate and obtain an impact value of the target factor on the sensing margin of the sense amplifier according to the first mapping relationship and the second mapping relationship.

[0076] In some embodiments, a first target loss corresponding to an error rate threshold is obtained based on a first mapping relationship, and a second target loss corresponding to the error rate threshold is obtained based on a second mapping relationship. The impact of the target factor on the sensing margin of the sense amplifier is calculated based on the first and second target losses. This arrangement allows the first mapping relationship to directly reflect the impact of the reference factor on the sensing margin, while the second mapping relationship can reflect the impact of both the reference factor and the target factor on the sensing margin. The impact of the target factor on the sensing margin can then be intuitively determined based on the first and second mapping relationships.

[0077] As an implementation method, a first fitting curve is obtained by curve fitting the first mapping relationship, and a second fitting curve is obtained by curve fitting the second mapping relationship. Because the first mapping relationship and the second mapping relationship each contain two mapping relationship sets, and the data in the two mapping relationship sets are symmetrical, the first fitting curve and the second fitting curve are symmetrical graphs. Thus, one error read rate corresponds to two loss amounts. A first target loss amount is calculated for the first fitting curve when the first read error rate is the error rate threshold. The first target loss amount is the larger or smaller of the two first loss amounts corresponding to the error rate threshold.

[0078] Calculate a second target loss amount for the second fitting curve when the second readout error rate is the error rate threshold. If the first target loss amount is the larger of the two first losses corresponding to the error rate threshold, then the second target loss amount is the larger of the two second losses corresponding to the error rate threshold. If the first target loss amount is the smaller of the two first losses corresponding to the error rate threshold, then the second target loss amount is the smaller of the two second losses corresponding to the error rate threshold.

[0079] As another implementation, a first loss corresponding to a first read error rate having a minimum difference from an error rate threshold and less than the error rate threshold is selected from the first mapping set in the first mapping relationship as the first target loss. A second loss corresponding to a second read error rate having a minimum difference from the error rate threshold and less than the error rate threshold is selected from the first mapping set in the second mapping relationship as the third target loss.

[0080] In some embodiments, a first loss difference between the first target loss and the second target loss is calculated, which can be used as an impact value of the target factor on the sensing margin of the sense amplifier.

[0081] In the above technical solution, a first mapping relationship between the first loss amount and the first error rate is obtained in the reference test mode, and a second mapping relationship between the second loss amount and the second error rate is obtained in the target test mode. The target test mode has more target factors than the reference test mode. Based on the first mapping relationship and the second mapping relationship, the bit line voltage loss amount caused by the introduction of the target factor can be obtained, and then the impact value of the target factor on the sensing margin of the sensitive amplifier can be determined.

[0082] like Figure 6 As shown, the following describes an implementation method for obtaining a first mapping relationship between a first loss amount and a first error rate. Specifically, the method includes the following steps:

[0083] S301: Determine first background data, first target data, and first control parameters according to reference factors.

[0084] The factors affecting the sensing margin of the sense amplifier include transistor mismatch of the sense amplifier, bit line coupling, power line coupling of the sense amplifier, channel resistance of the transistor in the memory cell, transistor contact resistance, and gate voltage effect of the transistor in the memory cell. The reference factor includes one or more combinations of transistor mismatch of the sense amplifier, bit line coupling, power line coupling of the sense amplifier, channel resistance of the transistor in the memory cell, transistor contact resistance, and gate voltage effect of the transistor in the memory cell.

[0085] Specifically, bit line coupling refers to the fact that the bit lines of the sense amplifier are metal lines located in the metal layer. Since the bit lines are relatively close to each other, coupling capacitance will be generated between two adjacent bit lines. When the voltages of the adjacent bit lines are high and low, respectively, the voltages of the two adjacent bit lines will affect each other through the coupling capacitance, thus introducing the bit line coupling effect.

[0086] Power line coupling in sense amplifiers specifically refers to the situation where, in actual circuits, different sense amplifiers share a single power line. When the target memory cell stores a first data value of "1" while the surrounding background memory cells store a second data value of "0," the pull-down effect of the power line is relatively strong, impacting the data readout process within the target memory cell and, more specifically, the sensing margin of the sense amplifier. Conversely, when the target memory cell stores a second data value of "0" while the surrounding background memory cells store a first data value of "1," the pull-up effect of the power line is relatively strong, impacting the data readout process within the target memory cell. This phenomenon is known as the power line coupling effect in sense amplifiers.

[0087] The first control parameter includes any one of a write operation recovery time, a transistor turn-on voltage, and a transistor turn-off voltage. By setting one or more of the first control parameters, and then designing the first background data and the first target data, the effects of each of these factors on the sensing margin of the sense amplifier can be reflected.

[0088] S302: Write first background data into the target storage area.

[0089] To increase test speed, a fast Y-direction write method is used to write the first background data to the memory cells. Before each write operation, a word line is turned on. After the contents of the eight memory cells on this word line are sequentially written, the word line is turned off. Then, the word line is turned on again and the contents of the eight memory cells are sequentially written. This word line is turned on and off repeatedly until all the corresponding memory cells on this word line are written. Then, the next word line is turned on and the same operation is repeated until all memory cells are written.

[0090] S303: Obtain the address of the current sub-region in the target storage region, and modify the data in the current sub-region to the first target data according to the address of the current sub-region and the first control parameter.

[0091] The target storage area includes multiple sub-areas, which are storage cells on the same word line and share a column selection line. By scanning each sub-area one by one, the background data in each sub-area is modified to the first target data.

[0092] In the current cycle, the address of the current sub-region in the target storage region is obtained, the current sub-region of the data to be modified is determined according to the address of the current sub-region, and the first target data is written into the current sub-region based on the first control parameter.

[0093] Since there are slight differences in the storage cells of each sub-region in the target storage area, the loss amount in different sub-regions is also different. By testing each sub-region one by one, the loss amount and data read error rate of each sub-region are obtained.

[0094] S304 : Setting a test condition that is not conducive to reading data based on the lower plate voltage of the memory cell.

[0095] Among them, the lower plate voltage of the storage unit refers to the lower plate voltage of the capacitor in the storage unit, and a test condition that is not conducive to reading the first data is created based on adjusting the lower plate voltage of the storage unit, or a test condition that is not conducive to reading the second data is created based on adjusting the lower plate voltage of the storage unit.

[0096] In some embodiments, when creating test conditions that are not conducive to reading the first data, the adjusted lower plate voltage of the storage unit can be made greater than the lower plate reference voltage. After adjusting the lower plate voltage, data is written to the storage unit, and then the lower plate voltage is adjusted back to the original value when reading the data in the storage unit. Since the voltage difference on the capacitor in the storage unit will not change, the upper plate voltage of the storage unit will also drop. Through such a setting, test conditions that are not conducive to reading the first data are created.

[0097] When creating test conditions that are not conducive to reading the second data, the adjusted lower plate voltage of the storage cell can be made lower than the lower plate reference voltage. After adjusting the lower plate voltage, data is written to the storage cell, and then the lower plate voltage is adjusted back to the original value when reading the data in the storage cell. Since the voltage difference on the capacitor in the storage cell does not change, the upper plate voltage of the storage cell will also rise. Through such an arrangement, test conditions that are not conducive to reading the second data are created.

[0098] In other embodiments, when creating test conditions that are not conducive to reading the first data, the lower plate voltage of the storage cell is used as the lower plate voltage reference, data is written to the storage cell, and then the lower plate voltage is adjusted downward when reading the data in the storage cell. Since the voltage difference on the capacitor in the storage cell does not change, the upper plate voltage of the storage cell will also decrease. Through such an arrangement, test conditions that are not conducive to reading the first data are created.

[0099] When creating test conditions that are not conducive to reading the second data, the lower plate voltage of the storage cell is set to the lower plate voltage reference value, data is written to the storage cell, and then the lower plate voltage is adjusted upward when reading the data in the storage cell. Since the voltage difference on the capacitor in the storage cell does not change, the upper plate voltage of the storage cell will also rise. Through such an arrangement, test conditions that are not conducive to reading the second data are created.

[0100] S305: Read the data in the target storage area, calculate the first loss amount and the first error rate of the current sub-area, and obtain a set of mapping relationships.

[0101] The first loss amount of the current sub-region can be calculated using the following formula:

[0102]

[0103] Wherein, Cs is the capacitance of the capacitor, Vblh is the high voltage on the bit line, that is, the upper plate voltage of the capacitor when writing the first data, Vap2 Bump refers to the adjustment amount of the lower plate voltage, Cbl is the bit line parasitic capacitance, Csa refers to the bit line coupling capacitance of the sense amplifier, and Vad2 is the precharge voltage before charge sharing on the bit line.

[0104] The first error rate of the current sub-region can be calculated by comparing the data read from the current sub-region with the first target data written into the current sub-region, counting the number of storage cells with different data in the current sub-region, and calculating the first error rate based on the number obtained from the count. Specifically, the first error rate is obtained by dividing the data of the storage cells with different data by the total number of storage cells in the current sub-region. This results in the first loss amount and the first error rate of the current sub-region.

[0105] S306: Determine whether all sub-regions in the target storage unit have been traversed. If so, end the process. If not, update the current sub-region to the next sub-region and return to S301.

[0106] In the above technical solution, by traversing each sub-region of the target storage unit one by one, the first loss amount and first error rate of the multiple sub-regions can be obtained, and the first loss amount and first error rate of the multiple sub-regions are combined into a first mapping relationship.

[0107] Through Figure 4A and Figure 4B The target storage area for the two parameter cases shown uses Figure 6 The test method shown is used to test and obtain Figure 7 As shown in the mapping diagram. Figure 7As shown, the thick line represents the mapping relationship under the first parameter case, that is, the mapping relationship when the memory cell transistor capacitance Cs = 5fF and the bit line coupling capacitance Cbl is 30fF. The thin line represents the mapping relationship under the second parameter case, that is, the mapping relationship when the memory cell transistor capacitance Cs = 10fF and the bit line coupling capacitance Cbl is 30fF. The mapping relationship is peak-shaped. Setting the error rate threshold to 10%, the loss values ​​corresponding to the two mapping relationship curves under the error rate threshold of 10% are different. The loss value corresponding to the first parameter case is 28.6mV and the corresponding supply value is 71.4mV. The loss value corresponding to the second parameter case is 50mV and the corresponding supply value is 125mV. Therefore, the peak diagram can directly reflect the loss value of the bit line voltage under different parameters, and can directly reflect the impact of the transistor capacitance Cs in the memory cell on the sensing margin.

[0108] The following describes an implementation method for obtaining a second mapping relationship between the second loss amount and the second error rate, which specifically includes the following steps:

[0109] S401: Determine second background data, second target data, and second control parameters according to reference factors and target factors.

[0110] The reference factors include one or more combinations of transistor mismatch of the sense amplifier, bit line coupling, power line coupling of the sense amplifier, channel resistance of the transistor in the memory cell, contact resistance of the transistor in the memory cell, and gate voltage effect of the transistor in the memory cell. The target factors include one or more combinations of transistor mismatch of the sense amplifier, bit line coupling, power line coupling of the sense amplifier, channel resistance of the transistor in the memory cell, contact resistance of the transistor in the memory cell, and gate voltage effect of the transistor in the memory cell.

[0111] The second control parameter includes any one of a write operation recovery time, a transistor turn-on voltage, and a transistor turn-off voltage. By setting one or more of these second control parameters, and then designing second background data and second target data, the impact of each of these factors on the sensing margin of the sense amplifier can be reflected.

[0112] S402: Write the second background data into the target storage area.

[0113] S403: Acquire the address of the current sub-region in the target storage region, and modify the data in the current sub-region to the second target data according to the address of the current sub-region and the second control parameter.

[0114] S404 : Setting a test condition that is not conducive to reading data based on the lower plate voltage of the memory cell.

[0115] S405 : Read the data in the target storage area, calculate the second loss amount and the second error rate of the current sub-area, and obtain a set of mapping relationships.

[0116] S406: Determine whether all sub-regions in the target storage unit have been traversed. If so, end the process. If not, update the current sub-region to the next sub-region and return to S401.

[0117] In the above technical solution, by traversing each sub-region of the target storage unit one by one, the second loss amount and second error rate of the multiple sub-regions can be obtained, and the second loss amount and second error rate of the multiple sub-regions are combined into a second mapping relationship.

[0118] Seven test modes are designed based on factors that affect the sensing margin of the sense amplifier. By combining the seven test modes, the influence of a certain factor on the sensing margin of the sense amplifier can be obtained.

[0119] Table 1 shows the factors of the test mode

[0120]

[0121] Based on the factors involved in the test modes in Table 1, the background data, target data, and control parameters for each test mode are set, as shown in Table 2.

[0122] Table 2 is the configuration table of the test mode

[0123] Test mode number Background Data Target data WRv Turn-on voltage Shutoff voltage (a) Data #55 Data#AA t2 Von1 - (b) Data #00 Data#AA t2 Von1 - (c) Data #00 Data#01 / 2 / 4 / 8 t2 Von1 - (d) Data #00 Data#01 / 2 / 4 / 8 t1 Von2 - (e) Data #00 Data#01 / 2 / 4 / 8 t1 Von1 - (f) Data #00 Data#01 / 2 / 4 / 8 t1 Von1 [Voff1,Voff2]

[0124] In Table 2, data #00 means that the data in a sub-area is 00000000, data #55 means that the data in a sub-area is 01010101, data #AA means that the data in a sub-area is 10101010, data #01 means that the data in a sub-area is 00000001, data #02 means that the data in a sub-area is 00000010, data #04 means that the data in a sub-area is 00000100, and data #08 means that the data in a sub-area is 00001000.

[0125] The first reference time t1 is less than the second reference time t2. When the write recovery operation time tWR is equal to t1, it is a short write recovery operation time. When the write recovery operation time tWR is equal to t2, it is a long write recovery operation time (long tWR). The first reference voltage Von1 is less than the second reference voltage Von2, and Voff1 is less than Voff2.

[0126] like Figure 8AAs shown, in test mode (a), the background data stored in two adjacent storage cells within each sub-region is different, for example, the background data is data #55 or data #AA. The target data stored in two adjacent storage cells within the sub-region is different, for example, the target data is data #55 or data #AA. The background data and target data are different, for example, when the background data is #55, the target data is #AA; when the background data is #AA, the target data is #55.

[0127] For each cycle, under the condition of long write recovery operation time tWR, the background data of the sub-region is rewritten to the target data. When the data in the sub-region is modified to the target data, the transistor turn-on voltage of the memory cell in the sub-region is the first reference voltage Von1.

[0128] In the case of the aforementioned background data and target data, the distribution of the first data "1" and the second data "0" of data #55 and data #AA is similar, and the distribution of the data stored in the surrounding memory cells has little impact on the reading of the current memory cell. Therefore, the influence of the power line coupling and bit line coupling of the sense amplifier on the sensing margin of the sense amplifier can be eliminated. In addition, the timing conditions of the write recovery operation time tWR are good. Therefore, the influence of the channel resistance of the transistor in the memory cell, the contact resistance of the transistor in the memory cell, the gate voltage effect of the transistor in the memory cell, and the write recovery operation time tWR on the sensing margin of the sense amplifier can be eliminated, thereby quantifying the influence of the transistor mismatch in the sense amplifier.

[0129] like Figure 8B As shown, in test mode (b), the background data stored in each storage unit in each sub-area is the same, for example: the background data is data #00, and the target data stored in two adjacent storage units in the sub-area are different, for example: the target data is data #AA or #55.

[0130] For each cycle, under the condition of long write recovery operation time tWR, the background data of the sub-region is rewritten to the target data. When the data in the sub-region is modified to the target data, the transistor turn-on voltage of the memory cell in the sub-region is the first reference voltage Von1.

[0131] In the aforementioned case of background data and target data, since the background data is identical, the pull-up or pull-down effect of the power line is more pronounced after the target data is written into the current sub-region. For example, when the background data is the number #00, the pull-down effect of the power line is more pronounced. Therefore, power line coupling of the sense amplifier is introduced. Since the distribution of the target data, the first data "1," and the second data "0," are comparable, the distribution of the stored data in the memory cells in the surrounding sub-regions has little impact on the reading of the memory cells in the current sub-region. Therefore, the impact of bit line coupling on the sensing margin of the sense amplifier can be eliminated. Furthermore, the timing conditions for the write recovery operation time tWR are optimal. Therefore, the effects of the write recovery operation time tWR, the channel resistance of the transistors in the memory cells, the contact resistance of the transistors in the memory cells, and the gate voltage effect of the transistors in the memory cells on the sensing margin of the sense amplifier can be eliminated, thereby quantifying the effects of power line coupling and transistor mismatch in the sense amplifier.

[0132] like Figure 8C As shown, in test mode (c), the background data stored in each storage cell within a sub-region is either the first data or the second data. For example, the background data in each sub-region is data #00. When the background data in each storage cell within a sub-region is the first data, only one storage cell within the sub-region stores the second data as the target data, while the target data stored in the other storage cells is the first data. For example, the target data is any one of data #00, data #01, data #02, data #04, and data #08. When the background data in each storage cell within a sub-region is the second data, only one storage cell within the sub-region stores the first data as the target data, while the target data stored in the other storage cells is the second data.

[0133] For each cycle, under the condition of long write recovery operation time tWR, the background data of the sub-region is rewritten to the target data. When the data in the sub-region is modified to the target data, the transistor turn-on voltage of the memory cell in the sub-region is the first reference voltage Von1.

[0134] It should also be noted that, when the target data conditions are met, the target data for the two loops can be different or the same. For example, if both data #01 and data #02 meet the target data conditions, data #01 can be selected as the target data in one loop, and data #02 can be selected as the target data in the other loop. Alternatively, data #01 can be selected as the target data in both loops.

[0135] In the aforementioned cases of background data and target data, since the background data is the same, the pull-up or pull-down effect of the power line is more pronounced. For example, when the background data is the number #00, the pull-down effect of the power line is more pronounced. Therefore, power line coupling of the sense amplifier is introduced. When the target data causes one of two adjacent bit lines to be high, and the target data causes the other to be low, bit line coupling is introduced. The timing conditions for the write recovery operation time tWR are relatively good, and the transistor turn-on voltage is relatively good. Therefore, the effects of the write recovery operation time tWR, the channel resistance of the transistor in the memory cell, the contact resistance of the transistor in the memory cell, and the gate voltage effect of the transistor in the memory cell on the sensing margin of the sense amplifier can be eliminated. The effects of power line coupling, bit line coupling, and transistor mismatch in the sense amplifier are quantified.

[0136] like Figure 8D As shown, the background data in the test pattern (d) is the same as that in the test pattern (c), and the target data in the test pattern (d) is the same as that in the test pattern (c).

[0137] For each cycle, under the condition of short write recovery operation time tWR, the background data of the sub-region is rewritten to the target data. When the data in the sub-region is modified to the target data, the transistor turn-on voltage of the memory cell in the sub-region is the second reference voltage Von2.

[0138] In the aforementioned cases of background data and target data, since the background data is the same, the pull-up or pull-down effect of the power line is more pronounced. For example, if the background data is the number #00, the pull-down effect of the power line is more pronounced. If the target data causes one of two adjacent bit lines to be high and the target data causes the other to be low, this introduces bit line coupling. The timing conditions of the write recovery time tWR are relatively poor, and the transistor turn-on voltage is higher. A high turn-on voltage can increase write speed. Assuming there is no contact resistance, data writing can also be completed within the short write operation recovery time tWR. If there is a contact resistance effect, the written data is insufficient, resulting in a read failure. Therefore, the contact resistance of the transistor in the memory cell can be introduced to eliminate the impact of the channel resistance of the transistor in the memory cell and the gate voltage effect of the transistor in the memory cell on the sensing margin of the sense amplifier. The effects of power line coupling, bit line coupling, transistor mismatch in the sense amplifier, and transistor contact resistance on the sense amplifier are quantified.

[0139] like Figure 8E As shown, the background data in the test pattern (e) is the same as that in the test pattern (c), and the target data in the test pattern (e) is the same as that in the test pattern (c).

[0140] For each cycle, under the condition of short write recovery operation time tWR, the background data of the sub-region is rewritten to the target data. When the data in the sub-region is modified to the target data, the transistor turn-on voltage of the memory cell in the sub-region is the first reference voltage Von1.

[0141] In the aforementioned cases of background data and target data, the pull-up or pull-down effect of the power line is more pronounced because the background data is the same. For example, when the background data is the number #00, the pull-down effect of the power line is more pronounced. If the target data causes one of two adjacent bit lines to be high and the target data causes the other to be low, this introduces bit line coupling. The timing conditions of the write recovery operation time tWR are relatively poor, and the transistor's turn-on voltage is relatively low. If the channel resistance or contact resistance is large, the voltage difference will be lost in the resistor. Therefore, the channel resistance and contact resistance of the transistor in the memory cell can be introduced to eliminate the impact of the gate voltage effect of the transistor in the memory cell on the sensing margin of the sense amplifier. The effects of the sense amplifier's power line coupling, bit line coupling, transistor mismatch in the sense amplifier, transistor contact resistance, and the channel resistance of the transistor in the memory cell are quantified.

[0142] like Figure 8F As shown, the background data in the test pattern (f) is the same as that in the test pattern (c), and the target data in the test pattern (f) is the same as that in the test pattern (c).

[0143] For each cycle, under the condition of a short write recovery operation time tWR, the background data of the sub-region is rewritten as the target data. When the data in the sub-region is modified to the target data, the transistor turn-on voltage of the storage unit in the sub-region is the first reference voltage Von1. A plurality of transistor turn-off voltages are generated according to the voltage range of the transistor turn-off voltage. When the data in the sub-region is modified to the target data in each cycle, the transistor turn-off voltage of the storage unit in the sub-region is set to one of the transistor turn-off voltages, and the transistor turn-off voltage of each cycle is different, thereby realizing the scanning of the transistor turn-off voltage. It should also be noted here that when the conditions of the target data are met, the target data of the two cycles can be different or the same. For example, if both data #01 and data #02 meet the conditions of the target data, data #01 can be selected as the target data in one cycle, and data #02 can be selected as the target data in the other cycle. Data #01 can also be selected as the target data in both cycles.

[0144] In the aforementioned cases of background data and target data, the pull-up or pull-down effect of the power line is more pronounced due to the identical background data. For example, when the background data is the number #00, the pull-down effect of the power line is more pronounced. If the target data causes one of two adjacent bit lines to be high and the target data causes the other to be low, bit line coupling will be introduced. The timing conditions of the write recovery operation time tWR are relatively poor, and the transistor's turn-on voltage is relatively low. If the channel resistance or contact resistance is large, the voltage difference will be lost in the resistor. Therefore, the channel resistance and contact resistance of the transistor in the memory cell can be introduced. Furthermore, by scanning the transistor's turn-off voltage, the gate voltage effect of the transistor in the memory cell can be introduced. This quantifies the effects of power line coupling, bit line coupling, transistor mismatch, transistor contact resistance, transistor channel resistance, and transistor gate voltage effect on the sense amplifier.

[0145] By testing the target storage area in the above test mode (a) to test mode (f), 6 mapping relationship curves are obtained, such as Figure 9 As shown in Figure 1, curve 1 corresponds to test mode (a), curve 2 corresponds to test mode (b), curve 3 corresponds to test mode (c), curve 4 corresponds to test mode (d), curve 5 corresponds to test mode (e), and curve 6 corresponds to test mode (f). The bit line voltage supply in test modes (a) to (f) is 80 mV.

[0146] The following example illustrates the influence of the target factors on the sensing margin of the sense amplifier obtained by combining the above six test modes.

[0147] Test pattern (a) is used as a reference test pattern, with reference factors including transistor mismatch of the sense amplifier. Test pattern (b) is used as a target test pattern, with reference factors including transistor mismatch of the sense amplifier and power line coupling of the sense amplifier. Test pattern (a) is performed on a target storage area to obtain a first mapping relationship. Test pattern (b) is performed on the target storage area to obtain a second mapping relationship. Based on the first and second mapping relationships, the impact of power line coupling of the sense amplifier on the sensing margin is determined. Figure 9 It can be seen that the power line coupling of the sense amplifier has an impact of 25mV on the sensing margin.

[0148] Test pattern (b) is used as a reference test pattern, with reference factors including transistor mismatch and power line mismatch of the sense amplifier. Test pattern (c) is used as a target test pattern, with reference factors including transistor mismatch of the sense amplifier, power line coupling of the sense amplifier, and bit line coupling. Test pattern (b) is tested on the target storage area to obtain a first mapping relationship. Test pattern (c) is tested on the target storage area to obtain a second mapping relationship. Based on the first and second mapping relationships, the impact of bit line coupling on the sensing margin is determined. Figure 9 It can be seen that the impact of bit line coupling on the sensing margin is 15mV.

[0149] Test mode (c) is used as a reference test mode, and reference factors include: transistor mismatch of the sense amplifier, power line coupling of the sense amplifier, and bit line coupling. Test mode (d) is used as a target test mode, and reference factors include: transistor mismatch of the sense amplifier, power line coupling of the sense amplifier, bit line coupling, and contact resistance of the transistor in the memory cell. Test mode (c) is tested on the target memory area to obtain a first mapping relationship. Test mode (d) is tested on the target memory area to obtain a second mapping relationship. Based on the first mapping relationship and the second mapping relationship, the impact of the contact resistance of the transistor in the memory cell on the sensing margin is obtained. Figure 9 It can be seen that the contact resistance of the transistor in the memory cell has an impact of 10mV on the sensing margin.

[0150] Test mode (d) is used as a reference test mode, and reference factors include: transistor mismatch of the sense amplifier, power line coupling of the sense amplifier, bit line coupling, and contact resistance of the sense amplifier. Test mode (e) is used as a target test mode, and reference factors include: transistor mismatch of the sense amplifier, power line coupling of the sense amplifier, bit line coupling, contact resistance of the transistor in the memory cell, and channel resistance of the transistor in the memory cell. Test mode (e) is tested on the target storage area to obtain a first mapping relationship. Test mode (d) is tested on the target storage area to obtain a second mapping relationship. Based on the first mapping relationship and the second mapping relationship, the influence of the channel resistance of the transistor in the memory cell on the sensing margin is obtained. Figure 9 It can be seen from FIG that the channel resistance of the transistor in the memory cell has an impact of 10 mV on the sensing margin.

[0151] Test mode (e) is used as a reference test mode, and reference factors include: transistor mismatch of the sense amplifier, power line coupling of the sense amplifier, bit line coupling, contact resistance of the transistor in the memory cell, and channel resistance of the transistor in the memory cell. Test mode (f) is used as a target test mode, and reference factors include: transistor mismatch of the sense amplifier, power line coupling of the sense amplifier, bit line coupling, contact resistance of the transistor in the memory cell, channel resistance of the transistor in the memory cell, and gate voltage effect of the transistor in the memory cell. Test mode (e) is tested on the target storage area to obtain a first mapping relationship. Test mode (f) is tested on the target storage area to obtain a second mapping relationship. Based on the first mapping relationship and the second mapping relationship, the influence of the gate voltage effect of the transistor in the memory cell on the sensing margin is obtained. Figure 9 It can be seen that the gate voltage effect of the transistor in the memory cell has an impact value of 10mV on the sensing margin.

[0152] An embodiment of the present application provides an electronic device, which includes a memory and a processor.

[0153] Wherein, the memory is used to store computer instructions executable by the processor;

[0154] When the processor executes the computer instructions, each step of the method in the above embodiment is implemented. For details, please refer to the relevant description of the above method embodiment.

[0155] Optionally, the memory can be independent or integrated with the processor. When the memory is independent, the electronic device further includes a bus for connecting the memory and the processor.

[0156] An embodiment of the present application further provides a computer-readable storage medium, in which computer instructions are stored. When a processor executes the computer instructions, each step of the method in the above embodiment is implemented.

[0157] An embodiment of the present application further provides a computer program product, including computer instructions, which, when executed by a processor, implement the various steps of the method in the above embodiment.

[0158] It should be noted that the high level and low level referred to in the above embodiments are relative concepts (i.e., the voltage value of the high level is higher than the voltage value of the corresponding low level), and do not limit the specific voltage value of the high level or the specific voltage value of the low level. Furthermore, the high levels applied to different signal lines in this specific embodiment are not limited to being equal. For example, the high level of the bit line and the high level of the word line can be different voltages. Nor is it limited to the high levels of a specific signal line being equal at different stages. For example, the high level applied to the bit line during a write 1 operation and during a read operation can be different voltages. Those skilled in the art will understand that the corresponding high and low level values ​​can be set arbitrarily based on process nodes, speed requirements, reliability requirements, etc.

[0159] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0160] It should be understood that the present application is not limited to the exact structure described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for testing a sensitive amplifier, characterized in that: The target storage area includes the sense amplifier and the storage cell, and the bit line is connected to the sense amplifier and the storage cell; the method includes: Obtaining a first mapping relationship between a first loss amount and a first error rate in a reference test mode; wherein the reference test mode includes a reference factor, the first loss amount is a loss amount of the bit line voltage caused by the reference factor, and the first error rate is a read error rate of data read from the target storage area under the effect of the first loss amount; Obtaining a second mapping relationship between a second loss amount and a second error rate in a target test mode; wherein the target test mode includes the reference factor and the target factor, the second loss amount is a loss amount of the bit line voltage caused by the reference factor and the target factor together, and the second error rate is a read error rate of data read from the target storage area under the effect of the second loss amount; An influence value of the target factor on the sensing margin of the sense amplifier is calculated based on the first mapping relationship and the second mapping relationship.

2. The testing method according to claim 1, wherein: The first mapping relationship includes a plurality of mapping relationships between the first loss amounts and the first error rates. Obtaining the first mapping relationship between the first loss amounts and the first error rates in a reference test mode specifically includes: Determining first background data, first target data, and first control parameters based on the reference factors; wherein the first control parameter includes any one of a write operation recovery time, a transistor turn-on voltage, and a transistor turn-off voltage; Writing the first background data into the target storage area; Acquire an address of a current sub-region within the target storage region, and modify data within the current sub-region to the first target data according to the address of the current sub-region and the first control parameter; Setting a test condition that is not conducive to reading data based on the lower plate voltage of the memory cell; Data in the target storage area is read, a first loss amount and a first error rate of the sub-area are calculated, and a set of mapping relationships is obtained.

3. The testing method according to claim 2, wherein: Setting a test condition that is not conducive to reading data based on the lower plate voltage of the memory cell specifically includes: Before writing the first background data into the target storage area, increasing the lower plate voltage of each storage unit in the target storage area; After modifying the data in the current sub-region to the first target data, setting a test condition that is not conducive to reading the first data by adjusting the lower plate voltage of each storage unit in the target storage region back to an initial value; Accordingly, setting a test condition that is not conducive to reading data based on the lower plate voltage of the memory cell specifically includes: Before writing the first background data into the target storage area, reducing the lower plate voltage of each storage unit in the target storage area; After the data in the current sub-region is modified to the first target data, a test condition that is not conducive to reading the second data is set by adjusting the lower plate voltage of each storage unit in the target storage region back to an initial value.

4. The testing method according to claim 3, wherein: in, The first mapping relationship includes a first mapping relationship set and a second mapping relationship set; The first mapping relationship set is a mapping relationship set obtained by setting a test condition that is not conducive to reading the first data based on the bottom plate voltage of the memory cell in the reference test mode; The second mapping relationship set is a mapping relationship set obtained by setting a test condition that is not conducive to reading out the second data based on the bottom plate voltage of the memory cell in the reference test mode.

5. The testing method according to claim 2, wherein: The sub-regions are memory cells on the same word line, and the memory cells share a column selection line.

6. The testing method according to claim 2, wherein: The second mapping relationship includes a plurality of mapping relationships between the second loss amount and the second error rate. Obtaining the second mapping relationship between the second loss amount and the second error rate in the reference test mode specifically includes: Determining second background data, second target data, and second control parameters based on the reference factor and the target factor; the second control parameter includes any one of a write operation recovery time, a transistor turn-on voltage, and a transistor turn-off voltage; writing the second background data into the target storage area; Acquire an address of a current sub-region within the target storage region, and modify data within the current sub-region to the second target data according to the address of the current sub-region and the second control parameter; Setting a test condition that is not conducive to reading data based on the lower plate voltage of the memory cell; Data in the target storage area is read, a second loss amount and a second error rate of the sub-area are calculated, and a set of mapping relationships is obtained.

7. The testing method according to any one of claims 1 to 6, characterized in that: Calculating an influence value of the target factor on the sensing margin of the sense amplifier according to the first mapping relationship and the second mapping relationship specifically includes: Calculate a first target loss amount corresponding to an error rate threshold according to the first mapping relationship, and calculate a second target loss amount corresponding to the error rate threshold according to the second mapping relationship; An influence value of the target factor on the sensing margin of the sense amplifier is calculated according to the first target loss amount and the second target loss amount.

8. The testing method according to claim 6, wherein: In the reference test mode, the first background data stored in two adjacent storage cells in the current sub-region are different, the first target data stored in two adjacent storage cells in the current sub-region are different, the first background data and the first target data are different; and the write operation recovery time when the data in the current sub-region is modified to the first target data is the second reference time; When the data in the current sub-region is the first target data, the transistor turn-on voltage of the storage unit in the current sub-region is modified to be the first reference voltage; In the target test mode, the second background data stored in each storage unit in the current sub-region is the same, and the second target data stored in two adjacent storage units in the current sub-region are different; and the write operation recovery time when the data in the current sub-region is modified to the second target data is the second reference time; When the data in the current sub-region is modified to the second target data, the transistor turn-on voltage of the storage unit in the current sub-region is the first reference voltage.

9. The testing method according to claim 6, characterized in that: In the reference test mode, the first background data stored in each storage unit in the current sub-region is the same, the first target data stored in two adjacent storage units in the current sub-region are different; and the write operation recovery time when the data in the current sub-region is modified to the first target data is the second reference time; When the data in the current sub-region is modified to be the first target data, the transistor turn-on voltage of the storage unit in the current sub-region is changed to the first reference voltage; In the target test mode, the second background data stored in each storage unit in the current sub-region is the same, the second target data stored in only one storage unit in the current sub-region is different from the second target data stored in other storage units in the current sub-region; and the write operation recovery time when modifying the data in the current sub-region to the second target data is the second reference time; When the data in the current sub-region is modified to the second target data, the transistor turn-on voltage of the storage unit in the current sub-region is the first reference voltage.

10. The testing method according to claim 6, wherein: In the reference test mode, the first background data stored in each storage unit in the current sub-region is the same, and the first target data stored in only one storage unit in the current sub-region is different from the first target data stored in other storage units in the current sub-region; and when the data in the current sub-region is modified to the first target data, the write operation recovery time is the second reference time, and when the data in the current sub-region is modified to the first target data, the transistor turn-on voltage of the storage unit in the current sub-region is the first reference voltage; In the target test mode, the second background data stored in each storage unit in the current sub-region is the same, and the second target data stored in only one storage unit in the current sub-region is different from the second target data stored in other storage units in the current sub-region; and when the data in the current sub-region is modified to the second target number, the write operation recovery time is the first reference time, and when the data in the current sub-region is modified to the second target data, the transistor turn-on voltage of the storage unit in the current sub-region is the second reference voltage, and the first reference time is less than the second reference time.

11. The testing method according to claim 6, characterized in that: In the reference test mode, the first background data stored in each storage unit in the current sub-region is the same, and the first target data stored in only one storage unit in the current sub-region is different from the first target data stored in other storage units in the current sub-region; and when the data in the current sub-region is modified to the first target data, the write operation recovery time is the first reference time, and when the data in the current sub-region is modified to the first target data, the transistor turn-on voltage of the storage unit in the current sub-region is the second reference voltage; In the target test mode, the second background data stored in each storage unit in the current sub-region is the same, and the second target data stored in only one storage unit in the current sub-region is different from the second target data stored in other storage units in the current sub-region; and when the data in the current sub-region is modified to the second target number, the write operation recovery time is the first reference time, and when the data in the current sub-region is modified to the second target data, the transistor turn-on voltage of the storage unit in the current sub-region is the first reference voltage; and the first reference voltage is less than the second reference voltage.

12. The testing method according to claim 6, wherein: In the reference test mode, the first background data stored in each storage unit in the current sub-region is the same, and the first target data stored in only one storage unit in the current sub-region is different from the first target data stored in other storage units in the current sub-region; and when the data in the current sub-region is modified to the first target data, the write operation recovery time is the first reference time, and when the data in the current sub-region is modified to the first target data, the transistor turn-on voltage of the storage unit in the current sub-region is the first reference voltage; In the target test mode, the second background data stored in each storage unit in the current sub-region is the same, and the second target data stored in only one storage unit in the current sub-region is different from the second target data stored in other storage units in the current sub-region; and when the data in the current sub-region is modified to the second target data, the write operation recovery time is the first reference time, when the data in the current sub-region is modified to the second target data, the transistor turn-on voltage of the storage unit in the current sub-region is the first reference voltage, and when the data in the current sub-region is modified to the second target data, the transistor turn-off voltage of the storage unit in the current sub-region is the current reference voltage. Furthermore, the transistor turn-off voltage of the memory cell in the next sub-region is different from the transistor turn-off voltage of the memory cell in the current sub-region.

13. An electronic device, characterized in that: include: a processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 12.

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