Sensitive amplifier control method and memory

Abstract

The invention provides a control method of a sensitive amplifier and a memory. The sensitive amplifier comprises a pre-charging stage, an offset elimination stage, a charge sharing stage and a sensing amplification stage. In the offset elimination stage, the first power end is controlled to be connected with power voltage, the second power end is controlled to be connected with grounding voltage, and the sensitive amplifier is controlled to form compensation voltage on the bit line and the complementary bit line; wherein the duration of the offset elimination stage is the optimal offset elimination duration, and the sensing margin of the sensitive amplifier is the maximum value under the optimal offset elimination duration. In the sensing amplification stage, the first power end is controlled to be connected with the power voltage, the second power end is controlled to be connected with the grounding voltage, the time when the first power end is connected with the power voltage is later than the time when the second power end is connected with the grounding voltage, and the sensitive amplifier is controlled to amplify the voltage difference on the bit line and the complementary bit line.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, a control method of a sense amplifier and a memory. Background Art

[0002] With the development of memory technology, memories are widely used in various fields. For example, dynamic random access memory (DRAM) is widely used.

[0003] The sense amplifier (SA) is an important component of semiconductor memory. Its main function is to sense and amplify the small signal on the bit line, and then perform read or write operations. Improvements to the sense amplifier are conducive to improving data reading and writing performance. Summary of the invention

[0004] The present disclosure provides a control method for a sense amplifier, wherein the sense amplifier is connected to a bit line and a complementary bit line, the bit line is connected to a storage unit, the sense amplifier includes a first power supply terminal and a second power supply terminal, and the method includes:

[0005] In the pre-charging stage, the first power supply terminal and the second power supply terminal are controlled to be connected to the pre-charging voltage, and the sense amplifier is controlled to drive the voltage on the bit line and the complementary bit line to the pre-charging voltage;

[0006] In the offset elimination phase, the first power supply terminal is controlled to be connected to the power supply voltage, the second power supply terminal is controlled to be connected to the ground voltage, and the sense amplifier is controlled to form a compensation voltage on the bit line and the complementary bit line; wherein the duration of the offset elimination phase is an optimal offset elimination duration, and the sensing margin of the sense amplifier is a maximum value under the optimal offset elimination duration;

[0007] In the charge sharing stage, the first power supply terminal and the second power supply terminal are controlled to be connected to the precharge voltage, the memory cell and the bit line share the charge, and a charge sharing voltage is formed on the bit line and the complementary bit line;

[0008] In the sensing and amplification stage, the first power supply terminal is controlled to be connected to the power supply voltage, and the second power supply terminal is controlled to be connected to the ground voltage. The time when the first power supply terminal is connected to the power supply voltage is later than the time when the second power supply terminal is connected to the ground voltage. The sense amplifier is controlled to amplify the voltage difference between the bit line and the complementary bit line.

[0009] In some embodiments, the control method further comprises:

[0010] Generate a plurality of first control scenarios, wherein each first control scenario includes a duration parameter of an offset elimination phase, and the duration parameters of the offset elimination phase in any two first control scenarios are different;

[0011] A first sensing margin of the sense amplifier in a first control scenario is obtained; and a duration parameter of an offset elimination phase corresponding to a maximum sensing margin among a plurality of first sensing margins is used as an optimal offset elimination duration.

[0012] In some embodiments, obtaining a first sensing margin of a sense amplifier in a first control scenario specifically includes:

[0013] acquiring a second sensing margin of a sense amplifier in a target storage area under a first control scenario when a condition unfavorable for reading out the first data is set;

[0014] acquiring a third sensing margin of a sense amplifier in a target storage area under a first control scenario when a condition unfavorable for reading out the second data is set;

[0015] A sum of the second sensing margin and the third sensing margin is calculated as the first sensing margin.

[0016] In some embodiments, obtaining a second sensing margin of a sense amplifier in a target storage area under a first control scenario when a condition unfavorable for reading out the first data is set specifically includes:

[0017] generating a plurality of first scanning voltages greater than a reference voltage of a lower plate of a memory cell;

[0018] For each first scanning voltage, the voltage in the storage unit in the target storage area is adjusted according to the first scanning voltage, and the duration of the offset elimination phase of the sense amplifier is controlled as a duration parameter, and the data read error rate of the storage unit in the target storage area is counted to obtain a first mapping relationship between the plurality of first scanning voltages and the read error rate under each first scanning voltage;

[0019] The second sensing margin is obtained by calculation according to the first mapping relationship.

[0020] In some embodiments, obtaining a third sensing margin of a sense amplifier in a target storage area under a first control scenario when a condition that is unfavorable for reading out the second data is set specifically includes:

[0021] generating a plurality of second scanning voltages less than a reference voltage of a lower plate of a memory cell;

[0022] For each second scanning voltage, the voltage in the storage unit in the target storage area is adjusted according to the second scanning voltage, and the duration of the offset elimination phase of the sense amplifier is controlled as a duration parameter, and the data read error rate of the storage unit in the target storage area is counted to obtain a second mapping relationship between the plurality of second scanning voltages and the read error rate under each second scanning voltage;

[0023] A third sensing margin is obtained by calculation according to the second mapping relationship.

[0024] In some embodiments, the control method further comprises:

[0025] Generate multiple second control scenarios, wherein each second control scenario includes a duration parameter of an offset elimination phase, a first moment when the first power supply terminal switches from being connected to a pre-charge voltage to being connected to a power supply voltage during a charge sharing phase, and a second moment when the second power supply terminal switches from being connected to a pre-charge voltage to being connected to a ground voltage during a charge sharing phase; the duration parameter of the offset elimination phase of each second control scenario is an optimal offset elimination duration, the first moment in the same second control scenario is later than the second moment, the first moments in any two second control scenarios are different, or the second moments in any two second control scenarios are different;

[0026] Acquire a sensing margin difference of the sense amplifier in each second control scenario; use a first moment corresponding to a minimum sensing margin difference among a plurality of sensing margin differences as an optimal first moment for the first power supply terminal to switch from being connected to a pre-charge voltage to being connected to a power supply voltage during a charge sharing phase, and use a second moment corresponding to the minimum sensing margin difference as an optimal second moment for the second power supply terminal to switch from being connected to a pre-charge voltage to being connected to a ground voltage during a charge sharing phase;

[0027] Correspondingly, controlling the first power supply terminal to connect to the power supply voltage, controlling the second power supply terminal to connect to the ground voltage, and the time when the first power supply terminal is connected to the power supply voltage is later than the time when the second power supply terminal is connected to the ground voltage, and controlling the sense amplifier to amplify the voltage difference between the bit line and the complementary bit line, specifically includes:

[0028] The first power supply terminal is controlled to switch from the pre-charge voltage to the power supply voltage during the charge sharing phase as the optimal first moment, the second power supply terminal is controlled to switch from the pre-charge voltage to the ground voltage during the charge sharing phase as the optimal second moment, and the sensitive amplifier is controlled to amplify the voltage difference between the bit line and the complementary bit line.

[0029] In some embodiments, obtaining a fourth sensing margin of the sense amplifier in each second control scenario specifically includes:

[0030] acquiring a fourth sensing margin of a sense amplifier in a target storage region under a second control scenario when a condition unfavorable for reading out the first data is set;

[0031] acquiring a fifth sensing margin of a sense amplifier in a target storage region under a second control scenario when a condition unfavorable for reading out the first data is set;

[0032] A difference between the fourth sensing margin and the fifth sensing margin is calculated as a sensing margin difference value.

[0033] In some embodiments, obtaining a fourth sensing margin of a sense amplifier in a target storage region under a second control scenario when a condition unfavorable for reading out the first data is set specifically includes:

[0034] generating a plurality of third scanning voltages greater than a reference voltage of a lower plate of a memory cell;

[0035] For each third scanning voltage, the voltage in the storage unit in the target storage area is adjusted according to the third scanning voltage, the duration of the offset elimination phase of the sense amplifier is controlled to be the optimal offset elimination duration, the moment when the first power supply terminal is switched from the pre-charge voltage to the power supply voltage in the charge sharing phase is controlled to be the first moment, and the moment when the second power supply terminal is switched from the pre-charge voltage to the ground voltage in the charge sharing phase is controlled to be the second moment, and the data read error rate of the storage unit in the target storage area is counted to obtain a third mapping relationship between multiple third scanning voltages and the read error rate under each third scanning voltage;

[0036] A fourth sensing margin is obtained by calculation according to the third mapping relationship.

[0037] In some embodiments, obtaining a fifth sensing margin of a sense amplifier in a target storage region under a second control scenario when a condition unfavorable for reading out the second data is set specifically includes:

[0038] generating a plurality of fourth scanning voltages greater than a reference voltage of a lower plate of a memory cell;

[0039] For each fourth scanning voltage, the voltage in the storage unit in the target storage area is adjusted according to the fourth scanning voltage, the duration of the offset elimination phase of the sense amplifier is controlled to be the optimal offset elimination duration, the moment when the first power supply terminal is switched from the pre-charge voltage to the power supply voltage during the charge sharing phase is controlled to be the first moment, and the moment when the second power supply terminal is switched from the pre-charge voltage to the ground voltage during the charge sharing phase is controlled to be the second moment, and the data read error rate of the storage unit in the target storage area is counted, and a fourth mapping relationship between a plurality of fourth scanning voltages and the read error rate under each fourth scanning voltage is obtained;

[0040] A fifth sensing margin is calculated according to the fourth mapping relationship, wherein the target storage area storage unit stores the second data, and the fourth scanning voltage is generated according to the reference voltage corresponding to the second data.

[0041] Some embodiments of the present application provide a memory, including: a storage unit, a sense amplifier and a controller, wherein the storage unit is connected to a bit line, the sense amplifier is connected to the bit line, the controller is connected to the sense amplifier, and the controller is used to implement the method involved in the above embodiments.

[0042] In the control method and memory of the sense amplifier provided by some embodiments of the present application, the working phases of the sense amplifier include a pre-charging phase, an offset elimination phase, a charge sharing phase, and a sensing amplification phase. The duration of the offset elimination phase is the optimal offset elimination duration. Under the optimal offset elimination duration, the sensing margin of the sense amplifier is the maximum value, and most of the mismatch noise and other noises of the sense amplifier can be eliminated. In the sensing amplification phase, the moment when the first power supply terminal is connected to the power supply voltage is controlled to be later than the moment when the second power supply terminal is connected to the ground voltage, and the sensing margin on the bit line and the complementary bit line can be adjusted to reduce the data preference of the sense amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0044] Figure 1 An architectural schematic diagram of a memory provided for some embodiments of the present disclosure;

[0045] Figure 2 An example diagram of a storage unit structure shown in some embodiments of the present disclosure;

[0046] Figure 3 A circuit schematic diagram of a sense amplifier provided in some embodiments of the present disclosure;

[0047] Figure 4A for Figure 3 An operating timing diagram of the sense amplifier shown;

[0048] Figure 4B for Figure 3 Another working timing diagram of the sense amplifier shown;

[0049] Figure 5 A flow chart of a control method of a sense amplifier provided in some embodiments of the present disclosure;

[0050] Figure 6 A graph showing the relationship between the offset elimination time and the compensation voltage provided in some embodiments of the present application;

[0051] Figure 7 for Figure 3 Another working timing diagram of the sense amplifier shown;

[0052] Figure 8 A schematic diagram of a first mapping relationship and a second mapping relationship in a first control scenario provided in some embodiments of the present application;

[0053] Fig. 9 A schematic diagram of a first mapping relationship and a second mapping relationship in different first control scenarios provided in some embodiments of the present application;

[0054] Fig.10 Schematic diagrams of third mapping relationships and fourth mapping relationships in different second control scenarios provided in some embodiments of the present application.

[0055] The above drawings show clear embodiments of the present disclosure, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0056] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0057] In the description of the present disclosure, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the feature. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0058] In the description of the present disclosure, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0059] At present, memory technology is developing rapidly. Taking DRAM as an example, the main applications include synchronous dynamic random access memory (Synchronous Dynamic Random-Access Memory, referred to as: SDRAM), various generations of double data rate (Double Data Rate, referred to as: DDR) SDRAM, various generations of low power double data rate (Low Power Double Data Rate, referred to as: LPDDR) SDRAM and other types.

[0060] Figure 1 This is a sample diagram of a memory architecture, such as Figure 1 As shown, taking DRAM as an example, it includes an address processing circuit 210, a command decoding circuit 220, a data input / output circuit 230, a row decoder 240, a column decoder 250, a sense amplifier (SA) 260 and a storage array. Among them, the address processing circuit 210, the command decoding circuit 220 and the data input / output circuit 230 belong to the peripheral area circuit, and the row decoder 240, the column decoder 250, the sense amplifier 260 and the storage array belong to the array area circuit. The storage array is mainly composed of a storage cell 270, a bit line BL and a word line WL. The word line WL in the storage array extends in the row direction, and the bit line BL in the storage array extends in the column direction. The intersection of the word line WL and the bit line BL is the storage cell 270 of the storage array.

[0061] Each storage unit 270 is used to store one bit of data. Figure 2 FIG. 1 is a structural diagram of a storage unit according to an embodiment of the present invention. Figure 2 As shown, the storage unit 270 includes a switch transistor M and a capacitor C, wherein any one of the source or drain of the switch transistor M is connected to the upper plate of the capacitor, the other of the source or drain of the switch transistor M is connected to the bit line BL, the lower plate of the capacitor C is connected to the power supply terminal, the voltage of the power supply terminal is the reference voltage of the lower plate, and the gate of the switch transistor M is connected to the word line WL. The capacitor C is used to store data, and the switch transistor M is used to turn off or turn on according to the selected state.

[0062] The word line WL of the row where the storage cell is located can be selected by the row decoder 240, and the corresponding switch transistor M in the figure is turned on, and the logic level of the bit line is set to 1, so that the upper plate of the capacitor C is charged, that is, the data "1" is written to the storage cell. Conversely, if 0 is to be written, the logic level of the bit line is set to 0, so that the upper plate of the capacitor C is discharged, that is, the data "0" is written to the storage cell.

[0063] As the integration of chips becomes higher and higher, the feature size of transistor technology is constantly decreasing. The threshold voltage fluctuation of MOS tubes in sense amplifiers and the susceptibility of small voltage signals to noise interference are becoming increasingly prominent, which seriously affects the accuracy of sense amplifiers in sensing data in storage cells. Sensing margin (SM) is an important indicator to measure the performance of sense amplifiers. The calculation formula of sensing margin SM is: SM = Supply dVBL-Required dVBL, where Supply dVBL specifically refers to the voltage difference between the bit line and the complementary bit line at the end of the charge sharing phase, Supply dVBL is also called the supply of sensing margin, Required dVBL refers to the voltage difference required for SA to correctly amplify, and Required dVBL is also called the loss of sensing margin. The loss of sensing margin is caused by the offset voltage and coupling noise caused by the mismatch of the threshold voltage of MOS tubes. Offset Calibration SenseAmplifier (OCSA) adds offset cancellation operation to eliminate the mismatch caused by the threshold voltage of transistors and improve the sensing margin.

[0064] For the convenience of description, the offset cancellation sensitive amplifier is referred to as the sensitive amplifier below. Figure 2 As shown, the sense amplifier 260 is connected to the bit line BL and the complementary bit line BLB, and the bit line BL is connected to the storage unit 270. The working stages of the sense amplifier include a precharge stage, an offset elimination stage, a charge sharing stage, and a sensing amplification stage. In the precharge stage, the sense amplifier drives the voltage of the bit line BL and the voltage on the complementary bit line BLB to the precharge voltage. In the offset elimination stage, the sense amplifier forms a compensation voltage on the bit line BL and the complementary bit line BLB to compensate for the mismatch between the MOS tubes. In the charge sharing stage, the storage unit 270 shares charge with the bit line BL to form a charge sharing voltage on the bit line BL. In the sensing amplification stage, the sense amplifier amplifies the voltage difference between the bit line BL and the complementary bit line BLB.

[0065] Figure 3 1 is a circuit diagram of an amplifier, which is only an example of a sense amplifier and does not limit the structure of the sense amplifier. The sense amplifier includes a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1, a second N-type transistor N2, a first switch unit 110, a second switch unit 120, a third switch unit 130 and a fourth switch unit 140.

[0066] Among them, the gate of the first P-type transistor P1 is connected to the drain of the second P-type transistor P2, the drain of the first P-type transistor P1 is connected to the drain of the first N-type transistor N1, and the source of the first P-type transistor P1 is connected to the first power supply terminal PCS. The gate of the second P-type transistor P2 is connected to the drain of the first P-type transistor P1, the drain of the second P-type transistor P2 is connected to the drain of the second N-type transistor N2, and the source of the second P-type transistor P2 is connected to the first power supply terminal PCS. The drain of the first P-type transistor P1 is connected to the complementary readout bit line SABLB, and the drain of the second P-type transistor P2 is connected to the readout bit line SABL. The gate of the first N-type transistor N1 is connected to the bit line BL, and the source of the first N-type transistor N1 is connected to the second power supply terminal NCS. The gate of the second N-type transistor N2 is connected to the complementary bit line BLB, and the source of the second N-type transistor N2 is connected to the second power supply terminal NCS.

[0067] The first end of the first switch unit 110 is connected to the gate of the first N-type transistor N1, the second end of the first switch unit 110 is connected to the drain of the first N-type transistor N1, and the control end of the first switch unit 110 receives the offset cancellation signal OC. The first end of the second switch unit 120 is connected to the drain of the second N-type transistor N2, the second end of the second switch unit 120 is connected to the gate of the second N-type transistor N2, and the control end of the second switch unit 120 receives the offset cancellation signal OC. The first end of the third switch unit 130 is connected to the bit line BL, the second end of the third switch unit 130 is connected to the drain of the second P-type transistor P2, and the control end of the third switch unit 130 receives the isolation control signal ISO. The first end of the fourth switch unit 140 is connected to the drain of the first P-type transistor P1, the second end of the fourth switch unit 140 is connected to the complementary bit line BLB, and the control end of the fourth switch unit 140 receives the isolation control signal ISO.

[0068] The sense amplifier further includes an equalization module 150, which is connected to the read bit line SABL and / or the complementary read bit line SABLB, and is also connected to a precharge power supply terminal, the voltage of which is a precharge voltage VBLP, which is half of the power supply voltage VDD. The equalization module 150 receives an equalization control signal EQ. Figure 3 In the figure, the equalization module 150 is connected to the read bit line SABL as an example.

[0069] The sense amplifier further includes a third P-type transistor P3 and a seventh N-type transistor N7, wherein the drain of the third P-type transistor P3 is connected to the first power supply terminal PCS of the sense amplifier, the source of the third P-type transistor P3 is connected to the first power supply line, the voltage on the power supply line is the power supply voltage VDD, and the gate of the third P-type transistor P3 receives the first power supply control signal SAP. The drain of the seventh N-type transistor N7 is connected to the second power supply terminal NCS of the sense amplifier, the source of the seventh N-type transistor N7 is connected to the second power supply line, the voltage on the second power supply line is the ground voltage VSS, and the gate of the seventh N-type transistor N7 receives the second power supply control signal SAN.

[0070] Figure 4A and Figure 4B for Figure 3 The working timing diagram of the sense amplifier shown in the figure is shown in the figure. Figure 4A and Figure 4B , in the precharge stage T1, the offset cancellation signal OC is high, and the third N-type transistor N3 is controlled to be in a closed state, so that the bit line BL is connected to the complementary read bit line SABLB. The offset cancellation signal OC is high, and the fourth N-type transistor N4 is controlled to be in a closed state, so that the complementary bit line BLB is connected to the read bit line SABL. The isolation control signal ISO is high, and the fifth N-type transistor N5 is controlled to be in a closed state, so that the bit line BL is connected to the read bit line SABL. The isolation control signal ISO is high, and the sixth N-type transistor N6 is controlled to be in a closed state, so that the complementary bit line BLB is connected to the complementary read bit line SABLB. The first power supply control signal SAP is high, the first power supply terminal PCS is disconnected from the first power supply line, and the first power supply terminal PCS is the precharge voltage VBLP, the second power supply control signal SAN is low, the second power supply terminal NCS is disconnected from the second power supply line, and the second power supply terminal NCS is the precharge voltage VBLP. The word line signal SWL is low, and the word line WL is in a non-open state. Under the control of the equalization control signal EQ, the equalization module 150 connects the read bit line SABL to the precharge power supply terminal, so as to drive the voltage on the bit line BL and the complementary bit line BLB to the precharge voltage VBLP.

[0071] In the offset elimination stage T2, the offset elimination signal OC is at a high level, controlling the third N-type transistor N3 to be in a closed state, and the first N-type transistor N1 to be in a diode connection state. The offset elimination signal OC is at a high level, controlling the fourth N-type transistor N4 to be in a closed state, and the second N-type transistor N2 to be in a diode connection state. The isolation control signal ISO is at a low level, controlling the fifth N-type transistor N5 and the sixth N-type transistor N6 to be in a disconnected state, the first power supply control signal SAP is at a low level, the first power supply terminal PCS is connected to the first power supply line, and the voltage of the first power supply terminal PCS is the power supply voltage VDD. The second power supply control signal SAN is at a high level, the second power supply terminal NCS is connected to the second power supply line, and the voltage of the second power supply terminal NCS is the ground voltage VSS, the word line signal SWL is at a low level, and the word line WL is in a non-open state. By setting in this way, in the offset elimination stage, the sense amplifier forms a compensation voltage on the bit line BL and the complementary bit line BLB to compensate for the mismatch between the MOS tubes.

[0072] In the charge sharing stage T3, the offset cancellation signal OC is at a low level, and the third N-type transistor N3 and the fourth N-type transistor N4 are controlled to be in an open state. The isolation control signal ISO is at a high level, and the fifth N-type transistor N5 and the sixth N-type transistor N6 are controlled to be in a closed state. The first power supply control signal SAP is at a high level, the first power supply terminal PCS is disconnected from the first power supply line, and the first power supply terminal PCS is a precharge voltage VBLP. The second power supply control signal SAN is at a low level, the second power supply terminal NCS is disconnected from the second power supply line, and the second power supply terminal NCS is a precharge voltage VBLP. The word line signal SWL is at a high level, and the word line WL is in an open state. Through such a setting, charge sharing is performed between the storage cell and the bit line BL, and a charge sharing voltage is formed on the bit line BL and the complementary bit line BLB.

[0073] In the sensing amplification stage T4, the offset cancellation signal OC is at a low level, and the third N-type transistor N3 and the fourth N-type transistor N4 are controlled to be in an open state. The isolation control signal ISO is at a high level, and the fifth N-type transistor N5 and the sixth N-type transistor N6 are controlled to be in a closed state. The first power supply control signal SAP is at a low level, the first power supply terminal PCS is connected to the first power supply line, and the voltage of the first power supply terminal PCS is the power supply voltage VDD. The second power supply control signal SAN is at a high level, the second power supply terminal NCS is connected to the second power supply line, and the voltage of the second power supply terminal NCS is the ground voltage VSS. The word line signal SWL is at a high level, and the word line WL is in an open state. By setting it in this way, in the sensing amplification stage, the sense amplifier amplifies the voltage difference between the bit line BL and the complementary bit line BLB.

[0074] However, the sense amplifier has a data preference problem. More specifically, the sense amplifier is more favorable for sensing and amplifying data "1", and is less favorable for sensing and amplifying data "0". Figure 4A and Figure 4B illustrate. Figure 4A For the case where data "1" is read from a storage cell under the most unfavorable environmental conditions, Figure 4A The most unfavorable situation in the medium environment refers to the threshold voltage of the first N-type transistor N1 being less than the threshold voltage of the second N-type transistor N2. Since the threshold voltage of the first N-type transistor N1 is less than the threshold voltage of the second N-type transistor N2, in the offset elimination stage, the voltage of the bit line BL connected to the first N-type transistor N1 will be less than the voltage of the complementary bit line BLB connected to the second N-type transistor N2, that is, the compensation voltage Vos is a negative value. Since the data "1" is stored in the storage cell, the voltage in the storage cell is greater than the precharge voltage, and the voltage difference between the storage cell and the bit line BL is relatively large. After the charge sharing stage under the voltage drive on the storage cell, the voltage difference between the bit line BL and the complementary bit line BLB is relatively large, and the sensing margin SM is also larger, which is conducive to accurate data reading.

[0075] Figure 4B In the worst case, the data "0" is read from the memory cell. Figure 4B The most unfavorable situation in the medium environment refers to the threshold voltage of the first N-type transistor N1 being greater than the threshold voltage of the second N-type transistor N2. Since the threshold voltage of the first N-type transistor N1 is greater than the threshold voltage of the second N-type transistor N2, in the offset elimination stage, the voltage of the bit line BL connected to the first N-type transistor N1 will be greater than the voltage of the complementary bit line BLB connected to the second N-type transistor N2, that is, the compensation voltage Vos is a positive value. Since the data "0" is stored in the storage cell, the voltage in the storage cell is less than the precharge voltage, and the voltage difference between the storage cell and the bit line BL is relatively small. After the charge sharing stage under the voltage drive on the storage cell, the voltage difference between the bit line BL and the complementary bit line BLB is relatively small, and the sensing margin SM is also smaller. In the sensing amplification stage, data flipping is likely to occur, which is not conducive to accurate data reading.

[0076] In addition, although the offset cancellation operation of the sense amplifier can eliminate the mismatch caused by the threshold voltage of the transistor, in the memory, the mismatch of the transistors in different sense amplifiers, the electrical signal noise, the parasitic capacitance of the bit line and the parasitic resistance of the bit line are all random, which results in different mismatches faced by all sense amplifiers. This still results in the mismatch of some sense amplifiers being unable to be eliminated.

[0077] Some aspects of the embodiments of the present disclosure relate to the above considerations. The following is an example introduction of the solution in combination with some embodiments of the present disclosure.

[0078] like Figure 5 As shown, some embodiments of the present disclosure provide a control method for a sense amplifier, wherein the sense amplifier is connected to a bit line and a complementary bit line, the bit line is connected to a storage unit, and the sense amplifier includes a first power supply terminal and a second power supply terminal. The control method specifically includes the following steps:

[0079] S101, in the pre-charging stage, controlling the first power supply terminal and the second power supply terminal to connect to the pre-charging voltage, and controlling the sense amplifier to drive the voltage on the bit line and the complementary bit line to the pre-charging voltage.

[0080] In this step, the sense amplifier includes an equalization module, and the equalization module is connected to the precharge power supply terminal, and the voltage of the precharge power supply terminal is the precharge voltage. The first power supply terminal and the second power supply terminal are connected to the precharge voltage, so that the voltage of the first power supply terminal and the voltage of the second power supply terminal are both the precharge voltage. When the voltage of the first power supply terminal and the voltage of the second power supply terminal are both the precharge voltage, the equalization module connects the bit line and the complementary bit line to the precharge power supply terminal, and drives the voltage on the bit line and the complementary bit line to the precharge voltage.

[0081] S102: In the offset elimination phase, the first power supply terminal is controlled to be connected to the power supply voltage, the second power supply terminal is controlled to be connected to the ground voltage, and the sense amplifier is controlled to form a compensation voltage on the bit line and the complementary bit line. The duration of the offset elimination phase is the optimal offset elimination duration, and the sensing margin of the sense amplifier is the maximum value under the optimal offset elimination duration.

[0082] In this step, the first power supply terminal is controlled to be connected to the power supply voltage so that the voltage of the first power supply terminal is the power supply voltage, and the second power supply terminal is controlled to be connected to the ground voltage so that the voltage of the second power supply terminal is the ground voltage. When the voltage of the first power supply terminal is the power supply voltage and the voltage of the second power supply terminal is the ground voltage, the sense amplifier is controlled to form a compensation voltage on the bit line and the complementary bit line.

[0083] by Figure 3 The structure of the sense amplifier shown in FIG. 1 is an example to illustrate the process of forming the compensation voltage. Figure 3 As shown, by controlling the first switch unit 110 and the second switch unit 120 to be closed, and the third switch unit 130 and the fourth switch unit 140 to be open, the sense amplifier forms a compensation voltage on the bit line and the complementary bit line.

[0084] The duration of the offset elimination phase will affect the magnitude of the compensation voltage formed on the bit line and the complementary bit line, and thus will affect the magnitude of the sensing margin on the bit line and the complementary bit line. Figure 6As shown, if the duration of the offset elimination phase is relatively long, for example, tOC3, a relatively large compensation voltage Vos3 will be formed on the bit line and the complementary bit line, that is, over-compensation. If the duration of the offset elimination phase is relatively short, for example, tOC1, a relatively small compensation voltage Vos1 will be formed on the bit line and the complementary bit line, that is, under-compensation. By making the duration of the offset elimination phase the optimal offset elimination duration, for example, making the duration of the offset elimination phase tOC2, the compensation voltage Vos2 on the bit line and the complementary bit line is optimized, thereby ensuring that the sensing margin on the bit line and the complementary bit line is maximized.

[0085] Among them, the duration of the offset elimination phase refers to the time from the start of the offset elimination phase to the end of the offset elimination phase. The third moment when the first power supply terminal switches from the pre-charge voltage to the power supply voltage during the offset elimination phase or the fourth moment when the second power supply terminal switches from the pre-charge voltage to the ground voltage during the offset elimination phase is used as the start time of the offset elimination phase. It can also be any moment between the third moment and the fourth moment as the start time of the offset elimination phase. Among them, the third moment is the moment when the voltage of the first power supply terminal changes from the pre-charge voltage to the power supply voltage, it can also be the moment when the voltage of the first power supply terminal is the power supply voltage, and it can be the moment from the start of switching to the completion of switching. The fourth moment is defined similarly and will not be repeated here. The size relationship between the third moment and the fourth moment is not limited here.

[0086] The fifth moment when the first power supply terminal switches from the power supply voltage to the pre-charge voltage in the offset elimination stage, or the sixth moment when the second power supply terminal switches from the ground voltage to the pre-charge voltage in the offset elimination stage is the termination moment of the offset elimination stage. It can also be any moment between the fifth moment and the sixth moment as the termination moment of the offset elimination stage. Among them, the fifth moment is the moment when the voltage of the second power supply terminal changes from the pre-charge voltage to the ground voltage, it can also be the moment when the voltage of the second power supply terminal is the ground voltage, and it can also be the moment from the beginning of the switch to the completion of the switch. The definition of the sixth moment is similar and will not be repeated here. The size relationship between the fifth moment and the sixth moment is not limited here.

[0087] At the same time, the first switch unit 110 and the second switch unit 120 are closed at the third moment, the fourth moment, or any time between the third moment and the fourth moment, and are opened at the fifth moment, the sixth moment, or any time between the fifth moment and the sixth moment, so that the sense amplifier forms a compensation voltage on the bit line and the complementary bit line. In an ideal case, the third moment is equal to the fourth moment, and the fifth moment is equal to the sixth moment.

[0088] S103 , in the charge sharing stage, controlling the first power supply terminal and the second power supply terminal to be connected to the precharge voltage, the memory cell and the bit line share charge, and forming a charge sharing voltage on the bit line and the complementary bit line.

[0089] The first power supply terminal and the second power supply terminal are controlled to be connected to the precharge voltage, so that the voltage of the first power supply terminal and the voltage of the second power supply terminal are both the precharge voltage, the word line is turned on, the switch transistor M in the memory cell is turned on, the memory cell capacitor C and the bit line share charge, and a charge sharing voltage is formed on the bit line and the complementary bit line. Since the duration of the offset elimination phase is the optimal offset elimination duration, the compensation voltage formed on the bit line and the complementary bit line in the offset elimination phase is optimal, and then the bit line shares charge with the memory cell, and the charge sharing voltage is formed on the bit line and the complementary bit line. At the end of the charge sharing phase, the voltage difference between the bit line and the complementary bit line is the largest, that is, the supply amount Supply dVBL of the sensing margin is the largest, so that the sensing margin is maximized.

[0090] S104, in the sensing and amplification stage, controlling the first power supply terminal to be connected to the power supply voltage, controlling the second power supply terminal to be connected to the ground voltage, and the time when the first power supply terminal is connected to the power supply voltage is later than the time when the second power supply terminal is connected to the ground voltage, and controlling the sense amplifier to amplify the voltage difference between the bit line and the complementary bit line.

[0091] Among them, the first moment when the first power supply terminal switches from the pre-charge voltage to the power supply voltage during the charge sharing stage can be used as the end moment of the charge sharing stage. The second moment when the second power supply terminal switches from the pre-charge voltage to the ground voltage during the charge sharing stage can also be used as the end moment of the charge sharing stage. It can also be any moment between the first moment and the second moment as the end moment of the charge sharing stage. Among them, the first moment can be the moment when the voltage of the first power supply terminal switches from the pre-charge voltage to the power supply voltage, it can also be the moment when the voltage of the first power supply terminal becomes the power supply voltage, or it can be the moment from the beginning to the completion of the switching. The second moment can be the moment when the voltage of the second power supply terminal switches from the pre-charge voltage to the ground voltage, it can also be the moment when the voltage of the second power supply terminal becomes the ground voltage, or it can be the moment from the beginning to the completion of the switching.

[0092] The first power supply terminal is controlled to be connected to the power supply voltage so that the voltage of the first power supply terminal is the power supply voltage, and the second power supply terminal is controlled to be connected to the ground voltage so that the voltage of the second power supply terminal is the ground voltage.

[0093] The first moment when the first power supply terminal is connected to the power supply voltage is later than the second moment when the second power supply terminal is connected to the ground voltage, so that the second power supply terminal first pulls down the bit line voltage and the complementary bit line voltage, and then the first power supply terminal and the second power supply terminal jointly drive the bit line and the complementary bit line. When the second power supply terminal is connected to the ground voltage, the voltage on the bit line turns on the transistor connected to the second power supply terminal and the bit line at the same time, and the voltage on the complementary bit line turns on the transistor connected to the second power supply terminal and the complementary bit line at the same time. The second power supply terminal pulls down the voltage on the bit line and the complementary bit line, which can adjust the voltage difference between the bit line and the complementary bit line at the end of the charge sharing phase, that is, the sensing margin on the bit line and the complementary bit line can be adjusted.

[0094] More specifically, when data "1" is stored in the memory cell, the second power supply terminal pulls down the voltage on the bit line and the complementary bit line. In the most unfavorable environmental condition, the threshold voltage of the first N-type transistor N1 is less than the threshold voltage of the second N-type transistor N2, the pull-down speed of the bit line voltage is greater than the pull-down speed of the complementary bit line voltage, and the voltage difference between the bit line and the complementary bit line at the end of the charge sharing phase becomes smaller, thereby reducing the sensing margin on the bit line and the complementary bit line.

[0095] When storing data "0" in the memory cell, the second power supply terminal pulls down the voltage on the bit line and the complementary bit line. In the most unfavorable environment, the threshold voltage of the first N-type transistor N1 is greater than the threshold voltage of the second N-type transistor N2, and the pull-down speed of the bit line voltage is less than the pull-down speed of the complementary bit line voltage. The voltage difference between the bit line and the complementary bit line at the end of the charge sharing phase becomes larger, so that the sensing margin on the bit line and the complementary bit line becomes larger. In this way, the difference between the sensing margin when storing data "1" in the memory cell and the sensing margin when storing data "0" in the memory cell can be reduced, reducing the data preference of the sense amplifier.

[0096] In the above technical solution, the sense amplifier includes a pre-charging stage, an offset elimination stage, a charge sharing stage and a sensing amplification stage. The duration of the offset elimination stage is the optimal offset elimination duration. Under the optimal offset elimination duration, the sensing margin of the sense amplifier is the maximum value, which can eliminate most of the mismatch noise and other noises of the sense amplifier. In the sensing amplification stage, the moment when the first power supply terminal is connected to the power supply voltage is controlled to be later than the moment when the second power supply terminal is connected to the ground voltage, so that the sensing margin on the bit line and the complementary bit line can be adjusted to reduce the data preference of the sense amplifier.

[0097] Below Figure 3 The structure of the sensitive amplifier shown in the figure illustrates the process of the control method provided by the present application. Figure 7 As shown, Figure 4AThe difference is that, in the sensing amplification stage, the start time of the first power control signal SAP being at a low level is later than the start time of the second power control signal SAN being at a high level, and compared with the moment when the first power terminal PCS is connected to the first power line, the moment when the second power terminal NCS is connected to the second power line is earlier by △t1. At this time, the first N-type transistor N1 is turned on under the control of the bit line voltage. In the most unfavorable environmental condition, the threshold voltage of the first N-type transistor N1 is less than the threshold voltage of the second N-type transistor N2, the pull-down speed of the bit line voltage is greater than the pull-down speed of the complementary bit line voltage, and the voltage difference between the bit line BL and the complementary bit line BLB at the end of the charge sharing stage becomes smaller, so that the sensing margin on the bit line BL and the complementary bit line BLB becomes smaller.

[0098] The following provides an implementation method for obtaining the optimal offset elimination duration, specifically:

[0099] S201: Generate multiple first control scenarios.

[0100] Each first control scenario includes a duration parameter of a pre-charging phase, a duration parameter of an offset elimination phase, a duration parameter of a charge sharing phase, and a duration parameter of a sensing amplification phase.

[0101] The duration parameters of the pre-charging phase, the offset elimination phase, the charge sharing phase and the sensing amplification phase are all related to the moment when the first power supply terminal is connected to the corresponding voltage and the moment when the second power supply terminal is connected to the corresponding voltage.

[0102] Here, the duration parameters of the offset elimination phase and the duration parameters of the charge sharing phase are used as examples. The third moment when the first power supply terminal switches from the pre-charge voltage to the power supply voltage in the offset elimination phase or the fourth moment when the second power supply terminal switches from the pre-charge voltage to the ground voltage in the offset elimination phase is used as the start time of the offset elimination phase. It can also be any moment between the third moment and the fourth moment as the start time of the offset elimination phase.

[0103] The fifth moment when the first power supply terminal switches from being connected to the power supply voltage to being connected to the pre-charge voltage in the offset elimination phase, or the sixth moment when the second power supply terminal switches from being connected to the ground voltage to being connected to the pre-charge voltage in the offset elimination phase is the end time of the offset elimination phase. Alternatively, any moment between the fifth moment and the sixth moment may be used as the end time of the offset elimination phase.

[0104] The end time of the offset cancellation phase is the start time of the charge sharing phase. The start time of the offset cancellation phase is the end time of the pre-charge phase.

[0105] The first moment when the first power supply terminal switches from the pre-charge voltage to the power supply voltage during the charge sharing phase is used as the end time of the charge sharing phase. The second moment when the second power supply terminal switches from the pre-charge voltage to the ground voltage during the charge sharing phase is used as the end time of the charge sharing phase. Any moment between the first moment and the second moment may also be used as the end time of the charge sharing phase.

[0106] The end time of the charge sharing phase is the start time of the sensing amplification phase.

[0107] The duration parameters of the offset elimination phase in any two first control scenarios are different, the duration parameters of the pre-charging phase in any two first control scenarios are the same, the duration parameters of the charge sharing phase in any two first control scenarios are the same, and the duration parameters of the sensing amplification phase in any two first control scenarios are the same.

[0108] S202: Acquire a first sensing margin of the sense amplifier in a first control scenario, and use a duration parameter of an offset elimination phase corresponding to a maximum sensing margin among a plurality of first sensing margins as an optimal offset elimination duration.

[0109] Acquiring a first sensing margin of the sense amplifier in the first control scenario refers to obtaining a sensing margin by testing the sense amplifier using the duration parameters of each stage in the first control scenario as test conditions.

[0110] More specifically, a condition that is not conducive to reading out the first data is set, and the duration parameters of each stage under the first control scenario are used as test conditions to test the sense amplifier to obtain the second sensing margin SM2. A condition that is not conducive to reading out the second data is set, and the duration parameters of each stage under the first control scenario are used as test conditions to test the sense amplifier to obtain the third sensing margin SM3, and the sum of the second sensing margin SM2 and the third sensing margin SM3 is calculated as the first sensing margin.

[0111] The upper plate of the capacitor is connected to the transistor. The first data is data "1", that is, the voltage of the upper plate of the capacitor in the storage unit is greater than the voltage of the lower plate of the capacitor. The second data is data "0", that is, the voltage of the upper plate of the capacitor in the storage unit is less than the voltage of the lower plate of the capacitor.

[0112] In the technical solution, a sensing margin under a condition that is not conducive to reading out the first data and a sensing margin under a condition that is not conducive to reading out the second data are obtained, and the sum of the two sensing margins is used as the sensing margin in the first control scenario. Considering the situation that two types of data are stored in the target storage area, the obtained sensing margin is more accurate.

[0113] In order to obtain a second sensing margin under a condition that is unfavorable for reading out the first data in a first control scenario, a plurality of first scanning voltages greater than a lower plate reference voltage of the memory cell are generated.

[0114] For each first scanning voltage, the voltage of the storage cell in the target storage area is adjusted according to the first scanning voltage, and the duration of the offset elimination phase of the sensitive amplifier is controlled to be the duration parameter under the first control scenario, and the data read error rate of the storage cell in the target storage area is counted to obtain a first mapping relationship between multiple first scanning voltages and the read error rate under each first scanning voltage.

[0115] More specifically, taking a first scanning voltage as an example, the lower plate voltage of all storage cells in the target storage area is adjusted to the first scanning voltage. The duration parameters of each stage under the first control scenario are used as test conditions, and the duration of the offset elimination stage of the sense amplifier is set to the duration parameter of the offset elimination stage under the first control scenario. The sense amplifier in the target storage area is tested, data is read from the bit line in the target storage area, and the data read error rate of the storage cells in the target storage area is counted to obtain Figure 8 A point in the graph is selected, for example, point 1. The horizontal axis of point 1 is the lower plate voltage, and the vertical axis of point 1 is the data read error rate.

[0116] By performing the above operation on each first scanning voltage, point 2, point 3, ... point 6 can be obtained, that is, a first mapping relationship X1 between multiple first scanning voltages and the readout error rate at each first scanning voltage is obtained.

[0117] The second sensing margin SM2 under the first control scenario is calculated according to the first mapping relationship. More specifically, the lower plate voltage range corresponding to when the readout error rate is less than the preset threshold is calculated according to the first mapping relationship, and the second sensing margin is calculated according to the lower plate voltage range. The first lower plate voltage corresponding to the preset threshold in the first mapping relationship is obtained, and the first difference between the first lower plate voltage corresponding to the preset threshold and the lower plate reference voltage is calculated, and the first difference is used as the lower plate voltage range corresponding to when the readout error rate is less than the preset threshold.

[0118] In the above technical solution, by scanning the lower plate voltage of the storage unit, the statistical data read error rate is counted to obtain the data read error rate under different storage unit voltages, and then the second mapping relationship is obtained, and the second sensing margin is obtained according to the second mapping relationship.

[0119] In order to obtain a third sensing margin under a condition that is unfavorable for reading the second data in a first control scenario, a plurality of second scanning voltages that are smaller than the bottom plate voltage of the memory cell are generated.

[0120] For each second scanning voltage, the voltage of the storage cell in the target storage area is adjusted according to the second scanning voltage, and the duration of the offset elimination phase of the sensitive amplifier is controlled to be the duration parameter under the first control scenario, and the data read error rate of the storage cell in the target storage area is counted to obtain a second mapping relationship between multiple second scanning voltages and the read error rate under each second scanning voltage.

[0121] The process of obtaining points 7 to 12 to obtain the second mapping relationship between the plurality of second scanning voltages and the read error rate at each second scanning voltage is similar to the process of obtaining the first mapping relationship, which will not be repeated here.

[0122] The third sensing margin SM3 is obtained by calculation according to the second mapping relationship. More specifically, the lower plate voltage range corresponding to when the readout error rate is less than the preset threshold is calculated according to the second mapping relationship, and the third sensing margin is obtained according to the lower plate voltage range. The second lower plate voltage corresponding to the preset threshold in the second mapping relationship is obtained, and the second difference between the lower plate voltage corresponding to the preset threshold and the lower plate reference voltage is calculated, and the second difference is used as the lower plate voltage range corresponding to when the readout error rate is less than the preset threshold.

[0123] In the above technical solution, by scanning the lower plate voltage of the storage unit, the statistical data read error rate is counted to obtain the data read error rate under the lower plate voltage of different storage units, and then the second mapping relationship is obtained, and the third sensing margin is obtained according to the second mapping relationship.

[0124] After obtaining the first sensing margin of the sense amplifier in the first control scenario, the duration parameter of the offset elimination phase corresponding to the maximum sensing margin among the plurality of first sensing margins is used as the optimal offset elimination duration. Fig. 9 As shown, the first mapping relationship and the second mapping relationship of the sensitive amplifier in three first control scenarios are obtained. The three first control scenarios are the first control scenario Ca11, the first control scenario Ca12 and the first control scenario Ca13. The duration parameter of the offset elimination phase in the first control scenario Ca11 is tOC1, the duration parameter of the offset elimination phase in the first control scenario Ca12 is tOC2, and the duration parameter of the offset elimination phase in the first control scenario Ca13 is tOC3. More specifically, the first mapping relationship X1 and the second mapping relationship X2 of the first control scenario Ca11 are obtained, and the first sensing margin of the first control scenario Ca11 is calculated according to the first mapping relationship X1 and the second mapping relationship X2. Similarly, the first sensing margin of the first control scenario Ca11 to the first sensing margin of the first control scenario Ca13 are obtained. The duration parameter of the offset elimination phase corresponding to the largest first sensing margin is selected from the three first sensing margins as the optimal offset elimination duration.

[0125] In the above technical solution, the first sensing margin under each first control scenario is obtained by testing the storage cells and the sensitive amplifiers in the target storage area, and then the duration parameter of the offset elimination phase under the largest sensing margin is selected from multiple first sensing margins as the optimal offset elimination duration, so that the optimal offset elimination duration can weaken or eliminate the mismatch noise and other noise of most sensitive amplifiers in the memory, thereby improving the data readout accuracy.

[0126] The following provides a method for obtaining an optimal start time for connecting the first power terminal to the power voltage and a time for connecting the second power terminal to the ground voltage.

[0127] S301: Generate multiple second control scenarios.

[0128] Each second control scenario includes a duration parameter of a pre-charging phase, a duration parameter of an offset elimination phase, a duration parameter of a charge sharing phase, and a duration parameter of a sensing amplification phase.

[0129] The duration parameters of the four stages have been explained in detail in S201 and will not be repeated here.

[0130] The duration parameter of the offset elimination phase of each second control scenario is the optimal offset elimination duration, and the first moment in the same second control scenario is later than the second moment. The first moments in any two second control scenarios are different or the second moments in any two second control scenarios are different.

[0131] The duration parameters of the pre-charging phases in any two second control scenarios are the same, and the starting moments of the charge sharing phases in any two second control scenarios are the same.

[0132] S302, obtaining a sensing margin difference of the sense amplifier in a second control scenario, obtaining a first moment corresponding to a minimum sensing margin difference among multiple sensing margin differences as an optimal first moment, and obtaining a second moment corresponding to the minimum sensing margin difference as an optimal second moment.

[0133] Wherein, obtaining the sensing margin difference of the sense amplifier in the second control scenario means that, using the duration parameters of each stage in the second control scenario as test conditions, the sense amplifier in the target storage area is tested when the condition is not conducive to reading the first data to obtain a fourth sensing margin. Using the duration parameters of each stage in the second control scenario as test conditions, the sense amplifier in the target storage area is tested when the condition is not conducive to reading the second data to obtain a fifth sensing margin. The difference between the fourth sensing margin SM4 and the fifth sensing margin SM5 is calculated as the sensing margin difference.

[0134] More specifically, when the condition is not favorable for reading the first data, and the duration parameters of each stage in the second control scenario are used as test conditions, the sense amplifier is tested to obtain a fourth sensing margin SM4. When the condition is not favorable for reading the second data, and the duration parameters of each stage in the second control scenario are used as test conditions, the sense amplifier is tested to obtain a fifth sensing margin SM5, and the difference between the fourth sensing margin SM4 and the fifth sensing margin SM5 is calculated as the sensing margin difference.

[0135] In order to obtain a fourth sensing margin SM4 under a second control scenario when the setting is not favorable for reading the first data condition, a plurality of third scanning voltages greater than the bottom plate reference voltage of the memory cell are generated.

[0136] For each third scanning voltage, the lower plate voltage of the storage unit in the target storage area is adjusted according to the third scanning voltage, and the duration of the offset elimination phase of the sensitive amplifier is controlled to be the optimal offset elimination duration, the moment when the first power supply terminal switches from the pre-charge voltage to the power supply voltage during the charge sharing phase is controlled to be the first moment under the second control scenario, and the moment when the second power supply terminal switches from the pre-charge voltage to the ground voltage during the charge sharing phase is controlled to be the second moment under the second control scenario, the sensitive amplifier in the target storage area is tested, the data read error rate of the storage unit in the target storage area is counted, and a third mapping relationship between multiple third scanning voltages and the read error rate under each third scanning voltage is obtained.

[0137] The fourth sensing margin SM4 in the second control scenario is calculated according to the third mapping relationship. More specifically, the lower plate voltage range corresponding to when the readout error rate is less than the preset threshold is calculated according to the third mapping relationship, and the fourth sensing margin is calculated according to the lower plate voltage range. The third lower plate voltage corresponding to the preset threshold in the third mapping relationship is obtained, and the third difference between the third lower plate voltage corresponding to the preset threshold and the lower plate reference voltage is calculated, and the third difference is used as the lower plate voltage range corresponding to when the readout error rate is less than the preset threshold.

[0138] In the above technical solution, by scanning the voltage of the memory cell and counting the statistical data read error rate, the data read error rate under different memory cell voltages is obtained, and then the third mapping relationship is obtained, and the fourth sensing margin is obtained according to the third mapping relationship.

[0139] In order to obtain a fifth sensing margin when the setting is not favorable for reading the second data condition under a second control scenario, a plurality of fourth scanning voltages smaller than the bottom plate voltage of the memory cell are generated.

[0140] For each fourth scanning voltage, the voltage in the storage unit in the target storage area is adjusted according to the fourth scanning voltage, and the duration of the offset elimination phase of the sensitive amplifier is controlled to be the optimal offset elimination duration, the moment when the first power supply terminal switches from the pre-charge voltage to the power supply voltage during the charge sharing phase is controlled to be the first moment under the second control scenario, and the moment when the second power supply terminal switches from the pre-charge voltage to the ground voltage during the charge sharing phase is controlled to be the second moment under the second control scenario, the sensitive amplifier in the target storage area is tested, the data read error rate of the storage unit in the target storage area is counted, and a fourth mapping relationship between multiple fourth scanning voltages and the read error rate under each fourth scanning voltage is obtained.

[0141] The fifth sensing margin SM5 is obtained by calculation according to the fourth mapping relationship. More specifically, the upper plate voltage range corresponding to the readout error rate is less than the preset threshold is calculated according to the fourth mapping relationship, and the fifth sensing margin is obtained according to the upper plate voltage range. The fourth lower plate voltage corresponding to the preset threshold in the fourth mapping relationship is obtained, and the fourth difference between the lower plate voltage corresponding to the preset threshold and the lower plate reference voltage is calculated, and the fourth difference is used as the lower plate voltage range corresponding to the readout error rate is less than the preset threshold.

[0142] In the above technical solution, by scanning the voltage of the memory cell and counting the statistical data read error rate, the data read error rate under different memory cell voltages is obtained, and then the fourth mapping relationship is obtained, and the fifth sensing margin is obtained according to the fourth mapping relationship.

[0143] After obtaining the sensing margin difference of the sense amplifier in the second control scenario, the first moment corresponding to the minimum sensing margin difference among the multiple sensing margin differences is obtained as the best first moment, and the second moment corresponding to the minimum sensing margin difference is obtained as the best second moment. Fig.10 As shown, the third mapping relationship X3 and the fourth mapping relationship X4 of the sensitive amplifier in five second control scenarios are obtained. The five second control scenarios are the first second control scenario Ca21, the second second control scenario Ca22, the third second control scenario Ca23, the fourth second control scenario Ca24 and the fifth second control scenario Ca25. The first moments and the second moments corresponding to the five second control scenarios are shown in Table 1.

[0144] Table 1

[0145] Ca21 Ca22 Ca23 Ca24 Ca25 First Moment t11 t12 t13 t11 t11 Second Moment t21 t21 t21 t22 t23

[0146] More specifically, the third mapping relationship X3 and the fourth mapping relationship X4 of the first second control scenario Ca21 are obtained, and the sensing margin difference of the first second control scenario Ca11 is calculated according to the third mapping relationship X3 and the fourth mapping relationship X4. Similarly, the sensing margin difference of the first second control scenario Ca21 to the sensing margin difference of the fifth second control scenario Ca25 is obtained. The second moments of the first second control scenario Ca21 to the third second control scenario Ca23 are the same, and the first moments are different. The first moment corresponding to the smallest sensing margin difference among the three sensing margin differences of the first second control scenario Ca21 to the third second control scenario Ca23 is selected as the best first moment. The first moment of the first second control scenario Ca21, the fourth second control scenario Ca24 and the fifth second control scenario Ca25 is the same, and the second moment is different. The second moment corresponding to the smallest sensing margin difference among the three sensing margin differences of the first second control scenario Ca21, the fourth second control scenario Ca24 to the fifth second control scenario Ca25 is selected as the best second moment.

[0147] In the above technical solution, the storage cells and the sense amplifiers in the target storage area are tested to obtain the sensing margin difference under each second control scenario, and then the first moment under the smallest sensing margin is selected from multiple sensing margin differences as the best first moment or the second moment as the best second moment, and the best first moment is used as the moment when the first power supply terminal switches from the pre-charge voltage to the power supply voltage during the charge sharing stage, and the best second moment is the moment when the second power supply terminal switches from the pre-charge voltage to the ground voltage during the charge sharing stage, thereby effectively eliminating the data preference of the sense amplifier.

[0148] Some embodiments of the present disclosure provide a control method for a sense amplifier, specifically including:

[0149] S201. In the pre-charging stage, the first power supply terminal and the second power supply terminal are controlled to be connected to the pre-charging voltage, and the sense amplifier is controlled to drive the voltage on the bit line and the complementary bit line to the pre-charging voltage.

[0150] S202: In the offset elimination phase, the first power supply terminal is controlled to be connected to the power supply voltage, the second power supply terminal is controlled to be connected to the ground voltage, and the sense amplifier is controlled to form a compensation voltage on the bit line and the complementary bit line. The duration of the offset elimination phase is the optimal offset elimination duration, and the sensing margin SM of the sense amplifier is the maximum value under the optimal offset elimination duration.

[0151] S203 , in the charge sharing stage, controlling the first power supply terminal and the second power supply terminal to be connected to the precharge voltage, the memory cell and the bit line share charge, and forming a charge sharing voltage on the bit line and the complementary bit line.

[0152] S204, in the sensing and amplification stage, the first power supply terminal is controlled to be connected to the power supply voltage, and the second power supply terminal is controlled to be connected to the ground voltage, and the moment when the first power supply terminal is connected to the power supply voltage is the optimal first moment, and the moment when the second power supply terminal is connected to the ground voltage is the optimal second moment, and the sense amplifier is controlled to amplify the voltage difference between the bit line and the complementary bit line.

[0153] In the above technical solution, the sense amplifier includes a pre-charging stage, an offset elimination stage, a charge sharing stage and a sensing amplification stage. The duration of the offset elimination stage is the optimal offset elimination duration. Under the optimal offset elimination duration, the sensing margin of the sense amplifier is the maximum value, which can eliminate most of the mismatch noise and other noises of the sense amplifier. In the sensing amplification stage, the moment when the first power supply terminal is connected to the power supply voltage is the optimal first moment, and the moment when the second power supply terminal is connected to the ground voltage is the optimal second moment. The sensing margin on the bit line and the complementary bit line can be adjusted to minimize the data preference of the sense amplifier.

[0154] Some embodiments of the present disclosure provide a memory, including: a storage unit, a sense amplifier and a controller, wherein the storage unit is connected to a bit line, the sense amplifier is connected to the bit line, the controller is connected to the sense amplifier, and the controller is used to implement the method involved in the above embodiments.

[0155] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0156] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A control method for a sensitive amplifier, characterized in that: The sense amplifier is connected to a bit line and a complementary bit line, the bit line is connected to a storage unit, the sense amplifier includes a first power supply terminal and a second power supply terminal, and the method includes: In the pre-charging stage, the first power supply terminal and the second power supply terminal are controlled to be connected to the pre-charging voltage, and the sense amplifier is controlled to drive the voltage on the bit line and the complementary bit line to the pre-charging voltage; In the offset elimination phase, the first power supply terminal is controlled to be connected to the power supply voltage, the second power supply terminal is controlled to be connected to the ground voltage, and the sense amplifier is controlled to form a compensation voltage on the bit line and the complementary bit line; wherein the duration of the offset elimination phase is an optimal offset elimination duration, and the sensing margin of the sense amplifier is a maximum value under the optimal offset elimination duration; In the charge sharing stage, the first power supply terminal and the second power supply terminal are controlled to be connected to the precharge voltage, the storage unit and the bit line perform charge sharing, and a charge sharing voltage is formed on the bit line and the complementary bit line; In the sensing and amplification stage, the first power supply terminal is controlled to be connected to the power supply voltage, and the second power supply terminal is controlled to be connected to the ground voltage, and the time when the first power supply terminal is connected to the power supply voltage is later than the time when the second power supply terminal is connected to the ground voltage, and the sense amplifier is controlled to amplify the voltage difference between the bit line and the complementary bit line.

2. The control method according to claim 1, characterized in that: The control method further comprises: generating a plurality of first control scenarios, wherein each of the first control scenarios comprises a duration parameter of the offset elimination phase, and the duration parameters of the offset elimination phase in any two of the first control scenarios are different; A first sensing margin of the sense amplifier in each of the first control scenarios is obtained; and a duration parameter of an offset elimination phase corresponding to a maximum sensing margin among a plurality of first sensing margins is used as an optimal offset elimination duration.

3. The control method according to claim 2, characterized in that: Acquiring a first sensing margin of the sense amplifier in the first control scenario specifically includes: acquiring a second sensing margin of a sense amplifier in a target storage area under the first control scenario when a condition unfavorable for reading out the first data is set; acquiring a third sensing margin of the sense amplifier in the target storage area under the first control scenario when a condition unfavorable for reading out the second data is set; A sum of the second sensing margin and the third sensing margin is calculated as the first sensing margin.

4. The control method according to claim 3, characterized in that: Acquiring a second sensing margin of the sense amplifier in the target storage area under the first control scenario when a condition unfavorable for reading the first data is set specifically includes: generating a plurality of first scanning voltages greater than a reference voltage of a lower plate of a memory cell; For each first scanning voltage, the lower plate voltage of the storage unit in the target storage area is adjusted according to the first scanning voltage, and the duration of the offset elimination phase of the sense amplifier is controlled to be the duration parameter in the first control scenario, and the read error rate of the data of the storage unit in the target storage area is counted to obtain a first mapping relationship between a plurality of the first scanning voltages and the read error rate under each of the first scanning voltages; The second sensing margin is obtained by calculation according to the first mapping relationship.

5. The control method according to claim 3, characterized in that: Acquiring a third sensing margin of the sense amplifier in the target storage area under the first control scenario when a condition that is unfavorable for reading the second data is set specifically includes: generating a plurality of second scanning voltages less than a reference voltage of a lower plate of a memory cell; For each of the second scanning voltages, the lower plate voltage of the storage unit in the target storage area is adjusted according to the second scanning voltage, and the duration of the offset elimination phase of the sense amplifier is controlled to be the duration parameter in the first control scenario, and the read error rate of the data of the storage unit in the target storage area is counted to obtain a second mapping relationship between multiple second scanning voltages and the read error rate under each of the second scanning voltages; The third sensing margin is obtained by calculation according to the second mapping relationship.

6. The control method according to claim 1, characterized in that: The control method further comprises: Generate multiple second control scenarios, wherein each of the second control scenarios includes a duration parameter of the offset elimination phase, a first moment when the first power supply terminal switches from being connected to the pre-charge voltage to being connected to the power supply voltage during the charge sharing phase, and a second moment when the second power supply terminal switches from being connected to the pre-charge voltage to being connected to the ground voltage during the charge sharing phase; the duration parameter of the offset elimination phase of each second control scenario is the optimal offset elimination duration, the first moment in the same second control scenario is later than the second moment, the first moments in any two of the second control scenarios are different, or the second moments in any two of the second control scenarios are different; Acquire a sensing margin difference of the sense amplifier in each second control scenario; use a first moment corresponding to a minimum sensing margin difference among the plurality of sensing margin differences as an optimal first moment for the first power supply terminal to switch from the pre-charge voltage to the power supply voltage during the charge sharing phase, and use a second moment corresponding to the minimum sensing margin difference as an optimal second moment for the second power supply terminal to switch from the pre-charge voltage to the ground voltage during the charge sharing phase; Correspondingly, controlling the first power supply terminal to connect to the power supply voltage, controlling the second power supply terminal to connect to the ground voltage, and the first power supply terminal to connect to the power supply voltage later than the second power supply terminal to connect to the ground voltage, and controlling the sense amplifier to amplify the voltage difference between the bit line and the complementary bit line, specifically includes: The first power supply terminal is controlled to switch from the pre-charge voltage to the power supply voltage during the charge sharing phase as the optimal first moment, the second power supply terminal is controlled to switch from the pre-charge voltage to the ground voltage during the charge sharing phase as the optimal second moment, and the sensitive amplifier is controlled to amplify the voltage difference between the bit line and the complementary bit line.

7. The control method according to claim 6, characterized in that: Acquiring a fourth sensing margin of the sense amplifier in each second control scenario specifically includes: acquiring a fourth sensing margin of a sense amplifier in a target storage area under the second control scenario when a condition unfavorable for reading out the first data is set; acquiring a fifth sensing margin of the sense amplifier in the target storage area under the second control scenario when a condition unfavorable for reading out the second data is set; A difference between the fourth sensing margin and the fifth sensing margin is calculated as the sensing margin difference value.

8. The control method according to claim 7, characterized in that: Acquiring a fourth sensing margin of the sense amplifier in the target storage area under the second control scenario when a condition unfavorable for reading the first data is set specifically includes: generating a plurality of third scanning voltages greater than a reference voltage of a lower plate of a memory cell; For each of the third scanning voltages, the lower plate voltage of the storage unit in the target storage area is adjusted according to the third scanning voltage, the duration of the offset elimination phase of the sense amplifier is controlled to be the optimal offset elimination duration, the moment when the first power supply terminal switches from the pre-charge voltage to the power supply voltage during the charge sharing phase is controlled to be the first moment in the second control scenario, and the moment when the second power supply terminal switches from the pre-charge voltage to the ground voltage during the charge sharing phase is controlled to be the second moment in the second control scenario, and the read error rate of the data of the storage unit in the target storage area is counted to obtain a third mapping relationship between a plurality of the third scanning voltages and the read error rate under each of the third scanning voltages; The fourth sensing margin is obtained by calculation according to the third mapping relationship.

9. The control method according to claim 7, characterized in that: Acquiring a fifth sensing margin of the sense amplifier in the target storage area under the second control scenario when a condition unfavorable for reading the second data is set specifically includes: generating a plurality of fourth scanning voltages less than a reference voltage of a lower plate of a memory cell; For each of the fourth scanning voltages, the lower plate voltage of the storage unit in the target storage area is adjusted according to the fourth scanning voltage, the duration of the offset elimination phase of the sense amplifier is controlled to be the optimal offset elimination duration, the moment when the first power supply terminal switches from the pre-charge voltage to the power supply voltage during the charge sharing phase is controlled to be the first moment in the second control scenario, and the moment when the second power supply terminal switches from the pre-charge voltage to the ground voltage during the charge sharing phase is controlled to be the second moment in the second control scenario, and the data read error rate of the storage unit in the target storage area is counted to obtain a fourth mapping relationship between a plurality of the fourth scanning voltages and the read error rate under each of the fourth scanning voltages; The fifth sensing margin is obtained by calculation according to the fourth mapping relationship.

10. A memory, characterized in that: include: A storage unit, a sense amplifier and a controller, wherein the storage unit is connected to the bit line, the sense amplifier is connected to the bit line, the controller is connected to the sense amplifier, and the controller is used to implement the method according to any one of claims 1 to 9.

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