Main word line driver and memory device using same

Abstract

The invention relates to a main word line driver and a memory device using the same. A memory device includes a first main word line signal, a second main word line signal, and a main word line driver. The first main word line signal is coupled to a first sub-word line driver block including n sub-word line drivers. The second main word line signal is coupled to a second sub-word line driver block including n sub-word line drivers. The main word line driver is configured to selectively enable one of the first main word line signal and the second main word line signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0082742 filed in the Korean Intellectual Property Office on June 27, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present technology relates to integrated circuit technology, and particularly to a main word line driver and a memory device using the same. Background Art

[0004] An electronic device includes many electronic components, and a computer system may include many electronic components composed of semiconductors. The semiconductor device constituting the computer system may include a processor or a memory controller operating as a master device and a memory device or a storage device operating as a slave device. The master device may provide a command address signal to the slave device. The slave device may perform various operations based on the command address signal. In addition, the master device and the slave device may transmit and receive data to each other.

[0005] As data communication speeds and data processing capabilities increase, memory devices with high data storage capacity are needed. In conventional technology, the data storage capacity of memory devices has been increased by shrinking technology and process optimization, but increasing the data storage capacity by only two-dimensional (2-D) design has reached its limit. Therefore, three-dimensional (3-D) memory devices that can support the maximum data storage capacity in the same area by stacking multiple memory cell arrays are being developed. Summary of the invention

[0006] In one embodiment, a main word line driver may include an enable control signal generating circuit, a first driver, and a second driver. The enable control signal generating circuit may be configured to generate an enable control signal based on a pre-decoding signal. The first driver may be configured to enable a first main word line signal based on the enable control signal and an even selection signal. The second driver may be configured to enable a second main word line signal based on the enable control signal and an odd selection signal.

[0007] In one embodiment, a memory device may include a plurality of memory cell arrays, a sub-word line driver block, and a main word line driver block. Each of the plurality of memory cell arrays may include a plurality of word lines and be stacked in sequence. The sub-word line driver block may be configured to enable a plurality of word lines of any one of the plurality of memory cell arrays based on a first main word line signal, a second main word line signal, and a sub-word line selection signal. The main word line driver block may be configured to enable a first main word line signal and a second main word line signal based on a pre-decoding signal and even and odd selection signals.

[0008] In one embodiment, a memory device may include a first main word line signal, a second main word line signal, and a first main word line driver. The first main word line signal may be coupled to a first sub-word line driver block including n sub-word line drivers. The second main word line signal may be coupled to a second sub-word line driver block including n sub-word line drivers. The first main word line driver may be configured to enable one of the first main word line signal and the second main word line signal based on a first bit of a pre-decoding signal and even and odd selection signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a diagram illustrating a configuration of a memory device according to an embodiment.

[0010] Figure 2 is a perspective view illustrating a configuration of a storage area according to one embodiment.

[0011] Figure 3 is a vertical cross-sectional view illustrating a configuration of a storage area according to one embodiment.

[0012] Figure 4 is a diagram illustrating a configuration of a main word line driver according to one embodiment.

[0013] Figure 5 is a timing diagram illustrating the operation of a memory device according to one embodiment. DETAILED DESCRIPTION

[0014] Figure 1 1 is a diagram illustrating a configuration of a memory device 100 according to an embodiment. Figure 1 , the memory device 100 may include a storage area 110, a command decoding circuit 120, an address latch circuit 130, a row decoder 140, a column decoder 150, a read and write circuit 160, and a data input / output circuit 170. The storage area 110 may include a plurality of memory cell array blocks. The plurality of memory cell array blocks may include a plurality of memory cells capable of storing data. For example, the storage area 110 may include a first memory cell array block MCA1 and a second memory cell array block MCA2. Figure 1 It is illustrated that the number of memory cell array blocks included in the storage area 110 is 2. However, the number of memory cell array blocks included in the storage area 110 may be 4, 8, or more. The first memory cell array block MCA1 and the second memory cell array block MCA2 may each include a plurality of word lines (not shown) and a plurality of bit lines BL. A plurality of memory cells may be coupled to points where a plurality of word lines and a plurality of bit lines BL intersect. The first memory cell array block MCA1 and the second memory cell array block MCA2 may each include a plurality of memory cell arrays. The plurality of memory cell arrays may be stacked into a plurality of layers to form the first memory cell array block MCA1 and the second memory cell array block MCA2. The space between the first memory cell array block MCA1 and the second memory cell array block MCA2 may be a row hole area 111. A main word line driver block MWD and a sub word line selection driver block FXD may be provided in the row hole area 111. Both sides of the first memory cell array block MCA1 may be elongated areas 112A and 112B. Sub word line driver blocks SWD may be disposed under the elongated regions 112A and 112B, respectively. Both sides of the second memory cell array block MCA2 may be elongated regions 113A and 113B. Sub word line driver blocks SWD may be disposed under the elongated regions 113A and 113B, respectively.

[0015] The main word line driver block MWD may generate a plurality of main word line signals MWL<0:k> (k is an integer equal to or greater than 5). For example, the main word line driver block MWD may receive a pre-decoding signal PXDEC, and may enable at least one main word line signal among the plurality of main word line signals MWL<0:k> based on the pre-decoding signal PXDEC. The number of bits included in the pre-decoding signal PXDEC may be half of the number of bits included in the main word line signal. The main word line driver block MWD may enable two main word line signals by using one bit of the pre-decoding signal PXDEC. For example, the main word line driver block MWD may enable (k+1) main word line signals by using a pre-decoding signal PXDEC having ((k+1) / 2) bits. The main word line driver block MWD enables (k+1) main word line signals by using a pre-decoding signal PXDEC having ((k+1) / 2) bits. Therefore, the number of bits included in the pre-decoding signal PXDEC and the number of wirings through which the pre-decoding signal PXDEC is transmitted may be reduced. The main word line signal MWL<0:k> may be coupled to the sub word line driver block SWD. The sub word line selection driver block FXD may generate a sub word line selection signal FX<0:2n-1> (n is an integer equal to or greater than 5) based on the selection decoding signal FXDEC, and may provide the sub word line selection signal FX<0:2n-1> to the sub word line driver block SWD. The sub word line driver block SWD may enable word lines of the first memory cell array block MCA1 and the second memory cell array block MCA2 based on the main word line signal MWL<0:k> and the sub word line selection signal FX<0:2n-1>.

[0016] Figure 2 2 is a perspective view illustrating a configuration of a storage area 200 according to an embodiment. The storage area 200 may be applied as Figure 1 The storage area 110 is shown in FIG. Figure 2, the storage area 200 may include a first memory cell array (MCA) block 210 and a second memory cell array (MCA) block 220. The first memory cell array block 210 may include n memory cell arrays 211_1 to 211_n. The n memory cell arrays 211_1 to 211_n may be stacked sequentially. For example, the first memory cell array 211_1 may be disposed at the bottom of the first memory cell array block 210. The second memory cell array 211_2 to the nth memory cell array 211_n may be stacked sequentially on the first memory cell array 211_1. The first memory cell array 211_1 to the nth memory cell array 211_n may include a plurality of word lines extending in a horizontal direction (ie, an x-axis direction). Both sides of the first memory cell array block 210 may each be formed in a stepped form. Both sides having a stepped form may be elongated regions 212A and 212B. The first memory cell array 211_1 to the nth memory cell array 211_n may have exposed portions in the elongated regions 212A and 212B, respectively. The nth memory cell array 211_n may have the largest area. The (n-1)th memory cell array 211_n-1 may have a smaller area than the nth memory cell array 211_n. The first memory cell array 211_1 may have the smallest area. In one embodiment, as shown in the figure, the n memory cell arrays may gradually widen from the first memory cell array 211_1 to the nth memory cell array 211_n. The first memory cell array 211_1 to the nth memory cell array 211_n may respectively form a layer of the first memory cell array block 210. A structure having a stepped form formed in each of the elongated regions 212A and 212B may be provided to independently enable the word lines of the first memory cell array 211_1 to the nth memory cell array 211_n. Sub word line driver blocks 213A and 213B may be disposed under the elongated regions 212A and 212B, respectively. The first to nth memory cell arrays 211_1 and 211_n may be coupled to the sub word line driver blocks 213A and 213B in the elongated regions 212A and 212B. The sub word line driver blocks 213A and 213B may be coupled to exposed portions of the first to nth memory cell arrays 211_1 and 211_n in the elongated regions 212A and 212B and may enable word lines of the first to nth memory cell arrays 211_1 and 211_n.

[0017] A plurality of memory cells may be formed in the middle portion of the first memory cell array block 210 except the elongated regions 212A and 212B. A plurality of memory cells of the first memory cell array 211_1 to the nth memory cell array 211_n may be coupled to the sense amplification block 214 through a bit line (not shown), which is formed in the middle portion in the vertical direction (i.e., the y-axis direction). The sense amplification block 214 may be disposed below the first memory cell array 211_1. The sense amplification block 214 may be disposed below the middle portion of the first memory cell array block 210 and may be disposed between the sub-word line driver blocks 213A and 213B. A row hole region 230 may be disposed between the first memory cell array block 210 and the second memory cell array block 220. A main word line driver block and a sub-word line selection driver block may be disposed in the row hole region 230. That is, the main word line driver block and the sub word line selection driver block may be disposed in a plane different from a plane in which the first memory cell array block 210 and the second memory cell array block 220 are disposed.

[0018] The second memory cell array block 220 may include n memory cell arrays 221_1 to 221_n. The n memory cell arrays 221_1 to 221_n may be stacked sequentially. For example, the first memory cell array 221_1 may be disposed at the bottom of the second memory cell array block 220. The second memory cell arrays 221_2 to the nth memory cell arrays 221_n may be stacked sequentially on the first memory cell array 221_1. The first memory cell arrays 221_1 to the nth memory cell arrays 221_n may include a plurality of word lines extending in a horizontal direction (i.e., an x-axis direction). Both sides of the second memory cell array block 220 may each be formed in a stepped form. Both sides having a stepped form may be elongated regions 222A and 222B. The first memory cell arrays 221_1 to the nth memory cell arrays 221_n may have exposed portions in the elongated regions 222A and 222B, respectively. The nth memory cell array 221_n may have the largest region. The (n-1)th memory cell array 221_n-1 may have a smaller area than the nth memory cell array 221_n. The first memory cell array 221_1 may have the smallest area. In one embodiment, as shown in the figure, the n memory cell arrays may gradually widen from the first memory cell array 221_1 to the nth memory cell array 221_n. The first memory cell array 221_1 to the nth memory cell array 221_n may form a layer of the second memory cell array block 220, respectively. The sub-word line driver blocks 223A and 223B may be disposed below the elongated regions 222A and 222B. The first memory cell array 221_1 to the nth memory cell array 221_n may be coupled to the sub-word line driver blocks 223A and 223B in the elongated regions 222A and 222B. The sub word line driver blocks 223A and 223B may be coupled to exposed portions of the first to nth memory cell arrays 221_1 and 221_n in the elongated regions 222A and 222B and may enable word lines of the first to nth memory cell arrays 221_1 and 221_n.

[0019] A plurality of memory cells may be formed in the middle portion of the second memory cell array block 220 except the elongated regions 222A and 222B. A plurality of memory cells of the first memory cell array 221_1 to the nth memory cell array 221_n may be coupled to the sense amplification block 224 through a bit line (not shown), which is formed in the middle portion in the vertical direction (i.e., the y-axis direction). The sense amplification block 224 may be disposed below the first memory cell array 221_1. The sense amplification block 224 may be disposed below the middle portion of the second memory cell array block 220 and may be disposed between the sub-word line driver blocks 223A and 223B. In one embodiment, the main word line driver block may be disposed below the memory cell array blocks 210 and 220 instead of the row hole region 230. The main word line driver block may be disposed below the middle portion of each of the first memory cell array block 210 and the second memory cell array block 220 together with the sense amplification blocks 214 and 224.

[0020] Return to reference Figure 1 , the command decoding circuit 120 may receive the command signal CMD, and may generate an internal command signal ICMD by decoding the command signal CMD. The internal command signal ICMD may include a read signal RD and a write signal WT. The command signal CMD may be a signal provided by a host device (not shown) coupled to the memory device 100. The host device may provide the command signal CMD to the memory device 100 so that the memory device 100 may perform various operations. The operation of outputting data stored in the memory device 100 to the host device may be a read operation. The operation of storing data received from the host device in the memory device 100 may be a write operation. When the host device provides a command signal CMD for enabling the memory device 100 to perform a read operation, the command decoding circuit 120 may generate a read signal RD by decoding the command signal CMD. When the host device provides a command signal CMD for enabling the memory device 100 to perform a write operation, the command decoding circuit 120 may generate a write signal WT by decoding the command signal CMD. The command decoding circuit 120 may provide an internal command signal ICMD to the read and write circuit 160 and the data input / output circuit 170 .

[0021] The address latch circuit 130 may receive an address signal ADD, and may generate a row address signal RADD and a column address signal CADD based on the address signal ADD. The address signal ADD may be a signal provided from a host device to the memory device 100. The host device may provide the address signal ADD to the memory device 100 to access the first memory cell array block MCA1 and the second memory cell array block MCA2 of the memory device 100. The address latch circuit 130 may latch the address signal ADD, and may output the latched address signal as a row address signal RADD or a column address signal CADD. For example, the address latch circuit 130 may output the address signal ADD received during an active operation of the memory device 100 as a row address signal RADD. The active operation may be an operation of activating the first memory cell array block MCA1 and the second memory cell array block MCA2 before performing a read operation and a write operation. The memory device 100 may enable the word lines of the first memory cell array block MCA1 and the second memory cell array block MCA2 based on the row address signal RADD during the active operation. The address latch circuit 130 may output an address signal ADD received during one of a read operation and a write operation of the memory device 100 as a column address signal CADD. During the read operation and the write operation, the memory device 100 may select a bit line BL of the first memory cell array block MCA1 and the second memory cell array block MCA2 based on the column address signal CADD. When a specific word line among the word lines of the first memory cell array block MCA1 and the second memory cell array block MCA2 is enabled and a specific bit line among the bit lines BL of the first memory cell array block MCA1 and the second memory cell array block MCA2 is selected, a memory cell that has been coupled between the enabled word line and the selected bit line may be accessed.

[0022] The row decoder 140 may receive a row address signal RADD. The row decoder 140 may generate a pre-decoding signal PXDEC and a selection decoding signal FXDEC by decoding the row address signal RADD. The row decoder 140 may provide the pre-decoding signal PXDEC and the selection decoding signal FXDEC to the main word line driver block MWD and the sub word line selection driver block FXD. The column decoder 150 may receive a column address signal CADD. The column decoder 150 may select a specific bit line among the bit lines BL of the first memory cell array block MCA1 and the second memory cell array block MCA2 based on the column address signal CADD. The column decoder 150 may couple the selected bit line to the read and write circuit 160.

[0023] The read and write circuit 160 may be coupled to the bit line BL through the column decoder 150. The read and write circuit 160 may receive a read signal RD and a write signal WT from the command decoding circuit 120. The read and write circuit 160 may be coupled to the data input / output circuit 170 through the global data line GL. The read and write circuit 160 may amplify data output from the first memory cell array block MCA1 and the second memory cell array block MCA2 through the bit line BL based on the read signal RD during a read operation of the memory device 100, and may output the data through the global data line GL. The read and write circuit 160 may receive data transmitted through the global data line GL based on the write signal WT during a write operation of the memory device 100, and may provide the received data to the bit line BL by amplifying the received data. The data received through the bit line BL may be stored in the first memory cell array block MCA1 and the second memory cell array block MCA2.

[0024] The data input / output circuit 170 may be coupled to the global data line GL and the data bus 101. The data bus 101 may be a signal transmission line coupling the host device and the memory device 100. The data input / output circuit 170 may receive a read signal RD and a write signal WT from the command decoding circuit 120. The data input / output circuit 170 may receive data transmitted through the global data line GL based on the read signal RD during a read operation of the memory device 100, may generate a data stream DQ based on the received data, and may transmit the data stream DQ to the host device through the data bus 101. The data input / output circuit 170 may receive a data stream DQ transmitted by the host device through the data bus 101 based on the write signal WT during a write operation of the memory device 100, and may transmit the data generated from the data stream DQ to the read and write circuit 160 through the global data line GL.

[0025] Figure 3 is a vertical cross-sectional view illustrating a configuration of a storage area 300 according to one embodiment. The storage area 300 may be applied as Figure 1 For the sake of clarity, Figure 3 The configuration of one memory cell array block 310 may be illustrated. Figure 3, the storage area 300 may include a memory cell array block 310. The memory cell array block 310 may include n memory cell arrays 311_1 to 311_n. The first memory cell array 311_1 may be disposed at the bottom of the memory cell array block 310. The second memory cell array 311_2 to the nth memory cell array 311_n may be sequentially stacked on the first memory cell array 311_1. Both sides of the memory cell array block 310 may be elongated regions 312A and 312B. The elongated regions 312A and 312B may each have a stepped form. The first memory cell array 311_1 to the nth memory cell array 311_n may each protrude the same region outward in the elongated regions 312A and 312B. In the middle portion of the memory cell array block 310 except the elongated regions 312A and 312B, the first memory cell array 311_1 to the nth memory cell array 311_n may each include a plurality of word lines.

[0026] Sub word line driver blocks SWDA and SWDB may be disposed under the elongated regions 312A and 312B, respectively. The first sub word line driver block SWDA may be disposed under the elongated region 312A, and the second sub word line driver block SWDB may be disposed under the elongated region 312B. The sub word line driver blocks SWDA and SWDB may each include sub word line drivers, the number of which corresponds to the product of the number of memory cell arrays included in the memory cell array block 310 and the number of main word line signals. The sub word line driver block SWDA may be coupled to the first memory cell array 311_1 to the nth memory cell array 311_n through the corresponding exposed portions of the first memory cell array 311_1 to the nth memory cell array 311_n in the elongated region 312A. The sub word line driver block SWDB may be coupled to the first memory cell array 311_1 to the nth memory cell array 311_n through the corresponding exposed portions of the first memory cell array 311_1 to the nth memory cell array 311_n in the elongated region 312B. A sense amplification block BLSA may be provided between the sub-word line driver blocks SWDA and SWDB. The sense amplification block BLSA may be provided below a middle portion of the memory cell array block 310. The first memory cell array 311_1 to the nth memory cell array 311_n may be coupled to the sense amplification block BLSA through the bit lines BL. The sense amplification block BLSA may include bit line sense amplifiers, the number of which corresponds to the number of bit lines BL. The side of the memory cell array block 310 and the sub-word line driver block SWDB may be a row hole region 320. A main word line driver block MWD may be provided in the row hole region 320. Although not shown in the figure, Figure 1The sub word line selection driver block FXD illustrated in FIG. 3 may also be disposed in the row hole region 320 .

[0027] The main word line driver block MWD can generate multiple main word line signals MWL <0> , MWL <1> , MWL <2> , MWL <3> , ... For example, the main word line driver block MWD may generate first to fourth main word line signals MWL <0> , MWL <1> , MWL <2> and MWL <3> The first main word line signal MWL <0> The first main word line signal MWL may be coupled to the sub word line driver block SWDA. <0> The second main word line signal MWL may be coupled to n sub word line drivers in the sub word line driver block SWDA. <1> The second main word line signal MWL may be coupled to the sub word line driver block SWDB. <1> The third main word line signal MWL may be coupled to n sub word line drivers in the sub word line driver block SWDB. <2> The third main word line signal MWL may be coupled to the sub word line driver block SWDA. <2> The fourth main word line signal MWL may be coupled to n sub word line drivers in the sub word line driver block SWDA. <3> The fourth main word line signal MWL may be coupled to the sub word line driver block SWDB. <3> It may be coupled to n sub word line drivers in the sub word line driver block SWDB.

[0028] In the sub-word line driver block SWDA, coupled to the first main word line signal MWL <0> The n sub word line drivers may be respectively coupled to the first to nth memory cell arrays 311_1 to 311_n and may enable the first word lines WL of the first to nth memory cell arrays 311_1 to 311_n. <0> The n sub word line drivers may be selectively activated based on the sub word line selection signal FX<0:n-1>. The first word lines WL of the first to nth memory cell arrays 311_1 to 311_n may be enabled. <0> The first word line WL coupled to the activated sub-word line driver <0> In the sub-word line driver block SWDB, coupled to the second main word line signal MWL <1> The n sub word line drivers may be respectively coupled to the first to nth memory cell arrays 311_1 to 311_n and may enable the second word lines WL of the first to nth memory cell arrays 311_1 to 311_n. <1> . It can be based on the sub-word line selection signal FX <n:2n-1>The n sub-word line drivers are selectively activated. The second word lines WL of the first to nth memory cell arrays 311_1 to 311_n may be enabled. <1> The second word line WL coupled to the activated sub-word line driver <1> In the sub-word line driver block SWDA, coupled to the third main word line signal MWL <2> The n sub word line drivers may be respectively coupled to the first to nth memory cell arrays 311_1 to 311_n and may enable the third word lines WL of the first to nth memory cell arrays 311_1 to 311_n. <2> The n sub word line drivers may be selectively activated based on the sub word line selection signal FX<0:n-1>. The third word lines WL of the first to nth memory cell arrays 311_1 to 311_n may be enabled. <2> The third word line WL coupled to the activated sub-word line driver <2> In the sub-word line driver block SWDB, coupled to the fourth main word line signal MWL <3> The n sub word line drivers may be respectively coupled to the first to nth memory cell arrays 311_1 to 311_n and may enable fourth word lines WL of the first to nth memory cell arrays 311_1 to 311_n. <3> . It can be based on the sub-word line selection signal FX <n:2n-1>The n sub-word line drivers are selectively activated. The fourth word lines WL of the first to nth memory cell arrays 311_1 to 311_n may be enabled. <3> The fourth word line WL coupled to the activated sub-word line driver <3> .

[0029] For example, if the memory cell array block 310 includes 32 memory cell arrays, the first to fourth main word line signals MWL <0> , MWL <1> , MWL <2> and MWL <3> Each of the first to fourth main word line signals MWL may be coupled to 32 sub word line drivers in the sub word line driver blocks SWDA and SWDB. If the memory cell array block 310 includes 64 memory cell arrays, the first to fourth main word line signals MWL <0> , MWL <1> , MWL <2> and MWL <3> 64 sub-word line drivers in the sub-word line driver blocks SWDA and SWDB may be coupled to each other. As the number of memory cell arrays included in the memory cell array block 310 increases, the number of sub-word line drivers coupled to one main word line signal increases. Therefore, the load of the main word line signal may increase, and the time taken to enable the word lines of the first memory cell array 311_1 to the nth memory cell array 311_n may be delayed. In order to constantly maintain the load of the main word line signal, the number of main word line signals needs to increase as the number of memory cell arrays included in the memory cell array block 310 increases. When the number of main word line signals increases, the power distribution network characteristics may deteriorate because the number of wirings in the horizontal direction that can be used to supply power decreases. In one embodiment of the present technology, as the number of memory cell arrays included in the memory cell array block 310 increases, the driving power of the main word line driver block MWD that drives the main word line signal can be increased without increasing the number of sub-word lines coupled to the main word line signal.

[0030] The main word line driver block MWD may include a first main word line driver MWD1 and a second main word line driver MWD2. The first main word line driver MWD1 and the second main word line driver MWD2 may each generate two main word line signals MWL, and may each selectively enable one of the two main word line signals MWL. The first main word line driver MWD1 may selectively enable the first main word line signal MWL based on at least some bits of the selection decoding signal FXDEC and the first bit of the pre-decoding signal PXDEC. <0> and the second main word line signal MWL <1> At least some bits of the selection decoding signal FXDEC may be used as the even and odd selection signal EOSEL. For example, the even and odd selection signal EOSEL may be one bit of the selection decoding signal FXDEC. One bit of the selection decoding signal FXDEC and / or the even and odd selection signal EOSEL may have a first logic level for asserting one of the sub-word line selection signals FX<0:n-1>, and may have a first logic level for asserting the sub-word line selection signal FX<0:n-1>. <n:2n-1>When used to enable the first main word line signal MWL <0> and the second main word line signal MWL <1> When the first bit of the pre-decoding signal PXDEC of at least one of the even and odd selection signals EOSEL is asserted and the even and odd selection signals EOSEL have a first logic level, the first main word line driver MWD1 may enable the first main word line signal MWL <0> When used to enable the first main word line signal MWL <0> and the second main word line signal MWL <1> When the first bit of the pre-decoding signal PXDEC of at least one of the even and odd selection signals EOSEL is asserted and the even and odd selection signals EOSEL have a second logic level, the first main word line driver MWD1 may enable the second main word line signal MWL <1> .

[0031] The second main word line driver MWD2 may selectively enable the third main word line signal MWL based on at least some bits of the selection decoding signal FXDEC and a second bit of the pre-decoding signal PXDEC. <2> and the fourth main word line signal MWL <3> When used to enable the third main word line signal MWL <2> and the fourth main word line signal MWL <3> When the second bit of the pre-decoding signal PXDEC of at least one of the even and odd selection signals EOSEL is asserted and the even and odd selection signals EOSEL have the first logic level, the second main word line driver MWD2 may enable the third main word line signal MWL <2> When used to enable the third main word line signal MWL <2> and the fourth main word line signal MWL <3> When the second bit of the pre-decoding signal PXDEC of at least one of the even and odd selection signals EOSEL is asserted and the even and odd selection signals EOSEL have a second logic level, the second main word line driver MWD2 may enable the fourth main word line signal MWL <3> The first main word line driver MWD1 and the second main word line driver MWD2 of the main word line driver block MWD can each enable two main word line signals based on one bit of the pre-decoding signal PXDEC and the even and odd selection signals EOSEL. Therefore, the main word line driver block MWD can only be based on the main word line signal MWL <0> , MWL <1> , MWL <2> , MWL <3> , ... corresponds to half the number of bits of the pre-decoding signal PXDEC to enable all main word line signals MWL <0> , MWL <1> , MWL <2> , MWL <3> 、….

[0032] Figure 4 4 is a diagram illustrating a configuration of a main word line driver 400 according to an embodiment. The main word line driver 400 may be applied as Figure 3 Each of the first main word line driver MWD1 and the second main word line driver MWD2 shown in FIG. Figure 4 , the main word line driver 400 may include an enable control signal generating circuit 410, a first driver 420, and a second driver 430. The enable control signal generating circuit 410 may receive a first pre-decoding signal PXDEC <0> The enabling control signal generating circuit 410 may be based on the first pre-decoding signal PXDEC <0> To generate the enable control signal PEN. Figure 4 as well as Figure 3 When the main word line driver 400 is applied as the first main word line driver MWD1, the first pre-decoding signal PXDEC <0> may be the first bit of the pre-decoding signal PXDEC and may be asserted to enable the first main word line signal MWL <0> and the second main word line signal MWL <1> The pre-decoding signal PXDEC.

[0033] When the first pre-decoding signal PXDEC <0> When asserted, the enable control signal generating circuit 410 may drive the first node ND1 to a voltage level of a ground voltage. The enable control signal generating circuit 410 may drive the enable control signal PEN to a voltage level of a first power supply voltage VPP based on the voltage level of the first node ND1. When the first node ND1 is driven to a voltage level of a ground voltage, the enable control signal generating circuit 410 may enable the enable control signal PEN by providing the first power supply voltage VPP as the enable control signal PEN. The enable control signal generating circuit 410 may further receive a word line disconnect signal WLOFF. The word line disconnect signal WLOFF may be Figure 1 4 is a signal enabled in the precharge operation of the memory device 100 illustrated in FIG. The memory device 100 may disable the word line that has been enabled during the precharge operation. Based on the word line disconnect signal WLOFF, the enable control signal generation circuit 410 may disable the enable control signal PEN by driving the enable control signal PEN to the voltage level of the ground voltage. The enable control signal generation circuit 410 may provide the second power supply voltage VDD to the first node ND1 based on the word line disconnect signal WLOFF. When the second power supply voltage VDD is provided to the first node ND1, the enable control signal generation circuit 410 may disable the enable control signal PEN. The second power supply voltage VDD may have a voltage level lower than the first power supply voltage VPP, and may have a voltage level higher than the ground voltage.

[0034] The first driver 420 may receive an enable control signal PEN and an even selection signal SWEV. The first driver 420 may enable a first main word line signal MWL based on the enable control signal PEN and the even selection signal SWEV. <0> When the enable control signal PEN and the even selection signal SWEV are enabled, the first driver 420 may enable the first main word line signal MWL <0> When the first main word line signal MWL <0> When enabled, the first driver 420 can maintain the first main word line signal MWL <0> The second driver 430 may receive the enable control signal PEN and the odd selection signal SWOD. The second driver 430 may enable the second main word line signal MWL based on the enable control signal PEN and the odd selection signal SWOD. <1> When the enable control signal PEN and the odd selection signal SWOD are enabled, the second driver 430 may enable the second main word line signal MWL <1> When the second main word line signal MWL <1> When enabled, the second driver 430 can maintain the second main word line signal MWL <1> The state of being enabled. Figure 3 The even and odd selection signals EOSEL illustrated in FIG. 1 may generate an even selection signal SWEV and an odd selection signal SWOD. For example, when the even and odd selection signals EOSEL have a first logic level, the even selection signal SWEV may be enabled, and the odd selection signal SWOD may be disabled. When the even and odd selection signals EOSEL have a second logic level, the even selection signal SWEV may be disabled, and the odd selection signal SWOD may be enabled.

[0035] The enable control signal generating circuit 410 may include a first transistor T11, a second transistor T12, a third transistor T13, a fourth transistor T14, and a fifth transistor T15. The first transistor T11, the fourth transistor T14, and the fifth transistor T15 may each be an N-channel MOS transistor. The second transistor T12 and the third transistor T13 may each be a P-channel MOS transistor. The gate of the first transistor T11 may receive the first pre-decoding signal PXDEC <0> . The drain of the first transistor T11 may be coupled to the first node ND1. The source of the first transistor T11 may be coupled to the ground voltage. The gate of the second transistor T12 may be coupled to the second node ND2. The source of the second transistor T12 may receive the first power supply voltage VPP. The drain of the second transistor T12 may be coupled to the first node ND1. The enable control signal PEN may be generated from the second node ND2. The gate of the third transistor T13 may be coupled to the first node ND1. The source of the third transistor T13 may receive the first power supply voltage VPP. The drain of the third transistor T13 may be coupled to the gate of the second transistor T12 and the second node ND2. The gate of the fourth transistor T14 may receive the word line disconnection signal WLOFF. The drain of the fourth transistor T14 may be coupled to the second node ND2. The source of the fourth transistor T14 may receive the ground voltage. The gate of the fifth transistor T15 may receive the word line disconnection signal WLOFF. The source of the fifth transistor T15 may receive the second power supply voltage VDD. The drain of the fifth transistor T15 can be coupled to the source of the first transistor T11. <0> When asserted, the first transistor T11 may couple the first node ND1 to the ground voltage, and the third transistor T13 may enable the enable control signal PEN by driving the second node ND2 to the voltage level of the first power supply voltage VPP. When the enable control signal PEN is enabled, the second transistor T12 may be turned off, and the voltage level of the first node ND1 may be maintained at a logic low level. When the word line disconnect signal WLOFF is enabled, the fourth transistor T14 may disable the enable control signal PEN by coupling the second node ND2 to the ground voltage. In addition, the fifth transistor T15 may provide the second power supply voltage VDD to the first node ND1 by providing the second power supply voltage VDD to the source of the first transistor T11. When the second power supply voltage VDD is provided to the first node ND1, the third transistor T13 may be turned off. When the enable control signal PEN is disabled, the second transistor T12 may be turned on, and the second transistor T12 may maintain the voltage level of the first node ND1 to a logic high level by providing the first power supply voltage VPP to the first node ND1.

[0036] The enable control signal generating circuit 410 may further include a sixth transistor T16. The sixth transistor T16 may be an N-channel MOS transistor. The gate of the sixth transistor T16 may receive the row enable signal XDECEN. The drain of the sixth transistor T16 may be commonly coupled to the source of the first transistor T11 and the source of the fifth transistor T15. The source of the sixth transistor T16 may be coupled to a ground voltage. The row enable signal XDECEN may be Figure 1 , and may be enabled when the row decoder 140 generates a pre-decoding signal PXDEC from the row address signal RADD. When the row enable signal XDECEN is enabled, the sixth transistor T16 may provide a ground voltage to the source of the first transistor T11 and the source of the fifth transistor T15.

[0037] The first driver 420 may include a first transistor T21, a second transistor T22, a third transistor T23, and a fourth transistor T24. The first transistor T21 may be a P-channel MOS transistor. The second to fourth transistors T22, T23, and T24 may each be an N-channel MOS transistor. The gate of the first transistor T21 may receive an enable control signal PEN. The source of the first transistor T21 may receive a first power supply voltage VPP. The drain of the first transistor T21 may be coupled to the first output node ON1. The first main word line signal MWL <0> Can be output through the first output node ON1. The gate of the second transistor T22 can receive the enable control signal PEN. The drain of the second transistor T22 can be coupled to the first output node ON1. The gate of the third transistor T23 can receive the even selection signal SWEV. The drain of the third transistor T23 can be coupled to the source of the second transistor T22. The source of the third transistor T23 can be coupled to the ground voltage. The gate of the fourth transistor T24 can be coupled to the first output node ON1. The drain of the fourth transistor T24 can be coupled to the second node ND2. The source of the fourth transistor T24 can be coupled to the ground voltage. When the enable control signal PEN and the even selection signal SWEV are enabled to a logic high level, the second transistor T22 and the third transistor T23 can be turned on, and the first main word line signal MWL <0> The first main word line signal MWL may be enabled to a logic low level because the ground voltage is provided to the first output node ON1 through the second transistor T22 and the third transistor T23. When either of the enable control signal PEN and the even selection signal SWEV is in a disabled state, the first main word line signal MWL <0> When the enable control signal PEN is disabled to a logic low level, the first transistor T21 may be turned on, and the first transistor T21 may provide the first power supply voltage VPP to the first output node ON1 to transmit the first main word line signal MWL to the first output node ON1. <0> Disable to logic high level. When the first main word line signal MWL <0> When in the disabled state, the fourth transistor T24 can maintain the level of the enable control signal PEN at a logic low level, and when the first main word line signal MWL <0> When in the enabled state, the fourth transistor T24 may be turned off.

[0038] The second driver 430 may include a first transistor T31, a second transistor T32, a third transistor T33, and a fourth transistor T34. The first transistor T31 may be a P-channel MOS transistor. The second to fourth transistors T32, T33, and T34 may each be an N-channel MOS transistor. The gate of the first transistor T31 may receive an enable control signal PEN. The source of the first transistor T31 may receive a first power supply voltage VPP. The drain of the first transistor T31 may be coupled to the second output node ON2. The second main word line signal MWL <1> The gate of the second transistor T32 may receive the enable control signal PEN. The drain of the second transistor T32 may be coupled to the second output node ON2. The gate of the third transistor T33 may receive the odd selection signal SWOD. The drain of the third transistor T33 may be coupled to the source of the second transistor T32. The source of the third transistor T33 may be coupled to the ground voltage. The gate of the fourth transistor T34 may be coupled to the second output node ON2. The drain of the fourth transistor T34 may be coupled to the second node ND2. The source of the fourth transistor T34 may be coupled to the ground voltage. When the enable control signal PEN and the odd selection signal SWOD are enabled to a logic high level, the second transistor T32 and the third transistor T33 may be turned on, and the second main word line signal MWL <1> The second main word line signal MWL may be enabled to a logic low level because the ground voltage is provided to the second output node ON2 through the second transistor T32 and the third transistor T33. When either of the enable control signal PEN and the odd selection signal SWOD is in a disabled state, the second main word line signal MWL <1> When the enable control signal PEN is disabled to a logic low level, the first transistor T31 may be turned on, and the first transistor T31 may provide the first power supply voltage VPP to the second output node ON2 to transmit the second main word line signal MWL to the second output node ON2. <1> Disable to logic high level. When the second main word line signal MWL <1> When in the disabled state, the fourth transistor T34 can maintain the level of the enable control signal PEN at a logic low level, and when the second main word line signal MWL <1> When in the enabled state, the fourth transistor T34 may be turned off.

[0039] The main word line driver 400 may selectively enable the first main word line signal MWL by using the even selection signal SWEV and the odd selection signal SWOD. <0> and the second main word line signal MWL <1> When the first main word line signal MWL <0> and the second main word line signal MWL <1> When each of the first and second main word line drivers is connected to n sub word line drivers, the main word line driver 400 may have a load corresponding to a total of 2n sub word line drivers. However, because the main word line driver 400 selectively enables the first main word line signal MWL <0> and the second main word line signal MWL <1> The load of the main word line driver 400 can be reduced to a load corresponding to the n sub word line drivers because the main word line driver 400 can be composed of a small number of transistors. In addition, since the main word line driver 400 can be composed of a small number of transistors, the main word line driver 400 can have a reduced circuit area, and through the reduced circuit area, the main word line driver 400 can increase the driving power of the main word line signal by increasing the size (i.e., the ratio of width to length) of the transistor driving the main word line signal.

[0040] Figure 5 is a timing diagram illustrating the operation of a memory device according to one embodiment. Figure 5 , the horizontal axis indicates time "t", and the vertical axis indicates voltage V. Figure 1 , Figure 3 and Figure 5 , the memory device 100 may receive a command signal CMD and an address signal ADD to enable an active operation to be performed. The address latch circuit 130 may generate a row address signal RADD from the address signal ADD and provide the row address signal RADD to the row decoder 140. The row decoder 140 may generate a pre-decoding signal PXDEC and a selection decoding signal FXDEC by decoding the row address signal RADD. Based on some bits of the pre-decoding signal PXDEC and the selection decoding signal FXDEC, the main word line drivers MWD1 and MWD2 of the main word line driver block MWD may each enable one of the two main word line signals MWL. The main word line signal that receives the enabled main word line signal and based on the sub-word line driver select signals FX<0:n-1> and FX <n:2n-1>Each of the sub-word line drivers selected among the sub-word line drivers of each of the sub-word line driver blocks SWDA and SWDB can enable the word line WLx of the memory cell array coupled to the sub-word line driver. When the word line WLx is enabled, charge sharing can occur between the bit line BLx and the inverted bit line (bit line bar) BLBx. The bit line sense amplifier of the sense amplification block BLSA can increase the voltage level of the bit line BLx by amplifying the difference between the voltage level of the bit line BLx and the voltage level of the inverted bit line BLBx, and can reduce the voltage level of the inverted bit line BLBx. Compared with the conventional technology (indicated by the dotted line), the timing at which the word line WLx is enabled can be advanced because the driving power of the main word line drivers MWD1 and MWD2 has been increased. If the word line WLx is enabled quickly, the operational reliability of the memory device 100 can be improved because the timing margin for charge sharing between the bit line BLx and the inverted bit line BLBx can be fully guaranteed.

[0041] As described above, it will be understood by those skilled in the art that the technology can be implemented in various other forms without departing from the technical spirit or essential characteristics of the technology. Therefore, it is to be understood that the aforementioned embodiments are illustrative rather than restrictive in all aspects. The scope of the technology is defined by the appended claims rather than by the detailed description, and all modifications or changes derived from the meaning and scope of the claims and their equivalents should be understood to be included within the scope of the technology.

Claims

1. A main word line driver, comprising: an enable control signal generating circuit configured to generate an enable control signal based on the pre-decoded signal; a first driver configured to enable a first main word line signal based on the enable control signal and an even selection signal; as well as The second driver is configured to enable a second main word line signal based on the enable control signal and the odd selection signal.

2. The main word line driver according to claim 1, wherein the enable control signal generating circuit is configured to: driving the first node to a voltage level of a ground voltage when the pre-decode signal is asserted, and The enable control signal is driven to a voltage level of a first power supply voltage based on the voltage level of the first node. 3 . The main word line driver according to claim 2 , wherein the enable control signal generating circuit is configured to drive the enable control signal to the voltage level of the ground voltage based on a word line disconnect signal.

4. The main word line driver according to claim 3, wherein: The enable control signal generating circuit is configured to: provide a second power supply voltage to the first node based on the word line disconnection signal, and The second power supply voltage has a higher voltage level than the ground voltage, and has a lower voltage level than the first power supply voltage. 5 . The main word line driver according to claim 1 , wherein the first driver is configured to enable the first main word line signal and maintain a state in which the first main word line signal has been enabled when the enable control signal and the even selection signal are enabled.

6. The main word line driver according to claim 5, wherein: The first driver includes a first transistor, a second transistor, a third transistor and a fourth transistor; The gate of the first transistor receives the enable control signal, the source of the first transistor receives a first power supply voltage, the drain of the first transistor is coupled to a first output node, and the first main word line signal is output from the first output node; A gate of the second transistor receives the enable control signal, and a drain of the second transistor is coupled to the first output node; A gate of the third transistor receives the even selection signal, a drain of the third transistor is coupled to a source of the second transistor, and a source of the third transistor is coupled to a ground voltage; and A gate of the fourth transistor is coupled to the first output node, a drain of the fourth transistor is coupled to the enable control signal, and a source of the fourth transistor is coupled to the ground voltage.

7. The main word line driver according to claim 5, wherein the second driver is configured to enable the second main word line signal and maintain a state in which the second main word line signal has been enabled when the enable control signal and the odd selection signal are enabled.

8. The main word line driver according to claim 7, wherein: The second driver includes a first transistor, a second transistor, a third transistor and a fourth transistor; The gate of the first transistor receives the enable control signal, the source of the first transistor receives a first power supply voltage, the drain of the first transistor is coupled to a second output node, and the second main word line signal is output from the second output node; A gate of the second transistor receives the enable control signal, and a drain of the second transistor is coupled to the second output node; A gate of the third transistor receives the odd selection signal, a drain of the third transistor is coupled to a source of the second transistor, and a source of the third transistor is coupled to a ground voltage, and A gate of the fourth transistor is coupled to the second output node, a drain of the fourth transistor is coupled to the enable control signal, and a source of the fourth transistor is coupled to the ground voltage.

9. A memory device comprising: a plurality of memory cell arrays stacked in sequence, each of the plurality of memory cell arrays comprising a plurality of word lines; a sub word line driver block configured to enable at least one word line among the plurality of word lines of each of the plurality of memory cell arrays based on a first main word line signal, a second main word line signal, and a sub word line selection signal; as well as A main word line driver block is configured to enable the first main word line signal and the second main word line signal based on a pre-decoding signal and even and odd selection signals.

10. The memory device of claim 9, wherein: The sub-word line driver block includes a first sub-word line driver block configured to enable a first word line of the plurality of memory cell arrays and a second sub-word line driver block configured to enable a second word line of the plurality of memory cell arrays, and Each of the first sub word line driver block and the second sub word line driver block includes a number of sub word line drivers equal to the number of a plurality of memory cell arrays that have been stacked.

11. The memory device of claim 10, wherein: The first sub word line driver block enables one of the first word lines of the plurality of memory cell arrays based on the sub word line select signal when the first main word line signal is enabled, and The second sub word line driver block enables one of the second word lines of the plurality of memory cell arrays based on the sub word line selection signal when the second main word line signal is enabled.

12. The memory device of claim 9, wherein the main word line driver block comprises a main word line driver configured to enable one of the first main word line signal and the second main word line signal based on the pre-decoding signal and the even and odd selection signals.

13. The memory device of claim 12, wherein the main word line driver is configured as: enabling an enable control signal when the pre-decode signal is asserted; The first main word line signal is enabled when the even and odd selection signals have a first logic level, and The second main word line signal is enabled when the even and odd selection signals have a second logic level. 14 . The memory device according to claim 9 , wherein the main word line driver block is disposed on a plane different from a plane on which the plurality of memory cell arrays are disposed.

15. The memory device of claim 9, wherein the main word line driver block is disposed below the plurality of memory cell arrays.

16. A memory device comprising: a first main word line signal coupled to a first sub word line driver block including n sub word line drivers; a second main word line signal coupled to a second sub word line driver block including n sub word line drivers; as well as The first main word line driver is configured to enable one of the first main word line signal and the second main word line signal based on a first bit of a pre-decoding signal and even and odd selection signals.

17. The memory device of claim 16, wherein the first main word line driver is configured as: enabling an enable control signal when the first bit of the pre-decode signal is asserted; enabling the first main word line signal when the even and odd selection signals have a first logic level, and The second main word line signal is enabled when the even and odd selection signals have a second logic level.

18. The memory device of claim 16, further comprising: a third main word line signal coupled to a third sub word line driver block including n sub word line drivers; a fourth main word line signal coupled to a fourth sub word line driver block including n sub word line drivers; as well as A second main word line driver is configured to enable one of the third main word line signal and the fourth main word line signal based on a second bit of the pre-decoding signal and the even and odd selection signals.

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