Decoder, decoding method, memory controller, memory system

Abstract

The embodiment of the present disclosure provides a decoder, comprising: a check node updating circuit, a variable node updating circuit; in a first time period, obtaining check node messages corresponding to different layers of a check matrix in different first updating units in a first updating unit of a level a; in the first time period, obtaining corresponding intermediate calculation values in different second updating units in a second updating unit of the level a; in a second time period after the first time period, each second updating unit except the second updating unit of the level a receives check node messages corresponding to each layer of the check matrix in turn, and each second updating unit receives the check node messages and calculates the intermediate calculation values of a next second updating unit to obtain variable node messages corresponding to different columns of the check matrix in different second updating units in the second updating unit of the level a.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, a decoder, a decoding method, a memory controller, a memory system, and an electronic device. BACKGROUND

[0002] With the rapid development of data storage technology, more and more data storage systems appear in electronic devices used by people, such as solid state drives (SSD) and the like. The SSD has been widely used in military, vehicle-mounted, industrial, medical and aviation fields due to its fast read and write speed, anti-vibration, low power consumption, no noise, low heat and light weight.

[0003] However, there are still many problems in the related art memory system that need to be solved. SUMMARY

[0004] According to a first aspect of an embodiment of the present disclosure, a decoder is provided, a check matrix corresponding to a code word of a frame includes a*a sub-matrices, a plurality of sub-matrices located in the same row in the check matrix constitute a layer of the check matrix, and a plurality of sub-matrices located in the same column constitute a column of the check matrix, wherein the a is a positive integer greater than 0, and the decoder includes:

[0005] The check node update circuit includes a first update unit of a level a, and each level of the first update unit is connected in turn. The variable node update circuit is connected with the check node update circuit, and includes a second update unit of a level a, and each level of the second update unit is connected in turn. Wherein,

[0006] In a first time period, each level of the first update unit of the check node update circuit, except the first level, receives the variable node message corresponding to each column of the check matrix in turn, and each level of the first update unit calculates the received variable node message and the message in the previous level of the first update unit, and obtains the check node message corresponding to different layers of the check matrix in different levels of the first update unit of the a level.

[0007] In the first time period, the variable node update circuit is configured to: the a-th level of the second update unit receives the variable node message corresponding to each column of the check matrix in turn, and each level of the second update unit, except the a-th level, receives the message of the next level of the second update unit and calculates, and obtains the corresponding intermediate calculation value in different levels of the a level of the second update unit.

[0008] In a second time period after the first time period, the variable node update circuit is configured to: each second update unit except the a-th second update unit successively receives the check node message corresponding to each layer of the check matrix, and successively calculates the received check node message and the intermediate calculation value of the next second update unit, to obtain the variable node message corresponding to different columns of the check matrix in different second update units in the a-th second update unit.

[0009] In some embodiments, each first update unit comprises a first delay unit, the first delay unit is configured to delay the updated message in each first update unit, each first update unit from the first first update unit to the a-1-th first update unit further comprises a first shift unit, each first update unit from the second first update unit to the a-th first update unit further comprises a comparison unit, the comparison unit is configured to compare the shifted message in the previous first update unit with the received variable node message to obtain a minimum value.

[0010] In some embodiments, the check node update circuit is configured to:

[0011] In the second time period, the comparison unit in each first update unit from the second first update unit to the a-th first update unit is closed.

[0012] In some embodiments, each second update unit comprises a second delay unit, each second update unit from the first second update unit to the a-1-th second update unit further comprises an addition unit and a second shift unit, the second delay unit is configured to delay the updated message in each second update unit, the second shift unit is configured to shift the updated message in each second update unit, and the addition unit is configured to add the message in the next second update unit with the received variable node message.

[0013] In some embodiments, the shift value of the first shift unit in the n-th first update unit is equal to the shift value of the second shift unit in the n-th second update unit, and n is less than or equal to a.

[0014] In some embodiments, the delay time of the first delay unit in each first update unit is h1, the delay time of the second delay unit in each second update unit is h2, and h1=h2.

[0015] In some embodiments, the decoder further comprises a first selector, the first selector comprises a first input end, a second input end and a first output end, the first input end is connected with the a-th first update unit, the second input end is configured to receive an all-zero message, and the first output end is connected with each second update unit from the first second update unit to the a-1-th second update unit.

[0016] The first selector is configured to select the message of the second input end as the output message of the first output end in a first time period, and select the message of the first input end as the output message of the first output end in a second time period.

[0017] In some embodiments, the decoder further comprises a second selector, the second selector comprising a third input end, a fourth input end, a second output end, the third input end being configured to receive the variable node message corresponding to each column of the check matrix, the fourth input end being connected with the first-stage second update unit, and the second output end being connected with the a-stage second update unit.

[0018] The second selector is configured to select the message of the third input end as the output message of the second output end in a first time period, and select the message of the fourth input end as the output message of the second output end in a second time period.

[0019] In some embodiments, the decoder further comprises a parity check circuit, the parity check circuit being connected with the variable node update circuit.

[0020] The parity check circuit is configured to receive the variable node message of the variable node update circuit, and substitute the received variable node message into the check equation for checking, if all the check equations are satisfied, it is determined that the decoding is successful; if all the check equations are not satisfied, it is determined that the decoding fails, and the check node message and the variable node message need to be updated in the next iteration until the decoding is successful or the maximum number of iterations is reached.

[0021] In some embodiments, the decoder further comprises:

[0022] a third selector, the third selector comprising a fifth input end, a sixth input end, a third output end, the fifth input end being configured to receive the initial channel message corresponding to each column of the check matrix, the sixth input end being connected with the first-stage second update unit, and the third output end being connected with the second-stage to the a-stage first update unit.

[0023] The third selector is configured to select the message of the fifth input end as the output message of the third output end in a first time period in a first iteration process.

[0024] In a first time period in the next iteration process, the message of the sixth input end is selected as the output message of the third output end.

[0025] According to a second aspect of the embodiments of the present disclosure, a memory controller is provided, comprising the decoder as described in any of the above embodiments.

[0026] According to a third aspect of the embodiments of the present disclosure, a memory system is provided, comprising the memory controller described in the above embodiments and a memory device coupled with the memory controller.

[0027] According to a fourth aspect of the embodiments of the present disclosure, an electronic device is provided, comprising the decoder described in any of the above embodiments and a memory device coupled with the decoder.

[0028] According to a fifth aspect of the embodiments of the present disclosure, a decoding method is provided, in which a frame of codewords including a*a sub-matrices is decoded, a plurality of sub-matrices in the same row of the check matrix constitute a layer of the check matrix, a plurality of sub-matrices in the same column of the check matrix constitute a column of the check matrix, and the method comprises:

[0029] In the first time period, each of the first updating units at levels other than the first level receives variable node messages corresponding to each column of the check matrix in turn, and each of the first updating units at levels other than the first level calculates the received variable node messages and the messages in the first updating unit at the previous level, to obtain check node messages corresponding to different layers of the check matrix in different first updating units at the a levels;

[0030] In the first time period, the second updating unit at the a level receives variable node messages corresponding to each column of the check matrix in turn, and each of the second updating units at levels other than the a level receives messages of the second updating unit at the next level and calculates, to obtain corresponding intermediate calculation values in different second updating units at the a levels;

[0031] In the second time period, each of the second updating units at levels other than the a level receives check node messages corresponding to each layer of the check matrix in turn, and each of the second updating units at levels other than the a level calculates the received check node messages and the intermediate calculation values of the second updating unit at the next level, to obtain variable node messages corresponding to different columns of the check matrix in different second updating units at the a levels.

[0032] In some embodiments, each of the first updating units at levels comprises a first delay unit, each of the first updating units at levels from the first level to the a-1 level further comprises a first shift unit, and each of the first updating units at levels from the second level to the a level further comprises a comparison unit.

[0033] The method comprises that the first delay unit outputs the updated messages in each of the first updating units at levels in a delayed manner, the first shift unit shifts the updated messages in the first updating unit, and the comparison unit compares the shifted messages in the first updating unit at the previous level with the received variable node messages to obtain a minimum value.

[0034] In some embodiments, the method further comprises:

[0035] In the second time period, the comparison units in the second stage to the a-th stage first updating units are closed.

[0036] In some embodiments, each stage second updating unit comprises a second delay unit, and the first stage to the a-1-th stage second updating units each further comprises an addition unit, a second shift unit;

[0037] The method further comprises that the second delay unit outputs the updated message in each stage second updating unit with a delay, the second shift unit shifts the updated message in the second updating unit, and the addition unit adds the message in the next stage second updating unit to the received variable node message.

[0038] In some embodiments, the decoder further comprises a first selector, which comprises a first input end, a second input end, and a first output end, the first input end is connected with the a-th stage first updating unit, the second input end is used for receiving all-zero message, and the first output end is connected with the first stage to the a-1-th stage second updating units;

[0039] The method further comprises that in the first time period, the message of the second input end is selected as the output message of the first output end, and in the second time period, the message of the first input end is selected as the output message of the first output end.

[0040] In some embodiments, the decoder further comprises a second selector, which comprises a third input end, a fourth input end, and a second output end, the third input end is used for receiving the variable node message corresponding to each column of the check matrix, the fourth input end is connected with the first stage second updating unit, and the second output end is connected with the a-th stage second updating unit.

[0041] The method further comprises that in the first time period, the message of the third input end is selected as the output message of the second output end, and in the second time period, the message of the fourth input end is selected as the output message of the second output end.

[0042] In some embodiments, the decoder further comprises a parity check circuit, which is connected with the variable node updating circuit.

[0043] The method further comprises that the variable node message of the variable node updating circuit is received, the received variable node message is substituted into the check equation for checking, if all the check equations are satisfied, it is determined that the decoding is successful, if all the check equations are not satisfied, it is determined that the decoding fails, and the check node message and the variable node message need to be updated in the next iteration until the decoding is successful or the maximum iteration number is reached.

[0044] In some embodiments, the decoder further comprises a third selector, the third selector comprising a fifth input, a sixth input, and a third output, the fifth input configured to receive the initial channel messages corresponding to the columns of the parity check matrix, the sixth input connected to the second update unit of the first stage, and the third output connected to the first update unit of the second stage to the a-th stage;

[0045] The method further comprises: in the first time period, selecting the message of the fifth input as the output message of the third output;

[0046] In the next iteration process, the message of the sixth input is selected as the output message of the third output. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figure 1 Schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0048] Figure 2a Schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0049] Figure 2b Schematic diagram of an exemplary solid state drive having a memory system according to an embodiment of the present disclosure;

[0050] Figure 3a Schematic diagram of a distribution of memory cells of a three-dimensional NAND type memory according to an embodiment of the present disclosure;

[0051] Figure 3b Schematic diagram of an exemplary memory device comprising a peripheral circuit according to an embodiment of the present disclosure;

[0052] Figure 4 Schematic diagram of a cross-section of a memory array comprising memory strings according to an embodiment of the present disclosure;

[0053] Figure 5 Schematic diagram of an exemplary memory comprising a memory array and a peripheral circuit according to an embodiment of the present disclosure;

[0054] Figure 6 Schematic diagram of a framework structure of a decoder according to an embodiment of the present disclosure;

[0055] Figure 7 Schematic diagram of a structure of a decoder according to an embodiment of the present disclosure;

[0056] Figure 8 Schematic diagram of a memory system according to an embodiment of the present disclosure;

[0057] Figure 9 Schematic diagram of an implementation flow of a decoding method according to an embodiment of the present disclosure;

[0058] Figure 10 A schematic diagram of a framework flow of a coding method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0059] Exemplary embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure can be embodied in various forms without being limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0060] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail so as not to unnecessarily complicate the present disclosure. In addition, it is to be understood that the terminology used herein is for the purpose of describing the particular embodiments only and is not intended to be limiting.

[0061] In the drawings, the size of layers, regions, elements, and the like can be exaggerated for clarity. Like reference numerals designate like elements throughout the specification.

[0062] It will be understood that when an element or layer is referred to as being "on" or "adjacent" another element or layer, it can be directly on the other element or layer or intervening elements or layers can also be present. In contrast, when an element is referred to as being "directly on" or "directly adjacent" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0063] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or

[0064] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0065] In order to enable a more detailed understanding of the features and technical content of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings, which are only used for reference and do not limit the embodiments of the present disclosure.

[0066] Figure 1 A block diagram of an exemplary system 100 having a memory in accordance with some aspects of the present disclosure is shown. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality device, or any other suitable electronic device having a memory. As shown in FIG. 1, the system 100 can include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 can be a processor (e.g., a central processing unit) or a system-on-a-chip (e.g., an application processor) of an electronic device. The host 108 can be configured to send data to or receive data from the memory device 104. Figure 1 The memory system 102 can be configured to store data received from the host 108. The memory system 102 can include one or more memory devices 104. The memory device 104 can be a volatile memory device, a non-volatile memory device, or a combination thereof. The memory device 104 can be a dynamic random access memory (DRAM), a static random access memory (SRAM), a ferroelectric random access memory (FeRAM), a phase change memory (PCM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), a flash memory, a micro-LED memory, or any other suitable memory device. The memory device 104 can be a three-dimensional (3D) cross-point memory device. The memory device 104 can be a memory device having a memory array with a plurality of memory cells arranged in a plurality of rows and a plurality of columns. The memory device 104 can be a memory device having a memory array with a plurality of memory cells arranged in a plurality of tiers. The memory device 104 can be a memory device having a memory array with a plurality of memory cells arranged in a plurality of rows, a plurality of columns, and a plurality of tiers.

[0067] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as secure digital cards, compact flash memory cards, universal serial bus flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0068] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable function, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices via at least one of various interface protocols, such as USB (Universal Serial Bus), MMC (Multi-Media Card), Peripheral Component Interconnect (PCI), Peripheral Component Interconnect High Speed ​​(PCHIHS), Advanced Technology Attached Protocol (ATIP), Serial Advanced Technology Attached Protocol (STP), Parallel Advanced Technology Attached Protocol (PATP), Minicomputer Small Interface Protocol (MSIP), Enhanced Small Disk Interface (MSDI), Integrated Drive Electronic Devices (IDED) Protocol (IDED), firmware protocols, etc.

[0069] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an embedded multimedia card package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2aIn one example shown in FIG. 1, the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a compact flash card, a smart media card, a memory stick, a multimedia card, a secure digital card, a UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 with a host (e.g., the host 108 in FIG. 1). In some embodiments, the memory card 202 can be a removable memory card. Figure 1 In another example shown in FIG. 1, the memory controller 106 and the plurality of memory devices 104 can be integrated into an SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 with a host (e.g., the host 108 in FIG. 1). In some embodiments, the storage capacity and / or operating speed of the SSD 206 can be greater than the storage capacity and / or operating speed of the memory card 202. Figure 2b In another example shown in FIG. 1, the memory controller 106 and the plurality of memory devices 104 can be integrated into an SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 with a host (e.g., the host 108 in FIG. 1). In some embodiments, the storage capacity and / or operating speed of the SSD 206 can be greater than the storage capacity and / or operating speed of the memory card 202. Figure 1

[0070] Figure 3a An exemplary structure of a memory array of a three-dimensional NAND memory is given in FIG. 2. As shown in FIG. 2, the memory array of the three-dimensional NAND memory is composed of a plurality of parallel and staggered memory cell rows parallel to gate isolation structures, and every four memory cell rows are separated by a gate isolation structure and an upper select gate isolation structure. Each memory cell row includes a plurality of memory cells. The gate isolation structure can include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory array into a plurality of memory blocks (Block). The plurality of second gate isolation structures can divide the memory block into a plurality of finger memory regions (Finger). The upper select gate isolation structure disposed in the middle of each finger memory region can divide the finger memory region into two parts, thereby dividing the finger memory region into two memory slices. Figure 3a One memory block contains 6 memory slices as shown in FIG. 2. In practical applications, the number of memory slices in one memory block is not limited to this. The memory cells coupled to one word line in one memory slice can be referred to as one memory page (Page). Here, the memory page is a physical page. Figure 3a

[0071] It should be noted that the number of memory cell rows between the gate isolation structure and the upper select gate isolation structure given in FIG. 2 is only exemplary and is not intended to limit the number of memory cell rows contained in one finger memory region of the three-dimensional NAND memory in the present disclosure. In practical applications, the number of memory cell rows contained in one finger memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc. Figure 3a

[0072] Figure 3b ​​​A schematic circuit diagram illustrating an exemplary memory device 300 including peripheral circuitry is shown in accordance with some aspects of the present disclosure. The memory device 300 can be an example of the memory device 104 in Figure 1 The memory device 300 can include a memory array 301 and peripheral circuitry 302 coupled to the memory array 301. By way of example, the memory array 301 is illustrated as a three-dimensional NAND-type memory array in which memory cells 306 are provided in the form of an array of memory strings 308, each extending vertically above a substrate (not shown). In some implementations, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, e.g., a voltage or charge, that depends on the number of electrons captured within a region of the memory cell 306. Each memory cell 306 can be a floating gate type of memory cell that includes a floating gate transistor, or a charge trap type of memory cell that includes a charge-trapping transistor.

[0073] In some implementations, each memory cell 306 is a single level cell (SLC) that has two possible memory states and thus can store one bit of data. For example, a first memory state "0" can correspond to a first voltage range, and a second memory state "1" can correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) that can store more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also referred to as a triple-level cell (TLC)), or four bits per cell (also referred to as a quad-level cell (QLC)). Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take on one of three possible programmed levels from an erased state by writing one of three possible nominal storage values to the cell. A fourth nominal storage value can be used for the erased state.

[0074] As Figure 3bAs shown in FIG. 3, each memory string 308 can include a bottom selected transistor (BST) 310 at its source end and a top selected transistor (TST) 312 at its drain end. The BST 310 and the TST 312 can be configured to activate a selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled through the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TST 312 of each memory string 308 is coupled to a respective bit line (BL) 316 from which data can be read or written via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor with the TST 312) or a deselect voltage (e.g., 0V) to the respective TST 312 via one or more top selected lines (TSL) 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of the transistor with the BST 310) or a deselect voltage (e.g., 0V) to the respective BST 310 via one or more bottom selected lines (BSL) 315.

[0075] As Figure 3bAs shown in the middle, the memory strings 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic unit of data for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased at the same time. To erase the memory cells 306 in a selected memory block, the source lines 314 coupled to the selected memory block and unselected memory blocks in the same face as the selected memory block can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be appreciated that in some examples, erase operations can be performed at a half memory block level, at a quarter memory block level, or at a level having any suitable number of memory blocks or any suitable fraction of a memory block. The memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a memory page 320 of memory cells 306. The size of a memory page 320 in bits can be related to the number of memory strings 308 coupled by a word line 318 in a memory block 304. Each word line 318 can include a plurality of control gates (gate electrodes) at each memory cell 306 in the corresponding memory page 320 and a gate line coupling the control gates. In conjunction with the foregoing Figure 3a A memory page 320 includes a plurality of memory cells 306, which are isolated from each other by upper select gate isolation structures and gate isolation structures, and the plurality of memory cells between the upper select gate isolation structures and the gate isolation structures are arranged into a plurality of memory cell rows, each of which is parallel to the gate isolation structures and the upper select gate isolation structures. The memory cells in a memory slice that share the same word line form a programmable (read / write) page.

[0076] Figure 4 A cross-sectional schematic diagram of an exemplary memory array 301 including memory strings 308 is shown in accordance with some aspects of the present disclosure. As shown in the left side of the figure, the memory array 301 includes a plurality of memory strings 308, each of which includes a plurality of memory cells 306. The memory cells 306 can be arranged in a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic unit of data for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased at the same time. To erase the memory cells 306 in a selected memory block, the source lines 314 coupled to the selected memory block and unselected memory blocks in the same face as the selected memory block can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be appreciated that in some examples, erase operations can be performed at a half memory block level, at a quarter memory block level, or at a level having any suitable number of memory blocks or any suitable fraction of a memory block. The memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a memory page 320 of memory cells 306. The size of a memory page 320 in bits can be related to the number of memory strings 308 coupled by a word line 318 in a memory block 304. Each word line 318 can include a plurality of control gates (gate electrodes) at each memory cell 306 in the corresponding memory page 320 and a gate line coupling the control gates. In conjunction with the foregoing Figure 4 As shown, the memory strings 308 can include a layer stack 410 including a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked one after another, and the memory strings 308 vertically penetrating the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 can be alternately stacked, and two adjacent gate layers 411 are separated by one insulating layer 412. The number of memory cells included in the memory array 301 is mainly related to the number of pairs of gate layers 411 and insulating layers 412 in the layer stack 410.

[0077] The constituent material of the gate layers 411 can include an electrically conductive material. The electrically conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, each gate layer 411 includes a metal layer, e.g., a tungsten layer. In some implementations, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 can include a control gate that surrounds a memory cell. The gate layers 411 at the top of the layer stack 410 can laterally extend as upper select gate lines, the gate layers 411 at the bottom of the layer stack 410 can laterally extend as lower select gate lines, and the gate layers 411 that laterally extend between the upper select gate lines and the lower select gate lines can as word line layers.

[0078] In some embodiments, the layer stack 410 can be disposed on a substrate 401. The substrate 401 can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0079] In some embodiments, the memory string 308 includes a channel structure that extends vertically through the layer stack 410. In some implementations, the channel structure includes a channel hole that is filled with a semiconductor material(s) (e.g., as a semiconductor channel) and a dielectric material(s) (e.g., as a memory film). In some implementations, the semiconductor channel includes silicon, e.g., polysilicon. In some implementations, the memory film is a composite dielectric layer that includes a tunneling layer, a storage layer (also referred to as a “charge trapping / storage layer”), and a blocking layer. The channel structure can have a cylindrical shape (e.g., a column shape). According to some implementations, the semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0080] Referring back to Figure 3bThe peripheral circuitry 302 can be coupled to the memory array 301 through the bit lines 316, the word lines 318, the source lines 314, the BSLs 315, and the TSLs 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory array 301 by applying voltage signals and / or current signals to and sensing voltage signals and / or current signals from each target memory cell 306 through the bit lines 316, the word lines 318, the source lines 314, the BSLs 315, and the TSLs 313. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor technology. For example, Figure 5 Some example peripheral circuitry is shown, the peripheral circuitry 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic circuit 512, registers 514, an interface 516, and a data bus 518. It should be understood that additional peripheral circuitry not shown in FIG. 5 can also be included in some examples. Figure 5

[0081] The page buffer / sense amplifier 504 can be configured to read data from and program (write) data to the memory array 301 according to control signals from the control logic circuit 512. In one example, the page buffer / sense amplifier 504 can store a page of program data (write data) to be programmed into one page 320 of the memory array 301. In another example, the page buffer / sense amplifier 504 can perform a program verify operation to ensure that data has been correctly programmed into the memory cells 306 coupled to a selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306 and amplify a small voltage swing to an identifiable logic level in a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic circuit 512 and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0082] ​Row decoders / word line drivers 508 can be configured to be controlled by control logic circuit 512 and to select / deselect memory blocks 304 of memory array 301 and to select / deselect word lines 318 of memory blocks 304. Row decoders / word line drivers 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, row decoders / word line drivers 508 can also select / deselect and drive BSLs 315 and TSLs 313. As described in detail below, row decoders / word line drivers 508 are configured to perform program operations on memory cells 306 coupled to selected word line(s) 318. Voltage generator 510 can be configured to be controlled by control logic circuit 512 and to generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to memory array 301.

[0083] Control logic circuit 512 can be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. Registers 514 can be coupled to control logic circuit 512 and include status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses used to control the operation of each of the peripheral circuits. Interface 516 can be coupled to control logic circuit 512 and act as a control buffer to buffer and relay control commands received from a host (not shown) to control logic circuit 512 and to buffer and relay status information received from control logic circuit 512 to the host. Interface 516 can also be coupled to column decoders / bit line drivers 506 via data bus 518 and act as a data I / O interface and data buffer to buffer and relay data to and from memory array 301.

[0084] The memory device in the embodiments of the present disclosure includes, but is not limited to, a three-dimensional NAND type memory, and is described by taking the three-dimensional NAND type memory as an example for ease of understanding.

[0085] Three-dimensional NAND type memory as a more stable storage device than the traditional magnetic disk storage, data read and write more quickly and conveniently, has penetrated into every corner of daily life. In order to meet the increasing demand for storage, the process size of three-dimensional NAND type memory is continuously reduced, the number of information bits in a single flash memory cell is increased, and the type of storage cell is continuously developed from SLC to MLC, TLC, QLC, which in turn causes the error probability of flash memory to rise. The traditional Bose Chaudhuri Hocquenghem (BCH) error correction code is not enough to ensure data security. As a kind of error correction method with error correction capability close to Shannon limit, low density parity check code (LDPC, Low Density Parity Check) is gradually replacing BCH and becoming the error correction coding method in the new generation of flash memory controller.

[0086] Figure 6 A framework structure diagram of a decoder proposed in an embodiment of the present disclosure is shown in Figure 6 The decoder includes a posterior probability storage circuit, a permutation circuit, a message update circuit, an inverse permutation circuit, and a node message storage circuit. In the decoding process, the posterior probability message in the posterior probability storage circuit is permuted by the permutation circuit, the check node message is updated in the message update circuit, and the updated check node message is obtained by the inverse permutation circuit.

[0087] LDPC codes can be divided into several types according to the construction method, one of which is based on Euclidean geometry (EG, Euclidean Geometries) and projective geometry (PG, Projective Geometries) on finite field, collectively known as finite geometric code (FG, Finite Geometric), which is known to have excellent error correction performance and a larger minimum distance. However, because the EG-LDPC code has a higher row weight and column weight, it is not conducive to implementation using the decoding architecture shown in Figure 6 or using the method of successive algorithm (MSA, Method of Successive Algorithm) and other algorithms. At present, the decoding of Euclidean geometry low density parity check (EG-LDPC, (Euclidean Geometries Low Density Parity Check)) code is mainly improved through algorithm, and the improvement of the decoder architecture is generally less. How to improve the decoder architecture to improve the throughput and reduce the resource usage becomes a problem to be solved.

[0088] Based on one or more of the above problems, an embodiment of the present disclosure provides a decoder, as shown in Figure 7As shown, the check matrix corresponding to one frame of code words includes a*a sub-matrices, a plurality of sub-matrices located in the same row of the check matrix constitute a layer of the check matrix, a plurality of sub-matrices located in the same column constitute a column of the check matrix, and the decoder includes:

[0089] The check node update circuit 701 includes a first update unit at each level, and the first update units at different levels are connected in sequence; the variable node update circuit 702 is connected with the check node update circuit 701, and the variable node update circuit 702 includes a second update unit at each level, and the second update units at different levels are connected in sequence; wherein,

[0090] In the first time period, the check node update circuit 701 is configured to: each first update unit at a level except the first level receives the variable node messages corresponding to each column of the check matrix in sequence, and calculates the received variable node messages and the messages in the first update unit at the previous level in sequence to obtain the check node messages corresponding to different layers of the check matrix in different first update units at the a levels;

[0091] In the first time period, the variable node update circuit 702 is configured to: the second update unit at the a level receives the variable node messages corresponding to each column of the check matrix in sequence, and each second update unit at a level except the second update unit at the a level receives the messages of the second update unit at the next level and calculates in sequence to obtain the corresponding intermediate calculation values in different second update units at the a levels;

[0092] In a second time period after the first time period, the variable node update circuit 702 is configured to: each second update unit at a level except the second update unit at the a level receives the check node messages corresponding to each layer of the check matrix in sequence, and calculates the received check node messages and the intermediate calculation values of the second update unit at the next level in sequence to obtain the variable node messages corresponding to different columns of the check matrix in different second update units at the a levels.

[0093] In some specific examples, each first update unit at a level is connected with the first update unit at the previous level and the first update unit at the next level, and the first update unit at the a level is connected with the first update unit at the first level; each second update unit at a level of the variable node update circuit 702 is connected with the second update unit at the previous level and the second update unit at the next level, and the second update unit at the a level is connected with the second update unit at the first level.

[0094] Here, a and n in the following are both positive integers greater than zero.

[0095] An exemplary check matrix is shown in Table 1. The following exemplary description is given with the check matrix shown in Table 1 as an example. The check matrix shown in Table 1 includes 5*5 sub-matrices. The plurality of sub-matrices located in the same row of the check matrix constitutes a layer of the check matrix, and there are 5 layers in total. The plurality of sub-matrices located in the same column of the check matrix constitutes a column of the check matrix, and there are 5 columns in total.B i represents a cyclic permutation matrix, and the value of i corresponds to the column number of the non-zero element in the first row of the cyclic permutation matrix. -1 represents a full zero matrix. Here, the variable node messages corresponding to the first column to the fifth column of the check matrix are L0, L1, L2, L3, and L4 in turn, and the check node messages corresponding to the first layer to the fifth layer of the check matrix are C0, C1, C2, C3, and C4 in turn.

[0096]

[0097] Table 1

[0098] The following exemplary description is given with the check matrix shown in Table 1 as an example to describe the case of the decoder of the above embodiment in the first iteration process.

[0099] In the case where the check matrix includes 5*5 sub-matrices, the check node update circuit 701 of the decoder includes 5 stages of first update units, and the variable node update circuit 702 includes 5 stages of second update units. The first time period includes five first sub-time periods, and the second time period includes five second sub-time periods. The duration of each of the five first sub-time periods is equal, the duration of each of the five second sub-time periods is equal, and the duration of the first sub-time period is equal to the duration of the second sub-time period.

[0100] It should be noted that the check matrix and the number of stages of the corresponding first update unit and second update unit listed here are only exemplary and do not limit the number of stages of the check matrix and the first update unit and the second update unit in the embodiments of the present disclosure.

[0101] In the jth first sub-time period, the second stage to the fifth stage of the first update unit each receive the initial channel message L j-1and the message of the first updating unit at the upper level in the last time period, to obtain a minimum value, thereby obtaining an intermediate calculation value, in the next first sub-time period, the value of the intermediate calculation value in the first updating unit at the upper level after permutation is passed to the first updating unit at the next level to participate in the calculation of the first updating unit at the next level, to obtain the intermediate calculation value of the first updating unit at the next level in the next sub-time period. After five first sub-time periods, the check node message corresponding to the fifth layer of the check matrix is obtained in the first updating unit at the first level, the check node message corresponding to the fourth layer of the check matrix is obtained in the first updating unit at the second level, the check node message corresponding to the third layer of the check matrix is obtained in the first updating unit at the third level, the check node message corresponding to the second layer of the check matrix is obtained in the first updating unit at the fourth level, and the check node message corresponding to the first layer of the check matrix is obtained in the first updating unit at the fifth level.

[0102] In the jth first sub-time period, the fifth second updating unit receives the initial channel message L j-1 In the next first sub-time period, the intermediate calculation value in the second updating unit at the next level is passed to the second updating unit at the upper level to participate in the calculation of the second updating unit at the upper level, to obtain the intermediate calculation value of the second updating unit at the upper level in the next first sub-time period, in the jth first sub-time period, the first to fourth second updating units receive all-zero messages, and calculate with the message passed by the second updating unit at the next level.

[0103] In the jth second sub-time period, the fifth second updating unit receives the message after permutation of the first second updating unit, each of the first to fourth second updating units receives the message of the second updating unit at the next level and the message passed by the fifth first updating unit, and calculates the two, after five second sub-time periods, the variable node message corresponding to the fifth column of the check matrix is obtained in the first second updating unit, the variable node message corresponding to the fourth column of the check matrix is obtained in the second second updating unit, the variable node message corresponding to the third column of the check matrix is obtained in the third second updating unit, the variable node message corresponding to the second column of the check matrix is obtained in the fourth second updating unit, and the variable node message corresponding to the first column of the check matrix is obtained in the fifth second updating unit.

[0104] In some embodiments, the decoder further comprises: a first selector 703, the first selector 703 comprising a first input end 709, a second input end 710, a first output end 706, the first input end 709 being connected with the first updating unit at the a level, the second input end 710 being used for receiving all-zero messages, and the first output end 706 being connected with the first to (a-1)th second updating units;

[0105] The first selector 703 is configured to select the message of the second input end 710 as the output message of the first output end 706 in the first time period, and select the message of the first input end 709 as the output message of the first output end 706 in the second time period.

[0106] In some embodiments, the decoder further comprises a second selector 704, the second selector 704 comprising a third input end 711, a fourth input end 712, a second output end 707, the third input end 711 being configured to receive the variable node message corresponding to each column of the check matrix, the fourth input end 712 being connected with the first-stage second update unit, and the second output end 707 being connected with the a-stage second update unit.

[0107] The second selector 704 is configured to select the message of the third input end 711 as the output message of the second output end 707 in the first time period, and select the message of the fourth input end 712 as the output message of the second output end 707 in the second time period.

[0108] In some embodiments, the decoder further comprises:

[0109] A third selector 705, the third selector 705 comprising a fifth input end 713, a sixth input end 714, a third output end 708, the fifth input end 713 being configured to receive the initial channel message corresponding to each column of the check matrix, the sixth input end 714 being connected with the first-stage second update unit, and the third output end 708 being connected with the second-stage to the a-stage first update unit.

[0110] The third selector 705 is configured to select the message of the fifth input end 713 as the output message of the third output end 708 in the first time period in the first iteration process.

[0111] In the first time period in the next iteration process, the message of the sixth input end 714 is selected as the output message of the third output end 708.

[0112] It can be understood that each iteration process is divided into a first time period and a second time period, in the first iteration process, the variable node message received in the variable node update circuit 702 and the check node update circuit 701 is the initial channel message (L0L1L2L3L4), wherein L iThe initial channel message corresponding to the i-th layer of the check matrix is verified. In the first iteration, in the first time period, the first selector 703 selects the all-zero message (00000) of the second input terminal 710 as the output message of the first output terminal 706, the second selector 704 selects the message (L0L1L2L3L4) of the third input terminal 711 as the output message of the second output terminal 707, and the third selector 705 selects the message (L0L1L2L3L4) of the fifth input terminal 713 as the output message of the third output terminal 708. In the first iteration, in the second time period, the first selector 703 receives the message of the first update unit of the a-th stage in the check node update circuit 701 as the output message of the first output terminal 706, the second selector 704 receives the message of the second update unit of the first stage in the variable node update circuit 702 as the output message of the second output terminal 707, and the third output terminal 708 of the third selector 705 does not output a message. The second iteration is different from the first iteration in that, in the first time period, the third selector 705 selects the message of the sixth input terminal 714 as the output message of the third output terminal 708, that is, selects the variable node message updated in the last iteration as the output message of the third output terminal 708.

[0113] In some embodiments, each first update unit comprises a first delay unit, the first update unit to the a-1-th stage further comprises a first shift unit, and the second update unit to the a-th stage further comprises a comparison unit; the first delay unit is configured to delay the updated message in each first update unit, the first shift unit is configured to shift the updated message in the first update unit, and the comparison unit is configured to compare the shifted message in the last first update unit with the received variable node message to obtain a minimum value.

[0114] Here, the comparison unit includes but is not limited to a comparator, and the comparison unit can compare to obtain a minimum value or a second minimum value. The first update unit to the fourth update unit in the variable node update circuit 702 can further comprise a selection unit, and the selection unit is configured to select the corresponding minimum value or second minimum value. Figure 7 In the above formula, comp represents the comparison unit, and sel0-sel3 represent the selection unit.

[0115] In some embodiments, the check node update circuit 701 is configured to:

[0116] In the second time period, the comparison unit in the second update unit to the a-th update unit is closed.

[0117] It can be understood that, in the second time period, the comparison unit in the check node update circuit 701 does not work, that is, in the second time period, the value in the first update unit of the previous stage is transmitted to the first update unit of the next stage without comparison.

[0118] In some embodiments, each second update unit comprises a second delay unit, and the first second update unit to the a-1th second update unit further comprises an addition unit and a second shift unit; the second delay unit is configured to delay the updated message in each second update unit; the second shift unit is configured to shift the updated message in the second update unit; and the addition unit is configured to add the message in the second update unit of the next stage and the received variable node message.

[0119] Here, the addition unit includes but is not limited to an adder.

[0120] Figure 7 In the formula, + represents the addition unit, D represents the first delay unit and the second delay unit.

[0121] In some embodiments, the shift value of the first shift unit in the n th first update unit is equal to the shift value of the second shift unit in the n th second update unit; and n is less than or equal to a.

[0122] Figure 7 In the formula, P0-P3 represent the first shift unit in the first first update unit to the fourth first update unit, respectively, and P0-P3 represent the second shift unit in the first second update unit to the fourth second update unit, respectively.

[0123] Here, the first shift unit of the n th first update unit is represented by P n-1 , and the second shift unit of the n th second update unit is represented by P n-1 , where n-1 represents the shift value of the shift unit, and the shift value of the first shift unit of the n th first update unit is equal to the shift value of the second shift unit of the n th second update unit.

[0124] In some embodiments, the delay time of the first delay unit of each first update unit is h1, the delay time of the second delay unit of each second update unit is h2, and h1=h2.

[0125] In some specific examples, the delay time of the first delay unit is equal to the time length of the first sub-time period and the time length of the second sub-time period, the delay time of the second delay unit is equal to the time length of the first sub-time period and the time length of the second sub-time period, and the time length of the first sub-time period is equal to the time length of the second sub-time period.

[0126] In some specific examples, in the first iteration process, at the initial time before the first time period, the value after the first delay unit in the check node update circuit 701 is set to the maximum value, and the value after the second delay unit in the variable node update circuit 702 is set to 0.

[0127] The intermediate calculation values in the first update unit of each stage and the second update unit of each stage in the first iteration process of decoding will be described in detail below.

[0128] In the first first sub-time period in the first iteration process, the initial channel message L0 enters the 2nd-5th first update units in the check node update circuit 701 through the third output end 708 of the third selector 705, and in each first update unit of the 2nd-5th first update units, L0 is compared with the value after the respective first delay unit (initially set to the maximum value) and temporarily recorded as D i ; at the same time, in the first first sub-time period in the first iteration process, the initial channel message L0 enters the 5th second update unit of the variable node update circuit 702 through the second output end 707 of the second selector 704, and the all-zero message of the second input end 710 of the first selector 703 enters the first-4th second update units through the first output end 706 and is added to the value after the second delay unit (initially set to 0) in the first-4th second update units. In the second first sub-time period to the fifth first sub-time period, the initial channel message L m-1 enters the check node update circuit 701 in turn, and after comparison with the value after permutation of the intermediate calculation value updated in the previous first sub-time period in the previous first update unit, the updated intermediate calculation value is obtained in each second update unit, and at the same time, the initial channel message L m-1 enters the variable node update circuit 702 and is added to 0.

[0129] The values after the first delay units in the first-5th first update units are recorded as D0-D4 respectively, and the values after the second delay units in the first-5th second update units are recorded as D5-D9 respectively. Taking D4 in the fifth first sub-time period as an example, in the first first sub-time period, L0 enters the check node update circuit 701 and is compared with the maximum value Max, and L0 is obtained, and at this time, D i 0 = Max. In the second first sub-time period, L1 enters the check node update circuit 701 and is compared with the value of D0 after permutation by the permutation matrix P0, and D1 = min(L1 Max 0), where the upper 0 represents the permutation unit identifier. In the third first sub-time period, L2 enters the check node update circuit 701, and after comparing with the value of D1 through the permutation unit P1, D2 = min(L2L1 1 ) is obtained. In the fourth first sub-time period, L3 enters the check node update circuit 701, and after comparing with the value of D2 through the permutation unit P2, D3 = min(L3(L2L1 1 ) 2 ) is obtained. In the fifth first sub-time period, L4 enters the check node update circuit 701, and after comparing with the value of D3 through the permutation unit P3, D4 = min(L4(L3(L2L1 1 ) 2 ) 3 ) is obtained. Similarly, the values in the other first update units in the fifth first sub-time period can be derived. Table 2 shows the values of D i corresponding to the initial time period, the first first sub-time period to the fifth first sub-time period.

[0130]

[0131] Table 2

[0132] After the fifth first sub-time period, each first update unit in the check node update circuit 701 completes the minimum sum comparison process of one layer of the check matrix, and obtains the updated check node message of each layer of the check matrix. In the next second time period, the check node update circuit 701 only transmits the updated check node message obtained by each first update unit to the variable node update circuit 702 after being permuted by the permutation unit, to participate in the calculation.

[0133] The specific shift in P i will be analyzed below by taking Table 2 as an example. In the fifth first sub-time period, the value corresponding to D4 is D4 = min(L4(L3(L2L1 1 ) 2 ) 3 ). The variable node message corresponding to the first column of the check matrix is L0, which does not exist in D4. It can be seen from the check matrix that D4 is the check node message of the first layer (the first column block of the first layer is 0). The check node message corresponding to the second column block B0 of the first layer is L1, which is obtained as (L1 1 ) after P1 in D4; the check node message corresponding to the third column block B1 is L2, which is obtained as min(L2L1 1 ) by comparing with (L1 1), so the message order B0 in the second column block needs to be converted into the message order B1 in the third column block, and the size of the small matrix in this example is 3*3, so the shift value of B1 is r(P1) = (r(B0) - r(B1) + 3), wherein r(P1) is the shift value of P1, and 3 is the rank of the small matrix; the check node message corresponding to the fourth column block B2 is L3, which is compared with ((L2L1 1 ) 2 ) to obtain min(L3(L2L1 1 ) 2 ), so the message order B1 in the third column block needs to be converted into the message order B2 in the fourth column block, so the shift value of P2 is r(P2) = (r(B1) - r(B2) + 3); by analogy, the shift value of P x is r(P x ) = (r(B x-1 ) - r(B x ) + 3).

[0134] Based on the check node message B3 obtained above, which is the message order of the last column, the second layer of the check matrix is then considered, and the message value of D3 is considered in the fifth first time period, and the order is the order of B2. After one P3 permutation, it becomes the order of B3 in the sixth second time period and enters the variable node update circuit 702. The remaining layers are the same, and after several permutations, they all become the order of B3 and enter the variable node update circuit 702. At the same time, it should be noted that during the first to fifth second time periods, the check node update circuit 701 only outputs the calculated check node messages in sequence. In order to prevent the comparison unit from comparing the messages corresponding to the subsequent layers with the messages after the first selector 703 when outputting the check node messages corresponding to the front layers, the comparison unit should be suspended at this time and the permuted data should be directly transmitted to the next first update unit.

[0135] Next, the D i corresponding value in the variable node update circuit 702 is introduced, and the message obtained in the check node update circuit 701 is denoted as C i (i is the layer number):

[0136] In the first first time period, the first selector 703 outputs 0, and the second selector 704 outputs L0, so D i = 0 (4 < i < 9), D9 = L0; in the second first time period, the first selector 703 outputs 0, and the second selector 704 outputs L1, so D i= 0 (4 < i < 8), D8 = L0, D9 = L1; the third first sub-time period, the first selector 703 outputs 0, the second selector 704 outputs L2, at this time D i = 0 (4 < i < 7), D7 = L0 3 , D8 = L1, D9 = L2; the fourth first sub-time period, the first selector 703 outputs 0, the second selector 704 outputs L3, at this time D i = 0 (4 < i < 6), D6 = L0 32 , D7 = L1 3 , D8 = L2, D9 = L3; the fifth first sub-time period, the first selector 703 outputs 0, the second selector 704 outputs L4, at this time D5 = L0 321 , D6 = L1 32 , D7 = L2 3 , D8 = L3, D9 = L4.

[0137] In the first second sub-time period, the first layer of the check matrix in the first update unit of the fifth stage corresponds to the updated check node message C0, i.e. min(L4(L3(L2L1 1 ) 2 ) 3 , directly enters the first stage to the fourth stage second update unit of the variable node update circuit 702, and is added to the value after permutation of the intermediate calculation value updated by the next stage second update unit in the variable node update circuit 702 in the last sub-time period. In the second to fifth second sub-time period, the check node messages of the second layer to the fifth layer of the check matrix updated in the first stage to the fourth stage first update unit enter the first stage to the fourth stage second update unit of the variable node update unit in turn after the comparison unit (closed in the second time period) and the permutation unit, and are added to the value after permutation of the intermediate calculation value updated by the next stage second update unit in the variable node update circuit 702 in the last sub-time period.

[0138] Then, the corresponding values of D i in the first to fifth second sub-time period in the variable node update circuit 702 are introduced in detail, and the message obtained in the check node update circuit 701 is denoted as C i (i is the layer number), and D5 in the fifth second sub-time period is taken as an example:

[0139] In the first second sub-time period, C0 enters the variable node update circuit 702, and is added to the value of D i (5 < i < 9), at this time D i = D i+1 + C0 (5 < i < 9), The second second sub-period, C1 enters the variable node update circuit 702, and after adding the value of D9, D8=C1+L0 is obtained 3210 ; the third second sub-period, C2 enters the variable node update circuit 702, and after adding the value of D8, D7=C2+(C1+L0 3210 ) 3 ; the fourth second sub-period, C3 enters the variable node update circuit 702, and after adding the value of D7, D6=C3+(C2+(C1+L0 3210 ) 3 ) 2 ; the fifth second sub-period, C4 enters the variable node update circuit 702, and after adding the value of D6, D5=C4+(C3+(C2+(C1+L0 3210 ) 3 ) 2 ) 1 .

[0140] Table III shows the values of D i corresponding to the first second sub-period to the fifth second sub-period.

[0141]

[0142] Table III

[0143] Similarly, the specific shift value in the variable node update circuit 702 is analyzed, and the analysis principle is roughly the same as that in the check node update circuit 701. Similarly, the D9 of the fifth second sub-period is taken as an example for brief description. At this time, D9=(C3+(C2+(C 1 +(C0+L4) 3 ) 2 ) 1 ) 0 , the first layer check node message (C0) from the check node update circuit 701 is added with the corresponding initial channel message (L4), and after passing through P3, it is added with the check node message (C1) of the next layer. Here, the check node messages from the check node update circuit 701 are all in the order of B3, but the second layer is in the order of B2. When adding, (C0+L4) needs to be replaced by P3 to be in the order of B2, and then added with C1. Therefore, r(P3)=(r(B2)-r(B3)+3), which is consistent with the shift value in the check node update circuit 701.

[0144] In some embodiments, the decoder further comprises a parity check circuit, which is connected with the variable node update circuit 702;

[0145] The parity check circuit is configured to receive the variable node message of the variable node update circuit 702, and substitute the received variable node message into the check equation for checking. If all check equations are satisfied, it is determined that decoding is successful. If all check equations are not satisfied, it is determined that decoding fails, and the check node message and the variable node message need to be updated in the next iteration until decoding is successful or the maximum number of iterations is reached.

[0146] Here, the parity check circuit can be specifically connected with the second delay unit in the first-stage second update unit in the variable node update circuit 702.

[0147] It can be understood that after the five first sub-time periods and the five second sub-time periods, the update of the check node message and the variable node message is completed, and the output in the variable node update circuit 702 will be divided into two paths, one of which is used for hard decision to determine whether decoding is successful, and the other of which outputs the check node update circuit 701 for the next iteration decoding. In the next iteration process, the third output end 708 of the third selector 705 selects the message input of the sixth input end 714 into the check node update circuit 701, and the remaining parts remain unchanged, until the entire decoding process is completed.

[0148] It can be understood that the present embodiment provides a new architecture of a decoder, which uses the first shift unit, the second shift unit, the first delay unit, the second delay unit, the comparison unit and the addition unit in the different first update units and the second update units, uses the simple shift delay function, adjusts the time length of the first delay unit and the second delay unit, and can complete the update of information.

[0149] In the present embodiment, the a-stage first update unit is used to complete the update of the check node message corresponding to each layer of the check matrix in the first time period, and the a-stage second update unit is used to complete the update of the variable node message corresponding to each column of the check matrix in the first time period and the second time period, so that the throughput can be improved and the resource utilization rate can be reduced.

[0150] Based on the above-described decoder, the present embodiment further provides a memory controller, which includes the decoder described in any of the above embodiments.

[0151] Based on the above-described memory controller, the present embodiment further provides a memory system, which includes the memory controller described in the above embodiment and a memory device coupled with the memory controller.

[0152] Figure 8A configuration block diagram of a memory system 601 is shown, which includes a memory controller 602 for controlling a memory device 603 to perform read / write operations, and the memory controller 602 and the memory device 603 can be coupled in any suitable manner. The memory controller 602 includes a control unit (e.g., a central processing unit) 608, a data buffer 609, an error correction module 606, a host I / F 605, and a memory I / F 607. In the present embodiment, the memory device 603 can be a semiconductor memory that stores data nonvolatilely, such as a NAND-type memory. The memory system 601 is connected to a host 604. The host I / F 605 outputs commands, valid data (write data), and the like received from the host 604 to an internal bus 610, and transmits valid data (read data) read from the memory device 603, responses from the control unit 608, and the like to the host 604.

[0153] The control unit 608 can instruct the memory I / F 607 to write valid data and parity data, a check matrix to the memory device 603 according to a command from the host 604, and the control unit can instruct the memory I / F 607 to read valid data and parity data, a check matrix from the memory device according to a command from the host 604.

[0154] The error correction module 606 here includes an encoding section and a decoding section, the encoding section encodes predetermined-size valid data to be written to generate parity data (e.g., a low-density parity-check code) and a corresponding check matrix, and the decoding section decodes using the parity data and the corresponding check matrix, and the decoding section here includes a decoder, and the parity-check code and the corresponding check matrix at the time of decoding can be acquired from the memory device.

[0155] Based on the above-described memory system, the present embodiment also provides an electronic device including the decoder described in any of the above embodiments, and a memory device coupled to the decoder.

[0156] Here, the decoder can be built into the memory controller, or can not be built into the memory controller, but can be provided outside the memory controller.

[0157] Here, the specific structure and composition of the memory controller, the memory system, and the electronic device can be referred to the foregoing description of the memory controller, the memory system, and the electronic device. Figure 1 、 Figure 2a 、 Figure 2b 、 Figure 3a 、 Figure 3b 、 Figure 4 、 Figure 5For the sake of brevity, the detailed description of the foregoing will not be repeated here.

[0158] Based on the above-described decoder, the embodiments of the present disclosure further provide a decoding method. In the decoding process of a frame of code words including a*a sub-matrices, a plurality of sub-matrices in the same row of the check matrix constitute a layer of the check matrix, and a plurality of sub-matrices in the same column constitute a column of the check matrix, as shown in Figure 9

[0159] In the first time period, each of the first updating units at different levels receives the variable node message corresponding to each column of the check matrix in turn, and each of the first updating units at different levels calculates the message in the previous first updating unit and the received variable node message to obtain the check node message corresponding to each layer of the check matrix in the first updating unit at different levels of the a first updating units;

[0160] In the first time period, the a-th second updating unit receives the variable node message corresponding to each column of the check matrix in turn, and each of the second updating units at different levels receives the message of the next second updating unit and calculates to obtain the corresponding intermediate calculation value in the second updating unit at different levels of the a second updating units;

[0161] In the second time period, each of the second updating units at different levels receives the check node message corresponding to each layer of the check matrix in turn, and each of the second updating units at different levels calculates the received check node message and the intermediate calculation value of the next second updating unit to obtain the variable node message corresponding to each column of the check matrix in the second updating unit at different levels of the a second updating units.

[0162] In some embodiments, each of the first updating units at different levels includes a first delay unit, and the first updating unit at the first level to the a-1th level further includes a first shift unit, and the first updating unit at the second level to the a-th level further includes a comparison unit.

[0163] The method includes that the first delay unit outputs the updated message in each of the first updating units at different levels in time delay, the first shift unit shifts the updated message in the first updating unit, and the comparison unit compares the shifted message in the first updating unit at the previous level with the received variable node message to obtain the minimum value.

[0164] In some embodiments, the method further includes:

[0165] In the second time period, the comparison unit in the second updating unit at the second level to the a-th level is turned off.

[0166] ​In some embodiments, each second update unit comprises a second delay unit, and the first to the a-1th second update units each further comprise an addition unit, a second shift unit;

[0167] The method further comprises that the second delay unit outputs the updated message in each second update unit with a delay, the second shift unit shifts the updated message in the second update unit, and the addition unit adds the message in the next second update unit to the received variable node message.

[0168] In some embodiments, the decoder further comprises a first selector comprising a first input end, a second input end, and a first output end, wherein the first input end is connected to the a-th first update unit, the second input end is configured to receive an all-zero message, and the first output end is connected to the first to the a-1th second update units.

[0169] The method further comprises that, in a first time period, the message of the second input end is selected as the output message of the first output end, and in a second time period, the message of the first input end is selected as the output message of the first output end.

[0170] In some embodiments, the decoder further comprises a second selector comprising a third input end, a fourth input end, and a second output end, wherein the third input end is configured to receive the variable node message corresponding to each column of the check matrix, the fourth input end is connected to the first second update unit, and the second output end is connected to the a-th second update unit.

[0171] The method further comprises that, in a first time period, the message of the third input end is selected as the output message of the second output end, and in a second time period, the message of the fourth input end is selected as the output message of the second output end.

[0172] In some embodiments, the decoder further comprises a parity check circuit connected to the variable node update circuit.

[0173] The method further comprises that the variable node message of the variable node update circuit is received, and the received variable node message is substituted into the check equation for checking. If all the check equations are satisfied, it is determined that the decoding is successful. If all the check equations are not satisfied, it is determined that the decoding fails, and the next iteration of updating the check node message and the variable node message is required until the decoding is successful or the maximum number of iterations is reached.

[0174] In some embodiments, the decoder further comprises a third selector, the third selector comprising a fifth input end, a sixth input end, and a third output end, the fifth input end being configured to receive the initial channel messages corresponding to the columns of the check matrix, the sixth input end being connected with the second updating unit of the first stage, and the third output end being connected with the first updating unit of the second stage to the a-th stage;

[0175] The method further comprises: in the first time period, selecting the message of the fifth input end as the output message of the third output end;

[0176] In the next iteration process, the message of the sixth input end is selected as the output message of the third output end.

[0177] Figure 10 A framework flowchart of a decoding method provided by the embodiments of the present disclosure is shown in the following. Figure 10 The decoding method of the embodiments of the present disclosure is further introduced.

[0178] In the first iteration process, the initial channel messages are first stored in the posterior probability storage circuit, and the check node updating circuit receives the initial channel messages L0, L1, L2, L3, and L4 in sequence in the first time period. The minimum or sub-minimum value is obtained after the initial channel messages pass through the comparison unit, and the check node messages corresponding to the first layer to the fifth layer of the updated check matrix are obtained after five first sub-time periods. In the variable node updating circuit, the initial channel messages and the updated check node messages are accumulated to obtain the updated variable node messages, and the updated variable node messages are obtained after five second sub-time periods. After updating the variable node messages, it is determined whether the maximum iteration number is reached. If the maximum iteration number is reached, the code word is output, and if the maximum iteration number is not reached, the next iteration is performed.

[0179] The decoding method has been described in detail on the decoder side, and will not be described here for brevity.

[0180] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the size of the sequence number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The sequence number of the above embodiments of the present disclosure is only for description, and does not represent the advantages and disadvantages of the embodiments.

[0181] The methods disclosed in the several method embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments.

[0182] The above merely provides a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A decoder, characterized in that, The parity check matrix corresponding to one frame of codewords includes a*a submatrices. Multiple submatrices in the same row constitute one layer of the parity check matrix, and multiple submatrices in the same column constitute one column of the parity check matrix. The decoder includes: The verification node update circuit includes a level A first update unit, with each level of the first update unit connected sequentially; the variable node update circuit is connected to the verification node update circuit, and the variable node update circuit includes a level A second update unit, with each level of the second update unit connected sequentially; wherein... During the first time period, the verification node update circuit is configured such that: each level of the first update unit except the first level first update unit receives the variable node messages corresponding to each column of the verification matrix in sequence, and calculates the received variable node messages with the messages in the previous level first update unit in sequence, and obtains the verification node messages corresponding to different layers of the verification matrix in different levels of the first update unit in the a level first update unit. During the first time period, the variable node update circuit is configured such that: the a-th level second update unit sequentially receives the variable node messages corresponding to each column of the verification matrix; the second update units at each level other than the a-th level second update unit sequentially receive messages from the next level second update unit and perform calculations; and the corresponding intermediate calculated values ​​are obtained in the different levels of the a-th level second update unit. In the second time period following the first time period, the variable node update circuit is configured such that: each level of the second update unit except for the a-th level second update unit receives the verification node messages corresponding to each layer of the verification matrix in sequence, and calculates the received verification node messages with the intermediate calculation values ​​of the next level second update unit in sequence, thereby obtaining the variable node messages corresponding to different columns of the verification matrix in different levels of the second update unit in the a-th level second update unit.

2. The decoder according to claim 1, characterized in that, Each level of the first update unit includes a first delay unit, and the first update units from the first level to the (a-1)th level also include a first shift unit, and the first update units from the second level to the ath level also include a comparison unit; the first delay unit is used to delay the output of the updated message in each level of the first update unit, the first shift unit is used to shift the updated message in the first update unit, and the comparison unit is used to compare the shifted message in the previous level of the first update unit with the received variable node message to obtain the minimum value.

3. The decoder according to claim 2, characterized in that, The verification node update circuit is configured as follows: During the second time period, the comparison units in the second level to the first update unit of level a are closed.

4. The decoder according to claim 2, characterized in that, Each level of the second update unit includes a second delay unit, and the first to a-1 level second update units also include an addition unit and a second shift unit; the second delay unit is used to delay the output of the updated message in each level of the second update unit, the second shift unit is used to shift the updated message in the second update unit, and the addition unit is used to add the message in the next level of the second update unit to the received variable node message.

5. The decoder according to claim 4, characterized in that, The shift value of the first shift unit in the first update unit of level n is equal to the shift value of the second shift unit in the second update unit of level n; n is less than or equal to a.

6. The decoder according to claim 4, characterized in that, The delay duration of the first delay unit in each first update unit is h1, and the delay duration of the second delay unit in each second update unit is h2, and h1=h2.

7. The decoder according to claim 1, characterized in that, The decoder further includes: a first selector, the first selector including a first input terminal, a second input terminal, and a first output terminal, the first input terminal being connected to the first update unit of the a-th level, the second input terminal being used to receive all-zero messages, and the first output terminal being connected to the second update units of the first level to the (a-1)-th level. The first selector is configured to: select a message from the second input terminal as the output message of the first output terminal during a first time period; and select a message from the first input terminal as the output message of the first output terminal during a second time period.

8. The decoder according to claim 1, characterized in that, The decoder further includes: a second selector, the second selector including a third input terminal, a fourth input terminal, and a second output terminal; the third input terminal is used to receive variable node messages corresponding to each column of the parity check matrix, the fourth input terminal is connected to the first-level second update unit, and the second output terminal is connected to the a-th level second update unit; The second selector is configured to: select a message from the third input terminal as the output message of the second output terminal during a first time period; and select a message from the fourth input terminal as the output message of the second output terminal during a second time period.

9. The decoder according to claim 1, characterized in that, The decoder also includes a parity check circuit, which is connected to the variable node update circuit. The parity check circuit is configured to: receive the variable node message from the variable node update circuit, and substitute the received variable node message into the check equation for verification. If all check equations are satisfied, the decoding is determined to be successful; if all check equations are not satisfied, the decoding is determined to be unsuccessful, and the check node message and variable node message need to be updated in the next iteration until the decoding is successful or the maximum number of iterations is reached.

10. The decoder according to claim 9, characterized in that, The decoder also includes: The third selector includes a fifth input terminal, a sixth input terminal, and a third output terminal. The fifth input terminal is used to receive the initial channel messages corresponding to each column of the parity check matrix. The sixth input terminal is connected to the first-level second update unit. The third output terminal is connected to the second-level to the a-th-level first update units. The third selector is configured to: select the message from the fifth input terminal as the output message from the third output terminal during the first time period of the first iteration process; In the first time period of the next iteration, the message from the sixth input terminal is selected as the output message from the third output terminal.

11. A memory controller comprising the decoder as described in any one of claims 1-10.

12. A memory system comprising a memory controller as claimed in claim 11 and a memory device coupled to the memory controller.

13. An electronic device comprising a decoder as claimed in any one of claims 1-10, and a memory device coupled to said decoder.

14. A decoding method, characterized in that, In the process of decoding a frame of codewords comprising an a*a submatrix of a parity check matrix, multiple submatrixes located in the same row of the parity check matrix constitute one layer of the parity check matrix, and multiple submatrixes located in the same column constitute one column of the parity check matrix. The method includes: In the first time period, all first update units except the first-level first update unit sequentially receive the variable node messages corresponding to each column of the verification matrix, and sequentially calculate the received variable node messages with the messages in the previous first update unit, thereby obtaining the verification node messages corresponding to different layers of the verification matrix in different first update units in the a-level first update unit. In the first time period, the second update unit of level a sequentially receives the variable node messages corresponding to each column of the verification matrix. The second update units at each level other than the second update unit of level a sequentially receive the messages of the next level second update unit and calculate, and obtain the corresponding intermediate calculated values ​​in the different levels of the second update units in the second update unit of level a. During the second time period, all levels of the second update unit except for the a-th level second update unit receive the verification node messages corresponding to each layer of the verification matrix in sequence, and calculate the received verification node messages with the intermediate calculation values ​​of the next level second update unit in sequence, thereby obtaining the variable node messages corresponding to different columns of the verification matrix in different levels of the second update unit in the a-th level second update unit.

15. The method according to claim 14, characterized in that, Each level of first update unit includes a first delay unit, and the first update units from the first level to the (a-1)th level also include a first shift unit, and the first update units from the second level to the ath level also include a comparison unit. The method includes: the first delay unit delays the output of the message updated in each level first update unit, the first shift unit shifts the message updated in the first update unit, and the comparison unit compares the shifted message in the previous level first update unit with the received variable node message to obtain the minimum value.

16. The method according to claim 15, characterized in that, The method further includes: During the second time period, the comparison units in the second level to the first update unit of level a are closed.

17. The method according to claim 15, characterized in that, Each level of the second update unit includes a second delay unit, and the second update units from the first level to the a-1th level also include an addition unit and a second shift unit; The method further includes: the second delay unit delays the output of the message updated in each level of the second update unit, the second shift unit shifts the message updated in the second update unit, and the addition unit adds the message in the next level of the second update unit to the received variable node message.

18. The method according to claim 14, characterized in that, The decoder executing the decoding method further includes: a first selector, the first selector including a first input terminal, a second input terminal, and a first output terminal, the first input terminal being connected to the first update unit of the a-th level, the second input terminal being used to receive all-zero messages, and the first output terminal being connected to the second update units of the first level to the (a-1)-th level. The method further includes: in a first time period, selecting a message from the second input terminal as the output message of the first output terminal; and in a second time period, selecting a message from the first input terminal as the output message of the first output terminal.

19. The method according to claim 14, characterized in that, The decoder executing the decoding method further includes: a second selector, the second selector including a third input terminal, a fourth input terminal, and a second output terminal; the third input terminal is used to receive variable node messages corresponding to each column of the parity check matrix, the fourth input terminal is connected to the first-level second update unit, and the second output terminal is connected to the a-th level second update unit; The method further includes: in a first time period, selecting a message from a third input terminal as the output message of a second output terminal; and in a second time period, selecting a message from a fourth input terminal as the output message of a second output terminal.

20. The method according to claim 14, characterized in that, The decoder that performs the decoding method further includes a parity check circuit, which is connected to the variable node update circuit; The method further includes: receiving the variable node message from the variable node update circuit, and substituting the received variable node message into the verification equation for verification. If all verification equations are satisfied, the decoding is determined to be successful; if all verification equations are not satisfied, the decoding is determined to be unsuccessful, and the verification node message and variable node message need to be updated in the next iteration until the decoding is successful or the maximum number of iterations is reached.

21. The method according to claim 20, characterized in that, The decoder further includes a third selector, which includes a fifth input, a sixth input, and a third output. The fifth input is used to receive the initial channel message corresponding to each column of the parity check matrix. The sixth input is connected to the first-level second update unit, and the third output is connected to the second-level to the a-th-level first update units. The method further includes: during the first time period, selecting the message from the fifth input terminal as the output message from the third output terminal; In the next iteration, the message from the sixth input terminal is selected as the output message from the third output terminal.

Images