Memory control method, control circuit and memory

Abstract

The invention provides a memory control method, a control circuit and a memory, the memory comprises a memory unit, the memory unit is connected with a bit line, the control method comprises the following steps: obtaining the working temperature of the memory, and adjusting the voltage of the memory unit in the memory according to the working temperature of the memory. Wherein the voltage of the storage unit comprises one or more of the voltage of the capacitor upper pole plate when the storage unit stores the first data, the voltage of the bit line before the transistor in the storage unit is started and the gate starting voltage of the transistor, and the voltage of the capacitor upper pole plate is larger than the voltage of the capacitor lower pole plate when the storage unit stores the first data.

Description

Technical Field

[0001] The present application relates to but is not limited to a memory control method, a control circuit and a memory. Background Art

[0002] With the development of memory technology, memories are widely used in various fields. For example, dynamic random access memory (DRAM) is widely used.

[0003] Therefore, the performance of the memory includes but is not limited to various timing parameters, data read accuracy and power consumption. The present application aims to improve the performance of the memory. Summary of the invention

[0004] The present application provides a control method for a memory, wherein the memory includes a storage unit connected to a bit line, and the method includes:

[0005] Get the operating temperature of the memory;

[0006] adjusting the voltage of a storage unit in the memory according to the operating temperature of the memory;

[0007] Among them, the voltage of the storage unit includes one or more of the voltage of the upper plate of the capacitor when the storage unit stores the first data, the voltage on the bit line before the transistor in the storage unit is turned on, and the gate turn-on voltage of the transistor. When the storage unit stores the first data, the voltage of the upper plate of the capacitor is greater than the voltage of the lower plate of the capacitor.

[0008] In some embodiments, adjusting the voltage of a storage unit in the memory according to the operating temperature of the memory specifically includes at least one of the following:

[0009] When the operating temperature of the memory is less than or equal to the first temperature threshold, controlling the voltage of the upper plate of the capacitor to be greater than the upper plate reference voltage when the storage unit stores the first data;

[0010] When the operating temperature of the memory is less than or equal to a first temperature threshold, controlling the voltage on the bit line before the transistor in the memory cell is turned on to be greater than a bit line reference voltage; and

[0011] When the operating temperature of the memory is less than or equal to the first temperature threshold, the gate turn-on voltage of the control transistor is the gate reference voltage.

[0012] In some embodiments, adjusting the voltage of a storage unit in the memory according to the operating temperature of the memory specifically includes at least one of the following:

[0013] When the operating temperature of the memory is greater than a second temperature threshold, controlling the voltage of the upper plate of the capacitor to be less than the upper plate reference voltage when the storage unit stores the first data;

[0014] When the operating temperature of the memory is greater than a second temperature threshold, controlling the voltage on the bit line before the transistor in the memory cell is turned on to be less than a bit line reference voltage; and

[0015] When the operating temperature of the memory is greater than a second temperature threshold, the gate turn-on voltage of the control transistor is less than the gate reference voltage;

[0016] The second temperature threshold is greater than the first temperature threshold.

[0017] In some embodiments, adjusting the voltage of a storage unit in a memory according to an operating temperature of the memory specifically includes:

[0018] When the operating temperature of the memory is greater than a first temperature threshold and less than or equal to a second temperature threshold, the voltage of the storage unit in the memory is adjusted according to the model of the memory, wherein the second temperature threshold is greater than the first temperature threshold.

[0019] In some embodiments, when the operating temperature of the memory is greater than the first temperature threshold and the operating temperature of the memory is less than or equal to the second temperature threshold, according to the model of the memory, specifically including:

[0020] When the operating temperature of the memory is greater than a first temperature threshold, the operating temperature of the memory is less than or equal to a second temperature threshold, and the type of the memory is low power consumption, controlling the voltage of the upper plate of the capacitor to be an upper plate reference voltage when the storage unit stores the first data; and

[0021] When the operating temperature of the memory is greater than the first temperature threshold, the operating temperature of the memory is less than or equal to the second temperature threshold, and the type of the memory is low power consumption, the voltage on the bit line before the transistor in the storage unit is turned on is controlled to be the bit line reference voltage.

[0022] In some embodiments, adjusting the voltage of a storage unit in the memory according to the model of the memory and the operating temperature of the memory specifically includes at least one of the following:

[0023] When the operating temperature of the memory is greater than the first temperature threshold, the operating temperature of the memory is less than or equal to the second temperature threshold; and the type of the memory is not low power consumption, controlling the voltage of the upper plate of the capacitor to be less than the upper plate reference voltage when the storage unit stores the first data; and

[0024] When the operating temperature of the memory is greater than the first temperature threshold, the operating temperature of the memory is less than or equal to the second temperature threshold, and the type of the memory is not low power consumption, the voltage on the bit line before the transistor in the storage unit is turned on is controlled to be less than the bit line reference voltage.

[0025] In some embodiments, when the first condition is met, the voltage of the upper plate of the capacitor when the storage unit stores the first data is greater than the voltage of the upper plate of the capacitor when the storage unit stores the first data when the second condition is met;

[0026] Among them, satisfying the first condition specifically includes: the operating temperature of the memory is greater than the first temperature threshold, the operating temperature of the memory is less than or equal to the second temperature threshold, and the type of the memory is not low power consumption; satisfying the second condition specifically includes: the operating temperature of the memory is greater than the second temperature threshold.

[0027] In some embodiments, the voltage on the bit line before the transistor in the memory cell is turned on when the first condition is satisfied is greater than the voltage on the bit line before the transistor in the memory cell is turned on when the second condition is satisfied;

[0028] Satisfying the first condition specifically includes: the operating temperature of the memory is greater than the first temperature threshold, the operating temperature of the memory is less than or equal to the second temperature threshold, and the type of the memory is not low power consumption; satisfying the second condition specifically includes: the operating temperature of the memory is greater than the second temperature threshold.

[0029] Some embodiments of the present application provide a control circuit of a memory, the memory comprising a storage unit, the storage unit being connected to a bit line, the control circuit comprising: a temperature monitoring circuit and a voltage control circuit;

[0030] The temperature monitoring circuit monitors the operating temperature of the memory;

[0031] The voltage control circuit is connected to the temperature monitoring circuit, and the voltage control circuit adjusts the voltage of the storage unit in the memory according to the working temperature of the memory;

[0032] Among them, the voltage of the storage unit includes one or more of the voltage of the upper plate of the capacitor when the storage unit stores the first data, the voltage on the bit line before the transistor in the storage unit is turned on, and the gate turn-on voltage of the transistor. When the storage unit stores the first data, the voltage of the upper plate of the capacitor is greater than the voltage of the lower plate of the capacitor.

[0033] Some embodiments of the present application provide a memory, including: a memory unit and the control circuit involved in the above embodiments, wherein the memory unit is connected to a bit line.

[0034] The control method, control circuit and memory of the memory provided in the present application include obtaining the operating temperature data of the memory, and adjusting one or more of the voltage of the upper plate of the capacitor, the bit line precharge voltage and the gate turn-on voltage of the transistor when the memory unit stores the first data according to the temperature data, so as to adjust the performance of the tail memory unit, thereby improving the overall performance of the memory and improving the pass rate of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0036] Figure 1 An example diagram of a memory architecture;

[0037] Figure 2 A structural diagram of a storage unit according to an embodiment of the present invention is shown;

[0038] Figure 3 for Figure 2 A circuit schematic diagram of the memory cell shown;

[0039] Figure 4 A schematic diagram of the structure of a storage unit;

[0040] Figures 5 to 8 A schematic flow chart of a memory control method provided in some embodiments of the present application;

[0041] Fig.9A A schematic diagram of the relationship between the core voltage of a memory cell and the bit line precharge voltage;

[0042] Fig. 9B A schematic diagram of the distribution of dVBL provided in some embodiments of the present application;

[0043] Figures 10 to 12 A flowchart of a memory control method provided in some embodiments of the present application.

[0044] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0045] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0046] At present, memory technology is developing rapidly. Taking DRAM as an example, the main applications include synchronous dynamic random access memory (Synchronous Dynamic Random-Access Memory, referred to as: SDRAM), various generations of double data rate (Double Data Rate, referred to as: DDR) SDRAM, various generations of low power double data rate (Low Power Double Data Rate, referred to as: LPDDR) SDRAM and other types.

[0047] Figure 1 This is a sample diagram of a memory architecture, such as Figure 1 As shown, taking DRAM as an example, it includes an address processing circuit 210, a command decoding circuit 220, a data input / output circuit 230, a row decoder 240, a column decoder 250, a sense amplifier (SA) 260 and a storage area. Among them, the address processing circuit 210, the command decoding circuit 220 and the data input / output circuit 230 belong to the peripheral area circuit, and the row decoder 240, the column decoder 250, the sense amplifier 260 and the storage area belong to the array area circuit. The storage area is mainly composed of a storage cell 270, a bit line BL and a word line WL. The word line WL in the storage area extends in the row direction, and the bit line BL in the storage area extends in the column direction. The intersection of the word line WL and the bit line BL is the storage cell 270 of the storage area.

[0048] Each storage unit 270 is used to store one bit of data. Figure 2 As shown, Figure 2 This is a structural example diagram of a storage unit shown in an embodiment. The storage unit 270 includes a switching transistor M and a capacitor Cs. Any one of the source or drain of the switching transistor M is connected to the upper plate of the capacitor, the other of the source or drain of the switching transistor M is connected to the bit line BL, and the lower plate of the capacitor Cs is connected to the power line. The gate of the switching transistor M is connected to the word line WL, and the gate turn-on voltage of the switching transistor M is called Vwlp. Among them, the capacitor Cs is used to store data, and the switching transistor M is used to turn off or turn on according to the selected state. The lower plate voltage of the capacitor Cs is called Vap2, and the pre-charge voltage before charge sharing on the bit line is called Vad2.

[0049] The word line WL of the row where the storage cell is located can be selected by the row decoder 240, and the corresponding switch transistor M in the figure is turned on, and the logic level of the bit line is set to 1, so that the upper plate of the capacitor Cs is charged, that is, the data "1" is written to the storage cell. Conversely, if 0 is to be written, the logic level of the bit line is set to 0, so that the upper plate of the capacitor Cs is discharged, that is, the data "0" is written to the storage cell.

[0050] Figure 3 for Figure 2 The circuit schematic diagram of the storage unit is shown in FIG. Figure 3 As shown, the resistance between the transistor M and the bit line BL is called the bit line contact resistance RBLC, the contact resistance between the transistor M and the capacitor Cs is called the transistor contact resistance RNC, and the resistance on the capacitor Cs is called the capacitor resistance RCH. When the data "1" is stored on the storage cell, the capacitor upper plate voltage is called the core voltage Vblh.

[0051] As the integration of chips becomes higher and higher, the feature size of transistor technology is constantly decreasing. The threshold voltage fluctuation of MOS tubes in sense amplifiers and the susceptibility of small voltage signals to noise interference are becoming increasingly prominent, which seriously affects the accuracy of sense amplifiers in sensing data in storage cells. Sensing margin (SM) is an important indicator to measure the performance of sense amplifiers. The calculation formula of sensing margin SM is: SM = Supply dVBL-Required dVBL, where Supply dVBL specifically refers to the voltage difference between the bit line and the complementary bit line at the end of the charge sharing phase, Supply dVBL is also called the supply of sensing margin, Required dVBL refers to the voltage difference required for SA to correctly amplify, and Required dVBL is also called the loss of sensing margin. The reasons for the loss of sensing margin mainly include the offset voltage and coupling noise caused by the mismatch of MOS tube threshold voltage.

[0052] Figure 4 A schematic diagram of the structure of a storage unit is shown in FIG. Figure 4 As shown, a first doping region and a second doping region are formed on the substrate, a word line is buried between the first doping region and the second doping region, and a channel is formed around the word line. The leakage current in the memory cell includes gate-induced drain leakage (Gate-Induced Drain Leakage, abbreviated as: GIDL) current, PN junction leakage (Junction Leakage) current and substrate leakage (Subthreshold Leakage) current.

[0053] Among them, GIDL current refers to a leakage mechanism of the transistor when it is turned off. Taking N-type transistor as an example, it occurs when the drain voltage is high and the gate voltage is zero or negative. In this case, the N-type transistor should be in the off state and the off current Ioff should be relatively small. However, due to the existence of GIDL current, the off current Ioff will be relatively large, and it will be more obvious as the negative gate voltage increases.

[0054] Generally speaking, memory cells are divided into main cells and tail cells according to the data retention time or the size of the sensing margin.

[0055] The bit line contact resistance RBLC, transistor contact resistance RNC and capacitor resistance RCH of the main unit are all small, and the gate induced drain leakage current and PN junction leakage current are small, which will cause the voltage difference dVBL between the bit line BL and the complementary bit line BLB to be relatively large, and the retention time and refresh time tREF are related to the voltage difference dVBL between the bit line BL and the complementary bit line BLB, and the sensing margin and refresh time tREF are related to the voltage difference ΔVBL between the bit line BL and the complementary bit line BLB. The sensing margin and data retention time of the main memory cell are relatively good.

[0056] The bit line contact resistance RBLC, transistor contact resistance RNC and capacitor resistance RCH of the tail memory cell are all large, and the gate induced drain leakage current and PN junction leakage current are large, which will cause the voltage difference dVBL between the bit line BL and the complementary bit line BLB to be relatively small, and the sensing margin and data retention time of the tail memory cell are both poor.

[0057] In addition, there is a data preference problem in the memory. When the test conditions that are not conducive to reading data "1" are set, the sensing margin when reading data from the memory is called the sensing margin of data "1" D1 SM, and when the test conditions that are not conducive to reading data "0" are set, the sensing margin when reading data from the memory is called the sensing margin of data "0" D0 SM. There may be a case where D1 SM and D0 SM are not equal. That is, the case where D1 SM is greater than D0 SM, or the case where D0 SM is greater than D1 SM.

[0058] For the tail memory cells, the leakage current, resistance and data preference in the memory cells are more obvious and will be further deteriorated as the operating temperature of the memory changes. Therefore, improving the performance and yield of the tail memory cells is the key to improving the overall performance and yield of the memory chip.

[0059] Some aspects of the embodiments of the present disclosure relate to the above considerations. The following is an example introduction of the scheme in combination with some embodiments of the present disclosure. For ease of description, data "1" is referred to as first data, and data "0" is referred to as second data.

[0060] Figure 5 The flowchart of the memory control method provided in some embodiments of the present application is as follows. Figure 5 As shown, some embodiments of the present application provide a memory control method comprising the following steps:

[0061] S101: Obtain the operating temperature of the memory.

[0062] In this step, a sensor may be used to detect the operating temperature of the memory.

[0063] S102: adjusting the voltage of the storage unit in the memory according to the working temperature of the memory.

[0064] In this step, the voltage of the storage cell includes one or more of the voltage Vblh of the upper plate of the capacitor when the storage cell stores the first data, the voltage Vad2 on the bit line before the transistor in the storage cell is turned on, and the gate turn-on voltage Vwlp of the transistor. When the storage cell stores the first data, the voltage of the upper plate of the capacitor is greater than the voltage of the lower plate of the capacitor.

[0065] For the convenience of subsequent description, the voltage Vblh on the upper plate of the capacitor when the memory cell stores the first data is referred to as the core voltage Vblh of the memory cell, and the voltage Vad2 on the bit line before the transistor in the memory cell is turned on is referred to as the bit line precharge voltage Vad2.

[0066] By adjusting the core voltage Vblh of the memory cell according to the operating temperature data of the memory, the voltage of the drain of the transistor and / or the source of the transistor can be reduced, the GIDL current can be reduced, the charge loss on the capacitor can be reduced, the sensing margin can be improved, the probability of the sensing error of the sensitive amplifier can be reduced, and the data reading accuracy of the memory can be improved. At the same time, by adjusting the core voltage Vblh of the memory cell according to the operating temperature data of the memory, the voltage difference Vgs from the gate to the source of the transistor can be adjusted, and the current Ids between the source and the drain of the transistor can be adjusted to adapt to a shorter write recovery time tWR and a shorter refresh time tREF.

[0067] By adjusting the bit line precharge voltage Vad2 according to the operating temperature data of the memory, the sensing margin of the first data or the sensing margin of the second data can be adjusted to adjust the data preference of the memory.

[0068] Under different operating temperatures of the memory, it is necessary to set different gate turn-on voltages Vwlp of the transistor.

[0069] In the above technical solution, the operating temperature data of the memory is obtained, and one or more of the voltage Vblh of the upper plate of the capacitor, the bit line precharge voltage Vad2, and the gate turn-on voltage Vwlp of the transistor are adjusted according to the temperature data when the memory unit stores the first data. The performance of the tail memory unit can be adjusted, thereby improving the overall performance of the memory and improving the pass rate of the memory.

[0070] More specifically, a first temperature threshold Th1 and a second temperature threshold Th2 are set to determine a high temperature range, a normal temperature range, and a low temperature range of the memory. The first temperature threshold Th1 is less than the second temperature threshold Th2. When the operating temperature of the memory is less than or equal to the first temperature threshold Th1, the memory operates in a low temperature range. When the operating temperature of the memory is greater than the first temperature threshold Th1, and the operating temperature of the memory is less than or equal to the second temperature threshold Th2, the memory operates in a normal temperature range. When the operating temperature of the memory is greater than the second temperature threshold Th2, the memory operates in a high temperature range.

[0071] The first temperature threshold Th1 and the second temperature threshold Th2 can be set according to actual needs, and only examples are given here. For example: the first temperature threshold can be between 15°C and 20°C. If the first temperature threshold Th1 is 20°C, the second temperature threshold Th2 is 45°C. When the operating temperature TCs≤20°C of the memory, the memory operates in the low temperature range. When the operating temperature of the memory is 20°C<Tc≤40°C, the memory operates in the normal temperature range. When the operating temperature Tc>40°C of the memory, the memory operates in the high temperature range.

[0072] In addition, a third temperature threshold Th3 and a fourth temperature threshold Th4 may be set, wherein the third temperature threshold Th3 is less than the first temperature threshold Th1, and the fourth temperature threshold Th4 is greater than the second temperature threshold Th2. When the operating temperature of the memory is less than or equal to the first temperature threshold Th1, and the operating temperature of the memory is greater than the third temperature threshold Th3, the memory operates in a low temperature range. When the operating temperature of the memory is greater than the second temperature threshold Th2, and the operating temperature of the memory is less than or equal to the fourth temperature threshold Th4, the memory operates in a high temperature range.

[0073] The third temperature threshold Th3 and the fourth temperature threshold Th4 can be set according to actual needs, which is only illustrated here. For example, the third temperature threshold Th3 is -40°C, and the fourth temperature threshold Th4 is 95°C. When the operating temperature of the memory is -40°C<Tc≤20°C, the memory works in a low temperature range. When the operating temperature of the memory is 40°C<Tc≤95°C, the memory works in a high temperature range.

[0074] Figure 6 The flowchart of the memory control method provided in some embodiments of the present application is as follows. Figure 6 As shown, adjusting the core voltage Vblh of the memory cell according to the operating temperature Tc of the memory specifically includes:

[0075] S201 . When the operating temperature Tc of the memory is less than or equal to the first temperature threshold Th1 , control the core voltage Vblh of the memory cell to be greater than the upper plate reference voltage Vref1 .

[0076] When the operating temperature Tc of the memory is less than or equal to the first temperature threshold Th1, the memory operates in a low temperature range.

[0077] In the low temperature range, the frequency response of the capacitor Cs in each memory cell is slow, and the effective capacitance value of the capacitor Cs is small, which will result in a small voltage difference dVBL between the bit line and the complementary bit line during charge sharing. This makes the sensing margin of the main memory cell and the tail memory cell relatively small, and the refresh time is relatively long. In other words, the performance of the main memory cell and the tail memory cell deteriorates a lot. Therefore, when working in the low temperature range, the main adjustment target is the main memory cell.

[0078] When the memory operates in a low temperature range, the core voltage Vblh of the memory cell is increased to increase the voltage difference between the bit line corresponding to the main memory cell and the complementary bit line, thereby increasing the sensing margin of the sense amplifier corresponding to the main memory cell.

[0079] For example, the plate reference voltage Vref1 is 1V. When the memory operates in a low temperature range, the core voltage Vblh of the memory cell is adjusted to be greater than 1V. More specifically, the core voltage Vblh of the memory cell has a value range of [1.02V to 1.06V]. In this way, the sensing margin of the sense amplifier corresponding to the main memory cell is improved.

[0080] S202 , when the operating temperature Tc of the memory is greater than the first temperature threshold Th1 and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2 , adjusting the core voltage Vblh of the memory unit according to the type of the memory.

[0081] When the operating temperature Tc of the memory is greater than the first temperature threshold Th1 and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, the memory operates in a normal temperature range.

[0082] When the memory operates in a normal temperature range, the power consumption of the memory is a key factor to be considered, especially for the memory used in mobile electronic devices. When adjusting the core voltage Vblh of the memory cell, it is necessary to avoid increasing the power consumption of the circuit.

[0083] When the memory operates in a normal temperature range, the type of the memory is obtained. The memory includes SDRAM, various generations of double data rate SDRAM, and various generations of low power double data rate SDRAM.

[0084] The generations of double data rate SDRAM include a 1st generation double data rate SDRAM, a 2nd generation double data rate SDRAM, ..., an xth generation double data rate SDRAM.

[0085] The generations of low power double data rate SDRAM include a 1st generation low power double data rate SDRAM, a 2nd generation low power double data rate SDRAM, ..., a yth generation low power double data rate SDRAM.

[0086] Among them, SDRAM and various generations of double data rate SDRAM are non-low power type memories, and various generations of low power double data rate SDRAM are low power type memories.

[0087] When the memory operates in a normal temperature range, different adjustment strategies for the core voltage Vblh of different memory cells are set according to the type of the memory.

[0088] In some embodiments, when the operating temperature Tc of the memory is greater than the first temperature threshold Th1, and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is low power consumption, the core voltage Vblh of the memory unit is controlled to be the upper plate reference voltage Vref1. That is, when the memory operates in a normal temperature range and the memory is a low power consumption memory, the core voltage Vblh of the memory unit is not adjusted, so as to avoid increasing the loss of the memory by adjusting the core voltage Vblh of the memory unit.

[0089] In some embodiments, when the operating temperature Tc of the memory is greater than the first temperature threshold Th1, the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is not low power, the core voltage Vblh of the memory cell is controlled to be less than the upper plate reference voltage Vref1. That is, when the memory operates in a normal temperature range and the memory is not a low power memory, the core voltage Vblh of the memory cell is adjusted to be less than the upper plate reference voltage Vref1, which can reduce the leakage current of the transistor in the memory, increase the voltage difference dVBL between the bit line corresponding to the memory cell and the complementary bit line, and improve the sensing margin of the tail memory cell. In addition, the core voltage Vblh of the memory cell is reduced, the voltage difference Vgs from the gate to the source of the adjustment transistor is increased, and the current Ids between the source and the drain of the transistor is increased to adapt to a smaller write recovery time tWR and a shorter refresh time tREF, thereby improving the overall performance of the memory.

[0090] For example, the upper plate reference voltage Vref1 is 1V. When the memory operates in a normal temperature range and the memory is a low-power memory, the core voltage Vblh of the memory cell is maintained unchanged, which is the upper plate reference voltage 1V. When the memory operates in a normal temperature range and the memory is not a low-power memory, the core voltage Vblh of the memory cell is controlled to be less than the upper plate reference voltage. More specifically, the value range of the core voltage Vblh of the memory cell is [0.99V~1.0V).

[0091] S203 , when the operating temperature Tc of the memory is greater than the second temperature threshold Th2 , controlling the core voltage Vblh of the memory cell to be less than the upper plate reference voltage Vref1 .

[0092] Among them, when the operating temperature Tc of the memory is greater than the second temperature threshold Th2, the memory operates in a high temperature range. When the memory operates in a high temperature range, the reliability of the transistors in the memory decreases and the leakage current is large. By adjusting the core voltage Vblh of the memory cell to be less than the upper plate reference voltage Vref1, the leakage current of the transistors in the memory can be reduced, the voltage difference dVBL between the bit line and the complementary bit line corresponding to the memory cell can be increased, and the sensing margin of the tail memory cell can be improved. In addition, the core voltage Vblh of the memory cell is reduced, the gate-to-source voltage difference Vgs of the adjustment transistor is increased, and the current Ids between the source and drain of the transistor is increased to adapt to a smaller write recovery time tWR and a shorter refresh time tREF, thereby improving the overall performance of the memory.

[0093] For example, the upper plate reference voltage Vref1 is 1V, and when the memory operates in a high temperature range, the core voltage Vblh of the memory cell is controlled to be less than the upper plate reference voltage. More specifically, the core voltage Vblh of the memory cell has a value range of [0.9V to 1.0V].

[0094] When the memory operates in a high temperature range and when the memory operates in a normal temperature range and the memory is not a low power memory, the core voltage Vblh of the memory unit is controlled to be lower than the upper plate reference voltage Vref1. Since the leakage of the transistor when the memory operates in a normal temperature range is lower than the leakage of the transistor when the memory operates in a high temperature range, the core voltage Vblh of the memory unit when the memory operates in a normal temperature range and the memory is not a low power memory is greater than the core voltage Vblh of the memory unit when the memory is controlled to operate in a high temperature range.

[0095] That is, when the first condition is met, the core voltage Vblh of the memory cell is greater than the core voltage Vblh of the memory cell when the second condition is met. Wherein, satisfying the first condition specifically includes that the operating temperature Tc of the memory is greater than the first temperature threshold Th1, the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is not low power consumption. Satisfying the second condition specifically includes that the operating temperature Tc of the memory is greater than the second temperature threshold Th2.

[0096] In the above technical solution, the core voltage Vblh of the memory cell is adjusted according to the operating temperature Tc of the memory, so as to improve the overall performance of the memory, and the core voltage Vblh of the memory cell is adjusted according to the type of memory when the memory operates in the normal temperature range, so as to adapt to the low power consumption requirements of the memory for mobile electronic devices.

[0097] Figure 7 The flowchart of the memory control method provided in some embodiments of the present application is as follows. Figure 7 As shown, the bit line precharge voltage Vad2 is adjusted according to the operating temperature Tc of the memory, specifically including:

[0098] S301 . When the operating temperature Tc of the memory is less than or equal to the first temperature threshold Th1 , control the bit line precharge voltage Vad2 to be greater than the bit line reference voltage Vref2 .

[0099] When the operating temperature Tc of the memory is less than or equal to the first temperature threshold Th1, the memory operates in a low temperature range.

[0100] When the memory operates in a low temperature range, the sensing margin D0 SM of the second data is smaller than the sensing margin D1 SM of the first data. By adjusting the bit line precharge voltage Vad2 to be greater than the bit line reference voltage Vref2, the sensing margin D1 SM of the first data can be reduced, the difference between the sensing margin D1 SM of the first data and the sensing margin D0 SM of the second data can be reduced, and the sensing margin D1 SM of the first data and the sensing margin D0 SM of the second data can be balanced.

[0101] For example, when the bit line reference voltage Vref2 is 0.5V, the bit line precharge voltage Vad2 is controlled to be greater than the bit line reference voltage Vref2 when the memory operates in a low temperature range. More specifically, the value range of the bit line precharge voltage Vad2 is [0.51V to 0.55V].

[0102] S302 , when the operating temperature Tc of the memory is greater than the first temperature threshold Th1 and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2 , adjusting the bit line precharge voltage Vad2 according to the type of the memory.

[0103] When the operating temperature Tc of the memory is greater than the first temperature threshold Th1 and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, the memory operates in a normal temperature range.

[0104] When the memory operates in a normal temperature range, the power consumption of the memory is a factor that needs to be considered, especially for the memory used in mobile electronic devices. Therefore, when adjusting the bit line precharge voltage Vad2, it is necessary to avoid increasing the circuit power consumption.

[0105] When the memory operates in a normal temperature range, different adjustment strategies for the bit line precharge voltage Vad2 are set according to the type of the memory to adjust the data preference of the memory.

[0106] When the memory operates in a normal temperature range, the sensing margin D1 SM of the first data is smaller than the sensing margin D0 SM of the second data.

[0107] In some embodiments, when the operating temperature Tc of the memory is greater than the first temperature threshold Th1, and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is low power consumption, the bit line precharge voltage Vad2 is controlled to be the bit line reference voltage Vref2. That is, when the memory operates in a normal temperature range and the memory is a low power consumption memory, the bit line precharge voltage Vad2 is not adjusted, so as to avoid increasing the loss of the memory due to adjusting the bit line precharge voltage Vad2.

[0108] When the operating temperature Tc of the memory is greater than the first temperature threshold Th1, the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is not low power consumption, the bit line precharge voltage Vad2 is controlled to be less than the bit line reference voltage Vref2. That is, when the memory operates in a normal temperature range and the memory is not a low power consumption memory, the bit line precharge voltage Vad2 is adjusted to be less than the bit line reference voltage Vref2, which can reduce the sensing margin D0 SM of the second data, and can reduce the difference between the sensing margin D1 SM of the first data and the sensing margin D0 SM of the second data, and balance the sensing margin D1 SM of the first data and the sensing margin D0 SM of the second data.

[0109] For example, when the bit line reference voltage Vref2 is 0.5V, when the memory operates in the normal temperature range and the memory is a low power memory, the bit line precharge voltage Vad2 is maintained unchanged, which is the bit line reference voltage 0.5V. When the memory operates in the normal temperature range and the memory is not a low power memory, the bit line precharge voltage Vad2 is controlled to be less than the bit line reference voltage Vref2. More specifically, the value range of the bit line precharge voltage Vad2 is [0.49V~0.5V).

[0110] S303 , when the operating temperature Tc of the memory is greater than the second temperature threshold Th2 , controlling the bit line precharge voltage Vad2 to be less than the bit line reference voltage Vref2 .

[0111] When the operating temperature Tc of the memory is greater than the second temperature threshold Th2, the memory operates in a high temperature range. When the memory operates in a high temperature range, the reliability of transistors in the memory decreases and the leakage current is large.

[0112] When the memory operates in a high temperature range, the sensing margin D1 SM of the first data is smaller than the sensing margin D0 SM of the second data. By adjusting the bit line precharge voltage Vad2 to be smaller than the bit line reference voltage Vref2, the sensing margin D0 SM of the second data can be reduced, and the difference between the sensing margin D1 SM of the first data and the sensing margin D0 SM of the second data can be reduced, so as to balance the sensing margin D1 SM of the first data and the sensing margin D0 SM of the second data.

[0113] For example, when the bit line reference voltage Vref2 is 0.5V, the bit line precharge voltage Vad2 is controlled to be smaller than the bit line reference voltage Vref2 when the memory operates in a high temperature range. More specifically, the bit line precharge voltage Vad2 has a value range of [0.45V to 0.5V].

[0114] When the memory operates in a high temperature range and when the memory operates in a normal temperature range and the memory is a non-low power memory, the bit line precharge voltage Vad2 is controlled to be lower than the bit line reference voltage Vref2. Since the leakage of the transistor when the memory operates in a normal temperature range is lower than the leakage of the transistor when the memory operates in a high temperature range, the bit line precharge voltage Vad2 when the memory operates in a normal temperature range and the memory is a non-low power memory is controlled to be higher than the bit line precharge voltage Vad2 when the memory operates in a high temperature range.

[0115] That is, when the first condition is met, the bit line precharge voltage Vad2 is greater than the bit line precharge voltage Vad2 in the memory cell when the second condition is met. Meeting the first condition specifically includes that the operating temperature of the memory is greater than the first temperature threshold, the operating temperature of the memory is less than or equal to the second temperature threshold, and the type of the memory is not low power consumption. Meeting the second condition specifically includes that the operating temperature of the memory is greater than the second temperature threshold.

[0116] In the above technical solution, the bit line precharge voltage Vad2 is adjusted according to the operating temperature Tc of the memory, so as to improve the overall performance of the memory, and the bit line precharge voltage Vad2 is adjusted according to the type of memory when the memory operates in the normal temperature range, so as to adapt to the low power consumption requirements of the memory for mobile electronic devices.

[0117] In some embodiments, adjusting the gate turn-on voltage Vwlp of the transistor according to the operating temperature Tc of the memory specifically includes:

[0118] S401 . When the operating temperature Tc of the memory is less than or equal to the first temperature threshold Th1 , the gate turn-on voltage Vwlp of the control transistor is controlled to be the gate reference voltage Vref3 .

[0119] S402 . When the operating temperature Tc of the memory is greater than the first temperature threshold Th1 and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2 , the gate turn-on voltage Vwlp of the control transistor is the gate reference voltage Vref3 .

[0120] S403 . When the operating temperature Tc of the memory is greater than the second temperature threshold Th2 , the gate turn-on voltage Vwlp of the control transistor is controlled to be less than the gate reference voltage Vref3 .

[0121] Among them, when the operating temperature Tc of the memory is greater than the second temperature threshold Th2, the memory operates in a high temperature range. When the memory operates in a high temperature range, the reliability of the transistor in the memory decreases and the leakage current is large. The gate turn-on voltage Vwlp of the control transistor is adjusted to be less than the gate reference voltage Vref3, that is, a smaller gate turn-on voltage is used. However, a smaller gate turn-on voltage will cause the sensing margin D1 SM of the first data to be less than the sensing margin D0 SM of the second data, so the bit line precharge voltage Vad2 can be controlled to be less than the bit line reference voltage Vref2 to reduce the sensing margin D0SM of the second data.

[0122] In the above technical solution, the gate reference voltage Vref3 is adjusted according to the operating temperature Tc of the memory, so as to improve the overall performance of the memory.

[0123] Figure 8 The flowchart of the memory control method provided in some embodiments of the present application is as follows. Figure 8 As shown, some embodiments of the present application also provide a memory control method, the control method comprising:

[0124] S501. When the operating temperature Tc of the memory is less than or equal to the first temperature threshold Th1, the core voltage Vblh of the memory cell is controlled to be greater than the upper plate reference voltage Vref1, and the bit line precharge voltage Vad2 is controlled to be greater than the bit line reference voltage Vref2.

[0125] S502 , when the operating temperature Tc of the memory is greater than the first temperature threshold Th1 and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2 , adjusting the core voltage Vblh and the bit line precharge voltage Vad2 of the memory cell according to the type of the memory.

[0126] More specifically, when the operating temperature Tc of the memory is greater than the first temperature threshold Th1, and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is low power consumption, the core voltage Vblh of the storage unit is controlled to be the upper plate reference voltage Vref1, and the bit line precharge voltage Vad2 is controlled to be the bit line reference voltage Ref2.

[0127] When the operating temperature Tc of the memory is greater than the first temperature threshold Th1, and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is not low power consumption, the core voltage Vblh of the storage unit is controlled to be less than the upper plate reference voltage Vref1, and the bit line precharge voltage Vad2 is controlled to be less than the bit line reference voltage Ref2.

[0128] S503 , when the operating temperature Tc of the memory is greater than the second temperature threshold Th2 , controlling the core voltage Vblh of the memory cell to be less than the upper plate reference voltage Vref1 , and controlling the bit line precharge voltage Vad2 to be less than the bit line reference voltage Vref2 .

[0129] In the above technical solution, the core voltage Vblh and the bit line precharge voltage Vad2 of the memory cell are adjusted according to the operating temperature Tc of the memory, so that the overall performance of the memory can be improved.

[0130] Here, the memory operates in a high temperature range, and the core voltage Vblh of the memory cell is controlled to be smaller than the upper plate reference voltage Vref1, and the bit line precharge voltage Vad2 is controlled to be smaller than the bit line reference voltage Vref2.

[0131] Fig.9A Schematic diagram of the relationship between the core voltage of the memory cell and the bit line precharge voltage. Fig.9A As shown, when the memory operates in a high temperature range, if the core voltage Vblh of the memory cell is still maintained at 1V, the bit line precharge voltage Vad2 is 0.5V, the voltage difference between the main memory cell and the bit line is 1.0V-0.5V=0.5V, and the voltage difference between the tail main memory cell and the bit line is 0.6V-0.5V=0.1V.

[0132] When the memory operates in a high temperature range, if the core voltage Vblh of the control memory cell is reduced to 0.95V and the bit line precharge voltage Vad2 is reduced to 0.475V, the voltage difference between the main memory cell and the bit line is 0.95V-0.475V=0.475V, and the voltage difference between the tail memory cell and the bit line is 0.58V-0.475V=0.105V. That is to say, after reducing the core voltage Vblh and the bit line precharge voltage Vad2 of the memory cell at the same time, the performance of the main memory cell is reduced, but the performance of the tail memory cell is improved, and the reduction of the main cell does not affect the qualified rate of the memory, but the improvement of the performance of the tail memory cell can improve the yield of the memory.

[0133] Fig. 9B The following is a schematic diagram of the distribution of dVBL provided in some embodiments of the present application. Fig. 9BAs shown, the horizontal axis dVBL is the voltage difference between the bit line BL and the complementary bit line BLB after the memory cell and the bit line BL share charge. The larger the dVBL, the higher the accuracy of reading and writing data. The dotted line corresponds to the dVbl distribution diagram before reducing the core voltage Vblh of the memory cell and the bit line precharge voltage Vad2, and the solid line is the dVbl distribution diagram after reducing the core voltage Vblh of the memory cell and the bit line precharge voltage Vad2. By reducing the core voltage Vblh of the memory cell, the dVBL of the main memory cell is reduced, but the dVBL of the tail memory cell is increased. The performance reduction of the main memory cell will not affect the qualified rate of the memory. The increase in dVBL of the tail memory cell helps to save the tail memory cell that cannot be correctly sensed and improve the qualified rate of the memory cell.

[0134] Fig.10 The flowchart of the memory control method provided in some embodiments of the present application is as follows. Fig.10 As shown, some embodiments of the present application also provide a memory control method, the control method comprising:

[0135] S601. When the operating temperature Tc of the memory is less than or equal to the first temperature threshold Th1, the core voltage Vblh of the memory cell is controlled to be greater than the upper plate reference voltage Vref1, the bit line precharge voltage Vad2 is controlled to be greater than the bit line reference voltage Vref2, and the gate turn-on voltage Vwlp of the transistor is controlled to be the gate reference voltage Vref3.

[0136] S602. When the operating temperature Tc of the memory is greater than the first temperature threshold Th1 and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, the core voltage Vblh and the bit line precharge voltage Vad2 of the memory cell are adjusted according to the type of the memory, and the gate turn-on voltage Vwlp of the transistor is controlled to be the gate reference voltage Vref3.

[0137] More specifically, when the operating temperature Tc of the memory is greater than the first temperature threshold Th1, and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is low power consumption, the core voltage Vblh of the storage unit is controlled to be the upper plate reference voltage Vref1, the bit line precharge voltage Vad2 is controlled to be the bit line reference voltage Ref2, and the gate turn-on voltage Vwlp of the transistor is controlled to be the gate reference voltage Vref3.

[0138] When the operating temperature Tc of the memory is greater than the first temperature threshold Th1, and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is not low power consumption, the core voltage Vblh of the storage unit is controlled to be less than the upper plate reference voltage Vref1, the bit line precharge voltage Vad2 is controlled to be less than the bit line reference voltage Ref2, and the gate turn-on voltage Vwlp of the transistor is controlled to be the gate reference voltage Vref3.

[0139] S603. When the operating temperature Tc of the memory is greater than the second temperature threshold Th2, the core voltage Vblh of the storage unit is controlled to be less than the upper plate reference voltage Vref1, the bit line precharge voltage Vad2 is controlled to be less than the bit line reference voltage Vref2, and the gate turn-on voltage Vwlp of the transistor is controlled to be less than the gate reference voltage Vref3.

[0140] In the above technical solution, the core voltage Vblh of the memory cell, the bit line precharge voltage Vad2 and the gate turn-on voltage Vwlp of the transistor are adjusted according to the operating temperature Tc of the memory, so as to improve the overall performance of the memory.

[0141] Fig.11 The flowchart of the memory control method provided in some embodiments of the present application is as follows. Fig.11 As shown, some embodiments of the present application also provide a memory control method, the control method comprising:

[0142] S701. When the operating temperature Tc of the memory is less than or equal to the first temperature threshold Th1, the core voltage Vblh of the memory cell is controlled to be greater than the upper plate reference voltage Vref1, and the gate turn-on voltage Vwlp of the transistor is controlled to be the gate reference voltage Vref3.

[0143] S702, when the operating temperature Tc of the memory is greater than the first temperature threshold Th1 and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, adjust the core voltage Vblh of the memory cell according to the type of the memory, and control the gate turn-on voltage Vwlp of the transistor to be the gate reference voltage Vref3.

[0144] More specifically, when the operating temperature Tc of the memory is greater than the first temperature threshold Th1, and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is low power consumption, the core voltage Vblh of the storage unit is controlled to be the upper plate reference voltage Vref1, and the gate turn-on voltage Vwlp of the transistor is controlled to be the gate reference voltage Vref3.

[0145] When the operating temperature Tc of the memory is greater than the first temperature threshold Th1, and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is not low power consumption, the core voltage Vblh of the storage unit is controlled to be less than the upper plate reference voltage Vref1, and the gate turn-on voltage Vwlp of the transistor is controlled to be the gate reference voltage Vref3.

[0146] S703, when the operating temperature Tc of the memory is greater than the second temperature threshold Th2, the core voltage Vblh of the memory cell is controlled to be less than the upper plate reference voltage Vref1, and the gate turn-on voltage Vwlp of the transistor is controlled to be less than the gate reference voltage Vref3.

[0147] In the above technical solution, the core voltage Vblh of the memory cell and the gate turn-on voltage Vwlp of the transistor are adjusted according to the operating temperature Tc of the memory, so that the overall performance of the memory can be improved.

[0148] Fig.12 The flowchart of the memory control method provided in some embodiments of the present application is as follows. Fig.12 As shown, some embodiments of the present application also provide a memory control method, the control method comprising:

[0149] S801. When the operating temperature Tc of the memory is less than or equal to the first temperature threshold Th1, the bit line precharge voltage Vad2 is controlled to be greater than the bit line reference voltage Vref2, and the gate turn-on voltage Vwlp of the transistor is controlled to be the gate reference voltage Vref3.

[0150] S802. When the operating temperature Tc of the memory is greater than the first temperature threshold Th1 and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, the bit line precharge voltage Vad2 is adjusted according to the type of the memory, and the gate turn-on voltage Vwlp of the transistor is controlled to be the gate reference voltage Vref3.

[0151] More specifically, when the operating temperature Tc of the memory is greater than the first temperature threshold Th1, and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is low power consumption, the bit line precharge voltage Vad2 is controlled to be the bit line reference voltage Ref2, and the gate turn-on voltage Vwlp of the transistor is controlled to be the gate reference voltage Vref3.

[0152] When the operating temperature Tc of the memory is greater than the first temperature threshold Th1, and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is not low power consumption, the bit line precharge voltage Vad2 is controlled to be less than the bit line reference voltage Ref2, and the gate turn-on voltage Vwlp of the transistor is controlled to be the gate reference voltage Vref3.

[0153] S803 . When the operating temperature Tc of the memory is greater than the second temperature threshold Th2 , the bit line precharge voltage Vad2 is controlled to be less than the bit line reference voltage Vref2 , and the gate turn-on voltage Vwlp of the transistor is controlled to be less than the gate reference voltage Vref3 .

[0154] In the above technical solution, the bit line precharge voltage Vad2 and the gate turn-on voltage Vwlp of the transistor are adjusted according to the operating temperature Tc of the memory, so as to improve the overall performance of the memory.

[0155] Some embodiments of the present application also provide a control circuit of a memory, the memory comprising a storage unit, the storage unit being connected to a bit line, the control circuit comprising: a temperature monitoring circuit and a voltage control circuit;

[0156] The temperature monitoring circuit monitors the operating temperature of the memory;

[0157] The voltage control circuit is connected to the temperature monitoring circuit, and the voltage control circuit adjusts the voltage of the storage unit in the memory according to the working temperature of the memory;

[0158] Among them, the voltage of the storage unit includes one or more of the voltage of the upper plate of the capacitor when the storage unit stores the first data, the voltage on the bit line before the transistor in the storage unit is turned on, and the gate turn-on voltage of the transistor. When the storage unit stores the first data, the voltage of the upper plate of the capacitor is greater than the voltage of the lower plate of the capacitor.

[0159] In some embodiments, the voltage control circuit is further configured to:

[0160] When the operating temperature of the memory is less than or equal to the first temperature threshold, controlling the voltage of the upper plate of the capacitor to be greater than the upper plate reference voltage when the storage unit stores the first data;

[0161] When the operating temperature of the memory is less than or equal to a first temperature threshold, controlling the voltage on the bit line before the transistor in the memory cell is turned on to be greater than a bit line reference voltage; and

[0162] When the operating temperature of the memory is less than or equal to the first temperature threshold, the gate turn-on voltage of the control transistor is the gate reference voltage.

[0163] In some embodiments, the voltage control circuit is further configured to:

[0164] When the operating temperature of the memory is greater than a second temperature threshold, controlling the voltage of the upper plate of the capacitor to be less than the upper plate reference voltage when the storage unit stores the first data;

[0165] When the operating temperature of the memory is greater than a second temperature threshold, controlling the voltage on the bit line before the transistor in the memory cell is turned on to be less than a bit line reference voltage;

[0166] When the operating temperature of the memory is greater than a second temperature threshold, the gate turn-on voltage of the control transistor is less than the gate reference voltage; and

[0167] The second temperature threshold is greater than the first temperature threshold.

[0168] In some embodiments, the voltage control circuit is further configured to:

[0169] When the operating temperature of the memory is greater than the first temperature threshold and the operating temperature of the memory is less than or equal to the second temperature threshold, the voltage of the storage unit in the memory is adjusted according to the model of the memory.

[0170] In some embodiments, the voltage control circuit is further configured to:

[0171] When the operating temperature of the memory is greater than a first temperature threshold, the operating temperature of the memory is less than or equal to a second temperature threshold, and the type of the memory is low power consumption, controlling the voltage of the upper plate of the capacitor to be an upper plate reference voltage when the storage unit stores the first data; and

[0172] When the operating temperature of the memory is greater than a first temperature threshold, the operating temperature of the memory is less than or equal to a second temperature threshold, and the type of the memory is low power consumption, controlling the voltage on the bit line before the transistor in the memory cell is turned on to be a bit line reference voltage;

[0173] The second temperature threshold is greater than the first temperature threshold.

[0174] In some embodiments, the voltage control circuit is further configured to:

[0175] When the operating temperature of the memory is greater than the first temperature threshold, the operating temperature of the memory is less than or equal to the second temperature threshold; and the type of the memory is not low power consumption, controlling the voltage of the upper plate of the capacitor to be less than the upper plate reference voltage when the storage unit stores the first data; and

[0176] When the operating temperature of the memory is greater than a first temperature threshold, the operating temperature of the memory is less than or equal to a second temperature threshold, and the type of the memory is not low power consumption, controlling the voltage on the bit line before the transistor in the memory cell is turned on to be less than a bit line reference voltage;

[0177] The second temperature threshold is greater than the first temperature threshold.

[0178] In some embodiments, when the first condition is met, the voltage of the upper plate of the capacitor when the storage unit stores the first data is greater than the voltage of the upper plate of the capacitor when the storage unit stores the first data when the second condition is met;

[0179] Among them, satisfying the first condition specifically includes: the operating temperature of the memory is greater than the first temperature threshold, the operating temperature of the memory is less than or equal to the second temperature threshold, and the type of the memory is not low power consumption; satisfying the second condition specifically includes: the operating temperature of the memory is greater than the second temperature threshold.

[0180] In some embodiments, the voltage on the bit line before the transistor in the memory cell is turned on when the first condition is satisfied is greater than the voltage on the bit line before the transistor in the memory cell is turned on when the second condition is satisfied;

[0181] Satisfying the first condition specifically includes: the operating temperature of the memory is greater than the first temperature threshold, the operating temperature of the memory is less than or equal to the second temperature threshold, and the type of the memory is not low power consumption; satisfying the second condition specifically includes: the operating temperature of the memory is greater than the second temperature threshold.

[0182] Some embodiments of the present application further provide a memory, comprising: a memory unit and the control circuit involved in the above embodiments, wherein the memory unit is connected to a bit line.

[0183] It should be noted that the high level and low level referred to in the above embodiments are relative concepts (i.e., the voltage value of the high level is higher than the voltage value of the corresponding low level), and the specific voltage value of the high level and the specific voltage value of the low level are not limited. In addition, it is not limited that the high levels applied on different signal lines in this specific embodiment are equal. For example, the high level on the bit line and the high level on the word line can be different voltages, and it is not limited that the high levels of a specific signal line at different stages are equal. For example, the high level applied to the bit line when writing 1 and when reading can be different voltage values. Those skilled in the art should understand that the corresponding high level and low level values ​​can be set according to the process node, speed requirements, reliability requirements, etc.

[0184] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0185] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A memory control method, characterized in that: The memory comprises a storage unit connected to a bit line, and the method comprises: Obtaining an operating temperature of the memory; adjusting the voltage of a storage unit in the memory according to the operating temperature of the memory; Among them, the voltage of the storage unit includes one or more of the voltage of the upper plate of the capacitor when the storage unit stores the first data, the voltage on the bit line before the transistor in the storage unit is turned on, and the gate turn-on voltage of the transistor. When the storage unit stores the first data, the voltage of the upper plate of the capacitor is greater than the voltage of the lower plate of the capacitor.

2. The control method according to claim 1, characterized in that: The voltage of the storage unit in the memory is adjusted according to the operating temperature of the memory, specifically including at least one of the following: When the operating temperature of the memory is less than or equal to a first temperature threshold, controlling the voltage of the upper plate of the capacitor to be greater than an upper plate reference voltage when the storage unit stores the first data; When the operating temperature of the memory is less than or equal to the first temperature threshold, controlling the voltage on the bit line before the transistor in the memory cell is turned on to be greater than a bit line reference voltage; as well as When the operating temperature of the memory is less than or equal to the first temperature threshold, the gate turn-on voltage of the transistor is controlled to be a gate reference voltage.

3. The control method according to claim 1, characterized in that: Adjusting the voltage of the storage unit in the memory according to the operating temperature of the memory specifically includes at least one of the following: When the operating temperature of the memory is greater than a second temperature threshold, controlling the voltage of the upper plate of the capacitor to be less than the upper plate reference voltage when the storage unit stores the first data; When the operating temperature of the memory is greater than the second temperature threshold, controlling the voltage on the bit line before the transistor in the memory cell is turned on to be less than a bit line reference voltage; as well as When the operating temperature of the memory is greater than a second temperature threshold, controlling the gate turn-on voltage of the transistor to be less than a gate reference voltage; The second temperature threshold is greater than the first temperature threshold.

4. The control method according to claim 1, characterized in that: Adjusting the voltage of a storage unit in the memory according to the operating temperature of the memory specifically includes: When the operating temperature of the memory is greater than a first temperature threshold and is less than or equal to a second temperature threshold, the voltage of the storage unit in the memory is adjusted according to the model of the memory; wherein the second temperature threshold is greater than the first temperature threshold.

5. The control method according to claim 4, characterized in that: When the operating temperature of the memory is greater than the first temperature threshold and the operating temperature of the memory is less than or equal to the second temperature threshold, according to the model of the memory, the method specifically includes: When the operating temperature of the memory is greater than a first temperature threshold, and the operating temperature of the memory is less than or equal to a second temperature threshold, and the type of the memory is low power consumption, controlling the voltage of the upper plate of the capacitor to be an upper plate reference voltage when the storage unit stores the first data; and When the operating temperature of the memory is greater than the first temperature threshold, and the operating temperature of the memory is less than or equal to the second temperature threshold, and the type of the memory is low power consumption, the voltage on the bit line before the transistor in the storage unit is turned on is controlled to be a bit line reference voltage.

6. The control method according to claim 4, characterized in that: The voltage of the storage unit in the memory is adjusted according to the model of the memory and the operating temperature of the memory, specifically including at least one of the following: When the operating temperature of the memory is greater than a first temperature threshold, and the operating temperature of the memory is less than or equal to a second temperature threshold; and when the type of the memory is not low power consumption, controlling the voltage of the upper plate of the capacitor to be less than the upper plate reference voltage when the first data is stored in the storage unit; as well as When the operating temperature of the memory is greater than the first temperature threshold, the operating temperature of the memory is less than or equal to the second temperature threshold, and the type of the memory is not low power consumption, the voltage on the bit line is controlled to be less than the bit line reference voltage before the transistor in the storage unit is turned on.

7. The control method according to claim 6, characterized in that: When the first condition is met, the voltage of the upper plate of the capacitor when the storage unit stores the first data is greater than the voltage of the upper plate of the capacitor when the storage unit stores the first data when the second condition is met; Among them, satisfying the first condition specifically includes: the operating temperature of the memory is greater than the first temperature threshold, the operating temperature of the memory is less than or equal to the second temperature threshold, and the type of the memory is non-low power consumption; satisfying the second condition specifically includes: the operating temperature of the memory is greater than the second temperature threshold.

8. The control method according to claim 6, characterized in that: When the first condition is met, the voltage on the bit line before the transistor in the memory cell is turned on is greater than the voltage on the bit line before the transistor in the memory cell is turned on when the second condition is met; Satisfying the first condition specifically includes: the operating temperature of the memory is greater than the first temperature threshold, the operating temperature of the memory is less than or equal to the second temperature threshold, and the type of the memory is not low power consumption; satisfying the second condition specifically includes: the operating temperature of the memory is greater than the second temperature threshold.

9. A memory control circuit, characterized in that: The memory includes a storage unit connected to a bit line, and the control circuit includes: a temperature monitoring circuit and a voltage control circuit; The temperature monitoring circuit monitors the operating temperature of the memory; The voltage control circuit is connected to the temperature monitoring circuit, and the voltage control circuit adjusts the voltage of the storage unit in the memory according to the operating temperature of the memory; Among them, the voltage of the storage unit includes one or more of the voltage of the upper plate of the capacitor when the storage unit stores the first data, the voltage on the bit line before the transistor in the storage unit is turned on, and the gate turn-on voltage of the transistor. When the storage unit stores the first data, the voltage of the upper plate of the capacitor is greater than the voltage of the lower plate of the capacitor.

10. A memory, characterized in that: include: A memory cell and a control circuit as claimed in claim 9, wherein the memory cell is connected to a bit line.

Images